CompE 470Digital Circuits

Course Syllabus Fall Semestre 2011

Department of Electrical and Computer Engineering San Diego State University Dr. Amir Alimohammad

Instructor: Amir Alimohammad, Assistant Professor Office: Fourth floor, Engineering, 403-E Phone: 619-594-2493 E-Mail: aalimohammad@mail.sdsu.edu Office Hours: Tuesdays and Thursdays 2 PM-3 PM. Feel free to make an appointment by email if you are not available during these hours. Class Website: TBA Class Schedule: 2 lectures per week; Tuesdays and Thursdays 5:30-6:45 Class Location: Geology, Mathematics & Computer Science (GMCS) - 214 Catalog Description: Design of digital electronic systems using commercially available highspeed digital devices and circuits Credits: 3.0 Prerequisite Course: CompE 270: Fundamentals on modeling and analysis of combinational and sequential digital systems Course Description: Design of digital systems using Verilog and VHDL hardware description languages, commercially-available computer aided design (CAD) tools, and configurable devices Topics Covered 1. Digital design methodologies and implementation strategies 2. Review of combinational digital design 3. Principles of sequential logic design 4. Verilog hardware description language 5. Digital design specification using Verilog 6. Synthesizable digital design using Verilog 7. VHDL hardware description language 8. Synthesizable digital design using VHDL Course Materials Lecture slides, class notes, academic articles, book chapters, industrial documentation and manuals, homework assignments, and quizzes Hand outs will be provided in class or will be posted on the class webpage. Check the class webpage regularly for updates Optional textbook: Advanced Digital Design with the Verilog HDL; Second Edition; Author: Michael D. Ciletti; Publisher: Prentice Hall, Pearson Education; Year: 2011
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CompE 470Digital Circuits

Course Syllabus Fall Semestre 2011

Department of Electrical and Computer Engineering San Diego State University Dr. Amir Alimohammad

Course Objectives 1. Gain a deeper understanding of design methodologies and implementation strategies, such as programmable processors, reconfigurable logic, and custom design 2. Model combinational and sequential digital modules and systems from initial specifications 3. Understand and write Verilog and VHDL hardware descriptive languages (HDLs) 4. Model, debug and simulate digital systems (e.g., using Mentor Graphics Modelsim) 5. Write synthesizable HDL models 6. Model digital designs in VHDL and Verilog for synthesis and timing analysis using a computer aided design tool, such as Xilinx ISE or Altera Quartus 7. Implement a verified design on a field-programmable gate array (FPGA) and perform postsynthesis verification Course Grading Homework assignments 20% Quizzes 20% Course Policies Most assignments involve HDL programming and using CAD tools 20% deduction per every late day Submit a written request along with your original assignment/exam to the professor for regrades. All submissions are re-graded in their entirety Quizzes are closed book and are given at the end of the lecture The final exam covers all topics As per 2011-2012 SDSU General Catalog (pages 460-474), San Diego State University expects the highest standards of academic honesty from all students. Violations of academic integrity including plagiarism, cheating, unauthorized collaboration on an exercise and/or exam, misappropriation of research materials , and any other forms of academic dishonesty that are intended to gain unfair academic advantage is not permitted. If your academic integrity is not maintained in an assignment or exam, you will automatically receive a grade of zero for that assignment or exam AND you will be reported to the Deans Office. Students who need accommodation of their disabilities should contact me to discuss specific accommodations for which they have received authorization. Please contact Student Disability Services (http://www.sa.sdsu.edu/sds/), before making an appointment to see me. Midterm exam 20% Final exam 40%

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