A SEMINAR REPORT ON

Low Power Design Methodologies for Mobile Communication

By Tallapalli Santosh Kumar (10B81D5715) M.Tech (VLSI System Design) I-year II-Semester

Under the Supervision of R.Ganesh Asst. Professor Dept of ECE

Department of Electronics and Communication Engineering CVR COLLEGE OF ENGINEERING ACCREDITED BY NBA, AICTE & Affiliated to JNTUH) Vastunagar, Mangalpalli (V) Ibrahimpatan (M), R.R. District, PIN 501 510

ABSTRACT

The rapid development of multimedia applications and the Internet leads to the demand of mobility for these services. New wireless standards are supporting high data rates and additional services, but they require complex realizations in both frontend and baseband of a mobile system. The obtainable performance of such a system is often limited by the power consumption of the implementation, as long stand-by and talk times are still key parameters of a mobile terminal. Also the thermal problem, given by insufficient heat removal with highly integrated high-performance circuits in narrow-spaced terminals, calls for optimizations concerning power consumption. This paper discusses the problem of power consumption in system on chip (SoC) design for mobile applications and presents methodologies for power optimized design.

Internal Guide Mr.R.Ganesh

INDEX
1. Introduction 1 2. Power Estimation on high abstraction levels 3. Low-Power Design Concepts 3.1. Concepts on higher abstraction levels 3.2. Concepts on implementation level 4. Low Power Layout Methodology 5. Conclusions 6. Acknowledgment 7. Bibliography 3 5 5 7 10 13 14 15

LIST OF FIGURES
Figure 1) Figure 2) Figure 3) Figure 4) Figure 5) Figure 6) Figure 7) Figure 8) Circuit schematic and signal diagram of a CMOS-Inverter Hardware/software co-simulation for power estimation Dependence of propagation delay on the supply voltage Performance-driven voltage scaling DC/DC converter for supply voltage regulation Measurement results of the DC/DC converter Low power layout methodology Place and route concepts 1 4 6 7 9 9 10 11

1. Introduction
Power consumption is a critical parameter in mobile battery-operated systems. Apart from design and user interface, parameters like operating and stand-by times have the main effect on the customer's choice in buying a mobile phone. Even its size and weight are determined by power consumption, as the battery of the handheld device mainly contributes to these criteria. Another issue is the problem densities in ever smaller packages that thermal situation. New generations of mobile phones offer a variety of accessories like calendars, email, games, music players and radio. Even executable software found its way to the device that becomes more and more an organizer. All these applications lead to intensive off-line operation, requiring activity in the digital (baseband) portion with standby in the RF part. Depending on the user's behavior this has a direct effect on the power allocation that will fall more intensively into the digital part than into the frontend. Nevertheless, the latter one is critical in terminals that support multi-standard like WCDMA and GSM. The user will not accept shorter operating times, e.g. in GSM mode, solely the power consumption has increased because of additional but not used functionality. of higher power become hard to manage in high-

performance systems. On the other hand, the performance itself is limited due to the

Figure 1: Circuit schematic and signal diagram of a CMOS-Inverter Today's design methodologies for system on chip development are mainly focused on performance, i.e. timing and accuracy. An optimization with respect to power consumption is usually not regarded as a first priority. Since power consumption will be 1

an important issue in future systems it is essential to establish a power driven component in the design flow. For power optimization of integrated circuits it is relevant to understand the causes of power consumption. Digital combinational and sequential CMOS design is usually based on a serial arrangement of complementary MOS transistors as shown in the circuit schematic and the corresponding signal diagram of the inverter example in Figure 1. Without switching activity either the PMOS or the NMOS transistor is switched off. Sub-threshold leakage currents through the transistor channel and reverse saturation currents in the diffusion regions of PMOS and NMOS transistors both cause the static power consumption Pstat

Both currents show an exponential dependence on the voltage: diode leakage depends on the voltage across the source/drain-bulk junctions of the transistors, while the sub-threshold current depends on the drain-source and gate-source voltages. The static power consumption is temperature dependent and mainly given by transistor geometries W and L. Leakage power is the major concern for circuits in stand-by mode. Since the gate length of deep-submicron CMOS technologies decreases, this effect becomes more and more important due to the increasing channel leakage current when the transistors are switched off. During the switching phase, for a short period of time, both NMOS and PMOS transistors are in saturation and simultaneously active. An instantaneous short-circuit current goes through the circuit branch directly to ground, causing the short-circuit power consumption Pshort.

with the transistor transconductance 0, threshold voltage vth, and the rise resp. fall times . Presuming this to be short, this effect is very small and can be neglected if the design is dimensioned and layouted properly.

During dynamic operation charging effects of parasitic wiring and load capacitors cause the dynamic power consumption Pdyn:

with the signal frequency f, the average load capacitance of internal and external nodes CL, and the switching activity factor . Power consumption in digital circuits is usually dominated by this effect. Approaches for reducing the dynamic power consumption by scaling th contributing parameters will be described in the following chapters. In analog design another item can be added to the total power consumption. Analog transistors usually operate in the linear range, so they need biasing for working in the correct operating point. For conventional operation in saturation the required DCparameters give a lower limit for the bias current. Operation in sub-threshold mode in the weak inversion range of a transistor offers a good alternative for low-power analog designs. In practice, appropriate models for weak inversion are often not available and designs might fail due to the insufficient modeling of this transistor region. This paper describes selected concepts and techniques for the power reduction of battery-powered on-chip systems. Chapter 2 introduces the problematic of power estimation on high abstraction levels. Approaches for the reduction of dynamic power consumption from system to implementation level are discussed in chapter 3. Chapter 4 focuses on the layout aspect.

2. Power Estimation on high abstraction levels

Embedded system design is usually carried out in a top-down approach. Partitioning is already done on system simulation level, dividing the required functionality into hardware and software function blocks. As stated before, power conscious design at this early stage is important for the final energy consumption of the system. So power estimation is already required on high abstraction levels of the design process .

Figure 2: Hardware/software co-simulation for power estimation In this design phase a straight-forward accurate and definite simulation of the power behaviour is hardly possible since the system level just describes the system functionality by a set of abstract mathematical equations. These equations can be transformed into architectures and circuit implementations in different ways. Exact power information can only be obtained for implementationrelated descriptions, whereas functional descriptions still offer a certain degree of freedom for implementation and so for energy consumption. On the other hand it is essential for the system designer to find a relative optimum rather than an absolute which leads to comparative power estimation. On system level two main approaches for power estimation are established. One approach is resting upon the estimation of the number of operations on algorithmic level and complexity/transition activity on implementation level . Based on high-level C/C++ language the architecture is synthesized to a coarse and preliminary implementation down to floorplan level and the estimated capacitive load is added to a model library. Then the power contribution of each active circuit module in each clock cycle is added. The current associated with each active module represents its power cost and is usually supposed to be constant and independent on the signal value, circuit state and correlation with other modules. Along with this, a model of component activity during the desired operations is required. This approach is based on the use of a software testbench as stimulus for the simulation. Feedback to the power models from real measurements of already existing components increases the accuracy.

Another approach is based on fast prototyping of system modules using lowpower FPGA implementations. Figure 2 shows that simulations take place in the usual system simulation environment. For power estimation a FPGA platform is added and a hardware/software co-simulation is applied. Measurement results are entered into macro models that are stored in a library for further use. The absolute power values of FPGA's and integrated circuits can not directly be compared since their power situation is different. To overcome this, tools are available to calculate the deviation. Most important for the system designer is the good relative accuracy that allows a comparison of different implementations. This approach enables power simulations for different system configurations and provides more flexibility

3. Low-Power Design Concepts

The design of low-power systems impacts all stages of the design process. The highest potential of energy reduction is given on high abstraction levels. Wrong decisions on system and algorithmic level, e.g. about partitioning or power management, can not be corrected on lower levels. On architecture level, methodologies like parallelism or pipelining, redundancy, RTL clock gating and energy-optimized coding style (e.g. the use of 'if' instead of 'case') lowers power consumption up to a certain degree. The powers saving capabilities in digital logic level are bound to the availability of optimized standard cells. Analog design offers a higher degree of freedom on circuit level, but it's difficult to define general rules. Analog and RF designs are very individual and lowpower methodologies vary in the particular case .

3.1. Concepts on higher abstraction levels.

A variety of architectural options exist for the implementation of signal processing algorithms. In telecommunication applications flexibility is an issue, as it enables multi-functional and multi-standard operations, and adaption to environmental conditions. General processors like ARM are flexible in a highest grade but not efficient concerning chip area and power consumption, providing not more than a few MIPS/mW. Power efficiency and area requirements can be improved by using alternative architectures like software programmable DSP or hardware reconfigurable processors, but on cost of flexibility. Best performance offers direct mapped hardware, providing 5

hundreds of MOPS/mW, but all flexibility is given up by choosing this architecture . As a compromise power optimized embedded generic or programmable virtual components are often used to improve design flexibility .

Figure 3: Dependence of propagation delay on the supply voltage An effective method of power optimization on medium abstraction levels is the reduction of switching activity. Architecture partitioning with respect to switching activity allows disabling the clock signals or reducing the clock rate in defined regions, depending on the computation activity. The insertion of different clock domains, known as clock rating, allows reduction of the switching activity mainly in data oriented paths. Disabling whole clock domains using the clock gating technique is most efficient in control orientated paths. Dependent on the data properties, coding can be another method to reduce switching activity. Counter encoding using the linear feedback shift register (LFSR) allows the replacement of the incrementer by just a few XOR-gates what reduces the hardware effort. In state machines, Gray coding reduces both the average number of logic transitions per clock and the overall number of transitions for a cycle .

3.2 Concepts on implementation level.

The most effective way to reduce dynamic power consumption on implementation level is scaling of the supply voltage due to the quadratic dependence. Limiting parameter is the propagation delay that increases with low supply voltages.

Figure 4. Performance-driven voltage scaling The parameters and Cox represent technology dependent constants. This equation is illustrated in Figure 3 for a typical deep-submicron CMOS technology whereas the delay is normalized to VDD = 3V. It can be seen that the propagation delay increases drastically as the supply voltage approaches the threshold voltage. On the other hand there is only little impact on performance with high supply voltages. Therefore, any voltage reduction must be balanced against performance reduction. To compensate and maintain the same data throughput extra hardware might be added. This leads to methodologies like architecture driven voltage scaling.For the desired performance a

trade-off between supply voltage and hardware concurrency in the system is found by transformation of the original architecture. Usually different function blocks of an on-chip system do not necessarily have to provide the same performance. To obtain an energy-optimized solution a variety of supply voltages is required. In practice this is hard to handle if the number of different supply voltages is high. Another issue is parameter variation in CMOS processes. Here the performance of a system is subject to technology dependent parameter tolerances. Hence a performance margin is required that could lead to an over-design, increasing the distance to the optimal solution.

To overcome these problems use a local supply voltage regulation. Using a DC/DC converter in a closed-loop arrangement, the operating voltage of a function block can be varied dynamically. The block diagram in Figure 4 shows a PLL-like control loop containing a DC/DC converter for local supply voltage generation. A test circuit in the feedback loop containing the critical circuit path is supplied with the regulated local supply voltage VDD'. The performance of this circuit is then compared with the required performance by a controller that adjusts the DC/DC converter output. This concept requires a sufficient matching of the delay in the critical paths of circuit and test circuit to avoid errors due to technology variations and temperature effects.

Two approaches for DC/DC conversion are commonly used. The Buck-Boost converter provides a good efficiency due to resonance effects, but the requirement of inductors makes this approach inappropriate for digital ASIC's. Alternatively, switchedcapacitor converters as shown in Figure 5 are based on CMOS compatible devices and combine low drop voltages with high efficiency and flexibility. The price is a larger ripple of the output voltage that requires filtering .

Figure 5: DC/DC converter for supply voltage regulation

Figure 6: Measurement results of the DC/DC converter. The resulting power reduction due to local supply voltage regulation is partly compensated by the energy requirements of the components in the control loop. Critical for this consideration is the low drop case, with VDD' close to VDD.

A DC/DC converter fabricated in a 0.18m CMOS process needs 0.82W for VDD = 1.8V and VDD' = 1.65V. Providing the maximum output current of 3mA, the efficiency is 87 percent. Area requirement for the DC/DC converter is 475m2, excluding the filter capacitor. The upper part of Figure 6 shows the gate voltage at the regulator transistor and the local supply voltage. The corresponding current can be seen at the bottom of the diagram. With a load of 1k and a filtering capacitor of 0.1F, the ripple on the generated supply VDD' is 2mVpp.

Figure 7: Low power layout methodology While the reduction of the supply voltage is a very efficient way to save power, a reduction of the operating frequency increases the propagation delay and doesn't reduce the total power consumption for a given performance since the operation takes longer. On the other hand a frequency reduction can be useful for non-time-critical algorithms due to the reduction of the peak current. The lower battery discharge current has a direct impact on the battery charging capacity and leads to higher charge availability.

4. Low Power Layout Methodology.

Target of power optimizations on layout level is the minimization of device parasitics which determine the static and dynamic MOS transistor behaviour and influence the power consumption. Minimization in that case means area reduction of the parasitic device and its related device area. This can be obtained by techniques like merging and sharing of MOS diffusion area and wells. The use of dedicated MOS transistor geometries like closed, waffle, finger or hexagon arrangements reduces parasitic drain-bulk and stray capacitances, whereby both dynamic behaviour and power 10

consumption are improved. Further improvement is obtained by the use of transistor folding techniques that decrease wire capacitances and resistances. Measurements have shown that the use of finger structures leads to power savings of more than 30% with an area reduction of 5%. For utilization of these optimizations in a digital design they have to be applied to standard cell libraries. As all these effects are related to the primitive device level it is worth to optimize them in a bottom-up design methodology that is shown in Figure 7. The optimized primitive devices are composed in the symbolic sub-cell level and finished on the physical cell level. The use of stick diagrams applies symbolic connections to the preplaced devices, with emphasis on keeping the dynamic signal wires short. Nodes showing a high switching activity like clock wires have to be routed with the highest priority to avoid coupling to other wires. It is obvious that they have to be shaped for minimum wire length and capacitance. Using metal wires for intrinsic routing leads to an area capacitance reduction of factor 3 compared to poly wires .

Figure 8: Place and route concepts In complex cells a partitioning into functional circuit blocks allows an adapted dimensioning of these blocks in accordance to their logic functionality and their dynamic parameters like delay, transition time and driving capability. Low-power optimizations on digital cell level are directly linked to noise behaviour. Minimized circuit capacitances lead to a reduced charge transfer for each 11

switching event. Digital switching noise in the substrate is lowered as well as the noise on the supply wires that arises from their resistive and inductive behaviour. This is an important effect for mixed-signal implementations. A drawback of the presented layout techniques is the lack of support by standard design environments. Special geometries, e.g. closed gates, lead to an insufficient support by standard models like bsim3v3. Both static and dynamic behaviour are determined by two-dimensional effects that are not yet captured by conventional models. The use of special layout shapes requires adapted run sets for DRC and layout extraction processes. This makes the verification difficult and might lead to design iterations. Parametric design techniques using circuit generators facilitate the design effort, since critical shapes can be adapted quite easily to a whole catalog of cells. This concept also supports a fast transfer to new fabrication processes . Energy reduction by lowering supply voltages can also be introduced to the digital top level layout. To take advantage of a good digital circuit partitioning a multi-supply backend approach for the different function blocks is essential. This assumes the availability of standard cell libraries that are characterized for the corresponding supply voltages. Further on the place and route (P&R) tool must be able to distinguish between the different supplies. Different examples for a dual voltage P&R concept are illustrated in Figure 8. Here, 'H' and 'L' mark the two supply voltages. In contrary to the singlevoltage approach in Figure 8a, the arrangement in Figure 8b shows one horizontal power track in each standard cell row, divided by power-stop cells between the different supply regions. A more flexible concept shown in Figure 8c deals with two horizontal power tracks in standard cells that provide dual-supply connections. The price for the dualvoltage layout is a slightly larger area due to the power-stop cells and additional vertical power rails.

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5.Conclusions
Aside Power consumption is one of the main issues in high-performance battery operated systems for mobile communication. In this paper a variety of approaches have been discussed with focus on CMOS digital integrated circuits. It is shown that optimizations on algorithmic and architectural levels of a design may have a major impact on power. Mistakes done in these early design stages can not be corrected in the further development process. Proper hardware/software partitioning and architecture selection are essential for power conscious system design. The antagonism between energy consumption and flexibility has to be balanced well. Methodologies like clock gating or coding are useful for further decrease. Main parameters for power reduction on circuit level are the switching activity and the supply or signal voltage. Supply voltage partitioning is supported by the presented performance driven voltage scaling concept, gaining from the square dependency between dynamic power consumption and signal voltage. The availability of standard cells with reduced parasitic capacitances allows an optimized physical implementation. An important issue for a power driven design flow is the combination of energy optimization and power estimation on all abstraction levels of a design. The establishment of power driven methodologies in the design flow of complex systems is enabling for new and highly sophisticated developments on a huge and growing market.

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6. Acknowledgment
The presented work was carried out within the German funded BMBF-project MENVOS (Methods for the development of power-optimized systems), No. 01M3047, that is related to the SSE/EKompaSS program. Partners in this project were Nokia Research Center, X-Fab Foundries GmbH, Catena Software GmbH, Gemac mbH, and the Universities of Dortmund, Saarland, and Freiburg.

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BIBLIOGRAPHY
[1] Design Technologies for Low Power VLSI Massoud Pedram

Department of EE-Systems,University of Southern California [2] Circuits Design for Low Power Kevin Nowka, IBM Austin Research Laboratory. [3]www.electronicsforu.com [4] www.Wikipedia.com [5] Low Power Design Methodologies for Mobile Communication Ralf Kakerow, Nokia Research Center, Bochum, Germany

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