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A 10-Mc/s, 0.5-m CMOS Constant-Fraction Discriminator Having Built-In Pulse Tail Cancellation
D. M. Binkley, Senior Member, IEEE, B. S. Puckett, Member, IEEE, B. K. Swann, Member, IEEE, J. M. Rochelle, Member, IEEE, M. S. Musrock, Member, IEEE, and M. E. Casey, Member, IEEE

AbstractA 0.5- m, fully-integrated CMOS, constant-fraction discriminator (CFD) is presented for 10-Mc/s operation. The CFD utilizes a timing-shaping filter to provide amplitude insensitive time discrimination without delay lines or other external components. Continuous-time baseline restorers are used to cancel CMOS dc offsets and provide signal tail cancellation for both the arming and constant-fraction signals. Near total signal tail cancellation at 100 ns permits operation at count rates up to 10 Mc/s. Measured intrinsic timing resolution is 40 to 90 ps FWHM for a 3.7:1 input dynamic range and measured walk is 20 ps for a 2.7:1 dynamic range increasing to 80 ps for a 3.7:1 dynamic range. Measured timing resolution for an LSO/PMT detector against a plastic/PMT detector is 1.00-ns FWHM at low count rates increasing to 1.27-ns FWHM at 6.0 Mc/s. The CFD is part of a 0.5- m CMOS front-end integrated circuit designed for large-area, high-count-rate LSO or BGO detectors used in PET medical imaging. Index TermsAnalog CMOS integrated circuits, constant fraction discriminator (CFD), front-end electronics, nuclear pulse timing, positron emission togography (PET), pulse tail cancellation.

II. CFD OVERVIEW A block diagram of the CMOS CFD is shown in Fig. 1. Constant-fraction (CF) shaping, normally done with an external delay line and attenuation network [2], is implemented in a monolithic shaping filter. In this shaping filter, an attenuated version of the CFD input signal is subtracted from a delayed version of the input signal rendering an output-pulse zero crossing time that is independent of input amplitude [3], [4]. Inside the CF shaping filter, a five-pole lowpass filter provides the needed signal delay, replacing the delay line used in the traditional CFD [2]. A delay-select line allows the time delay to be selected at nominally 4.5 or 7.5 ns to accommodate either fast or slow rise-time photomultiplier tubes (PMTs). Both the CF and arming circuits shown in Fig. 1 include continuous-time baseline restorer (BLR) circuits to cancel dc baseline errors due to circuit offsets and varying event count rates. In addition, these BLR circuits provide built-in signal decay tail cancellation through continuous-time, wideband, negative feedback. The pulse tail cancellation, needed for high count-rate operation, is illustrated at the CF and arming BLR outputs. The CF BLR circuit holds the CF signal baseline near zero whereas the arming BLR holds the arming signal baseline below zero by an amount equal to the selected CFD arming threshold. A CF comparator is used to sense the zero crossing at the CF BLR output, providing the needed amplitude-independent time pickoff. An arming comparator is used to enable or arm time discrimination only when the arming BLR output exceeds a preset CFD arming threshold. Arming logic provides traditional arming where the CFD output is present whenever both arming and zero-crossing detection occur, or slow rise time reject (SRT) arming where the output is present only if arming precedes zerocrossing detection. III. CIRCUIT OPERATION

I. INTRODUCTION ONSTANT fraction discriminator (CFD) time pickoff, being substantially free of time walk for varying input pulse amplitude, is used for positron emission tomography (PET) and other systems requiring timing coincidence measurement. In recent years, the high detector density of modern PET systems has resulted in CMOS integration of the front-end electronics, including fully integrated CFD circuits [1]. However, these early systems were designed in 2- m CMOS for operation at dead times of approximately 600 ns. The recent commercialization of large-area LSO PET detectors requires CFDs having substantially less dead time of 100 ns. A 0.5- m CMOS CFD meeting these requirements is presented here.

Manuscript received November 25, 2001; revised March 14, 2002. This work was supported by CTI PET Systems, Inc., and Concorde Microsystems, Inc. D. M. Binkley was with Concorde Microsystems, Inc., Knoxville, TN 37922 USA. He is now with the Electrical and Computer Engineering Department at the University of North Carolina at Charlotte, Charlotte, NC 28223 USA (e-mail: dmbinkle@uncc.edu). B. S. Puckett was with the University of Tennessee, Knoxville, TN 37901 USA. He is now with Analog Devices, Inc., Greensboro, NC 27410 USA (e-mail: Scott.Puckett@analog.com). B. K. Swann and J. M. Rochelle are with Concorde Microsystems, Inc., Knoxville, TN 37922 USA (e-mail: swann@cms-asic.com; rochelle@cms-asic.com). M. S. Musrock and M. E. Casey are with CTI PET Systems, Inc., Knoxville, TN 37922 USA (e-mail: Mark.Musrock@cpspet.com; Mike.Casey@cpspet.com). Publisher Item Identifier S 0018-9499(02)06143-9.

A. Pulse-Tail Cancellation Methods When the duration of a detector decay tail limits operation at high count rates, it is usually necessary to utilize pulse-tail cancellation to shorten the decay tail and permit a rapid return to the baseline. When the decay tail is exponential, the zero in a pole-zero network can effectively cancel the pole associated with the tail decay [5]. The pole-zero network will necessarily introduce its own pole, but the time constant associated with this pole can be made shorter than the original decay tail time constant. If the pole-zero network is tuned to the decay tail of the detector pulse, which may be due to either detector operation or a pole in the detector preamplifier, the pulse duration

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Fig. 1. Block diagram of the CMOS CFD. The circuit uses a nondelay-line CF shaping filter for monolithic integration. Wideband, continuous-time baseline restorers provide dc offset cancellation and pulse tail cancellation. The built-in pulse-tail cancellation permits operation at 10-Mc/s count rates.

can be reduced considerably. Pole-zero tail cancellation techniques have been reported in bipolar integrated circuits [6], [7] and CMOS integrated circuits [8] to reduce the long ion decay tail associated with proportional chamber detectors. Due to the requirements of tuning a pole-zero network over CMOS process variations and the large decay time constant difference of LSO and BGO scintillation detectors (having 40 ns and 300 ns decay time constants respectively), the pole-zero technique is not used in the CMOS CFD presented here. If the zero of a pole-zero network is placed at the origin (0 Hz or dc), the circuit reduces to a simple, single-pole high-pass filter. Such a circuit has the advantage of totally blocking dc signals, including CMOS mismatch related voltages while eliminating the need for tuning the zero frequency. This type of circuit is used in a CMOS integrated circuit [9] for canceling the decay associated with straw tube ionization chambers. The continuous-time BLR used in the CMOS CFD presented here has similar response to the single-pole high-pass filter, providing pulse tail cancellation without tuning while also removing circuit dc offsets. B. Continuous-Time BLR for Pulse Tail Cancellation Signal dc offset and pulse-tail cancellation is provided in the CMOS CFD by a continuous-time BLR conceptually illustrated in Fig. 2. Here error between the BLR output signal and a base. This line reference causes output current in transconductor current charges capacitor , changing its voltage so the BLR . Delay output error is cancelled through difference amplifier provides a sampling delay to minimize BLR canelement cellation of the input signal leading edge. , the BLR has If sampling delay is not present, response given by (1) where (2)

Fig. 2. Block diagram of the continuous-time BLR. The circuit removes dc offsets and cancels the decay tail of the input signal.

The BLR response in (1) is equal to the response of a and time single-pole CR highpass filter having gain of as given in (2). constant of If an exponentially decaying scintillation detector signal with , the resulting zero rise time is applied to the BLR with output signal response is given by (3) is the scintillator decay time constant. The time-dowhere is then given by main output signal for (4) , effective pulse-tail cancellation is possible If where the first term in (4) is a desired, near-unity positive-decaying exponential having the shorter highpass time constant, and the second term is an undesired, much smaller negative-decaying exponential tail having the longer scintillator time constant . This is illustrated in Fig. 3 for BGO and LSO detector signals applied to the BLR having an 8-ns highpass time constant.

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Fig. 3.

Illustration of pulse tail cancellation for BGO and LSO signals applied to BLR without sampling delay.

At high count rates, the undesired exponential tail (second term in (4)) results in a baseline shift that can be expressed as a fraction of the desired signal peak (first term in (4)). This fraction for a periodic count rate having period is found from the sum of previous pulse decay tails and is given by (5) ns) and For a BLR highpass time constant of 8 ns ( ns), (5) gives a a periodic count rate of 10 MHz ( ns) and 6.7 for baseline error of 1.8 for LSO ( ns) signals. The baseline error without the BLR BGO ( would be much higher at 8.9 for LSO and 253 for BGO signals as given by the summation in (5) without the multiplier . of C. CFD Arming Signal The detector signal connecting to the arming BLR (Fig. 1) in the CMOS CFD has finite rise time due to the rise time of the detector PMT and subsequent amplification stages. The detector signal rise time (10%90%) is approximately 10 ns and is modeled here by a zero rise time signal applied to a lowpass filter consisting of three real, 2.5-ns poles. When this 10-ns rise-time signal is applied to the arming BLR, some cancellation occurs along the leading edge of the in Fig. 2) reduces signal. The addition of a sampling delay ( this leading-edge signal loss. Sampling delay is introduced by three real, 1-ns real poles that approximate one deliberate and two parasitic poles in the CMOS implementation of the arming and CF BLRs.

Fig. 4. illustrates the arming BLR output for BGO and LSO detector signals having 10-ns rise times. The output is shown with and without the 3-ns sampling delay for a BLR highpass time constant of 8 ns. There is a 28% increase in output signal level for both BGO and LSO signals when the sampling delay is included. At 100 ns, the baseline error is 4.4 (relative to the peak output signal) for both BGO and LSO signals, with or without the sampling delay. The LSO baseline, however, decays much more rapidly at a time constant of 40 ns compared to 300 ns for BGO. Increasing the sampling delay somewhat above 3 ns would increase the BLR output signal level with little effect on pulse tail cancellation. However, the sampling delay introduces extra phase shift in the BLR negative feedback loop affecting feedback stability and response. D. CFD Constant-Fraction Signal In addition to connecting to the arming BLR, the detector signal also connects to the CF shaping filter (Fig. 1). This circuit, illustrated in Fig. 5, subtracts the input signal from a delayed version having gain of two providing an output zero crossing that is independent of input amplitude. This nondelay-line CFD circuit, utilizing a signal fraction of one-half and delay provided by multiple real poles, is described in detail in [3], [4]. As described later, this circuit lends itself to monolithic CMOS implementation using a current-mode lowpass delay circuit. Fig. 5 and other nondelay-line time pickoff circuits suitable for monolithic integration are similar to the traditional CFD circuit where a fraction of the input signal is subtracted from a delayed version of the input using a delay line [2]. One circuit utilizes the delay associated with the distributed resistance and capacitance of monolithic structures, such as polysilicon resis-

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(a)

(b) Fig. 4. Illustration of pulse tail cancellation in CFD arming signals for (a) BGO and (b) LSO detector signals applied to BLR with and without sampling delay.

Fig. 5. Block diagram of CF shaping filter. This nondelay-line circuit provides an output zero crossing that is insensitive to input amplitude.

tors [10]. Another circuit subtracts a fraction of the input signal from a single-pole highpassed version of the input [11] giving equal response as the circuit of Fig. 5 for a single-pole delay [3]. Additionally, it is possible to utilize a single-pole, highpass CR filter to create an amplitude-independent zero crossing [12]. The circuit of Fig. 5, however, utilizes a high number (five) of isolated poles resulting in less deterioration in output zero-crossing rise time or slope. Like the CFD arming channel, the CF channel utilizes a BLR to cancel circuit dc offsets and provide pulse-tail cancellation (Fig. 1). This BLR is identical to the one described for the

arming channel. Fig. 6 illustrates the CF BLR output for BGO and LSO detector signals having 10-ns rise times. Again, the output is shown with and without the 3-ns sampling delay for a BLR highpass time constant of 8 ns. There is a 33% increase in output signal level for both BGO and LSO signals when the sampling delay is included. At 100 ns (not shown in Fig. 6), the baseline error is 3.7 (relative to the peak output signal) for BGO and 4.4 for LSO signals with the sampling delay. As in the arming signals of Fig. 4, the baseline decays much more rapidly for LSO signals compared to BGO signals. E. CFD Arming and CF Signals for 10-MHz Periodic Events Fig. 7 shows the arming and CF signals for BGO signals at a periodic count rate of 10 MHz, with and without the presence of the BLRs. Fig. 8 shows the arming and CF signals for LSO signals at the same count rate. Again, BLR time constants of 8 ns are used along with a 3-ns sampling delay. Significant pulse pileup reduction is evident, especially for the BGO signals (Fig. 7) where arming threshold discrimination and

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(a)

(b) Fig. 6. Illustration of pulse tail cancellation for (a) BGO and (b) LSO CF signals applied to BLR with and without sampling delay.

zero-crossing CF timing would be impossible without the pulse tail cancellation provided by the BLRs. The baseline error is 25 mV or 12.5% of the 200 mVpk signal for the BGO arming signals. This error is 26 mV or 10.8% of the 240 mVpk signal for the BGO CF signals. The baseline error is 29 mV or 5% of the 580 mVpk signal for the LSO arming signals. This error is 36 mV or 5% of the 725 mVpk signal for the LSO CF signals.

F. CFD Arming and CF Signals for 10-Mc/s Random Events Actual BGO and LSO signals are not periodic events but Poisson events occurring randomly in time. Monte Carlo simulation was performed in order to estimate the baseline mean and standard deviation. Single event signals were convolved with a series of impulses occurring randomly in time. The resulting signals were sampled immediately before the impulses (or detector events) to assess the spectrum of the baseline signal. One million events were simulated at an average count rate of 10 Mc/s for each baseline signal considered.

The Monte Carlo simulated baseline mean is 9.3 mV or (4.7% of the 200 mVpk signal) with a standard deviation of 60.9 mV (30.5% of the signal) for the BGO arming signals. The baseline mean is 8.4 mV (3.5% of the 240 mVpk signal) with a standard deviation of 76.3 mV (31.8% of the signal) for the BGO CF signals. The baseline mean is 21.9 mV (3.8% of the 580 mVpk signal) with a standard deviation of 171 mV (29.5% of the signal) for the LSO arming signals. The baseline mean is 19.5 mV (2.7% of the 725 mVpk signal) with a standard deviation of 217 mV (29.9% of the signal) for the LSO CF signals. Interestingly, the simulated baseline means are less than those reported in Section III-E for periodic events. However, the standard deviation of the baseline signals is significantly greater than the means and is nearly 30% the signal peak for both BGO and LSO signals. This illustrates that there is considerable fluctuation of the baseline associated with the random time occurrence of events. The baseline signals have a nonGaussian spectra having maximum density at zero volts with a decaying distribution for negative voltages. This distribution appears somewhat exponential for LSO signals and asymmetrically Gaussian for BGO signals.

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(a)

(b) Fig. 7. Illustration of pulse tail cancellation for (a) arming and (b) CF signals for BGO signals applied at a periodic rate of 10 MHz.

IV. CMOS CIRCUITS A. Description A large number of custom, 0.5- m analog CMOS circuits make up the integrated CFD illustrated in Fig. 1. Differential current-mode and voltage-mode circuits are used in the arming and CF channels to minimize even-order distortion, power supply noise coupling, noise coupling from other circuits, and systematic circuit offsets. Traditional CMOS logic circuits are used for the arming logic with the exception of flip flops that

have been designed for low metastability to maximize logic performance for signals near the CFD threshold. Fig. 9 is a single-ended depiction of the differential circuits used in the CF shaping filter and its associated BLR. The CFD detector input voltage is converted to multiple signal currents ( ) by an input transconductor and current mirror system. One signal current is delayed and given a current gain of two ). Another signal current is subtracted from this current ( ). This current is converted to giving an output CF current ( ) by low-capacitance high-resistance polysilicon voltage (

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(a)

(b) Fig. 8. Illustration of pulse tail cancellation for (a) arming and (b) CF signals for LSO signals applied at a periodic rate of 10 MHz.

resistors (two of these since all signals are differential). This voltage is sampled by the BLR circuit which provides a correc) to cancel circuit dc offsets and the signal tion current ( ) provides an decay tail. The differential output voltage ( amplitude-independent zero crossing that is sensed by the CF comparator. The BLR circuit of Fig. 9 consists of an operational transconductance amplifier (OTA) designed for linear operation at input voltages up to approximately 1 V. The current output of this OTA feeds an internal compensation capacitor creating a correction

voltage. This voltage is sensed by another OTA that provides the necessary BLR output correction current. Unlike the gated BLR circuits used in a previous 2- m PET front-end integrated circuit [1] and described in [13], the BLRs in the 0.5- m CMOS CFD operate with continuous-time negative feedback. Fig. 10 shows an abbreviated schematic of the five-pole delay circuit shown in Fig. 9. This is a differential current-mode circuit consisting of grounded-gate MOSFETs where signal poles are introduced by the addition of poly-poly capacitors between the MOS sources and ground. This results in the introduction of

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arming voltage sensed by the BLR circuit. An integrated 8-b analog-to-digital converter provides a deliberate CFD threshold offset at the input of the arming BLR. This lowers the arming baseline by the selected CFD threshold such that the arming condition is met when the arming signal exceeds zero. B. Performance Simulations Post-layout SPICE simulations were performed on the full CMOS CFD for statistically noiseless LSO and BGO detector signals at a periodic rate of 10 MHz. Signals representing 1x, 0.5x and 1.5x photopeak levels were used to simulate a 3:1 dynamic range. The differential arming and CF signal voltages simulated in the CMOS CFD closely match those shown in Figs. 7 and 8 for BGO and LSO signals, respectively, with the exception that 1x, 0.5x and 1.5x signals are used in the CMOS simulations. The simulated BGO arming signal is 142 mVpk (1x) having a baseline error shift of 18 mV or 12.7% of the peak signal. The simulated BGO CF signal is 188 mVpk (1x) having a baseline error of 20 mV or 10.6% the signal peak. The simulated LSO arming signal is 480 mVpk (1x) having a baseline error shift of 25 mV or 5.2% of the peak signal. The simulated LSO CF signal is 680 mVpk (1x) having a baseline error of 34 mV or 5% the signal peak. The BGO signals are smaller because of the smaller input levels required due to severe pulse pileup (see Fig. 7). Since the simulated CMOS CFD signals for periodic events at 10 MHz closely match the signals shown in Figs. 7 and 8, it is expected that the mean and standard deviation of the baselines would be similar to those predicted in Section III-F for random events at 10 Mc/s. Here the baselines were found to have maximum density at zero volts with a decaying distribution for negative baseline voltages. Time pickoff error for the CMOS CFD was simulated for 10-MHz periodic events including the arming and CF comparators and the arming logic in addition to the arming and CF circuits previously described. A 1.2-ns peak-to-peak timing error is observed for 10-MHz BGO signals over the 3:1 dynamic range. This time pickoff error is much less at 350 ps peak-to-peak for the larger LSO signals at the same rate and dynamic range. Most of the time pickoff error is time walk for the 3:1 dynamic range input due to the presence of a nonzero baseline at the CF signal. This baseline error, described above, is approximately 10% and 5% of the BGO and LSO CF pulses respectively for 1x photopeak signals at a count rate of 10 MHz. The baseline error reduces to near zero at low count rates, being limited only by the CMOS mismatch offset at the input of the CF BLR circuit. The presence of input amplitude induced CFD time walk caused by CF baseline error is discussed in detail in [14]. Measured CFD amplitude walk, described later, is only 80 ps for a 3.7:1 dynamic range at low count rates where the CF baseline is nearly zero. High count rate walk timing errors of 1.2 ns (BGO) and 350 ps (LSO) peak-to-peak should negligibly increase timing resolution above the intrinsic timing resolution of approximately 3 ns (BGO) and 1 ns (LSO) FWHM for LSO/PMT and BGO/PMT scintillation detectors. The CMOS CFD simulations do not include the statistical noise of the detectors and the statistical occurrence of overlap-

Fig. 9. CMOS implementation of CF shaping filter with BLR for circuit dc offset and signal tail cancellation. The actual circuit utilizes differential signal paths.

Fig. 10. Abbreviated schematic of CMOS current-mode delay circuit used in CF fraction shaper. Three of the five lowpass poles are shown.

independent, isolated real poles having time constants of 0.9 ns , where is the total source caas approximated by is the MOS transconductance. The pole time pacitance and constants are increased to 1.5 ns when differential capacitors are introduced across related MOS sources. These capacitors are connected by MOS switches to provide a long CF delay setting of approximately 7.5 ns compared to the normal setting of approximately 4.5 ns. This permits the use of slower rise time PMTs in scintillation detectors. Low-voltage biasing techniques are used to set the gate bias of the grounded gate MOS devices in Fig. 10. This permits a maximum number of ground-gate stages without the introduction of current mirrors. The use of grounded-gate MOS stages driven from high impedances (current mode) significantly reduces the introduction of MOS dc mismatch and noise due to the high level of MOS source degeneration. External transconductor and current mirror circuits dominate the MOS dc mismatch and noise of these grounded-gate stages. Circuitry for the CFD arming channel is similar to that of the CF shaper shown in Fig. 9, except the signal delay and signal subtraction circuits are omitted. Here, the input signal currents are summed with the BLR output currents with the differential

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Fig. 11.

Measured intrinsic timing resolution and walk.

ping pulses associated with random events in time. Simulation of timing resolution and energy cutoff resolution of CFD circuits is described in [15] where scintillation statistical noise, PMT single-electron response and transit time spread, and impulse response of the front-end and CFD circuits are used in Monte Carlo simulations. This assumes the front-end CFD circuits are sufficiently linear. These Monte Carlo simulations can be further expanded to include pulse pileup and baseline fluctuation associated with random detector events at high count rates. Although not studied in detail, initial Monte Carlo timing simulations were performed considering the pulse pileup and baseline fluctuation simulations described in Section III-F. These simulations indicate the non-Gaussian baseline spectrum distorts the CFD timing spectrum some from the normal Gaussian spectrum expected. A Gaussian timing spectrum is expected for timing on a large number of photoelectrons with or without the presence of Gaussian electronic noise or Gaussian baseline fluctuation at high count rate. CMOS CFD timing jitter, measured at 90 ps FWHM or less as described below, is much easier to predict than the resolution due to detector statistical noise and pulse pileup, especially since the CF shaping circuit is a continuous-time circuit. Steady-state noise analysis (or SPICE simulation with accurate MOS noise models) can be used to find the CF signal noise. Timing jitter is then found by dividing the total rms noise on the CF signal by the zero-crossing slope. This assumes the CF signal noise sufficiently exceeds the noise present at the input of the CF comparator. V. MEASURED PERFORMANCE The 0.5- m CMOS CFD was fabricated using the MOSIS fabrication service. Fig. 11 shows measured intrinsic timing resolution and walk for voltage pulse inputs having a 2-ns rise time,

increased to approximately 5 ns by the input transconductor system that provides signal currents to the CFD circuits. Jitter decreases from 90 ps FWHM (23-mV input) to 40 ps FHWM (85-mV input). Walk is 20 ps for inputs between 23 and 63 mV (2.7:1 dynamic range), increasing to 80 ps for inputs between 23 and 85 mV (3.7:1 dynamic range). The increase in walk for the 85-mV input signal, corresponding to a differential CFD input current of approximately 170 A for a 2-mS transconductance in the input transconductor system, is due primarily to time distortion in the current-mode delay circuit (Fig. 10). Here, a large signal current causes device currents to deviate measurably from their fixed dc bias currents. Fig. 12 shows measured energy discrimination at four threshold levels for a LSO/PMT detector excited by a Na source. The gated energy spectra indicate the CFD arming threshold can be set at 150 keV to essentially collect all events surrounding a 511-keV photo peak associated with PET applications. Measured timing resolution for a LSO/PMT detector and reference plastic/PMT detector is 1.0 ns FWHM and 1.8 ns FWTM at count rates below 400 kcps when excited by a Na source. The timing resolution increases to 1.12, 1.21 and 1.27 ns FWHM for count rates of 1.4, 3.2 and 6.0 Mc/s respectively. Timing resolution at the count rate of 6.0 Mc/s is illustrated in Fig. 13. An FWTM measure of timing resolution is not meaningful at this count rate where the random coincidence rate approaches or exceeds 10% the timing photopeak value. An F source is used for the high count rate data and the energy threshold for all timing measurements was 250 keV. VI. CONCLUSION A fully-integrated, 0.5- m CMOS CFD has been designed and evaluated for high-count-rate PET applications. Measured

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Fig. 12.

Measured energy discrimination at four threshold levels for

Na source and LSO/PMT detector.

Fig. 13.

Measured timing resolution for a LSO/PMT detector with plastic/PMT reference detector excited by an

F source at a count rate of 6.0 Mc/s.

timing jitter and walk (3.7:1 dynamic range) are under 100 ps FWHM and low count-rate timing resolution for a LSO/PMT detector against a plastic/PMT detector is 1.0 ns FWHM and 1.8 ns FWTM. The timing resolution degrades modestly to 1.27 ns FWHM at a count rate of 6.0 Mc/s. The complete CMOS CFD was simulated at the transistor level by SPICE for detector signals over a 3:1 dynamic range at a periodic count rate of 10 Mc/s. These simulations show a peak-to-peak timing error of 350 ps for LSO signals and 1.2 ns for BGO signals, the BGO signals exhibiting severe pileup (over 250%) prior to the BLR circuits. These simulations suggest the CMOS CFD will degrade timing resolution only slightly above the intrinsic resolution of LSO/PMT (approx-

imately 1 ns FWHM) and BGO/PMT (approximately 3 ns FWHM) detectors at high count rates. Methods for Monte Carlo performance simulation were described to include detector statistical noise and pulse pileup at high count rates. These effects were intrinsically considered in the measurements. The CMOS CFD is part of a 0.5- m front-end integrated circuit designed for large area, high count rate LSO or BGO detectors used in PET medical imaging. ACKNOWLEDGMENT The authors wish to acknowledge C. Hopper, University of North Carolina at Charlotte, for assistance in preparing this paper.

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