Lecture 26 Semiconductor Memories

Digital Integrated Circuits Memory Prentice Hall 2000

Periphery
Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Digital Integrated Circuits Memory Prentice Hall 2000

Memory Timing: Definitions

Read Cycle READ Read Access WRITE Write Access Data Valid DATA Data Written Read Access Write Cycle

Digital Integrated Circuits

Memory

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Memory Timing: Approaches

MSB LSB

Address Bus RAS

Row Address Column Address Address Bus

Address Address transition initiates memory operation

CAS

RAS-CAS timing

DRAM Timing Multiplexed Adressing

Digital Integrated Circuits Memory

SRAM Timing Self-timed

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Address Transition Detection

VDD

A0

DELAY td

ATD

ATD

A1

DELAY td

... AN-1 DELAY td

Digital Integrated Circuits

Memory

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DRAM Timing

Digital Integrated Circuits

Memory

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Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder

NOR Decoder

Digital Integrated Circuits

Memory

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Dynamic Decoders
Precharge devices GND GND VDD WL3 WL3 VDD WL2

WL2 WL1 WL0

VDD

VDD

WL1

WL0

VD D

A0

A0

A1

A1

A0

A0

A1

A1

Dynamic 2-to-4 NOR decoder

2-to-4 MOS dynamic NAND Decoder

Propagation delay is primary concern

Digital Integrated Circuits Memory Prentice Hall 2000

A NAND decoder using 2-input predecoders

WL 1

WL 0

A0A1 A0 A1 A0A1 A0A 1

A 2A3 A2 A3 A2A3 A2A3

A1 A 0

A0

A1

A3 A2

A2

A3

Splitting decoder into two or more logic layers produces a faster and cheaper implementation
Digital Integrated Circuits Memory Prentice Hall 2000

4 input pass-transistor based column decoder

BL0 S0 S1 S2 S3 BL1 BL2 BL3

A0

A1

2 input NOR decoder

vantage: speed (tpd does not add to overall memory access time) only 1 extra transistor in signal path advantage: large transistor count
Digital Integrated Circuits Memory Prentice Hall 2000

4-to-1 tree based column decoder

BL0 A0 A0 A1 A1 BL1 BL2 BL3

D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Digital Integrated Circuits Memory Prentice Hall 2000

Decoder for circular shift-register

VDD WL0 R VDD R VDD WL1 R VDD VDD WL2 ... VDD VDD

Digital Integrated Circuits

Memory

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Sense Amplifiers
C V t = ---------------p Iav large make V as small as possible

small

Idea: Use Sense Amplifer small transition input

Digital Integrated Circuits Memory

s.a. output
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Differential Sensing - SRAM

VDD VDD PC VDD x SE WLi y M3 M1 BL M4 M2 M5 x x SE VDD y x

BL

EQ

(b) Doubled-ended Current Mirror Amplifier VDD SRAM cell i y Diff. x Sense x Amp y y D D x SE y x

(a) SRAM sensing scheme.

Digital Integrated Circuits Memory

(c) Cross-Coupled Amplifier

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Latch-Based Sense Amplifier

EQ BL VDD SE BL

SE

Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Digital Integrated Circuits Memory Prentice Hall 2000

Single-to-Differential Conversion
WL BL x Diff. S.A. x
+ _

cell

Vref

How to make good Vref?

Digital Integrated Circuits Memory Prentice Hall 2000

Open bitline architecture

EQ R L1 L0 VDD SE BLL BLR R0 R1 L

CS

... CS

CS

SE

CS

... CS

CS

dummy cell

dummy cell

Digital Integrated Circuits

Memory

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DRAM Read Process with Dummy Cell

6.0 4.0 BL 2.0 0.00 BL 5.0 V (Volt) 1 2 3 t (nsec) (a) reading a zero 4 5 4.0 3.0 2.0 1.0 0.00 V (Volt) 4.0 BL BL 1 2 3 t (nsec) 4 5 2.0 1 2 3 4 (c) control signals 5 EQ WL SE

V (Volt)

6.0

0.00

(b) reading a one

Digital Integrated Circuits Memory Prentice Hall 2000

Single-Ended Cascode Amplifier

VDD

Vcasc

WLC

WL

Digital Integrated Circuits

Memory

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