The IEEE Region 8, EUROCON 2007, International Conference on "Computer as a Tool" (IEEE EUROCON'07), Warsaw, Poland, September 9-12,

2007.

Power Consumption in Wireless Networks: Techniques & Optimizations

N. Sklavos*, Member IEEE, K. Touliou, Member IEEE
*

University of Patras, Patras, Greece, email: nsklavos@ieee.org ENST-Telecom, Paris, France, email: k.touliou@ieee.org architectures of modern cellular phones are studied in detail. The impact of each one of the mobile systems modules, in the overall power consumption of the platform, is analyzed. The most efficient power management techniques, that could developed so far, are proposed. Alternative solutions in each case are suggested, according to the specifications and design limits each time. Conclusions are given regarding the power consumption optimizations. Finally, future directions and answers to the problem of consumption are proposed. This paper is organized as follows: In Section I, a short introduction is given. Section II presents the architectures pf wireless devices. In Section III deals with power consumption for each unit of the architecture. In the next section power reduction mechanisms are proposed. Finally, the paper ends with conclusions and outlook. II. MULTI-PROCESSOR PLATFORM First generations mobile phones, where only phone related services were supported, made use of simple system architecture. Typically, two basic subsystems where included: the analog and the baseband. The former supported the RF operations, whereas the latter implemented the physical layer of the protocol. However, the transition from a voice-centric cellular system to datacentric 3G systems forced the design of a complete new architectural scheme. The new design approach must be able to support rich multimedia applications, high-end operating systems and various user interfaces. Thus, the most suitable architecture is one employing multiple processing units, each one of which handles different tasks [1], [5]. The structure of a multi-core architecture for modern mobile phones is illustrated in Figure 1.

AbstractPower consumption has become an important concern when it comes to the implementation phase of wireless devices. Especially, in mobile phones, where design characteristics like size and weight are forbidden the use of large batteries, minimizing power loss is quite challenging. In this paper, power issues of new generations cellular phones have been explored in detail, at a system level. The study presents that CPUs, memories and the devices display are the modules that consume most of the power resources. In an attempt to provide solutions against the increasing energy demands, various power managements techniques are proposed. Among them the most well known is the voltage and frequency scaling techniques. KeywordsPower Consumption, Design Techniques, VLSI. Wireless Networks,

I. INTRODUCTION Until recently, the expectations of mobile phone users were focused on one and only capability: achieving voicecall functionalities. Since then, however, wireless technology has experienced such a tremendous growth that managed to change the whole telecommunications scenery. Right off the shelf cellular devices support new enhanced features and applications, almost comparable to those offered by desktop computers. From web browsing, Global Positioning System (GPS), to audio and image processing, new generations wireless phones have been transformed to outstanding multimedia platforms. Unfortunately, all these features can be supported only by high performing processors and efficient design schemes that push the power requirements to prohibitive values. Power consumption is a major constraint when designing wireless devices. This is because the latter do not have the privilege of a continuous power supply, but they draw current from batteries, that offer a limited amount of energy. Especially in mobile phones, where the size and the weight put additional specifications limits, the use of heavy and large battery packs is inappropriate. The limited battery lifetime is always a bottleneck for the development of improved portable electronic products. Although, battery technology has been improved over the years, it definitely has not kept up with the advances in other technological fields. Therefore, it is left on the hands of other scientific fields to find solutions where battery technology seems to have failed. Indeed, the last decade an intense research in various areas has been focused on minimizing the power consumption of wireless platforms. In this paper, power issues in 3G mobile phones are investigated from the system level point of view. The

Fig. 1. Multi-core architecture of 3G cellular systems

The IEEE Region 8, EUROCON 2007, International Conference on "Computer as a Tool" (IEEE EUROCON'07), Warsaw, Poland, September 9-12, 2007.

A typical 3G cellular system consists of four basic subblocks: The RF Unit that focuses on protocol stack and modem processing operations. A Network Unit that provides connection to various networks, e.g. Bluetooth and WLAN, broadcasting functionalities and location-based services (GPS). The Application & Control Unit that implements multi-media streaming and control specific functions. A Power Management Unit, designated to power control mechanisms and battery related functionalities. Also, the system architecture contains: external memories for program and data storage, communications infrastructure meaning the camera and the display. Other input/output peripherals such as keypad, microphone and speakers are also included. The study of the power consumption in portable phones would require a first estimation of the power loss at this top level. In Figure 2, a graphical representation of the power consumption of the subsystems is given [2] :
Power consumption distribution 45.0% 40.0% 35.0% 30.0% 25.0% 20.0% 15.0% 10.0% 5.0% 0.0%
1 2 3 Subsystems 4 5

the application unit incorporates two processors. A general purpose RISC processor (Reduced Instruction Set Computer) designated to the control specific functions and a Digital Signal Processor (DSP), that implements signal processing algorithms [1], [5]. The structure of the application unit is illustrated also in the next Figure 3.

Fig. 3. Structure of the Application and Control Unit

Applications

Cellular

Memory Display

Others

Fig. 2. Power distribution in 3G cellular systems.

It is clearly defined that the most power consuming subsystem is the application engine, with 40% of the energy spent on audio and video processing operations. The RF subsystem comes immediately after, where a significant power loss occurs during modem/cellular applications. Also, the memories seem to be an important consuming module by utilizing the 20% of the total available power. Moreover, the display of the device has high energy needs, demanding around 17.5% of the systems power resources. Finally, the lowest energy requirements are imposed by the remaining units, peripherals and other I/Os devices. III. DEALING WITH POWER CONSUMPTION ISSUES A. Application and Control Unit As the name implies, this unit has two distinct missions. The first handles all multi-media operations and user interfaces. In this unit, tasks like image processing, compression and audio/video coders are implemented. The second responsibility of the unit includes the control of all other modules and the establishment of every possible connection, i.e. among the units and the devices peripherals. In order to accomplish both functionalities,

As it is shown, the RISC processor is an ARM microcontroller usually connected to instruction and data caches for quick memory access. On the other side the DSP is connected to a set of dedicated audio converters in order to support audio functionalities including speech recognition, noise reduction and echo cancellation. For video related tasks, the DSP communicates with power 3D accelerators, to deliver outstanding media capabilities and high quality images. The two processors are connected to a ROM for the systems booting, a SRAM, an interrupt controller and several timers. Since, different types of external memories can be attached to wireless devices, e.g. NOR flash, SDRAM, a memory controller is needed. The latter is often supported by a direct memory access unit (DMA). Finally, a crypto-processor is included to implement different cryptographic algorithms and ensure data protection and secure network access. Inside the application and control unit the components with high power dissipation are the CPUs of the ARM and the DSP, the internal buses, the caches and other logic units. CPU: The power consumption in the CPU is related to the power loss during the execution of an instruction [7]. In most of the architectures, instructions are executed in five stages, i.e. fetch, decode, execute, memory, write back. The total power consumption per instruction, is calculated by the dissipation in each one of the executing stages. Therefore, the smaller the amount of code fetched from the memory or the fewer the read/write data operations, the less the power dissipation [7]. Interconnection Buses: In a multicore architecture, interconnecting links must be provided to make possible the communication between the different processors and the memory. The communications channels are implemented using buses, multiplexers and drivers. Thus, a considerable amount of power is drained by the high capacitance of the additional hardware [7].

The IEEE Region 8, EUROCON 2007, International Conference on "Computer as a Tool" (IEEE EUROCON'07), Warsaw, Poland, September 9-12, 2007.

Additional Units: For the implementation of algebraic operations, the use of arithmetic and logic units (ALUs), shifters and multipliers is essential. Also, architectural design techniques such as pipelining, or loop unrolling often demand the placement of additional registers and control modules in the system. Of course the additional hardware increase the power dissipation. B. RF Subsystem The RF sybsystem is responsible for the data transportation related operations. The components that have remained from first generations mobile phones, i.e. the digital and analog baseband chip are included in this module. The digital baseband chip, designed to support all 3G protocol standards (GSM, GPRS and UMTS), is placed around an efficient DSP. The latter is needed to implement all layer 1 signal processing algorithms, such as Viterbi Decoders, Autocorrelators and Turbo Coders. The analog baseband chip of the cellular unit deals with signals transmission and reception issues. Using amplifiers, baseband filters, data converters and an antenna, this subsystem manage to provide all voiceband, mixed-signal and power control functionalities. Inside the cellular subsystem, the most power consuming modules are the CPU of the DSP, from the digital baseband side and the RF part from the analog side [9]. In the analog subblock, power is dissipated during communication related operations, i.e. signal transmission and reception. Different modes of operation such as standby, talking, ringing or calling push the energy requirements at different levels. For example, the power dissipation is higher during talk than standby mode. This happens because in order to transmit the signal from the mobile terminal to the base station during a call, the power amplifier spends significant energy resources [9]. C. Memories & Caches In memories, power loss can be either static or dynamic. Static power loss is caused by current leakage, whereas the dynamic one occurs on each to program or data memory access. As already mentioned, the energy dissipation is proportional to the amount of data or code being transferred. Therefore, data compression and code optimization techniques that eliminate the frequency of memory accesses can reduce the power loss [7]. The smaller the memory space and the closer to the processor, the less the power consumed during an access [7]. That is the purpose of the two caches connected to the ARM processor. However, caches come along with an additional power impact. Calculating the caches contribution in the power consumption is quite tricky. A lot of parameters need to be taken account such as the size and configuration of the cache, the associability, word line and index size and the switching bus activity. D. Liquid Crystal Displays Liquid Crystal Displays (LCD) and display backlights account for important energy overheads in batteryoperated device. How much are the overheads depend on

the size of the display, the technology and the use or lack of colors. For example, bigger or brighter screens result in more power consumption when compared to screens of lower quality. Also, the architecture of the display can determine the energy loss. Displays with internal memory, for example, seem to spend less battery resources [9]. This is due to the fact that the internal memory can store the display content temporarily minimizing the accesses to external memories and thus, the power consumption. IV. POWER REDUCTION MECHANISMS With power consumption being so critical in wireless devices, it no surprising why so much research has been focused on power management techniques. Since the three most important contributors in the power loss is the CPU, the memory and the display, the employed techniques involve mostly these subsystems. A. Low Power Processors In order to minimize the power loss in the CPU in the power consumption, power efficient processors need to be used. The ARM and DSP are example of such processors that eliminate the power loss by decreasing the frequency of bus transfers and memory accesses. ARM: For example, the Cortex A8, which is the latest ARM processor planned to be used in future platforms uses [6]: A 13-stage pipeline with efficient branch predictor to minimize the penalties associated with deep pipelines. Two level caches of various configured size with Hash Virtual Address Buffer (HVAB) prediction. This feature activates the memory only when it is needed and thus, reduces power consumption. 32 bit data and instruction set + Thumb extension. The Thumb extension set improves code density by compressing common 32-bit instructions into 16-bit operation codes [3], [6]. During the execution, the Thumb translates the codes by expanding the instructions into the expected 32-bit format in real time. This technique reduces the amount of code by 30% and therefore, increases the power saving. DSP: An example of a power efficient DSP, often combined to an ARM processor on a single-chip, is the TMS320C55x. This DSP focuses on a reduction of power dissipation [5]: Efficient buses that perform up to three data reads and two data writes in a single cycle. An increased parallelism by using two multiplyaccumulate units (MAC) and two ALUs that execute instructions in parallel. One 24 kb instruction cache to minimize external memory accesses, improving data throughput and conserving system power. Variable byte width instruction set for improved code density.

The IEEE Region 8, EUROCON 2007, International Conference on "Computer as a Tool" (IEEE EUROCON'07), Warsaw, Poland, September 9-12, 2007.

B. Energy Efficient Memory Schemes Memory Hierarchy: With an efficient memory hierarchy, significant power savings can be achieved. A frequently used scheme takes advantage of both the concept of locality and that of the memory split. It suggests the partition of the memory in more blocks, with the smaller one being placed closer to the execution units [7]. The access to these blocks is significantly faster and less power consuming. Thus, saving frequently used code or data in these memory blocks, great power savings can be accomplished. The concept of memory hierarchy is shown in Figure 4. The partition of the memory can be further used to minimize the power loss. Careful studies of algorithms revealed that most of the time, fetches hit within a small memory area. Therefore, the power consumption can be decreased by activating only the block currently used and shutting down the rest. Mobile/Cellular Memories: In addition, advances in memory technology have resulted in the development of a new range of memories such as CellularRAM and MobileRAM. These have been designated for wireless, battery operating devices. CellularRAM is actually a pseudo SRAM, that permits self-refresh and recharged operations inherent in DRAM technology. It also provides lower standby and operating currents that have an impact on total power consumption [8]. MobileRAM reduces the core voltage and the standby current while introducing a key new low-power feature called on-chip temperature sensor (OCTS) [8]. This feature by sensing the temperature chooses the most efficient, in terms of power, memory refresh rate. C. Power Control Techniques for Displays In order to reduce the power consumed by the display, the use of energy adaptive LCD systems has been proposed [4]. This technique suggests the trade off between quality and power consumption. Depending on the application requirements and users demands, a reduction of brightness or size of the display, may be done for shake of power efficiency. This approach is further motivated by research results that showed that the window of focus, meaning the users area of interest utilizes only 60% of the total screen area [4]. Based on these observations, techniques that modify the clarity of the image and color depth of the non-active screen areas are often used, while leaving the active screen area unchanged. D. Power Management Unit Gating Clock: In order to reduce the overall systems power consumption, a commonly employed technique is the gating clock [7], [3]. This method disables the clock of subsystems or modules whenever they are not in use. This approach, of course, implies the grouping of functions in different clock domains and the use of appropriate software, through which the reduction or suspension of the selected clocks can be accomplished. Voltage and Frequency scaling: The dynamic voltage and frequency scaling technique (DVFS) takes advantage the relation of power, voltage and frequency to achieve

power savings. Power consumption is proportional to the operating voltage and frequency according to the following equation:

Pd = aC eff V

Hence, scaling down the voltage supply and the clock frequency can result in a decrease of the systems power dissipation

[9], [7], [3]. Based on this idea, the DVFS method changes dynamically the voltage and frequency according to the performance requirements of the running application. In order to support the DVFS technique, 3G mobile phones have multiple on chip voltage domains, asynchronous interfaces and variable-frequency clock generators. This allows different values of voltage and frequency, among the various processors and peripherals. V. CONCLUSIONS & OUTLOOK As wireless communications industry is growing, users demands for new enhanced features and long battery life are increasing. Hence, power has become the first class design constraint, when comes to rich multimedia portable devices. These factors cause such an intense research around power management techniques, for mobile devices. Different scientific fields investigate the energy dissipation at a different level. A system-level approach focuses on the power consumption of the CPUs, memories, buses or the display of the device. ACKNOWLEDGMENT This wok has been supported by the State Scholarships Foundation (IKY), under the Program of Scholarships for Post Doc Research. REFERENCES
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