ECEN 665 Edgar Snchez-Sinencio

Mixer
A1 Mixer Output A2

Analog and Mixed-Signal Center, TAMU

What Devices Perform Frequency Translation?

Linear, time-invariant systems can not generate spectral component not present in the input. Mixer must be non-linear or time-variant system. Historically, a lot of devices are being tried as mixers: electrolytic cells, magnetic ribbons, brain tissues, rusty scissors, vacuum tubes and transistors. Virtually any nonlinear elements can be used as mixer. Some nonlinearities work better and more practical.

Most mixer implementations use some kind of multiplication of two signals in time domain: RFLO IFLO IF (down conversion) RF (up conversion)
A1 Mixer Output

Mathematical Model

A2

( A1 cos 1t ) ( A2 cos 2t ) =

A1 A2 AA cos(1 2 )t + 1 2 cos(1 + 2 )t 2 2

Up conversion filters out 1- 2 component. Down conversion filter out 1+ 2 component.

Mixer Metrics Mixer Metrics

In order to evaluate the performance of mixers, several metrics are defined: Conversion gain/loss Noise figure Port isolations Linearity Power consumption

Mixer Metrics (contd)

Conversion Gain Conversion gain or loss is the ratio of the desired IF output (voltage or power) to the RF input signal value ( voltage or power). More specifically:
Voltage Conversion Gain = r.m.s. voltage of the IF signal r.m.s. voltage of the RF signal

IF power delivered to the load Power Conversion Gain =Gc = Available power from the source

The power gain definition is actually transducer power gain.

Mixer Metrics (contd)

Double side-band (DSB)
Desired Signal

Mixers noise figure

2S i G
RF IF

Si Ni
f RF1 f LO

Si
f RF2

no

2N i G
LO

FDSB

IF

N no =1+ 2 N iG

Single side-band (SSB)

Desired Signal

SiG
RF IF

FSSB = 2 +
2N i G

Si Ni
f RF1 f LO f RF2

no

FSSB = 2 FDSB
FSSB = FSSB +

N no N iG

LO

IF

Single side-band with image rejection filtering

Desired Signal
RF IF

SiG

Ni

Si
f RF1 f LO f RF2

no

FSSB < 2 FDSB

f
IF

Gim 1 G

LO

N i G(1+Gim)

Where Nno, Ni, and G are the output noise power, the input noise power, and the gain of the system, respectively.

Mixer Metrics (contd)

Port isolation
LO-to-RF leakage, which will mix with LO again, causes self-mixing problem in direct conversion. Due to the nonzero reverse gain of LNA, the LO leakage may even reach the antenna through the LNA LO-to-IF feed through may cause desensitization of the blocks following the mixer. (recall that the LO power is usually greater than that of the desired IF signal.) RF-to-LO feed through allows interferers and spurs present in the RF signal interact with the LO. RF-to-IF feed through may cause problems in direct conversion architecture due to the low-frequency evenorder inter-modulation product.
RF IF

LO

RF

IF

LO

RF

FILTER

FILTER

IF

FILTER LO

A diode mixer concept

RS

Equivalent Circuit Cd(V)

Mixer Topologies
Discrete implementations: Single-diode and diode-ring mixers Schottky barrier diode is preferred to regular diode due to its low junction capacitance and low series resistor IC implementations: MOSFET passive mixer Gilbert-cell based mixer Harmonic mixer

Passive mixer topologies Single-diode:

VIN
L C R

VOUT

CMOS Passive Mixer

C1 L1

Single-balanced:
RS/2
LO IF RF

L3 RG

LO C3

M1

VRF RS/2

VIF CL

M2

LO

Double-balanced:
LO

L4

LO

M3

M4

LO

C2
IF

L2

RF

SSB noise figure of a mixer is 3 dB higher than the DSB noise figure if the signal and image bands experience equal gains at the RF port of a mixer.

multipliers.ppt

Multipliers
What is a multiplier?

x
Z = Kxy y Where x and y are the input signals, Z is the output and K is a constant with suitable dimensions.

How do you obtain a multiplier?

Nonlinear Device i.e.,
2 i0 = avi + bvi

v1 ( t ) vi ( t ) v ( t ) 2

Nonlinearity cancellation scheme

i 0 = kv1 ( t ) v 2 ( t )

+ cv3 + i

Fig. 1 Basic idea of multiplier

Transconductance-Mode Multiplier
v1 G m1 v1 G m1

v1 G m1

i 0 = k1v1v 2 + k 2 v1

i0

i0 I bias1
v2 G m2 i2

I bias1

I bias1

(a)

i2

(b)
G m1 v2 G m2 i2 v1

(c)

I bias 2

G m1

v1

I bias1

i 0 = k1v1v 2
v2 G m2

I bias1
i2 i2 I bias1

i 0 = 2k1v1v 2

I bias 2
G m1 v1

I bias 2

G m1

(d)

I bias1

(e)

Fig. 2 Multiplication operation using programmable transconductor

How Does It Work?

i 0 = G m1v1 where G m1 = G m1 (I bias1 ) For a bipolar transconductor, G m1 becomes I G m1 = bias1 2Vt + G m2 v 2 (t) I i 0 ( t ) = G m1v1 = bias1 v1 ( t ) 2Vt i0 (t) = I v ( t ) v 2 ( t ) I bias1v1 ( t ) G m 2 v1 ( t ) v 2 ( t ) I bias1 v1 ( t ) = bias 2 1 + + 2Vt 2Vt 2Vt 2Vt 2Vt

(1) (2a)

(2b) (3a) (3b)

or i 0 ( t ) = k1v1 ( t ) v 2 ( t ) + k 2 v1 ( t ) Thus , i 0 ( t ) represents the multiplication of two signals v1 ( t ) and v 2 ( t ) , and an unwanted component , k 2 v1 ( t ) . This component can be eliminated as shown in Fig . 2(d) . Better cancellation is achieved when the third transconductor (G m2 ) becomes a fully differential transconductor , and v1 and v 2 are fully differential inputs as illustrated in Fig . 2(e). i 0 ( t ) = 2k1v1 ( t ) v 2 ( t )

(3c)

(4)

ACTIVE MIXER
io = k1v1v2

For a mixer, the variables for the multiplier become io = iIF (t ) k1 = Go v1 = vRF (t ) v2 = f (vLO (t )) Thus
iIF (t ) = vRF (t )Go f [vLO (t )] ; vLO (t ) = ALO cos LOt
1

f ()

m
V
LO

+ LO

vLO (t )

A Sigmoidal Function

We have two important cases:

+ 1 for vLO > VLO 0 for vLO < VLO f (VLO (t )) = - - - - - - - - - - - - - - - - v LO (t ) VLO + or m vLO (t ) for VLO < vLO (t ) < VLO + VLO VLO

+ Assume ALO < VLO , VLO

then

iIF (t ) = vRF (t )Go ALO cos LOt

iIF (t ) = Go ALO ARF cos RF t cos LOt iIF (t ) =

For vRF (t ) = ARF cos RF t , iIF (t ) yields

Go ALO ARF {cos(RF LO )t + cos(RF + LO )t} 2 After filtering (RF + LO ) ; Go ALO 2

iIF = GC ARF cos(RF LO )t ; GC =

This case corresponds to a multiplier where iIF (t) is a function of ALO The conversion gain is given by

Pout ( = IF ) . Pin ( = RF )

For this case, the maximum output noise occurs in comparison of large driving ALO. That is the case to be discussed next.

Now let us focus on the case of large ALO, that is

+ ALO > VLO , V LO + 1 for vLO (t ) > VLO f (v LO (t )) = 0 ( 1) for vLO (t ) < VLO

and recall

vRF vRF
+1 -1

RF

vLO

4
LO

14 3
3LO

1 4 5
5LO

LO - RF LO + RF 3 LO RF 5LO RFc

Time-Domain

To handle mathematically the product vRF(t) vLO(t) we resort to fourier series to express vLO(t) and its product with vRF(t). 4 F [vLO (t )] = Then 1 sin n ot n =1,3 ,5 ,L n

4 4 iIF (t ) = Go vRF (t )v LO (t ) = Go ARF cos RF t sin LO t + sin 3 LO t + 3 4 4 sin 5 LO t + sin 7 LO t + L 5 7 Let us focus on the term
G A 41 4 [sin(LO + RF )t + sin(RF LO )t ] Go ARF cos RPt sin LOt = o RF 2

Using a suitable filter one can, ideally, end with

iIF (t )

2Go ARF 2G A sin(RF LO )t = o RF sin IF t 2G GC = o

VDD RL IIF v+ LO vRF IRF M3 vLO VDD

MIXER IMPLEMENTATIONS
vIF (t ) = iIF (t )RL n sin 1 2 cos n t vIF (t ) = ARF cos RF t Go + o 2 n =1 n 2
Undesirable vRF(t) feedthrough.

GC =

1 1 (g m3 RL )

Unbalanced Mixer (see Figs 2(b) & (c))

VDD
+ iIF

VDD
iIP

vIF (t ) = ARF cos RF t 2Go

vLO

sin

n =1

+ vLO

n 2 cos n t o n 2

iIF vRF

No even harmonics Undesirable vLO(t) feedthourgh

Single Balanced Mixer (see Fig 2(d))

VDD
R
LO

+ iIF

VDD
iIF

R
LO vLO vLO

iIF1 M1 M1 v
+ LO

M2 M2

+ vLO vRF

+ RF

M3

M3

I SS

v 4g R GC = m 3 L C MOS Version

RF

+ vRF

RE

RE I EE VEE

vIP 3

R +r = 4 2 vT E e r e BJT Version

32

Double Balanced Mixer The conversion gain with a differential load CL is GV = Ideal Square Wave Mixing GV = Non-Ideal Mixing Functions 2 gm R 1 + s 2 RCL 2 g m R sin(tr T ) 1 + s 2 RCL (tr T )

Bulk-Driven Mixer
RL + vRF + RL

Pluses Low Power Consumption Low Power Supply Good Conversion Gain NF Reasonable Acceptable IIP3 (poor) Minus High ALO (power) Low Gain Compression
RL
vLO

+ LO

vRF

LO

+ vRF

I bias

RL vRF vLO vRF vLO I SS

RL vRF vLO v
+ RF
v lo

RL
+ vLO

Rs 2

Rs 2 Ls

Ls L

vRF

Minimum SupplyHeadroom DB Mixer

A Possible Floating Gate Mixer

Distortion, Low Frequency Analysis of MOS Gilbert Mixer

It can be proved that one can express
I SS n 2 2 3 (a1vRF + a2vRF + a3vRF + L) + 1 I 2 vRF (t ) = 2 I SS n 8 SS n 2I 2 I SS I SS n = SS = k o cox(W L )
I SS n 2 1 2 ; a2 = 0 ; a3 = 8 I SS n 3 a1
2

2 3 (a1vRF + a2vRF + a3vRF + L)

3

Solving for these coefficients, it can be obtained the following:

a12 = Thus HD3 = 1 a3 2 1 o cox(W L )3 2 ARF = ARF I SS 4 a1 32

IM 3 = 3HD3 Assuming we are interested that the amplitude of the inteference can be denoted as AINT. Then
2 3 AINT IM 3 = 2 32(VGS3 VT )

Furthermore, it can be shown that

2 AINT IM 3 = 2 AIP 3

then A
2 IP 3

2 2 AINT 32(VGS3 VT ) Aint erference 32 2 = = = (VGS3 Vt ) 2 IM 3 3 Aint erference 3 2

Example
VGS3 VT = 0.4V , ARF = AINT = 0.212V p or

3.472 dBm

Assuming the vLO(t) is not large enough to force switching. Then

2 3 AINT IM 3 = 31.6dB 2 32(VGS3 VT )

AIP 3 = 1.3064V p = 2 1.3064 0.3536 Vrms IIP3 = Pi dBm

dBm

IM 31dB = 3.472 + 15.8 = 12.33dBm 2

Mixer Noise
vLO not switching case LO switches behave like a regular Differential pair Maximum output noise contribution Noise factor for a mixer is given by
F= N o ( source ) (IF ) N o tot (IF )

VLO switching case LO switches behave like a Cascode transistor Minimal output noise contribution.

where N o ( source ) DSB = N o ( source )SSB + 3dB and NFDSB NFSSB 3dB

TYPICAL BJT MIXER NOISE AT VARIOUS vLO LEVELS

Output Noise 10 8 Top Transistors 6 Total

Bottom Transistors

2 -0.1 0 0.1

Source resistance vLO (instantaneous)

s/n around vLO = 0 is very poor (gain is also low)

A Popular mixer topology: IC implementation

Gilbert-Cell based mixer
IF

Single or Double-balanced mixer

Good LO-IF isolation (40dB~60dB)

LO
M3 M4 M5 M6

M1, M2 work as V-I converter M3~M6 work as current commuting switches LC tank: zero-headroom Low IF noise figure problem

M1

M2

RF

Transconductance conversion gain:

Gc =

gm

Harmonic mixing: Bipolar implementation

VCC IF

Sub-harmonic mixer
RL

RL

RF LO

RF

Two emitter-coupled BJT pairs work as two limiters. The small RF signal will modulate the zero crossing point of the relatively large LO signal.

Design Considerations for Gilbert-cell Mixer

Load noise V-I converter noise whit noise: up/down conversion flicker noise: up conversion Switch pair noise High frequency noise of switches or coming together with LO signal flicker noise modulates switching point Charging and discharging the parasitic capacitance at the commonsource of differential pair makes flicker noise appearing at output
H. Darabi, A.A. Abidi, Noise in RF-CMOS mixers: a simple physical model, IEEE JSSC Vol. 35 Issue: 1 , Jan. 2000 pp. 15 -25

Noise contributions

Design Considerations for Gilbert-cell Mixer (contd)

Linearity
V-I converter The arguments of LNA linearity apply here Switch pair Low frequency: higher LO swing better linearity High frequency: Optimal LO swing
M. T. Terrovitis, R. G. Meyer, Intermodulation distortion in current-commutating CMOS mixers, IEEE JSSC, Vol. 35 Issue 10 , Oct. 2000 pp. 1461 -1473

Mixer topologies for Narrowband Applications

Discrete implementations: Single-diode and diode-ring mixers IC implementations: MOSFET passive mixer Gilbert-cell based mixer Harmonic mixer

Diode Mixers
Singlediode:
VIN
L C R

Singlebalanced:
VOUT
LO IF RF

Double-balanced:
LO IF

RF

The single-diode mixer is the simplest and oldest passive mixer. The output RLC tank is tuned to the desired IF, and input is the sum of RF, LO and DC bias.This mixer can not provide any isolation and conversion gain. However, at very high frequency (millimeterwave band) this kind of mixer is extremely useful.

LO is large enough to make the diodes work as switches, regardless of the level of RF signal. When the diodes are on, RF and IF are connected together, so the RF-IF isolation is poor. But the RF signal is commonmode for the transformer, so the RFLO isolation is excellent.

Due to the symmetry of the circuit, isolations between each pair of ports are excellent, mainly limited by the device matching. The diode mixer is pretty much linear and the upper limit of the dynamic range is constrained by diode break-down. Typically, double-balanced mixers can achieve conversion loss of around 6dB, isolation of at least 30dB.

CMOS Passive Mixer

Input LC network provide matching and filtering. R1 sets the input common-mode level.
C L
1 1

RS/ 2 VR
F

L RG3 L
4

L O C
3

M
1

VI
F

M
2

RS/ 2 C L
2 2

C L O M
3 L

M
4

Due to the matching network, voltage L conversion gain can O be greater than 1. Noise figure and IIP3 L are strong functions O of LO drive level.

MOSFET M1~M4 are working as switches and are driven by LO in anti-phase. Only one diagonal pair of transistors is conducting at any given time. When M1 and M4 are on, VIF equals VRF, and when M2 and M3 are on, VIF equals VRF. So it is equivalent to observe that the mixer multiplies the RF signal by square wave whose amplitude is alternating between +1 and 1 and whose frequency is that of LO.

Gilbert-Cell Based Mixer

IF

L O R F

M3 M4

M5 M6

M1

M2

This is a double-balanced mixer. Good LO-IF isolation (40dB~60dB) can be achieved due to the symmetry. M1 and M2 work as V-I converter and M3~M6 are driven by large enough LO, working as current commuting switches. LC tank is to create zero-headroom AC current source. If the power supply voltage is not a limitation factor, the LC tank can be replace with a transistor working as current source.

The linearity of the mixer is limited by the Transconductance conversion linearity of the V-I converter. For low IF, the 2 gain: Gc = g m noise figure is limited by the flicker noise of the current switches and for higher IF, the Additional linearization techniques can be applied to improve the linearity noise figure is limited by the thermal noise of of the mixer. the circuit.

Sub-sampling Mixer
2
VC

M6 M3 M4 M5
IF

3
RF

1_ M
b

M1 M2 3

1 1_
b

The sampler must have good time resolution. So the clocks absolute time jitter must be a tiny fraction of the carrier period. Noise folding make the mixer present large noise figure. The linearity of the mixer is high

VC
M

M7 2

Properly designed track-andhold circuit works as subsampling mixer

Harmonic Mixer (I)

Harmonic mixer has low self-mixing DC offset. It is very attractive for direct conversion application. The RF single will mix with the second harmonic of the LO. So the LO can run at half rate, which make the VCO design easier. Because of the harmonic mixing, conversion gain is usually small (several

Harmonic Mixer (II)

VCC R
L

IF

R
L

R F

L O

R F

Two emitter-coupled BJT pairs work as two limiters. The odd symmetry of their transfer function suppress even order distortion including LO selfmixing. The small RF signal will modulate the zero crossing point of the relatively large LO signal. The output of the mixer is rectangular wave in the pulse width modulation fashion, a low pass filter will demodulate the

Harmonic Mixer (III)

Simulated waveforms of the harmonic mixer:

IF @ 100kHz

LO @ 1GHz RF @ 2GHz+100kHz

A Bulk-Driven, Gate-Driven, Multiplier

Calculate the input impedance looking at the bulk, and the output voltage Vo expression of the simple bulk-driven amplifier. Note that the circuit has two small signal input signals. Vin1 is injected to the bulk and Vin 2 to the gate. Also determine an expression for iD .

VD

For low frequency

Vbias 2
iD

M2 Vo M1 Vin1

Z in

= @ bulk

For high frequency

Vbias 1 + Vin 2

= Z in

g mb1

1 + g 01 + g 02

@ bulk

The drain current containing the DC and small signal is

1 w id = K p vGS VTD + 1 2 f 2 l

])]2

w 1 iD = K p vin2 + Vbias1 VTD 2 F vin1 + 2 F 1 L 2

We will use the following approximation for the square root containing Vin1 by means of a Taylor Series:
ax a x 2 a +L
; a = 2 F & x = vin1

w 1 vin1 iD = Kp vbias1 VTo + 2 F + vin 2 2 F + L 2 2 2 f

( (

w 1 vin1 iD = Kp vbias1 VTo + vin 2 + L 2 2 2 F iD = I D + id

w 1 = Kp vbias1 VTo L 2

[(

)2 + L] )

w 2 1 vin1vin 2 2 2 vin1 + iD = Kp vin2 + v + vbias1 VTo vin2 + 2 vbias1 VTo L 2 2 F 2 2 F F in1 vin1 vin2 2 2 w Vbias1 VTo 1 2 + id = Kp vin1 + 2 Vbias1 VTo vin2 + v +v L 2 2 F 2 F F in1 in2

2 2 id = a1vin1 + a2vin 2 + aM vin1vin 2 + a3vin1 + a4vin 2

Simulation Results

Vin1: Constant Input, Vin2: 20KHz Sine Input

Simulation Results

Vin1, Vin2 are sine signal with same frequency

Simulation Bulk-Driven Multiplier Results

Vin1: 18KHz, Vin2: 20KHz sine wave, Vout: Modulated Output

RF Front-end for Bluetooth Low IF Receiver

Vdd

LNA

Voltage Gain: 18dB Noise Figure:2.6dB IIP3: 0dBm

Vin+

Ldd Vo Vb M2

Ldd

M2

Vb

Lg

M1 Ls

M1 Ls

Lg

Vin-

Current: 4.4mA Gate NQS resistance Rgs=1/5gm Supply: 3V Gat induced noise modeled by gate NQS resistance Vg2 = 4kTRgs

RF Front-end for Bluetooth Low IF Receiver

Mixer
VDD

Double balanced mixer Current injection to alleviate the trade off between the linearity and power supply voltage Voltage conversion gain: 26dB Noise figure: 12.4dB IIP3: -3dBm
RF+

IF+

IF-

LO-

LO+

LO+

P A D

P A D

VGA

RF-

P A D VGB

P A D

RF Front-end for Bluetooth Low IF Receiver

Mixer layout considerations
The length of the poly gate should be kept short enough to reduce the effect of gate resistance For the layout of poly-poly capacitor, if the bottom plate is floating, the parasitic capacitance from it to substrate should be considered. It is about of the nominal capacitance. De-coupling capacitor may be needed to prevent the circuits from oscillation Metal should be wide enough to carry large current. The current density allowed through metal is about 1mA/1m Guarding rings are required around the circuits to provide isolation from other blocks

Front-end for BT/WiFi Receiver

LNA

Differential structure MOS transistor is more linear Inductor degeneration

Vin+

VDD Ld Ld

Vo+ Vo-

LNA_cas_bias

Cascoded BJT: better matching On-chip input matching Noise figure: 1.6dB Power/Voltage gain: 13dB Power consumption: 16mW NMOS attenuator for low gain(3dB)
LNA_rf_bias VinLs Ls

Cm

LNA_bypass LNA bypass switches and attenuator

i_tail

Front-end for BT/WiFi Receiver

LNA simulation results

Sparameters

Noise figure

1dB compression point

IIP3

Front-end for BT/WiFi Receiver

LNA Layout

Symmetrical layout Deep trench lattice under spiral inductor Inductors are placed far apart to avoid coupling Differential inputs are decoupled by GSGSG pattern
580um

3n H

1n H 570um

Front-end for BT/WiFi Receiver

I/Q Mixer
Fully-differential structure to suppress common-mode noise I/Q branches share the same RF drive stage to achieve better matching between I and Q Bipolar current switches requires low LO drive power (10dBm)
RF_in LO_bias VDD IFI IFQ

LO_bias

imix_bias

LOI

LOQ

Resistive loads have higher linearity and lower low-frequency noise compared to PMOS active load.

IIP3: 2dBm NF: 10.6dB Gain: 18.5dB Power: 8.8mW

Front-end for BT/WiFi Receiver

I/Q Mixer Simulation Results Conversion Gain Noise Figure

IIP3

Front-end for BT/WiFi Receiver

I/Q Mixer Layout

180um

130um

Front-end for BT/WiFi Receiver

Biasing Circuits for the Front-end 2m A 410u A 12.8u A

1.6 2.2 V V 1.4 V

Front-end for BT/WiFi Receiver

Performance of the front-end Overall Gain Noise Figure

LO drive: -10dBm Noise Figure: 5.5dB Overall gain: 33dB P 38 3 W

Front-end for BT/WiFi Receiver

I/Q mismatch: amplitude 2.3% phase 1.7 degrees S11: High gain mode

1dB compression

S11: Low gain mode

Circuit Implementation --- Merged LNA and Mixer (An alternative way)
VDD

Power: 28.5mW Noise Figure: 3.6dB Gain: 33.4dB

IFQ

IFI

VB_LO

VB_LO

Inter stage matching Inductive degeneration Current re-use

LOI

LOQ
VB_CAS

VB_RF

RF_IN

Low power consumption

Simulation Results --- Merged LNA and Mixer

S11 Gain

Noise Figure

References 1. B. Leung, VLSI for Wireless Communication, Prentice Hall Upple Saddle, NJ 2002, Chapter 4 2. T. Lee , The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edition, Cambride University Press 2004, Chapter 13 3. B. Razavi, RF Microelectronics., Prentice Hall Upple Saddle, NJ 1998, Chapter 6.2 4. G. Han, E. Sanchez-Sinencio, CMOS transconductance multipliers: a tutorial , IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , Volume: 45, Issue: 12 , pp. 1550 1563, Dec 1998