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The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability. This paper provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level array package methodologies. The focus of the IPC document is to provide useful and practical information to those who are considering the adoption of bare die or die size array components.
The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability. This paper provides a comp…