David Bouse Johnny Chen

Introduction
This report is divided into three main sections. The first section is the design and simulation of the transconductance base VCO, the second section is the design and simulation of the emitter coupled multivibrator, and the third section is the appendix (lab 1,3,4,5). We have excluded our lab 2 work from this report, because we utilized the built in frequency function in LTSpice to measure the frequency of our final simulations. Both David Bouse and Johnny Chen were originally working with separate lab partners, but teamed up after both respective partners dropped this course. The implications of this are that some of the graphs will show the names of our previous partners.

Section 1
Design of the Ideal VCO Our strategy for designing this VCO was to begin using ideal gain blocks. With the use of these ideal blocks we were able to calculate the value of the capacitor and the two resistors shown on Figure 1: OTA based VCO on the final project sheet. A simplified version of this figure was created below for reference in this section.

Figure 1 We began by looking at the Schmitt trigger portion of this circuit and calculating values for R1 & R2. The equations used for the following calculations were obtained from [Jaeger; page 765]. Similar calculations were also completed in lab 4 [Appendix C; Homework #2].

David Bouse Johnny Chen

Letting R1 = 2K Therefore: R2 = 18K Next, we calculated a starting value for the capacitor. Using the capacitor equation:

Letting i(t) = 500A C = 250pF With the completion of these calculations, we had values for all of the passive components for the ideal VCO. The next step in our design was to begin the design of the first gain block in the circuit. Design of the Transconductance Block Using an Ideal Current Source In this section we will show the steps taken to design the BJT programmable transconductor block using an ideal current source. Once this block was designed with the ideal current source, we built the current source on the transistor level. The design of the current source will be shown in the next section. The first consideration for our transconductor block was the size of devices to use from the cpi library. We are given access to three sizes of NPNs and three sizes of PNPs to choose from. The relative sizes are 2, 8, & 32. For example the three NPNs we are given are the wn2, wn8, and the wn32. There are two main differences between these devices that needed to be discussed in order to understand which transistor was appropriate to use in each block of this design. Real Estate Consideration: The numbers 2, 8, & 32 correspond to the Emitter areas for the different devices. Therefore the chip space (Real Estate) for the wn8 is four times the space required for a wn2, and the space required for a wn32 is sixteen times that needed for a wn2. From this consideration, we have chosen to use the smallest possible device for each of our
2

David Bouse Johnny Chen

blocks of this circuit. Wherever possible we have opted to use the wn2s and wp2s to save on IC Real Estate. Current capability Consideration: All six of the BJTs have a limitation of the amount of current they can handle, and this is primarily determined by the size of the emitter area. Therefore the wp8 can handle four times the current of the wp2, the wp32 can handle four times the current of the wp8, and so forth. During the design process we had to keep these current limits in mind. If we were able to achieve our desired current using a wn2 or wp2, then this was the choice, but in situations where the maximum current was not sufficient we moved up to a wn8 or wp8 for example.

Lab 1 Contributions: A considerable amount of knowledge was also gained about the differences of the devices in lab 1 [Appendix A]. We compared results from simulations using the wn2 and wn8.

Figure 2 The circuit in figure 2 was used in lab 1 to compare the DC gain characteristics of the wn2 to that of the wn8 transistor. Now we will look at the two resulting graphs and draw some conclusions from the results.

Figure 3

David Bouse Johnny Chen

Figure 4

Figure 3 is a gummel plot for the wn2 transistor and figure 4 is the same type of graph for the wn8 transistor. These graphs display the gain of the transistor verses the collector current. Maximum Gain for wn2 occurs around 200uA. Maximum Gain for wn8 occurs around 800uA. These results were useful for the final project because they gave us some idea of the relationship between the Gain of the transistors as a function of the collector current. This also gave us a ballpark range of the acceptable currents of two of the devices.

Figure 5 The schematic in figure 5 was used to determine the output characteristics of the wn2.

David Bouse Johnny Chen

Figure 6 Figure 6 shows the resulting graph of the wn2 transistor. This graph gives us an idea of the Vce necessary to achieve our desired currents. We can see that a Vce drop of 2.5V would safely give us a transistor in the Forward-Active region. Since our power supplies is 5V in our gain blocks, we should be able to maintain this voltage across the transistors. With these considerations in mind, we will begin discussing the process taken to design our BJT programmable transconductor block. The general topology for this gain block was taken from Figure 1 in lab 3. However, as discussed above, we began our design with an ideal current source. This topology is a differential pair with an active load.

Figure 7

Figure 7 shows our starting topology. We used 2K resistors in the active load because these were the values used in lab3, and because this value can be easily created by two parallel 4k resistors from the cpi library. Since our current source is set to operate at 500A we opted to begin this design using the wn8s and wp8s. To begin testing this circuit we connected the gain block to an ideal version of the remaining VCO circuit.

David Bouse Johnny Chen

Figure 8 Figure 8 shows our schematic used to test the transconductance gain block in the ideal VCO. As you can see we created a new symbol for the transconductance block that looks similar to the symbol of an op-amp.

Figure 9 Figure 9 shows our output from the schematic above. The frequency was measured quickly using the periods in the graph, and was valued at 0.90461 MHz. This result is approximately 0.1 MHz different than our desired frequency, but is accurate enough for the start of this design. Up to this point we had primarily relied on qualitative results obtained from lab 1 and lab 3 to design this gain block; however, we next began our design of the current source on the transistor level.

Design of the Current Source for the Transconductance Block For our current source, we needed to control the current from a control voltage. To accomplish this, we will use a reference current generation with resistor reference [Jaeger, Figure 16.23].
6

David Bouse Johnny Chen

To create a reference current that is voltage dependent, we input our VCtrl above the resistor. The reference current generated is then described by the equation:

We also addeded another reference current generation in order to obtain the current needed for our center frequency without affecting the current change/voltage needed to obtain our 75 kHz/V. We used the following schematic with R3 representing our load from our transconductor.

Figure 10 For our design, we aimed for a current of 500A with a swing of 37.5A. We first designed our circuit to obtain the correct current swing needed. By solving the following equations and assuming a VBE of 0.7V:

We obtained a value of 26.666k for our resistor. With this value, we have a center current IREF0 of 161.25A. We then computed the value needed at R1 such that an input of 0V at V Ctrl resulted in a current of 500A. We then solved the following equation to obtain our resistor value:
7

David Bouse Johnny Chen

We obtained a value of 12.693k for R1.

Design of the Main Gain Block We began our design by creating a differential pair with an active load. In a similar approach to the design of the transconductance block, we started by using an ideal source, and then later designed the current source on the transistor level. Device choice: Our initial choice for the transistors of this gain block, were the wn2s and wp2s due to the smaller emitter area. We had to verify that the current maximums would not be reached and that the frequency response of these devices was sufficient. From figure 1 in Appendix A, we saw that the wn2 devices should stay in the Forward-Active region since our rails would be at 5V, and the graph shows the active region being from approximately 0.3V and greater. Since we used a 500A current source, we wanted to achieve adequate gain in this current region. From figure 3 in Appendix A, it is clear that the maximum current gain is near this region. Therefore the wn2s and wp2s should work well for this gain block and also minimize the size of our circuit. Main Topology: To begin our design we constructed a bipolar differential amplifier with an active load. The topology from figure 16.37 in Jaeger was used with one slight modification. We added two resistors to the top of the active load in order to limit the current at this point. The added resistors increased the impedance seen from the output looking into the emitter of U2 by a factor of 2k. See figure 11 below.

David Bouse Johnny Chen

Figure 11 Since this topology has been used in both lab 3 & lab4 [Apendix B, C], we conducted very little simulations at this point, and went on to begin designing the output stage. Output Block: We chose to start our design with a standard class-A output block. The topology for this part of the circuit was obtained from figure 15.31 in Jaeger. The main difference is that we used a wn2 instead of the Mosfet shown in the figure. We also began this block with a 500A ideal current source. See the figure 12 below.

Figure 12 Next we checked the offset voltage of this amplifier circuit. The offset voltage is the value of the voltage that must be applied to the signal input to achieve an output voltage of zero. However to check this parameter, we applied 0V to both of the signal inputs and measured the output voltage.

David Bouse Johnny Chen

Figure 13 From figure 9, we can see that the output voltage is approximately 0.814V with 0V applied to the inputs. Since we hoped to achieve an output voltage near 0V, we added a diode connected transistor to our circuit as seen in figure 14.

Figure 14 Again we set both of the input voltages to 0V, and run a transient analysis. The output voltage of this simulation can be seen in figure 15 below.

Figure 15 With the addition of this diode connected transistor on the output stage, our output voltage has dropped from 814mV to 5.94mV, therefore our offset voltage is at . With a sufficient
10

David Bouse Johnny Chen

amount of gain, we will have an adequate offset voltage for our design. We understand the efficiency limitation of this choice for our output stage ( 25%)[Jaeger; pg.1008], but since efficiency is not a consideration for this design, we did implement this design. Next we began to design the current sources for this gain block. Current Source Design: We began the design of the current source using the Wilson topology shown our text [Jaeger, Figure 16.16]. The motivation of this choice was due to the independence from the power supply. However we quickly abandoned this topology when we encountered inconsistencies between our expected current results and our simulated results. Instead, we simplified our current source to be a simple current mirror using wn2 transistors. The topology for this design was taken from figure 16.23 in Jaeger. There is one slight difference between the figure in the text and our design; we connected the resistor to V cc instead of ground. By connecting to Vcc we were able to get our calculations to work out better. The schematic for this design is shown below.

Figure 16 In the schematic you can see the addition of the non-ideal current source, and the use of cpi library resistors. For simplicity we have changed the active load resistors to 4K since this will have little effect on our circuit. Our next step was to calculate the current produced by our current source, simulate our results, and make a comparison. By writing the following voltage equation:

Solving for IREF:

11

David Bouse Johnny Chen

If we were to change the resistor value to 20K:

Since the current doesnt have to be exactly 500A for this gain block, we chose to use the 16K resistor to give us a current near 581 A. We simulated this current source with our circuit to find the simulated value for the current. See figure 17.

Figure 17 There was a slight discrepancy between our hand calculations and the simulated results, but this can be explained by the VBE drop. We assumed VBE = 0.7, but in LTSpice this value was 0.812V. Another reason for this difference is that we assumed that IREF was the same as the current into the differential pair. This current source should be sufficient to continue on with our design. In the next section of this report, we began to test this main gain block to determine if any more changes needed to be made. Testing of the Main Gain Block Now that we had successfully designed our main gain block, we begin verifying the functionality of this circuit with LTSpice simulations.

12

David Bouse Johnny Chen

Figure 18 Figure 18 shows the latest version of the main gain block that we would be verifying in this section of the report. We began by looking at the gain of this circuit. Gain: By running a frequency sweep in LTSpice we were able to simulate the gain of this circuit, and the results are shown below in figure 19.

Figure 19 From the graph of this simulation we found the gain to be 63.28dB. Gain = 63.28dB = 1315.2

13

David Bouse Johnny Chen

Frequency cutoff: We used the same frequency sweep from the gain simulation to calculate the high frequency cutoff. See the graph below.

Figure 20 Since the gain was at 63.28 dB, we find the location where the gain has dropped to approximately 60.28 dB. The frequency at this location is our 3dB cutoff frequency. Fcutoff = 11.735 MHz. Input resistance: To simulate the input resistance of our main gain block, we connected the rails to ground, connected one of the signal inputs to ground, and applied a 1V test source to the other input terminal. See the schematic below.

Figure 21
14

David Bouse Johnny Chen

From this schematic, we ran a transient analysis for 50s and plotted the test voltage over the current through the test voltage, as seen in figure 22 below.

Figure 22 From figure 22 you can see that the input resistance of our gain block is approximately 39.63M. From Table 16.4 in Jaeger, we can see that the input resistance of a A741 is around 2M; therefore, our input resistance should be more than sufficient for this design.

Output Resistance: We used LTSpice to simulate the output resistance of our main gain block. First we connected both of the signal inputs to ground and inserted a test ac current source at the output, as seen in the schematic shown in figure 23.

Figure 23
15

David Bouse Johnny Chen

We found that the rails had to remain powered to accurately measure the output resistance. This can be explained by the dependence of the cpi library devices on the rail voltages. After running an ac analysis and plotting the voltage of the test source over the current, the following graph was created.

Figure 24 From figure 24, it is clear that our output resistance is approximately 629 for a frequency of 1MHz. From table 16.4 in Jaeger, typical values for the A741 output resistance are 75. We would expect to have a higher output resistance on our circuit since we only used a class-A output stage, while the A741 utilizes the more complex class-AB stage. Common Mode Characteristics: We explored the common mode behavior of our circuit using the following schematic, as demonstrated by Paul Van Halen at the ECE 322 Lecture on March 8, 2011.

Figure 25
16

David Bouse Johnny Chen

Figure 26 Seen above is the resulting graph for our common mode characteristics. These results match those generated in lecture closely, and are sufficient to continue on with our design.

Redesign of our Gain Block We decided to use a ground reference above the resistor for our reference current so that it became less dependent on the supply voltage as well as reducing the amount of resistors needed to produce the same amount of current. We also replaced the wn8 transistors with wn2 since we were not running a high amount of current through those transistors, so we felt that wn2s would be sufficient. For the resistors above the PNP transistors, we decided to use a lower resistance value so that a lower voltage drop would occur through the resistors allowing us be closer to the high rail voltage. For these resistors, we chose to use 125 resistors. With this topology and a target current of 500A, the resistor needed at the reference current became

We determined that a resistor value of 8.6k was needed. Since we did not need the current to be exactly 500A, we decided to reduce this amount to 8k. After this adjustment, we noticed that the output voltage when the inputs were grounded increased. To reduce this voltage, we added another diode connected transistor to bring this voltage closer to 0V. With these considerations, we have the following schematic.

17

David Bouse Johnny Chen

Figure 27 Testing of the Redesigned Main Gain Block Now that we have successfully designed our main gain block, we will begin verifying the functionality of this circuit with LTSpice simulations and hand calculations. For our circuit, we calculated our gain by using the formula, . We can calculate our RL by taking the parallel combination of the impedance seen into the collector of transistor U2 and U3. For exact calculations, we would also need to take into consideration the parallel combination of the impedance seen in the base of U5, however this has a much higher impedance and will have minimal effect in our calculation. The impedance seen in U3 is simply r03 with IC3=285.177A and the impedance seen in U2 is calculated to be r02(1+gm2RE) with IC2=290.306A. For these devices, our VA=31.515 and we will use standard room temperature for VT=.02585. Our gain then becomes: ( giving us a gain of 860.976. ) ( ( ))

18

David Bouse Johnny Chen

Figure 28 From the simulation shown above, we see that our gain block has a gain of 890.041 and a -3db cutoff frequency of 14.4544 MHz. We see that having neglected the contribution of the impedance seen into the base of U5 increased our calculated gain was 3.26% lower than our actual gain.

Figure 29 For the simulation above, we used a step response in steps of 1V to determine the voltage needed at the input in order to have a 0V output. We determined that our offset voltage is at 553V.

19

David Bouse Johnny Chen

Figure 30 In the simulation above, we determined that our output impedance to be at 582.122.

Figure 31

From the simulation above, we determined our input impedance to be at 2.95992 M.

20

David Bouse Johnny Chen

Figure 32

The common mode characteristics can be seen in figure 32 above. Initial Test of VCO

Figure 33: Center Frequency

21

David Bouse Johnny Chen

Figure 34: Frequency at VCtrl=1

Figure 35: Frequency at VCtrl=-1

22

David Bouse Johnny Chen

Frequency 0 1 -1

VCtrl 982.281 kHz 982.048 kHz 985.762 kHz

Table 1: Results From our results, we can see that our frequency change does not have a linear relationship with the change in VCtrl. This suggests that one of the transistors may be going into saturation mode. [Appendix C]. To rectify this, we will reduce our capacitor size so that the current required for our center frequency and frequency swing can be reduced as well. We chose to use a 100pF capacitor and will need to modify our current source in the transconductance stage to create the appropriate frequencies. With the 100pF capacitor, we will need a center current of 200A and a change of current of 15A. We also noted that only a portion of the current produced in our current source is being delivered to our capacitor. Because we neglected to take into account the base currents in our transconductor stage and that the opamp will also take in some current, through our measurements we determined that 96% of the produced current is used in the capacitor. With this in consideration, we will need a change of 15.625A and a center current of 208A. Through our calculation, we determined that we will require a resistor R2=64k and R1=30k. With these new values, we obtained the following results.

Figure 36: Center Frequency

23

David Bouse Johnny Chen

Figure 37: Frequency at VCtrl=1V

Figure 38: Frequency at VCtrl = -1V Frequency 0 1 -1 VCtrl 1.244 MHz 1.283 MHz 1.168 MHz

Table 2: Results
24

David Bouse Johnny Chen

We can see that our lower frequency swing has a change of roughly 76kHz, however our upper frequency swing is at 39kHz. We also noted that our center frequency is much higher than what we expected it to be. The current through our capacitor is much higher than what we expected it to be, with the center current being at 250A rather than the 200A we expected. The extra current that we are achieving can be explained in our current mirror. The current that we calculated were for the reference current, however the mirrored current have a factor added. [Appendix D]. For our next test, we will reduce the overall current and test if the upper frequency swing is still limited. The lower current may reduce the voltage drops across the resistors enough where all the transistors will remain in the active mode. We then readjusted our current source so that the center current is at a much lower rate. We also added a few more resistors to R2 to lower our change of frequency. This added resistor will create higher impedance in the node at VCtrl, thus adding 1V to the input will create a lower change in current. We chose to add an additional 2k to R2. For R1, we calculated the current to be at 140A. We will reduce this value by 50A, thus shooting for a value of 90A. We calculated this value to be 46.66k. We decided to use a 46k resistor because there was some current loss due to the added resistance at R2. With these new values, we have the following schematic:

Figure 39: Final Transconductance Schematic

25

David Bouse Johnny Chen

Final Test

Figure 40: Final Schematic

Figure 41: Frequency Vs Voltage Error %

26

David Bouse Johnny Chen

VCtl 0 -1 1

Frequency 998.211 kHz 923.31 kHz 1.07131 MHz

Table 3: Results

27

David Bouse Johnny Chen

Section 2

Emitter-Coupled Multivibrator VCO Initial Design For our design, we used the wn8 model transistors because each transistor will have roughly 500-2mA of current passing through the collector. With the wn2, the characteristics have a fast roll off after 300A while the wn8 have a roll off after 2mA [Appendix A; Figure 3,5]. We then calculated the resistor values to achieve 500A through the resistor with a change of 37.5A for +/- 1V at VCtrl to achieve a center frequency of 1 MHz and a change of frequency of 75 kHz/V. Through our initial calculations, we obtained the following values *Appendix D; Initial Designs+:

R1=R2 R3=R4 R5 C

6.625k 1k 4.583k 250pF

Table 4: Initial Values

28

David Bouse Johnny Chen

Figure 42: Initial Schematic

29

David Bouse Johnny Chen Test Results

Figure 43: Test 1 Output

F0 dt dv I(capacitor) IREF IR1 IR5 VBE

657.255kHz 750.847ns 959.119mV 317A 1.961mA 639.5A 2.05045mA 807.257mV

Table 5: Test 1 Results From our calculation, we should see roughly half the current through R1 that is being produced at IREF, however we are seeing significantly less current than expected. First we will look at the currents through R1 and R2 to see if the currents are split unevenly between the two.

30

David Bouse Johnny Chen

Figure 44: Current through R1 and R2 The current split between the two resistors is roughly the same, so the problem must be due to the current source U10. From our measurement, we see that VCE of that transistor is at -698.997mV, meaning our transistor is currently in saturation. Modification We created enough current through the capacitor to achieve our oscillation frequency without creating a high voltage drop across the resistor R1 to maintain an active operation for transistor U10. We then added another current source to draw current from transistors U3 and U4, while bypassing resistor R1 to reduce the voltage drop across R1. We first reduced IREF down to roughly 200A so that the drop across R1 is minimized by a factor of 10. Because of the lower current value through the transistors, we also changed the transistors to wn2s. For our added current source, we used a wn8 transistor so that the current produced through that transistor is 4 times as much as IREF. To produce the 500A through the capacitor, we required 500A through transistors U3 and U4, so the combined current through R1 and our new current source needed to be at 1mA. With the new current source producing roughly 4*IREF and the current through R1 being 0.5*IREF, we determined the current needed at IREF by solving the equation [Appendix D; Equation 3]: ( ( ) )

31

David Bouse Johnny Chen For this target current, we determined that the value needed at R5=46k.

Figure 45: Test 2 Schematic

32

David Bouse Johnny Chen Test Results

Figure 46: Test 2 Output

Figure 47: Voltage through capacitor

33

David Bouse Johnny Chen

F0 F1 F-1 dt dv I(capacitor) IREF IR1 IR5 VBE

792.96kHz 869.524kHz 720.6kHz 575.08ns 1.2518V 544.272A 192.149A 179.492A 205.7A 779.088mV

Table 6: Test 2 Results

With these results, we are seeing a center frequency of 793kHz with a change of +76.564kHz/-72.36kHz. From our measurements, we can see that there is a much higher dv than we expected. This is due to the early voltage effect of transistors D1 and D2. Because the value of VA is at 29.76V, VCE has a high impact on the current [Appendix D; Equation 3]. Due to this, more current is allowed to flow through the resistors, creating a larger VBE, causing our dv to increase. Modification With our new values, we calculated a required current of 625.9A through the capacitor to obtain a center frequency of 1 MHz and a change in current of 46.94A for a change of 75kHz/V. To obtain these values, a current of 220.966A is required from IREF and a resistor value of 35.33k for R5. The change of current produced from the change in current in R1 as well as some current change in the current source added in our circuit due to the change of VCE. We also required a resistor value of 9.33k for R1 and R2 to obtain the appropriate frequency swing *Appendix D; Initial Design+.

34

David Bouse Johnny Chen

Figure 48: Test 3 Schematic

35

David Bouse Johnny Chen Results

Figure 49: Test 3 Output

VCtrl 0 1 -1

Frequency 1.00295MHz 1.07526 MHz 930.261 kHz

Table 7: Results

Figure 50: Frequency vs Voltage @ Vc Error Percentage 36

David Bouse Johnny Chen We observed our center frequency to be off by 2.57 kHz and our change of frequency is off by 2.69 kHz. Final Adjustments In order to lower our center frequency, we had to decrease the amount of current through the capacitor. Then we added a few more ohms to our current source at R5, effectively decreasing the amount of current being supplied to the multiple current sources, which then decreased the overall current running through the capacitor. We then reduced the resistance at R1 and R2 in order to achieve a higher current swing when VCtrl is at +/- 1V. This higher current swing increased the frequency swing when we input a voltage at VCtrl. For our values, we decided to add 125 to R5 and reduced R1 and R2 by 66.67.

Figure 51: Final Schematic

37

David Bouse Johnny Chen Final Results

VCtrl 0 1 -1

Frequency 999.423 kHz 1.07478 MHz 924.283 kHz

Table 8: Final Results

Figure 52: Frequency vs Voltage @ Vc Error Percentage For our design, we saw that our frequency had a linear relationship with the input control voltage. We observed an increase of 75.357 kHz for an input of 1V and a decrease of 75.14 kHz for an input of -1V from the center frequency. With the -1V input, we are seeing an error of .085% and for the 1 V, we are seeing an error of .020%.

38

David Bouse Johnny Chen

Section 3

Apendix A Lab 1 LTSpice Tutorial

Part 1 DC Characteristics

Figure 1 This graph shows the output characteristics for the wn2 circuit shown below. I c versus Vce is shown above.

Figure 2 This is the LT Spice schematic of the wn2 circuit.

39

David Bouse Johnny Chen

Figure 3 This is the Gummel Plot of the wn2 Ic/Ib. The graph shows the gain of the amplifier. The highest gain is shown on the graph at 200uA. Our schematic is shown below with the wn2.

Figure 4

Figure 5 This is the Gummel Plot of the wn8 Ic/Ib. The graph shows the gain of the amplifier. The highest gain is shown on the graph at 800uA, which is 4 times the highest gain of the wn2 which is true to the characteristics of the transistor.

40

David Bouse Johnny Chen

Figure 6 This shows the LTSpice schematic of the wn8 transistor circuit.

The maximum gain of the wn2 circuit was located at an input current of 200 uAmps, and the maximum gain of the wn8 circuit was located at an input current of 800 uAmps. Therefore the current is four times more in the wn8 than in the wn2. Part 2:

Figure 7

This is the graph of frequency versus gain of the wn2. Below are the schematic and the unity gain frequencies.

41

David Bouse Johnny Chen

Figure 8 -0.6 V 32.2MHz -0.7 V 1.08 GHz -0.8 V 6.86 GHz Table 1 -0.9 V 5.86 GHz

This table shows the unity gain frequencies for the four different input voltages.

Figure 9 This graph is our gummel plot for the circuit shown in the schematic below. Where we plotted Ic/Ib*1.5g with the X-axis on a logarithmic scale and the Y-axis on a linear scale.

42

David Bouse Johnny Chen

Figure 10

Part 3:

Figure 11 This is the ac analysis sweep on the circuit shown in the schematic bellow, where we plotted the output voltage at the odm node. This output voltage represents a difference in the two input voltages. Since there is a 0.5 V ac signal being applied at the same time as a -0.5 V ac signal the net signal appears to be zero.

43

David Bouse Johnny Chen

Figure 12

Figure 13 This graph shows represents the differential input impedance of the circuit where we graphed 1/Ib.

44

David Bouse Johnny Chen

Figure 14 This graph shows the new circuit with a single ac voltage source applied to both input points with an amplitude of 1 V.

Figure 15 This is the graph of the output voltage of the modified circuit with a single ac source.

45

David Bouse Johnny Chen

Figure 16 This is the graph of the differential input impedance of the modified circuit.

Figure 17 After changing the ac value on the source to 0 V and attaching an alternating current source to the output with amplitude of 1 A, this is the graph of the output voltage. This graph represents the output voltage when the collector current is forced to have an amplitude of 1 A.

46

David Bouse Johnny Chen

Appendix B Lab 3 BJT Programmable Transconductor

Abstract: In this lab we were required to build an actively loaded gain stage, using a voltage controlled bias current. Design: In the lab handout we were giving a circuit to build, a programmable transconductance circuit. We were then required to calculate several parts of the circuit that would affect the gain of the circuit. These design steps are outlined in the lab handout under homework. Homework (Small signal): 1. The circuit from figure 1 was constructed using LT Spice, and the following graphs are a result of this circuit simulation. 2. The value of R1 was calculated to be 24K Ohms, which resulted in our desired current of 240 uA through the resister. 3. By creating the small signal model and calculating gm and rpi we were able to determine the small-signal transconductance gain of the amplifier. See question 6 for the results. 4. We utilized our small signal model to determine the input impedance of the amplifier. One simplification we made was the assumption that ro was large enough to neglect. This resulted in an input impedance of 2rpi. 5. The resistors R1 & R2 create a similar impedance for the two transistors in the current mirror. This limits the amount of current that can flow through the two transistors. 6. We ran an ac sweep to determine the transconductance gain of this amplifier. See the graph below.

Figure 1

47

David Bouse Johnny Chen The bandwidth obtained from this graph is approximately 4.2 MHz. The gain of 47 dB is also apparent on this graph. 7. We had some difficulty calculating the correct resistor value once Vamp is replaced by a resistor. With the help of a sweep on LT Spice and the TA, we found 10K Ohms to be an appropriate value. The value resulted in the desired gain of 50 seen in the LT Spice graph below.

Figure 2 8. This alteration changed our bandwidth to 527.3 KHz, which seems to be an acceptable value for this type of circuit. 9. After adding a 15 pF capacitor in parallel with the output resistor our bandwidth dropped to 116.1 KHz. Since this alteration creates a low pass filter these results seem resonable. See LT Spice graph below.

Figure 3

48

David Bouse Johnny Chen Homework (Large Signal): 1. By changing R1 to 10 Kohms we observed a change of plus/minus 50 uA in the current through the resistor when we apply a change of plus/minus 1 V to Vctl. 2. Using a value of 10 K for R1 the output current was observed to be 550 uA when V = -1V 3. When V = 0V the output current was 600 uA. 4. When V = 1V the output current was 650 uA. 5. This does not meet the design specifications, because we need the current to vary between 450 uA and 550uA. 6. Once we calculated and added the correct resistor for R6. We were able to meet our design goals. Procedure (Small Signal): 1. After building this circuit we encountered some difficulties. The first attempt didnt work correctly, we tried multiple corrections but were unable to obtain a working circuit. On our second attempt the circuit worked well after some minor corrections to the wiring. 2. The gain of our simulation was 4.41 and the gain of our physical circuit was 3.94. These results agree with our expectations. Since we are using non-ideal components in the physical circuit, the gain should be less than the ideal simulation on LT-Spice. 3. We observed a non-distorted sine wave with input voltages varying between 30 mV and 50 mV. See our screen shot below.

49

David Bouse Johnny Chen

Figure 4 4. The average gain of our circuit was 5. The Bode plot of this can be seen below.

Figure 5 5. The measured bandwidth of our circuit is approximately 1 MHz. 6. The simulated bandwidth is 3.97 MHz, so our measured bandwidth is approximately of the simulated bandwidth. This seems inconsistent to us, but we were unable to increase the 50

David Bouse Johnny Chen bandwidth or our circuit at this time. Some of the decrease can be explained by non-ideal components. Large Signal 1. Since we already built this circuit in part 1, we began testing for the large signal input. 2. When we applied a square wave input signal of plus/minus 1V to our circuit we did obtain a triangle wave on the output. See the LT Spice graph below.

Figure 6

3. The design did not meet our current requirements. The current was not in the desired region. 4. After adding the CA3096P transistors to create the modified topology, the circuit did meet our requirements. The current was within the specified region.

Theses remaining graphs show the output of the circuit from part 2 as we changed the frequency.

51

David Bouse Johnny Chen

Figure 7

Figure 8

Conclusion: We had built the circuit the way it was in the lab handout. When we were testing the small signal calculations to check if our calculations were correct LT Spice was not giving us correct results, specifically for the small signal bode plot. We did not know that the transistors, Q7 and Q6, were not supposed to initially be connected. We eventually got the correct bode plot for the small signal model after some clarification. We were also confused on the differential voltage gain when we had to replace Vamp with a resistor. We had to rebuild the circuit one because we couldnt figure the problem out.

52

David Bouse Johnny Chen Even with the rebuilt circuit there was still a misplaced wire. We did eventually get it working and tested with correct results.

53

David Bouse Johnny Chen

Appendix C Lab 4 Voltage Controlled Oscillator

Introduction: The objective of this lab was to design a voltage controlled oscillator with a center frequency of 1MHz and a sensitivity of KHz with a change of 1V on the input control. We utilized the BJT programmable transcondutor from lab 3, but we added an integrator (capacitor) and a Schmitt trigger to the output. The output current from the transconductor goes directly into the capacitor, which is connected to ground and the input of the Schmitt trigger. The capacitor will charge, until it reaches the trigger level of the Schmitt trigger, and then begin to discharge; this action will produce a ramp function on the capacitor, and a square wave on the output of the Schmitt trigger. The control input voltage at the current source on the transconductor can vary the current that is delivered to the integrator. This change in current will produce a slope of the ramp function, which will alter the frequency of the square wave output from the Schmitt trigger. Hence, the voltage control can control the frequency of the oscillator. Homework: 1. By using the inverting Schmitt trigger, we are confident that the capacitor output will decrease once the high trigger level is reached. Since the voltage at the negative input terminal of the op-amp is tied to the voltage of the capacitor, once the high trigger level is reached this voltage will attempt to drop to Vee instantly, but the capacitor will resist this change. Hence the capacitor will start to discharge immediately. 2. The following hysteresis equation was found on page 765 of Jaeger:

Letting R6 = 1K; R7 = 23k

Now will calculate R11 & R10 to give us an output of 1V:

54

David Bouse Johnny Chen

Letting R11 = 1k; R10 = 11K

The next step is to calculate R8 & R9 to vary Vc between 5.5 & 6.5V.

Letting R8 = 47K; R9 = 55.5K

3. Next we used the standard capacitor voltage equation to calculate the value for the capacitor in our circuit.

Given the current requirement of 500uA, and the desired frequency of 1MHz:

4. By using the same relationships from problem 3, we find that a change of 25A will give us the desired frequency change of 50KHz. 5. In this problem we were required to calculate R1, to give us a current change of 25A. When we have 0V applied to the control source, the voltage across R1 is 6V, and since the necessary current is 1000A, the following calculation will give us resistance.

55

David Bouse Johnny Chen

6. Our original simulation gave us a center frequency of 371,680 Hz. In order to find some direction for modifying our circuit, we observe the current at our capacitor. We found the peak value to be 456A, so we adjusted R1 to 5.4K to correct this current. After correcting the current the frequency was still measured to be 371,680 Hz. We found this issue to be caused by the delay of the op-amp used in for the Schmitt trigger. To compensate for this delay, we adjusted our capacitor to 112.5pF. This change in capacitance slightly affected our current, so we changed R1 down to 5.2K. One other issue we observed was that the output from the Schmitt trigger was actually changing from 10.5V, instead of 12V. Using the equation from problem 2, we changed R11 to 11.618K. After all adjusting these parameters, we found our center frequency to be 1.04 MHz with a sensitivity of 446 KHz for Vctl = 1, and 955 KHz for Vctl = -1V.

Figure 1: This is the final schematic for our VCO circuit.

56

David Bouse Johnny Chen

Figure 2: Output voltage for Vctl = -1 V; Frequency = 955kHz.

Figure 3: Output voltage for Vctl = 0v; Frequency = 1.004 MHz

Figure 4: Output voltage for Vctr = 1 V; Frequency = 1.0446MHz.

57

David Bouse Johnny Chen

Figure 5: Current at capacitor for Vctr = 0V.

Figure 6: Voltage across the capacitor for Vctr = 0V.

Procedure 1. We physically built our circuit on the bread board. At first our circuit was not functioning, due to improperly connecting some of the rails on the op-amps. We also realized that we had blown two of our op-amps during the build, so replaced these ICs and our circuit began to oscillate. 2. After the corrections discussed in question 1, our circuit did oscillate correctly. 3. With the Vctl set to 0V, our center frequency was 765 KHz.

58

David Bouse Johnny Chen

Figure 7: This is a screen shot from the oscilloscope showing our center frequency of 765 KHz. 4. With Vctl = 1V, our frequency was 795 KHz, and with Vctl = -1V, our frequency was 735 KHz. This shows that the sensitivity of our circuit is closer to 30 KHz for a Vctl = 1V.

Figure 8: Frequency when Vctl = 1V.

59

David Bouse Johnny Chen

Figure 9: Frequency when Vctl = -1V. 5. The oscillation frequency as a function of Vctl between -5v and 5v. Volts -5 -4 -3 -2 -1 0 1 2 3 4 5 Oscillation Frequency in kHz 574 620 662 700 735 765 795 823 848 872 895 Table 1

60

David Bouse Johnny Chen

900

850

800

Frequency (Hz)

750

700

650

600

550 -5

-4

-3

-2

-1 0 1 Control Voltage (V)

Figure 10: Graph of the control voltage vs. the frequency. 6. The linearity range of the Vco is when Vctl=-1v to Vctl=1v. The difference between the frequencies at those two points compared to Vctl=0v is the same difference at 30kHz. 7. The linearity of this VCO is caused by a transistor going into the saturation region. Since Vctl has a direct impact on the Vce of Q5, once the control voltage goes beyond 1V, the transistor begins to saturate. 8. When we set the Vctl to be a sinusoidal signal, we observe a type of frequency modulation. The output frequency of the system is function of the changing voltage of the Vctl.

61

David Bouse Johnny Chen

Appendix D Emitter-Coupled Multivibrator VCO

Introduction The emitter-coupled multivibrator is a device used in the implementation of a voltage control oscillator (VCO). For our circuit, we will design our VCO to have a center frequency of 1MHz with a sensitivity of 50 kHz/V. When our input is grounded, the VCO will output a square waveform with a frequency of 1MHz. When we input a voltage of +/- 1V on the input, we will achieve a frequency of 1.05MHz and 0.95 MHz respectively. In our design, we will use the following topology:

62

David Bouse Johnny Chen

Figure 1: Emitter-Coupled Multivibrator [2] Methodology This circuit is active in two states, which creates the oscillation in our output. In the first state, the transistor Q1 is active while transistor Q2 is inactive. When Q1 is active, the transistor allows current to flow through it which then allows transistor D1 to be active as well. Transistors Q3 and Q4 are always active because they are biased with a current source with their base tied to VCtrl. When Q2 is inactive, Q4 will draw current across the capacitor from left to right. This current then causes the voltage at the emitter of Q2 to drop as a ramp function described by the equation: 63

David Bouse Johnny Chen (1) Once the voltage decreases by 2 VBE, the voltage is sufficiently low enough to allow transistor Q2 to become active while also causing Q1 to become inactive. This process is then repeated, creating the oscillation in our output due to Q1 and Q2 switching on and off. The transistors Q7 and Q8 are acting as our class A output stage, creating a buffer for the circuit from any load we may attach to the output. Transistors Q5 and Q6, along with resistors R1 and R2, allow us to change the current through our multivibrator as a function of VCtrl-Vb If both R1 and R2 are equal, as well as VB and VCtrl being at the same potential, then the current created from Q10 will be split evenly between the two resistors. When we apply a voltage at VCtrl or Vb, the voltage at the nodes above the resistors are different creating an uneven split in current among the two resistors. Resistor R5 and transistors Q9-Q11 are used to create multiple current sources to bias the rest of the circuit. The reference current is created through the diode connected transistor (Q9) and copied among the other transistors. For multiple current sources with BJT transistors, the output current for each transistor can be calculated using the equation: [1] (2)

Resistors R3 and R4 are used to determine the VBE drop of transistors D1 and D2. When D1 or D2 is active, the current through the transistor can be calculated by the equation: [1] ( )( ) (3)

In this case where the transistors are diode connected, VBE and VCE is the product of the resistor (IR) and the current through the resistor. The sum of IR and IC, when the transistor is active, will always equal the current through Q1 or Q2, minus some base current for the class A output stages. This current is then split among the transistors Q3 and Q4 with one half of the current passing through the capacitor. The sum of the currents through Q3 and Q4 must equal the current through R1, which is then determined by our multiple current source configurations and the value of the base voltages (VCtrl and VB). If the resistor values we chose are very small, then the VBE is going to be small as well, causing a very fast switching between Q1 and Q2 being in the active and inactive stages. When the resistors are very large, they do not require as much current to create the necessary VBE drop for the transistors. In this is the case, there is enough of the current left for both D1 and D2 to be simultaneously active. We would no longer have the oscillation at the output; rather it becomes a DC voltage. Initial Design For our design, we begin by determining the characteristics of the CA3046 NPN transistors from viewing the model parameters.

64

David Bouse Johnny Chen

Is VA

145.76 100

Table 1: CA3046 NPN Characteristics

Next we chose a value for our capacitor of 250pF and also note that the positive feedback in our system will cause fast switching once Q1 or Q2 start to turn on. Due to this, we will assume for our switching [2]. To determine the current needed through the capacitor, we will use equation (1) with dv=2*VBE for each half cycle. For our calculation, we will use the values of C=250pF, dv=1V, and dt=0.5s giving us a required current value of 500A. To achieve this current, we will develop a current source to meet these specifications. From the equations: (4) Along with equation (2), we determined that we will require a reference current of 2.069mA. Using equation (3) to determine VBE, we determined that the resistor value needed at . Next, we will need to determine the values of R1 and R2 to achieve a frequency of 50kHz/V. From equation (1), we determined that we will require a current change of +/- 25A. To achieve this change in our capacitor, we will need a change of 50.343A in R1. If we were to apply 1V at VCtrl, the voltage potential above resistor R1 will be 1V higher than that of R2. We can calculate how much the current will split by solving VCtrl is at 1 V, the current change in , assuming that R1 and R2 have the same values. For the case where while the change in . For an increase of 50.343A

in R1, we will require that R1=R2=9.932k. Lastly, we will use 1k for resistors R3 and R4 which should provide enough voltage drops to achieve proper oscillation while limiting only one transistor (D1 or D2) to be active at any one time.

65

David Bouse Johnny Chen

Figure 2: Initial Schematic

66

David Bouse Johnny Chen Test Results

Figure 3: Device Simulation

67

David Bouse Johnny Chen

F0 F1 F-1 dt dv I(capacitor) IREF IR1 IR5 VBE

988.068kHz 1.035MHz 940kHz 479.809ns 952.733mV 494A 1.99193mA 1.00324mA 2.06899mA 674.21mV

Table 2: Initial Results In our initial simulation, we see that the center frequency is below our target frequency by 12 kHz. However, the change in frequency when we input +/- 1V in VCtrl is very close to our calculation at 48 kHz/V. One of the discrepancies we see is in IREF, measured at 1.99193mA rather than the 2.069mA we calculated. The reason for this is that the current we calculated is actually seen through R1. The current IC through Q9 is IR1 minus the base currents for the multiple current sources. On the other hand, the current being produced in Q10 is also increased by a factor of ( ), so we are able to retrieve some of the current loss in our calculated IREF. When we calculated the current through the capacitor, we neglected the small amount current in the emitter of the inactive transistor, producing 4A less than the current we calculated. Modification Because our change of frequency is very close to our specifications, we will focus on increasing the current IREF in order to obtain the correct center frequency desired. From our measurements, we can see that the ratio between factor of . To get the extra 6A through the capacitor, we will need 6A more through transistors Q3 and Q4. These collector currents relate to their emitter currents by a . Using these calculations, we determined that we will require an increase of 24.9175A through R5. However, by increasing the current in R1, we will also decrease the value of VCE10, thus lowering the current amount slightly. To offset this, we will increase the current through R5 by 26A. Using the values of VBE our simulation, we determined that we will require a resistor value of 11.134k for R5.

68

David Bouse Johnny Chen

Figure 4: Trial 2 Schematic

69

David Bouse Johnny Chen Results

Figure 5: Output at 0V

Figure 6: Output at 1V

70

David Bouse Johnny Chen

Figure 7: Output at -1V

VCtrl 0 1 -1
Lab Simulation

Frequency 999kHz 1.047MHz 950kHz

Table 3: Test 2 Results

In our lab simulation, we used 10k for resistors R1 and R2 and 11.120k for resistor R5, a 235pF for our capacitor, and LM3046N transistor array. Our simulation obtained the following results:

71

David Bouse Johnny Chen

Figure 8: Output at VCtrl = 0V

72

David Bouse Johnny Chen

Figure 9: Output at VCtrl = 1V

73

David Bouse Johnny Chen

Figure 10: Output at VCtrl = -1V

VCtrl 0 1 -1

Frequency 995.1 kHz 1.044 MHz 942.9 kHz

Table 4: Lab Results

74

David Bouse Johnny Chen

Figure 11: Frequency Vs. Voltage at VCtrl We can see a linear relationship between frequency at voltage between the ranges of -4.5V and 6.5V. When the voltage at VCtrl becomes too low, then the transistor Q10 will become inactive and reach saturation. This is because the collector node at Q10 is determined by VCtrl-VBE-IR(R1). Once this voltage drops below the base voltage of Q10, the transistor is no longer in its active region. We were unable to determine the upper limit for our linearity due to the limitations of our power supply. We were only able to input a maximum of 6.5 V into our VCtrl.

75

David Bouse Johnny Chen

Figure 12: Output (Va-Vb) with 50 kHz sin input with 2V pk-pk When we input a sine wave into our system, we can see the differential output with a high frequency in a lower frequency envelope.

76

David Bouse Johnny Chen

Figure 13: Voltage across capacitor with 50 kHz sin input with 2V pk-pk We can see that the voltage across the capacitor has the same characteristic as the output voltage. We can see the high frequency triangle wave that inside the lower frequency envelope.

REFERENCES USED [1] Microelectronics book [2] Lab 5 handout

77

David Bouse Johnny Chen

REFERENCES

Microelectronic Circuit Design (Fourth Edition) Authors: Richard C. Jaeger, Travis N. Blalock Copyright: 2011 McGraw-Hill Companies, Inc.

Lab 1 (See Appendix A) Authors: David Bouse, Dan Schilling

Lab 3 (See Appendix B) Authors: David Bouse, Dan Schilling

Lab 4 (See Appendix C) Author: David Bouse, Johnny Chen

Lab 5 (See Appendix D) Author: David Bouse, Johnny Chen

78