ELEN 665 (ESS)

A M S C

Analog and Mixed-Signal Center

Receiver Architectures: Fundamentals and Properties

Analog and Mixed Signal Center- Texas A&M University (ESS)

How can we relax or solve this image rejection problem ?

A possible solution is the use of more than one IF stage. This can relaxed the specs of the filters and other building blocks. How many IF stages are required ?
This depends on the design specs, a rule of thumb is to keep the ratio between the operating frequency before and after a downcoversion should be lower than 10. Say for a signal at 900 MHz can be first downconverted to an IF of 250 MHz, then filter out unwanted signal and second downconverted to 50 MHz and in a third downconversion the IF is 10 MHz. How complex will be the filtering, power consumption and cost?
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LNA
BPF X BPF

Automatic Gain Control

Y Z BPF

LO1
X

LO2

0
LO1

LO1

0 - LO1 LO2

LO2

Double Superheterodyne Architecture

Multi-Stage IF Receivers
From stage to stage the desired signal is further and further downconverted until the desired final IF is obtained. The ratio between the operating frequency before and after downconversion is usually kept lower than 10, say 4. For instance a 1800 MHz signal is first downconverted to a first IF of 450 MHz, then consecutively to 90 MHz and finally to 18 MHz. Note that each downconvertion stage has the same mirror frequency trouble than the single-stage IF receiver. Significant filtering between stages is required. This filtering is done with off chip filters to further complicate the sensitivity to parasitic components, also the power consumption will be high.
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The Image-Reject Receiver or Super Heterodyne Receiver with Quadrature Down-conversion

Image Reject Filter
LNA AGC

90o
90
A D C D S A P D C

D/A

PLL

PLL

0o
D/A

Good performance in terms of image and spurious suppression.

A complex mixer is required. In the DSP a complex non-linear algorithm control the DC-level dynamically. Low integration due to the use of SAW filters. Limited multi-standard ability.
Due to the difficulty to design broadband I/Q phase shifters an alternative solution (Weaver) solution is next discussed. 5 Analog and Mixed Signal Center, TAMU

The Barber-Weaver Receiver

RF Mixers 0 or Low IF1 Filter
IF1 Mixers IF2 Filter and ADC

AGC AGC

LNA

Double the silicon area and power dissipation

I LO1
Difficult Matching of I & Q Paths Operates with low IF1 and IF2

0 or Low IF1 Filter

Q LO2

+j

+j

Signals in the Weaver Architecture

-j Desired Channel sin1 t -1 0 1 cos1 t

0 0 -j BPF

0 I A sin2 t cos2 t B

Image

+
+ 0

BPF

Main drawback of this architecture is incomplete image rejection due to phase and gain mismatch. Harmonics of the second LO frequency may downconverted unfiltered interferers from the first IF to the second.

0 0

Analog and Mixed Signal Center, TAMU

What other receiver structures alternatives can be considered and with what properties ?

Can we make the IF very low, say to DC ? How and at what price ?

Direct Conversion or Zero-IF front end Receiver

Low Noise Amplifier (LNA)

BPF

LPF

0 The LPF can be integrated. No image signal exists The RF spectrum is translated to the baseband in the first downconversion. The LO is equal to the input carrier frequency. This architecture operates only with double-sideband AM signals because it overlaps negative and positive parts of the input spectrum. For frequency and phase-modulated signals, the downconversion needs 9 quadrature outputs. Two sides of FSK (or QPSK) carry different information.

Direct Conversion Front End Receiver With Quadrature Down-Conversion for FSK (digital) Demodulation Phase Detector I
LNA BPF sin0 t cos0 t I

LPF

Limiting and Tone Detector

D Ck

Q
Zero IF

LPF Q

No image rejection filter is needed. Offset voltages can degrade the S/N and saturate the following stages. Isolation between ports is not ideal. I/Q mismatch degrades the downconversion constellation

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Analog and Mixed Signal Center, TAMU

FSK Direct Conversion Receiver.The frequency shift keyed signals appear with opposed relative phase at the phase detector, giving a binary mark or space output according to weather the input signal is lower or higher than the local oscillator frequency. Let assume these inputs (mark and space) signals are: S M = cos( + D )t

S S = cos( D )t The quadrature oscillator signals to the mixers are: LO I = cos t LO Q = sin t
The mixer outputs when a mark is sent are:

I M = S M LO I = cos( + D )t cos t I M = 0.5[cos( + D ) + cos D t ]

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QM = S M LOQ = cos( + D )t sin t QM = 0.5[sin(2 + D )t sin D t ]

Similarly when a space is sent:

I S = 0.5[cos D t + cos( 2 + D )t QS = 0.5[sin(2 D )t + sin D t ]

The double frequency components of I and Q are removed in the LPF of each channel, yielding:

I M = +0.5 cos D t QM = 0.5 sin D t I S = +0.5 cos D t QS = +0.5 sin D t

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Direct-Conversion Receiver (continues)

An alternative implementation
AGC LNA A D C D S A P D C

90
AGC

Allow for high level integration. Low power consumption. PLL Eliminate passive IF filters Good for SSB digital modulation Good Multi-standard ability.

DC offset problem. Increased ADC dynamic range. Because of limited filtering Need of a high-Q VCO.

Moves design efforts to baseband. Unprotected LO leakage into antenna. I/Q match required over high gain range
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Analog and Mixed Signal Center, TAMU

Low IF Receiver Architecture

All advantages of direct conversion. More difficult image rejection. DC spur (offset) outside the signal bandwidth. Digital processing includes adjacent channel image rejection. All weakness of direct conversion without the DC offset problem. In Band image rejection.
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Image Rejection Mixer Analysis ( same as in previous pages 11 & 12)

I (t ) = cos ( LO t ) cos ( RF t )
Image Reject Mixer

cos (RFt)

Q(t) LPF LNA Qlp (t) Ilp (t)

I(t)

Adjacent Channel Filter

Q(t ) = sin ( LO t ) cos (RF t ) = 0.5 {sin [( LO RF )t ] + sin [(LO + RF )t ]}

= 0 .5 {cos [( LO RF t )] + cos [(LO + RF )t ]}

BPF

-90
LPF

BPF

-90
Ilp (t)

Qlp (t ) = 0.5 sin [( LO RF )t ] = 0 .5 sin ( IF t ) I lp (t ) = 0 .5 cos IF 90 o = 0 .5 sin ( IF t )

v o (t ) = I lp (t ) + Qlp (t ) = sin ( IF t ).

I lp ` (t ) = 0.5 cos[( LO RF )t ] = 0 .5 cos (IF t )

cos (LOt)

(LO > RF)

The image input signal, for high-side injection of the LO, is v l,lm (t)=cos[( LO + IF )t].

I (t ) = cos[( LO + IF )t ] cos ( LO t ) = 0.5{cos (IF t ) + cos [(2 LO + IF )t ]} I lp ` (t ) = 0.5 cos ( IF t ) I lp (t ) = 0 .5 sin ( IF t )

Q (t ) = sin ( LO t ) cos [( LO + IF )t ] = 0.5 sin ( IF t ) + 0 .5 sin [(2 LO + IF )t ] Qlp (t ) = 0.5 sin ( IF t )

vo ,Im (t ) = I lp (t ) + Qlp (t ) = 0 ;

Image response can be completely suppressed.

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0.35m CMOS Bluetooth Low-IF Receiver IC: An example of a Low-IF topology

2.4GHz 2MHz I RF filter LNA PLL
Developed in about 1 years by : Authors:Wenjun Sheng, Bo Xia,Ahmed Emira, Chunyu Xin, Ari Ari Valero-Lopez, Sung Tae Moon and Edgar Sanchez-Sinencio.

Demodulator

Q Polyphase Filter

Offset Cancellation /Decision

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0.35m CMOS Bluetooth Low-IF Receiver IC

Publications:
2002 RFIC Conference, Best Student Paper Award (third place). Journal of Solid-State Circuits: January 2003 (Receiver) and August 2003 (Demodulator). Transactions on Circuits and Systems II: November 2003 (Complex Filter).
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TRANSCEIVER CELLULAR RADIO BLOCK DIAGRAM

Antenna

Power Amplifier A/D and D/A Converters Data, Voice Frequency Interface

Duplexer

Transmitter

Receiver

Digital Signal Processor (DSP)

Reference Oscillator

Frequency Synthesizer

Processor

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GSM RECEIVER SYSTEM REQUIREMENTS

Signal Level (dBm) 0 Blocking -23 dBm Blocking -43 dBm -40

Wanted-120dBm -80

-120 fo +1MHz +2MHz +3MHz

Gain of wanted signal > 100 dB Noise Figure of LNA input less than 8 dB

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Subsampling Receiver
RF Stage
RF=1846MHz

IF to Baseband RF to IF
Subsampling AGC fs
Digital Mixer Digital LPF
o

RF BPF

LNA

IMG REJ

IF BPF 246 MHz RF LO 1.6 GHz

ADC

90

Digital LPF LO

q 2 digital low frequency mixers, no noise and distortion. q Easier I&Q matching. q No DC offset and 1/f noise. Aliasing q More digital means easier integration on a CMOS process. q SNR degradation due to noise folding q ADC & SH have to run at high clock to minimize noise 20 folding.

Example: 1.8 GHz GSM Specifications: IF carrier frequency = 246 MHz, Channel BW = 200 KHz, Input Dynamic Range = 90 dB .

Sub-sampling Receiver: Basic Idea

fs/4 fs/4 BW

fs Aliased signal to baseband

2fs

4fs f IF=246MHz IF Signal

The sampling rate, fs, can be much less than the IF carrier. But, fs > 2BW must be satisfied (to avoid destructive aliasing).

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Wideband IF Receiver:

The mirror signal is different from the wanted signal.

Image Rejection Architecture
A D C D S A P D C

LNA

90

HF LO PLL

PLL LF LO

4 Allow for high level integration. 4 Relaxed RF PLL specification, VCO could be made on-chip. 4 Channel-selection performed by IF PLL lower the required divider ratio. 4 Good Multi-standard ability. 4 Alleviated DC offset problem. 8 Increase of 1dB compression point of second set of mixer. 8 Increased ADC dynamic range because limited filtering in comparison with the heterodyne receiver. 22 8 Feasibility has not been proven for GSM. Analog and Mixed Signal Center, TAMU

Receiver Architectures Wideband Digital IF Receiver

LNA

AGC

ADC

DDC

DSP

PLL

vMore digital parts allow for higher level integration. v Relaxed RF PLL specification. v No I&Q mismatch. v Good Multi-standard ability. v Increase of 1dB compression point of LNA and mixer. v Critical performance required of ADC. v High performance required of DSP.

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Receiver Technology Trends

Traditional Superheterodyne Increasing Integration
Borrows from handset chip integration, or new architecture like direct-conversion.

IF-Sampling/Digital I&Q
Reduces receiver size by eliminating IF stages New architectures using more digital processing

Multi-mode, Wideband
Large reduction in receiver size Major architectures shift to DSP-intensive radio, highly programmable
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Software Receiver

LNA

ADC

DDC

DSP

Band Select High Intercept Point Amplifiers Filter Remove Amplify signals without the unwanted spectrum introduction of significant intermodulation products

High Intercept Wide Dynamic Fixed Function Fast DSP Point Mixers Range ADC DSP digitally with on-chip selects and translate digitize entire Memory filters the demodulates input spectrum spectrum for to ADC signal digital channel channel of signal bandwidths interest selection

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Analog and Mixed Signal Center, TAMU

SOFTWARE RADIO
Antenna RF (1-2 GHz) LNA+ VGA Digital bitstream BPF ADC DSP

Idea introduced in 1991 by Joe Mitola Direct RF digitization Single / multiple channels sets ADC BW Reconfiguration by DSP software programs

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SOFTWARE DEFINED RADIO

Antenna RF (1-2 GHz) IF (100-200 MHz) IF ADC Digital bit stream

BPF

LNA

VGA

LO1

IF digitization No specific standard for IF location Reduced DC offset, flicker noise problems

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Literature survey
Ref
Vessal (JSSC 04) Kaplan (CICC 03) Chandrasekaran (CICC 02) Cherry (TCAS 2000) Gao (VLSI 98) Jayaraman (GaAs 97)

Type
Nyquist (FI) CT BP S? SC LP S? with mixer CT BP S? CT BP S? CT BP S?

Fo Fs SNR Power GHz GHz 1 MHz BW (mW)

0 - 0.7 1.3 0.9 2 4.3 0.1 48 dB 62 dB 25 dB (bad SNDR) 51 dB 48 dB 55 dB 3500 6200 30

Tech
SiGe HBT InP HBT 0.25m CMOS 0.5m SiGe 0.5m SiGe GaAs

1 1 0.8

4 4 3.2

450 350 1800

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Examples of Standards ( simplified versions)

Bluetooth Data rate Power Modulation Frequency Band 1Mb/s Lower FH-GFSK 2.4 2.48GHz 802.11b (Wi-Fi) 1-11Mb/s Higher DSSS-CCK 2.4 2.48GHz

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IEEE 802.15.4 (Zigbee) Parameter

Frequency Range Channel spacing North America 2402-2480 MHz 5 MHz North America 902-928 MHz 5 MHz

Europe
2412-2472 MHZ 5 MHz

Multiple access CSMA/CA method Duplex method FDD Users per channel Modulation Peak bit rate 255 OPQSK, BT=0.5 250 kHz

CSMA/CS FDD 255 OPQSK, BT=0.5 40 kHz

TDMA FDD 255 GFSK,BT=0.5 250 KHz

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Parameter

800 MHz

1900 MHz 1850-1910 MHz 1930-1990 MHz 1250 kHz 48 CDMA/FDM FDD More than 15
QPKK/OQPSK

Asia 1920-1980 MHz 2110-2170 MHz 1250 kHz 48 CDMA/FDM FDD More than 15
QPKK/OQPSK

Summary of IS-95 CDMA

Mobile-to-base 824-849 MHz frequency Base-to-mobile 869-894 MHz frequency Channel spacing Number of channels 1250 kHz 20

Multiple access CDMA/FDM method Duplex method FDD Users per channel Modulation Channel bit rate (chip rate) More than 15
QPKK/OQPSK

1.2288 Mb/s

1.2288 Mb/s

1.2288 Mb/s

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UMTS/DCS1800 Specifications
DCS1800 Frequency Band Channel BW System Sensitivity BER
1805 - 1880 MHz 200 kHz -102 dBm

UMTS
2110 - 2170 MHz 5 MHz -117 dBm(@32ksps) 1e-3 10 - 15 MHz: -56 dBm 15 - 60 MHz: -44 dBm 60 - 85 MHz: -30 dBm > 85 MHz: -15 dBm 5 MHz: -52 dBm

1e-3 600 - 800 kHz: -43 dBm Blocking 800 - 1600 kHz: -43 dBm Characteristics 1600 - 3000 kHz: -33 dBm > 3000 kHz: -26 dBm Cochannel: -9 dBc Adjacent Channel 200 kHz: 9 dBc Interference 400 kHz: 41 dBc 600 kHz: 49 dBc

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Multi-Channel, Multi-Mode Dynamic Range (1) DCS1800

-15 dBm -99 dBm

BW=2170-1805 =365 MHz

LNA
0 dBm -84 dBm

BW=max(band) =75 MHz

Amp
-4 dBm

-114 dBm

ADC
13 dBm -60 dBm

-99 dBm

-77 dBm

Gain: 10 dB Gain: 15 dB Input 1dB Input 1dB compression: -13 dBm compression: 2 dBm

Gain: 17 dB Fullscale Voltage: Input 1dB 2 Vpp compression: 0 dBm

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Multi-Channel, Multi-Mode Dynamic Range (2) DCS1800

PB Blocker CW carrier Wanted Signal Px Noise PSD

PB = 13 dBm Px = -60 dBm

To ensure that the quantization noise power is negligible compared to that of In channel interferers and other sources of thermal quantization noise BW=200 kHz and device noise, choose SNRQF = 20 dB With Fs = 150 MHz, calculated resolution of ADC is 11 bits. The SFDR (for single blocker) can be calculated by: SFDR = PB - Px + SNRQF = 93 dB Required ADC Spec.: FS >= 150 MHz, b = 11, SFDR = 93 dB Current State of the art ADC: Fs = 80 MHz, b = 14, SFDR = 100 dB(AD6644)
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How much Conversion Gain is required?

Amp

LNA

ADC
13 dBm

-26 dBm(DCS1800) -30 dBm(UMTS)

Between the antenna and the ADC, 39 dB(for DCS1800) or 43 dB (for

UMTS) of power gain is required for a maximum signal to drive the ADC to full-scale. However, since several signals could phase align, some guard-banding is needed. Since it is not very probable that multiple signals will phase align converter clipping is not likely. Gain is distributed between the antenna and the ADC, low noise components should be used to maintain sensitivity, key specifications are Noise Figure and Third Order Intercept Point.
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Sensitivity (DCS1800/UMTS)
The maximum signal -26 dBm(DCS1800) or -30 dBm(UMTS) is at FS, therefore SNR of the signal is : - DCS1800 68 + 28 = 96 dB (68 dB is from 11 bits ADC, 28 dB is from processing gain) - UMTS 68 + 15 +21 = 104 dB Most processing algorithms require 10 dB SNR minimum for a reasonable bit error rate - Therefore, the -26 dBm signal can be reduced by 86 dB (96 - 10) for DCS1800 and -30 dBm signal can be reduced by 94 dB (104 - 10) for UMTS before too little SNR remains. Sensitivity would be -112 dBm (-26-86) or -124 dBm (-30-94) minus NF and multi-carrier guarding.

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REFERENCES
[1] B. Leung, VLSI for Wireless Communication Prentice Hall, Upple Saddle River,NJ 2002
[2] T. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998. [3] C. Chien , Digital Radio Systems on a Chip, Kluwer Academic Publishers, Boston, 2001. [4] B. Razavi, RF Microelectronics, Prentice Hall, Upple Saddle River,NJ 1998 [5] A. Bensky, Short-range Wireless Communication: Fundamentals of RF System Design and Application, 2 nd Edition, Amsterdam, -Newnes-Elsevier 2004

Analog and Mixed Signal Center- Texas A&M University (ESS)

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