2009-02-13 11

A Bandpass Analog-to-Digital Converter

Using Voltage-Controlled Oscillators
Young-Gyu Yoon & SeongHwan Cho
Communication Circuits and Systems Group, KAIST
http://ccs.kaist.ac.kr
Berkeley Wireless Research Center
CCS Group @ KAIST
Y.G. Yoon et al., Time-based Bandpass ADC using Time-Interleaved Voltage-Controlled
Oscillators, IEEE Trans. On Circuits & Systems I, Dec., 2008.
2009-02-13
Motivation
Next-generation receivers require multi-mode multi-standard
communication.
Programmable and digital-intensive receiver is necessary.
ZigBee
Bluetooth
WLAN
USN
RFID
DECT
W-CDMA
UWB
GSM
GPS
2 CCS Group @ KAIST
2009-02-13
Receiver Architectures
3 CCS Group @ KAIST
Large dynamic range
Many analog components
Low programmability
Highly digital
High programmability
Dynamic range is limited (ADC)
High power consumption (ADC)
A/D conversion at RF A/D conversion at IF
Low-power high-performance ADC is necessary.
ADC
LNA
DBB
ADC LNA IF Amp
LO
DBB
2009-02-13
Bandpass ADCs for Direct RF Sampling
Nyquist ADC Bandpass ADC
f
f
4 CCS Group @ KAIST
Bandpass ADC can be more efficient than a Nyquist
ADC for a narrow-band communication receiver.
Conventional RF bandpass ADC
Mostly implemented in expensive processes due to high
speed requirement
SiGe BiCMOS, InP HBT, etc
High power consumption due to high-speed analog
components (loop filter & DAC)
Filter is not programmable.
) (s H
DAC
+

Analog
Input
Digital
Output
CLK
2009-02-13 CCS Group @ KAIST 5
High Performance BP ADCs
A Low-Noise 40Gs/s Continuous-Time Bandpass
ADC Centered at 2GHz for Direct Sampling Receivers
Continuous-time bandpass architecture using Gm-LC
LNA included in main path
Center frequency 2GHz
Sampling frequency 40GHz
SNR @ 10MHz BW 63dB (0dBm input)
Power consumption 1.6W
Supply Voltage 2.5V
Technology 0.13m SiGe BiCMOS
Active area 2.40mm
2
Chalvatzis et al., A Low-Noise 40-GS/s Continuous-Time Bandpass ADC Centered at 2GHz for Direct Sampling Receivers,
IEEE JSSC May, 2007.
2009-02-13 6 CCS Group @ KAIST
High Performance BP ADCs
Continuous-time bandpass architecture
Passive L & C for band-pass filtering
Center frequency 950MHz
Sampling frequency 3.8GHz
SNR @ 1MHz BW 59dB
Power consumption 75mW
Supply Voltage 1.25V
Technology 0.25m SiGe BiCMOS
Active area 1.08mm
2
Thandri and Martinez, "A 63 dB SNR, 75-mW Bandpass RF ADC at 950 MHz Using 3.8-GHz Clock in 0.25-um
SiGe BiCMOS Technology," IEEE JSSC, Feb. 2007
2009-02-13 7 CCS Group @ KAIST
2009-02-13 88
Previous Works on Direct RF Sampling
Ref f
carrier
f
sample
BW SNDR Power Supply Process Mscl
JSSC
2007
1.8~2.0GHz 40GHz 60MHz 55dB 1.6W
V
DD
=2.5V
V
SS
=0V
0.13um SiGe
BiCMOS
4
th

2.40mm
2
JSSC
2007
950MHz 3.8GHz 1MHz 59dB 75mW
V
DD
=1.25V
V
SS
=-1.25V
0.25um SiGe
BiCMOS
4
th

1.08mm
2
TCAS-II
2000
1GHz 4GHz 20MHz 37dB 450mW
V
DD
=5V
V
SS
=0V
0.5um SiGe
HBT
4
th

1.36mm
2
CICC
2003
1.3GHz 4.3GHz 200MHz 39dB 6.2W
V
DD
=5V
V
SS
=-5V
InP HBT
4
th

5.28mm
2
Goal
800MHz ~
2.4GHz
6.4GHz 20MHz 55dB ~ 15mW
V
DD
=1V
V
SS
=0V
65nm
CMOS
Time-
based
ADC
CCS Group @ KAIST
Conventional bandpass ADCs rely on fast devices (SiGe BiCMOS) and none
have yet developed a CMOS RF sampling ADC.
Analog circuits are extensively used in conventional bandpass ADCs
Not compatible with future nanoscale CMOS devices.
Contents
Motivation
Introduction to the VCO-based ADC
Time-based ADC
Operation principle
Proposed VCO-based bandpass ADC
Implementation
Measurement results
Conclusion
2009-02-13 CCS Group @ KAIST 9
2009-02-13 10 10
Time-based Signal Processing
Time-based ADC is a promising candidate for direct RF sampling
bandpass ADCs.
Conventional ADC
Time-based ADC
In a deep-submicron CMOS process, time-domain resolution of a digital signal edge
transition is superior to voltage resolution of analog signals.
[ Staszewski et al., All digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS , IEEE JSSC, 2004 ]
CCS Group @ KAIST
Time domain
VDD
GND
GND
VDD
Faster transition
VDD
VDD
GND GND
noise
Voltage domain
Lower SNR
2009-02-13 11
Operation Principle
VCO : Voltage-to-phase conversion
Counter: Phase quantization
Digital code generator: LUT
- Counting the edges of VCO output
ex) rising edge detection LSB = 2
ex) rising/falling edge detection LSB =
- Mapping circuit
Analog
input
Time
CLKs CLKs CLKs
Time
VCO
output
voltage
VCO
output
phase
Time
VCO
Voltage to
phase
domain
Rising edge
Counter out
= 3
Rising edge
Counter out
= 5
2
VCO
Analog
Input
Digital
Output
Digital Code
Generator
Counter
clk
H. Burke, A survey of analog-to-digital converters, Proceedings of the IRE, 1954.
A. Iwata et al., The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage-Controlled Oscillator as a
Multibit Quantizer, IEEE Trans. Circuits Syst. II,, July 1999.
A. Younis, H. Marwan, and R. Moises, Method and system for VCO-based analog-to-digital conversion (ADC), US pat.
# : 6,809,676 , 2004.
E. Alon, et al, Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise, IEEE Symp.
on VLSI Circuits, 2004
CCS Group @ KAIST
2009-02-13 12
Resolution of VCO-based ADC
f
max
f
min
9
2
t
Sampling period
(Conversion Window)
1LSB(2)
1LSB(2)
Number of
rising edges
max min
V -V
=8
1LSB
Resolution(N=3)
2
2
log
1 ( )
log
1 ( )
MAX MIN
FS
V V
Resolution=
LSB V
V
LSB V
| |
|
\ .
| |
=
|
\ .
2
max min
2
2
log
1 ( )
2 ( )
log
1 ( )
2
log
1 ( )
max min
VCO period
tune
sample
Resolution
LSB rad
K V V T
LSB rad
f
f LSB rad
| |
=
|
\ .

| |
=
|
\ .
| |

=
|
|
\ .
1LSB
V
max
V
min
For high resolution ADC, a wide tuning range VCO is necessary.
CCS Group @ KAIST
2009-02-13 13
Operation Principles Revisit
Inherent 1-st order noise shaping property.
VCO Counter
Sampling Clock
x[n]
Digital
output
S/H
input
Y[n]
{ }
{ }
1
[ ] [ ]
2 [ ] [ ] [ ]
2 [ ] [ 1] [ ]
1
[ ] [ ] [ ] [ 1]
2
1
( ) ( ) (1 ) ( )
2
VCO
i
VCO
VCO
p n K x n
y n p n e n
y n e n e n
y n K x n e n e n
Y z K X z z E z

=
= +
= +
= +
=
VCO output
Counter
Ouput
y[n]
4 3 ...
Sampled
Input
x[n]
p
i
[n]
n n-1 n+1
Sampling
clock
0
2
VCO
phase shift
p[n]
e[n]
p[n]
time
4
6
8
10
e[n-1] e[n] p
i
[n+1] p
i
[n]
e[n-1]
CCS Group @ KAIST
A. Iwata et al. The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a
multibit quantizer," IEEE Trans. Circuits Syst. II, 1999.
1
( 1) NTF z

=
2009-02-13 14
SNR of VCO-based ADC
0 10 20 30 40 50 60 70 80 90 100
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Frequency[MHz]
P
S
D
[
d
B
]
f
sample
= 200MHz
VCO Tuning Range : 50MHz~1GHz
Input frequency = 5MHz
ENOB = 8.48(bits)
Oversampling can be used to increase the resolution.
6.02 3.41 30log( )
Q
SNR M OSR +
2
/ 2
2
log
1 ( )
sample in
tune
Q
sample
where OSR f f
f
M
f LSB rad
=
| |

=
|
|
\ .
Example)
CCS Group @ KAIST
2009-02-13 15
Past Work on VCO-based ADCs
A. Iwata et al., The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage-
Controlled Oscillator as a Multibit Quantizer, IEEE Trans. Circuits Syst. II, July 1999.
R. Naiknaware et al., Time-referenced single-path multi-bit ADC using a VCO-based quantizer,
IEEE Trans. Circuits Syst. II, July 2000.
T.Watanabe, et al., An All-Digital Analog-to-Digital Converter With 12-uV/LSB Using Moving-Average
Filtering, IEEE JSSC, Jan. 2003.
J.Kim et al., A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator,
ISCAS 2006
U. Wismar et al., A 0.2V 0.44W 20kHz Analog to Digital Modulator with 57fJ/conversion FoM,
ESSCIRC, 2006.
Straayer et al., A 10-bit 20MHz 38mW 950MHz CT ADC with a 5-bit noise-shaping VCO-based
Quantizer and DEM circuit in 0.13um CMOS, VLSI 2007.
z
-1
DAC
Counter VCO
Analog
Integrator
Oversampling
Clock(fos)
Digital
output
Y(z)
Analog
input
X(z)
VCO
Analog
Input
Digital
Output
Digital Code
Generator
Counter
clk
CCS Group @ KAIST
2009-02-13
n n+1
Time (sample)
Sampling Clock
VCO Input 1
VCO phase 1
6
2
4
] 2 [ n e
] [n e
[ 2]
i
p n +
CLK1
CLK2
VCO Input 2
VCO phase 2
6
2
4
0
0
n-1
] 1 [ n e
[ ]
i
p n
[ 1]
i
p n +
n+2
Analog Input
n+3
] [n
[ 3]
i
p n +
] 1 [ + n e
] [n x G
v
] 1 [ + n
] 1 [ + n x G
v
Analog
Input
x(t)
Digital
Output
y[n]
MUX
Counter VCO S/H
CLK1
Counter VCO S/H
CLK2
Reset
(CLK2)
Analysis of Two-Channel Time Interleaved VCO-ADC
16 CCS Group @ KAIST
2
( ) 1 NTF z z

=
( )
( )
( )
( ) { }
2
[ ] [ ] [ ]
1
[ ] [ ] [ ]
2
1
[ ] [ ] [ ]
2
1
[ ] [ 2 ] [ ]
2
1
( ) ( ) 1 ( )
2
v i
v i
v
v
n G x n p n
y n n e n
G x n p n e n
G x n e n e n
Y z G X z z E z

= +
=
= +
= +
= +
SNR of the Two-channel T.I. VCO-ADC
Increase in |NTF| is canceled by the increased quantizer resolution.
2009-02-13 CCS Group @ KAIST 17
2
2
2
1 1
8 8 / 2
1
4
8
tune
S FS
s
tune
s
f
P V
f
f
f
| |

= =
|
\ .
| |

=
|
\ .
( )( )
( )
( )
1
2 1 1
1
2 1 , 1
( ) 1 1 1
2 1 , 1
z z
NTF z z z z
z z

= = +

+

2
10log 6.02log 3.41 30log
S tune
e s
P f
SNR OSR
P f
| | | |
= = +
| |
\ . \ .
/
2
/
/
2
/
3
2
( ) | ( ) |
( ) 4 | 1|
4
36
OSR
e N
OSR
OSR
j
N
OSR
P S NTF d
S e d
OSR

=
=

| |
=
|
\ .

/ 2
(input referred quantization step)
s
FS
tune
f
V
f
=
Proposed N
th
-order ADC architecture
Analog
Input
x(t)
Digital
Output
y[n]
Counter VCO S/H
Reset
(CLK1)
Counter VCO S/H
Reset
(CLK2)
Counter VCO S/H
Reset
(CLK3)
Counter VCO S/H
Reset
(CLKN)
CLK2
(f
s
/N)
CLK1
(f
s
/N)
CLK3
(f
s
/N)
CLKN
(f
s
/N)
MUX
CCS Group @ KAIST 2009-02-13 18
( )
1
( ) 1
1 , 1
N
NTF z z
N z z

=

Comparison to a Conventional -ADC
Interleaving conventional DSM results in same NTF but quantization
noise increases
Constant quantization noise level with time-interleaving is a
unique property of VCO-based bandpass ADC.
0
| ) ( | f Q
N
2nd
4th
8th
16th
32th
0
| ) ( | f Q
N
2nd
4th
8th
16th
32th
TI VCO-based ADCs
TI conventional ADCs
CCS Group @ KAIST 2009-02-13 19
Behavioral Simulation Results
2009-02-13 20
N=2 N=4
N=16 N=128
Bandstop noise-shaping property is shown.
Increasing the number of channels results in more available bands.
SNR is nearly the same regardless of the number of channels.
CCS Group @ KAIST
Performance of the Proposed ADC architecture
CCS Group @ KAIST 2009-02-13 21
N = 4
f
s
= 2GHz
8stage VCO (16phase) with tuning
range of 100MHz - 450MHz
Ideally, more than 10bits can be achieved with less than
10MHz of bandwidth.
Practical Issues: Effect of Non-Idealities
Issues in VCO-based ADCs
Non-linearity of VCO tuning curve
Non-linearity of S/H circuit
Phase noise of sampling clock
Phase noise of VCO
Meta-stability of flip-flops
Backward coupling in VCO (output to input)
Issues in time-interleaved ADCs
Mismatch between sub-ADCs
Timing mismatch (input and clock skew)
Issues in time-interleaved VCO-based ADCs
Coupling between VCOs
CCS Group @ KAIST 2009-02-13 22
Practical Issues: Non-linearity of S/H & VCO
Non-linearity results in harmonic spurious tones in the output.
Harmonic spurs limit SNDR performance.
Two-tone simulation with non-linearity
CCS Group @ KAIST 2009-02-13 23
2009-02-13 24
Effect of VCO Phase Noise
0 100 200 300 400 500 600 700 800 900 1000
-120
-100
-80
-60
-40
-20
0
PSD from CppSim
Frequency [MHz]
P
S
D

[
d
B
]
0 100 200 300 400 500 600 700 800 900 1000
-140
-120
-100
-80
-60
-40
-20
0
PSD from CppSim
Frequency [MHz]
P
S
D

[
d
B
]
-120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70
3
4
5
6
7
8
9
10
11
12
13
Phase noise @ 1MHz offset [dBc/Hz]
E
N
O
B

f
o
r

1
0
M
H
z

b
a
n
d
w
i
d
t
h

[
b
i
t
]
Assuming power consumption of ~ 1mW,
phase noise of -100dBc @ 1MHz ,
f
osc
=500MHz results in -153dB of FOM.
Ideal VCO
VCO with phase noise
Phase noise limits the timing accuracy and hence the resolution of the ADC.
FOM of ~ -150 is easily achievable in todays ring oscillators.
CCS Group @ KAIST
Effect of Clock Jitter
2009-02-13 25
< 0.1% clock jitter is required for > 10bit performance.
CCS Group @ KAIST
Metastability and Coupling
Meta-stability of flip-flops
Not an issue if the resolution of flip-flops is better than
the time-resolution of VCOs.
Also first-order shaped.
Backward coupling in VCO
VCO output can corrupt its input.
Effect can be minimized if its tuning range of the VCO
does not overlap with the input frequency range.
CCS Group @ KAIST 2009-02-13 26
Practical Issues : Mismatch between sub-ADCs
Mismatch between sub-ADCs
One of the performance bottleneck in time-interleaved ADCs
Simulated by giving random mismatch in the tuning curves of the VCOs
ENOB degradation due to mismatch
e.g.) 60dB 50dB with 1% mismatch
CCS Group @ KAIST 2009-02-13 27
Conclusions
Time-interleaved VCO-based ADCs exploiting
time-based signal processing has been
introduced.
RF signals can be digitized in an energy & area efficient manner.
Limitations of the proposed ADC include
Timing mismatch, non-linearity, supply noise, phase noise, etc.
Performance can improved with better measurement layout,
measurement setup and already established calibration
techniques.
Time-based signal processing will become
increasingly more prevalent in the future
2009-02-13 CCS Group @ KAIST 28
29/44
References
[1] R. B. Staszewski et al., All-digital TX frequency synthesizer and discrete-time receiver for
bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, vol. 39, pp. 2278-2291, Dec
2004.
[2] A. Iwata, N. Sakimura, M. Nagata, and T. Morie, The architecture of delta sigma analog-to-
digital converters using a voltage-controlled oscillator as a multibit quan-tizer," IEEE Trans.
Circuits Syst. II, vol. 46, pp. 941-945, July 1999.
[3] Y-.G. Yoon et al., A time-based bandpass ADC using time-interleaved voltage-controlled
oscillators, IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3571-3581, Dec 2008
[4] Y.-C. Jenq, Digital spectra of nonuniformly sampled signals : Fundamentals and high-speed
waveform digitizers," IEEE Trans. Instrum. Meas., vol. 37, pp. 245-251, June 1988.
[5] J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control,"
IEEE J. Solid-State Circuits, vol. 35, pp. 1136-1145, Aug. 2000.
[6] H. Wang, "A 1.8V 3mW 16.8GHz frequency divider in 0.25um CMOS," in IEEE Int. Solid-State
Circuits Conference, Digest of Technical Papers, 2000.
[7] T. Chalvatzis et al., A low-noise 40-GS/s continuous-time bandpass ADC centered at 2 GHz
for direct sampling receivers, IEEE J. Solid-State Circuits, vol. 42, pp. 1065-1075, May 2007.
[8] B. K. Thandri and J. S. Martinez, A 63dB SNR, 75-mW bandpass RF ADC at 950MHz using
3.8-GHz clock in 0.25-um SiGe BiCMOS technology, IEEE J. Solid-State Circuits, vol. 42, pp.
269-279, Feb 2007.
[9] J. Rychaert et al., "A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-
image RF bandpass ADC in 90nm CMOS," in Proc. of Asian Solid-State Circuits
Conference.
2009-02-13 CCS Group @ KAIST
2009-02-13 CCS Group @ KAIST 30
2005.3~ , 13 students
Research area of interest
PLL : Low-noise low-power frequency synthesis, clock generation
& building blocks for wireless applications
ADC: Reconfigurable, ADCs for software radios
Bio-medical circuits: Health care and neuro-science
Communication Circuits & Systems (CCS) Group
Wireless Transceivers & PLLs
PLL-based transmitter for non-continuous modulation. [Lee, IEEE TCAS2007]
2009-02-13 CCS Group @ KAIST 31
JSSC
04
JSSC
07
This
work
Optimality
Test
X X O
Cal Time 12.6 us 4 us 350 ns
Cycles to
Calibrate
2
n
Curves
20.5 n 5 2
n
n+2
Base
Band
Frequency
Synthesizer
DI(t)
DQ(t)
/ 2
Frequency
Synthesizer
[Lee, IEEE TCAS2, 07]
Divide-by-2
Programmable
divider
DSM
PFD
Vmid
External loop filter
K<14:0>
REF
2.4~2.5-GHz output
Charge recycling path
Signal
Decoupling
capacitor
Level
Shifter
[Park, Symp. on VLSI 08]
[Lee, A-SSCC 07]
800uW charge recycling frequency synthesizer [Park, VLSI08]
Low-jitter PLL with fast & accurate frequency calibration. [Lee, A-SSCC07]
Low-noise all digital PLLs
Building Blocks for PLLs: PVT Immune VCOs
2009-02-13 CCS Group @ KAIST 32
VCO with wide tuning range & immunity to PVT variations [Park, IEEE MTT08]
Design techniques for robust low-voltage VCOs [Park, IEEE MTT09]
Charge-recycling VCO & prescaler [Park, IEEE MWCL08]
V
DD_dig
Voltage
Boosting
Circuit
V
DD
V
out_n
V
out_p
V
DD_dig
Amplitude
Detector
V
b
V
b
V
DD_dig
b
off
V
out_n
V
out_p
V
out_n V
out_p
V
out_p
V
out_n
[Park, ESSCIRC06, IEEE MTT09, IEEE MWCL09]
JSSC 2005 This work
Tech 0. 18-um 0. 18-um
Frequency 3.8 GHz 2.41 GHz
Tuning
Range
3 % 20 %
Supply 0.5 V 0.5 V 0.43 V
Phase Noise
@ 1-MHz
-119 -117.3 -115.6
FoM -193 -190 -191
FoMT -182.5 -196 -197
Area 0.23 mm
2
0.31 mm
2
Building Blocks for PLLs: Low Noise VCOs
2009-02-13 CCS Group @ KAIST 33
[Ku, IEEE MWCL08]
N+ P+ N+ N+ N+
P-Well
Deep N-Well
N-Well N-Well
P-Substrate
V-NPN
C E B E C
Vc
[Ku, IEEE MTT06]
Low-noise VCO using parasitic V-NPN [Ku, IEEE MTT06]
Optimum current mirror ratio for VCOs [Park, IEEE MTT09]
Building Blocks for PLLs: VCO, Divider & DCOs
2009-02-13 CCS Group @ KAIST 34
Multi-modulus injection locked frequency divider [Lee, A-SSCC07]
High resolution DCO using complimentary varactors [Han, EL08]
Self-noise canceling VCO [Cho, EL08]
Input
Output
D
1
D
2
D
3
M
1
D
0
A B
D
4
D
2n
D
2n+1
Programmable
delay cells
[Lee, A-SSCC07]
C
proposed
= C
NMOS
C
PMOS
[Han, EL08]
D
D
VCDL
PD
ICP
C0
vctrl
ICP

D
[Cho, EL08]