Section: TE-C Roll #

Computer Organization and Architecture TE-C

Wednesday, April 18, 2007
QUIZ # 4: Instruction Set Design
Max Marks = 45; Max Time: 20 minutes
Please state your (valid) assumptions and write your answers in the space provided.

Statement
A microprocessor (MP) Instruction Set has to meet the following design criteria:

• 512 different operations

o Should support instruction listed in question 3 below.
• 3 Special Purpose Registers: Program Counter - PC, Stack Pointer - SP, Index Register - IX
• Only memory access instructions supported are: (Ri can be any of the registers)
o MOVE Ri, (address) ; Ri  (address)
o STORE Ri, (address) ; Ri  (address)
o MOVE Ri, Displacement
o STORE Ri, Displacement
• Should be able to directly access 220 locations of memory
• Does not care about multiple of 8 or power of 2 for length

1. Please provide a minimum number of addressing modes for MP, please explain reasons for your
selection (5 points)
Immediate, Register and displacement . Other modes can be generated from these 3 modes. Use of either
address = 0 or value in R = 0 results in one of the missing modes

2. Answer the following while selecting an optimal length for instructions of MP (10 points)
a. Should MP follow orthogonality? Please explain. (2 points)

Yes to provide 512 different operations

b. Total number of GPRs – provide reasoning (3 points)
3 register instruction can be code with 18 bits  6 bits for one register  64 GPRS, if two sets are used
then total GPRs = 64 + 64 = 128 but that will require identify the set for at least 3 register instructions

c. If you are using mode bits then why and how many? (4 points)
3 bits to maintain orthogonality. 2 for 3 addressing modes + 1 for register set. But if we restrict the use of
register sets for 3 register instruction only then 2 bits should be enough

d. Optimal Instruction length (1 point)

9 (opcode) + 2 (mode) + 20 (direct address) = 31
Section: TE-C Roll #
3. Write their machine code for the instructions in the following table (24 = 4+4+4+4+4+4 points):
No. Instruction mnemonics Instruction Machine Code
Example
a Relative Addressing without an MOV R1,(14 bit 00 1 0 14 bit address
SPR adds)
b SUB R1,R2,R3 01 3 1 2 3 3 (Last 2 bits identify
3 register operand ALU instruction)
c SUB R1,R2 01 2 1 2 2 (last 2 bits identify 2
register operands)
d MOVE R2, (address) 00 2 2 address (14 bit max)

e Pre-indexing addressing mode MOV (20 bit 00 2 18 bits address

instruction using IX register as the address)
index register
f Post-indexing addressing mode MOV R1, (14 00 2 1 14 bit address
instruction without the IX register bit address)

4. How can you decrease the length of the instruction that you have chosen in question 2 while still
meeting the design criteria of the statement points above, please explain (6 points)
a. Use of an Accumulator will provide 20 bit direct addressing for 30 bit instruction length
5. Mode bit coding:
Mode code Purpose
00 Immediate mode with first register set
01 Displacement mode with first register set only
10 Register mode with register set A
11 Register mode with register set B