Characterization of a Generic 45nm CMOS Technology

Taslima Rahman
Electrical Engineering Department San Jose State University San Jose, CA, USA SJSU ID: 003135458 taslima.rahman@gmail.com
AbstractThe purpose of this assignment is to understand the MOSFET characteristics of generic 45nm technology using commercial EDA tool. Cadence schematic composer tool is used for schematic capture and Spectra simulator tool is used for circuit simulation. From Spectre simulations I-V graph DC current voltage characteristic of NMOS and PMOS transistors are determined as a functions of the terminal voltages. I-V Graph is also used for the output resistance(rds) and transconductance (gm) of the transistor.

I. INTRODUCTION The MOSFET is considered as one of the extensively used device in electronics world, especially in Digital Integrated circuits. From Digital point of view, it acts as a switch. The purpose of this report is to study the linear and nonlinear drain current characteristics of a transistor. In this regard, different regions of operation are analyzed. MOSFET is considered as a four terminal device. Fig.1. shows the normal NMOS device. .

positive voltage is applied on gate which is less than the threshold voltage than no channel will be created; i.e. no current (IDS =0) is flowing between drain and source. This region is called cutoff region. If gate voltage is greater than threshold voltage channel starts to create. This region is called triode region. This region exists until the drain to source voltage (VDS) is less than the (VGS - VT) voltage. In triode region transistor acts like a resistor because a linear relationship exists between voltage and current. When VDS is greater than (VGS - VT) transistors enters into active region. In this region transistor acts like non-ideal current source. Following equations are drain to source current for triode region and active saturation region of NMOS transistor.

Similar equations exist for PMOS device also, but with the polarities of the voltages reversed. To study these characteristics a test bench is designed for NMOS and PMOS transistors using schematic composer in the Cadence CAD tool. The gpdk090_AnalogIC library is used to choose the NMOS_1V and PMOS_1V transistors. Spectre simulator and calculator in the Cadence tool are used to simulate the design and to calculate the second order and third order derivatives of Transconductance (gm) and output resistance (rds). DC analysis, parametric analysis and transient analysis of terminal voltages are performed to study the device characteristics.

Fig.1. N channel MOSFET From the above figure we can differentiate all four terminals which are drain, source, gate and body respectively. At this point we are considering that the source and body are connected to ground. Now if

II. NMOS DC CHARATERISTICS NMOS transistor formed on p-type substrate, where electrons are acting as charge carrier through channel. When the positive gate to source voltage is greater than the threshold voltage, substrate holes get depleted and channel starts to create.

Fig.2. shows the testbench schematic for NMOS_1V device where V1 and V2 are the controlling voltage to control the gate to source and drain to source voltage respectively. Both source and body in the NMOS (nmos1v) are grounded to avoid the body effect analysis.

In parametric analysis V1 is swiped from 0 to 1V. Fig.4. shows the multiple IDS vs VDS graphs for different VGS. This graph clearly shows the cutoff region, triode region and active region.

Fig.4. NMOS I-V curve with parametric analysis From the above figure we see that IDS varies with VDS in saturation/active region because NMOS has finite output resistance rds. Fig.2. NMOS Test bench schematic A. Output I-V Characteristics At first IDS vs VDS is Obtained by swiping the V2 voltage from 0 to 1V using linear steps of 100mV and V1 as 500mV. IDS Vs VDS output I-V curve for the NMOS device when VGS = 500mV is shown in Fig.3. B. Output Resistance (rds) With rising VDS, the value of IDS remains reasonably constant because the channel is pinched off at the drain end. This is called CHANNEL LENGTH MODULATION. As a result, by studying the variation of rds, we can understand the effect of increasing VDS on IDS. To find these curves, we can make use of the output I-V curves. The inverse of the derivative (this gives the slope of the curve) gives the value of rds. Similarly higher order derivatives can be obtained. The Calculator tool provided in Cadence with a special built in function deriv to take the derivatives. The first order, second order and the third order derivatives for obtaining the values of r ds are shown below in Fig 5, Fig 6 and Fig 7 respectively. It is given by the following expression

The output resistance is an important device parameter of MOSFETs as it limits the maximum gain of MOS amplifiers used in single stage or multiple stages. Fig.3. NMOS I-V curve when Vgs=500mV

obtain the various curves for gm. The first order, second order and third order curves are shown below in Fig 9, Fig 10 and Fig 11 respectively. It is given by the expression

According to the IDS equation, IDS = k' (W/L) (VGS-VT) 2 the relationship between IDS and VGS is non-linear. Based on the above equation the current is proportional to the square of VGS. Hence we can expect a parabolic curve. The IDS-VGS input curve was plotted by DC analysis of V1 (VGS) by linearly sweeping 0V to 1V in steps of 100mV, at VDS = 500mV. The Fig. 8 shows the IDS Vs VGS input I-V curve for the NMOS device.

Fig.5. 1st order (rds)

Fig.6. Second order rds

Fig. 8. IDS Vs VGS curve at VDS = 500mV The parametric analysis of IDS vs VGS curves were obtained by swiping VDS from 0 to 1 V. Fig. 9. Shows the graphs for IDS vs VGS at different VDS. Fig.7. Third order rds C. Transconductance (gm) Transconductance is defined as the value of drain to source current IDS divided by the value of gate to source voltage VGS for a constant value of drain to source voltage VDS. One of the important parameter to find out MOSFETs intrinsic gain A = gm* rds. The slope of transfer curves gives the value of transconductance. With the help of the derivative function of the Calculator tool in Cadence we can

Fig. 9. IDS Vs. VGS Input Curves - Parametric Analysis of V2(VDS)

Using derivative function of calculator tool in Cadence we find out the first order, second order and third order of gm. The plots for the transconductance (gm), second order gm and third order gm are shown in the Fig. 10, Fig. 11 and Fig. 12 respectively.

Fig.13Transconductance (gm) with different VDS Fig. 10. Transconductance (gm) From the above curves we can observe that gm decreases after it reaches its maximum value.
TABLE I Maximum transconductance values and VGS values for different VDS values

VDS (volts)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

VGS (volts)
0.502 0.603 0.705 0.803 0.797 0.901 0.902 0.902 0.904 0.905

gm (A/V) or(S)
39.08 65.34 85.49 92.06 99.07 104 107 110 112 114

Fig. 11. Second order gm

Fig. 12. Third order gm

From Fig.13. we can obtain the gm_MAX for different VDS.

When VGS < VTH, there is no channel formed between drain and source so there is no current exist, so in this case gm=0. When VDS exceeds overdrive voltage device goes in saturation mode. Ideally from the gm equation, it should vary linearly with VGS which is not the case as we look at the second order derivative curves where the curve has a positive slope instead of a constant value of gm which clearly depicts that gm depends on the higher order values of VGS. The maximum value of gm occurs at VGS = VDS + VTH. When VDS is less than the overdrive voltage, the device enters into the triode region. From 2nd and 3rd order derivative curves the value of gm decreases with increasing VGS due to the dependence on higher order values of VGS. In short channel MOS, the horizontal electric field goes to the high field values due to which the carrier velocity approaches to the scattering limited velocity. At this moment, gm = IDS/(VGS VTH) which means that at higher values of overdrive, this ratio is low, as transconductance is

given by the ratio change in drain current to change in gate to source voltage. At higher values of V GS, IDS attains saturation values and the increase in its value is also small as compared to the increase in value of gate to source voltage. So the ratio also decreases which in turn means that gm decreases. D. OFF-State Current In 45nm technology we found out that even the gate voltage was zero still there was some current flowing which is identified as OFF state current also known as subthreshold leakage current. OFF current is calculated by performing the transient analysis of the device for 1ns at V1 =0 and V2 = 1V. Fig. 14 shows the OFF current in NMOS.

III. PMOS DC CHARATERISTICS PMOS characteristics are analyzed same as NMOS, but with proper terminal voltage orientation. PMOS is created on n-type substrate. Source and bulk are connected to ground to avoid any body effect. Drain is connected with positive terminal of V1 voltage and gate is connected with negative terminal of the V2 voltage. All the polarities have been reversed and so is the direction of the current. Now the current flows from source towards drain. Fig.15. shows the schematic for the PMOS transistor along with the terminal voltages.

Fig. 14. OFF Current in NMOS at V1=0 and V2 = 1V The off current for NMOS was found to be 25.065nA. The device off-current is a function of the channel length(L) and the channel width (W) of the device. It is comprised of device channel current at Vg = 0 V, which is an exponential function of channel length, and device corner current, which depends on the device width. As channel length decreases, I_off increases exponentially. In the fig.14. above shows the Subthreshold leakage current. The source-bulk junction and the drain-bulk junction are nothing but PN junctions. So even when there is no channel existing between source and drain due to zero gate voltage, still reverse leakage currents flow in between due to minority charge carriers. The junction leakage current occurs from the source or drain to the substrate through the reverse biased diodes when a transistor is OFF. Subthreshold or weak inversion conduction current between source and drain in an MOS transistor occurs when gate voltage is below VTH.

Fig. 15. PMOS Test bench schematic Analysis starts with single ISD vs VSD curve which is obtained by swiping VSD voltage from 0 to 1V with 100mV linear increment steps and fixing V SG to be 500mV. Fig.16. shows IV graph for VSG =500mV.

Fig. 16. ISD Vs VSD curve at VSG = 500mV

A. Output I-V Characteristics Using parametric analysis tool, multiple I SD vs VSD graph were obtained for different VSG. Here V1 and V2 both swiped from 0 to 1V with 100mV linear increment steps. Fig.17. shows these graphs. From this graph we identified about three modes operation Cut-off, Triode and Active. As can be seen from the curves, the current ISD vary with VSD in saturation.

Fig.19. Second order Output Resistance

Fig. 17. ISD Vs VSD Output Curves - Parametric Analysis of V1 (VSG) B. Output Resistance (rsd) Output resistance is given by the change in source voltage with respect to the change in source current when gate voltage is constant. The inverse of derivative of the slope of the ISD vs VSD curve gives the output resistance rsd. Analog Environment tool Calculator, in the Cadence CAD tool, is used to calculate and plot output resistance rsd. Second and third order rsd values are also calculated and plotted. The plots for the output resistance rsd, second order rsd and third order rsd are shown in the Fig.18, Fig.19 and Fig.20 respectively. Fig..20. Third order Output Resistance

C. Transconductance (gm) The transconductance (gm) of a PMOS device is defined as the change in source-drain current (ISD) due to change in source-gate voltage (VSG) at constant VSD. According to the IDS equation, ISD = k' (W/L) (VSG-VT) 2 the relationship between ISD and VSG is non-linear since the current is proportional to the square of V SG. Hence we can expect a parabolic curve. The ISD-VSG input curve was plotted by DC analysis of VSG by linearly sweeping it from 0-1V in steps of 10mV, at VSD = 500mV. The Fig. 21 shows the ISD Vs VSG input I-V curve for the PMOS device. Using parametric analysis tool different ISD VS VSG are plotted by swiping VSD from 0 to 1V and linear steps 100mV. The ISD VS VSG input I-V curves for different values of VSD are shown in the Fig. 22. Second and third order gm values are calculated and plotted using the Cadence calculator tool. The plots for the transconductance (gm), second order gm and third order gm are shown in the Fig. 23, Fig. 24 and Fig. 25 respectively.

Fig. 18. Output Resistance (rsd)

Fig. 21. ISD Vs VSG curve at VSD = 500mV

Fig. 24. Second order gm

Fig. 22. ISD Vs VSG Input Curves - Parametric Analysis of V2 (VSD)

Fig. 25. Third order gm The values of the transconductance can be obtained from the ISD-VSG curves by calculating the derivative of their slope by using the derivative function in the calculator tool. The curves for the transconductance for various values of VSD are shown in the Fig. 26.

Fig. 23. Transconductance (gm)

TABLE II Maximum transconductance values and VSG values for different VSD values

VSD (volts)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

VSG (volts)
0.602 0.604 0.704 0.802 0.903 1 1 1 1 1

gm (A/V) or(S)
16.86 29.43 38.57 44.81 49.02 51.79 53.91 55.47 56.73 57.80

If we compare the transconductance values for NMOS and PMOS, we can see that NMOS has higher transconductance values than that of PMOS which means that electron mobility is higher in NMOS than holes mobility in PMOS. So we can come up with conclusion that NMOS has better current output. D. OFF-State Current It is observed that there some current flows through the transistor even when the input voltage is zero. This current is known as OFF-State current. OFF current is calculated by performing the transient analysis of the device for 1ns at V1=0 and V2 = 1V. Fig. 27. shows the OFF current in PMOS.

Fig. 26. gm plots for different values of V SD The above curves show that after attaining its maximum value gm starts to decrease. In the triode region transistor act as resister and channel formed is uniform in this region. Therefore output current I SD changes linearly with the input voltage V SG. The transconductance (gm) is a measure of change in ISD with respect to change in VSG. In Active region ISD becomes function of (VSG-VT). As (VSG-VT) increases and goes close to VS the channel gets pinched-off near source junction as it becomes more reverse biased and the increased depletion region pushes the channel in, near the source junction. This causes the velocity saturation of the charge carriers (holes in this case). Hence, the current saturates and thus further change in the VSG does not change the current ISD beyond its saturation value ISD-SAT. Therefore further increase in the VSG, gm decreases. The current also depends upon higher order derivatives of VSG which become negative after a certain value of VSG for a given VSD. Adding these negative values to the value of gm decreases the total output. As can be seen, the values of gm start decreasing after the first order derivative becomes zero. Hence to find the maximum value of gm, we need to measure gm when the (partial derivative of gm with respect to VSG) = 0. The values of V1 (VSG) for maximum gm along with maximum gm values are shown below in TABLE II.

Fig. 27. OFF Current in PMOS at V1=0 and V2 = 1V The off current for PMOS was found to be 29.383pA. The off current value for PMOS is less than that of for the NMOS. By observing off state current values for both NMOS and PMOS we can say that for switching application PMOS has better performance.

IV. CONCLUSION In this assignment, the main goal is to get familiarize with the Cadence design tool and to see the characteristics of the NMOS and PMOS of the generic 45nm CMOS technology. We see that the current equations for the MOSFETs depend upon more than one parameter. The transconductance of the transistor decreases as the gate voltage reaches a saturation point as the mobility of the carriers gets saturated which is mainly due to the velocity saturation. Parameters such as channel length/width, the gate oxide thickness, grain boundary barrier lowering effect for which the mobility of carriers will also decease due to contact pressure. Sub threshold leakage is responsible for the small current even when the transistor is off. And as the size of the transistors and thickness of the insulating region are decreased leakage increases exponentially.

REFERENCES [1] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill Publication, 2002. [2] Paul R. Gray, P.J. Hurst, S.H. Lewis and Robert G.Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, Wiley, 2001. [3] S.M.Sze, Semiconductor and Physics [4] Sedra and Smith, Analog Circuit Design [5] http://en.wikipedia.org/wiki/MOSFET [6] http://en.wikipedia.org/wiki/Transconductance [7] http://web.cs.mun.ca/~paul/transistors/node1.html [8]http://newton.ex.ac.uk/teaching/resources/rjh/phy3 129/par t3L8.p