CS305ComputerArchitecture Autumn2010 Lecture04

BhaskaranRaman DepartmentofCSE,IITBombay
http://www.cse.iitb.ac.in/~br/ http://www.cse.iitb.ac.in/synerg/doku.php?id=public:courses:cs305autumn10:start

Today'sTopics

TheMIPSinstructionset(continued)

Branchinginstructions Instructionencoding

TestYourUnderstanding...

Whatisthemaximumarrayindexwhichcanbe supportedinasingleloadinstruction

Assumethatthearrayisof32bitintegers

Isasubiinstructionneeded?Whyorwhynot? Issubinstructionneeded?Whyorwhynot? Ifthenumberofregistersisincreasedto64,what implicationdoesithaveontheinstructionencoding?

TestYourUnderstanding(continued)...

TranslatethefollowingCcodeintoassemblylang.:

Ex1:a[300]=x+a[200];//all32bitint Whatmoreinformationdoyouneed? Ex2:a[300]=x+a[i+j];//all32bitint Canyoudoitusinginstructionsknowntoyousofar?

#ains0,xins1 #iins2,jins3 add $t2,$s2,$s3 muli $t2,$t2,4 add $t3,$t2,$s0 lw $t0,0($t3) add $t1,$t0,$s1 sw 1200($s0),$t1

#ains0,xins1 lw $t0,800($s0) add $t1,$t0,$s1 sw 1200($s0),$t1

NotionofRegisterAssignment

Registersarestaticallyassignedbythecompilerto registers Registermanagementduringcodegeneration:oneof theimportantjobsofthecompiler Examplefrompreviousexercise...

Instructionsfor BitWiseLogicalOperations
Logical C/C++/Java Operators Operators Shift Left << Shift Right >> Bit-by-bit AND & Bit-by-bit OR | Bit-by-bit NOT ~ MIPS Instructions sll srl and, andi or, ori nor

InstructionEncoding

Encoding:representinginstructionsasnumbers/bits

Recall:instructionsarealsostoredinmemory! Encoding==(assemblylanguage>machinelanguage)

MIPS:allinstructionsareencodedas32bits(why?) Also,allinstructionshavesimilarformat(why?)

MIPSInstructionFormat
opcode (6) rs (5) rt (5) rd (5) shamt (5) funct (6)

R-type instruction: register-register operations

opcode (6) rs (5) rt (5) immediate/constantoroffset (16)

I-type instruction: loads, stores, all immediates, conditional branch, jump register, jump and link register
opcode (6) offsetrelativetoPC (26)

J-type instruction: jump, jump and link, trap and return

TheNotionoftheProgramCounter

Program (inmemory) PC

InMIPS:(only)specialinstructionsfor PCmanipulation PCnotpartoftheregisterfile Insomeotherarchitectures:arithmetic ordatatransferinstructionscanalsobe usedtomanipulatethePC

Theprogramisfetchedand executedinstructionby instruction ProgramCounter(PC) Aspecial32bitregister Pointstothecurrent instruction Forsequentialexecution PC+=4foreach instruction Nonsequentialexecution Implementedthrough manipulationofthePC

BranchingInstructions

Storedprogramconcept:usuallysequential execution Manycasesofnonsequentialexecution:

Ifthenelse,withnesting Loops Procedure/functioncalls Goto(badprogrammingnormally) Switch:specialcaseofnestedifthenelse

Instructionsetsupportfortheseisrequired...

ConditionalandUnconditionalBranches

Twoconditionalbranchinstructions:

beq <reg1>,<reg2>,<branch_target> bne <reg1>,<reg2>,<branch_target> j <jump_target>

Anunconditionalbranch,orjumpinstruction:

Branch(orjump)targetspecification:

Inassemplylanguage:itisalabel Inmachinelanguage,itisaPCrelativeoffset

Assemblercomputesthisoffsetfromtheprogram

UsingBranchesforIfThenElse
if(i==j){f=g+h;}else{f=gh;} #Conventioninmyslides: #s0,s1...assignedtovariables #inorderofappearance #s0isi,s1isj #s2isf,s3isg,s4ish bne $s0,$s1,ELSE add $s2,$s3,$s4 j EXIT ELSE: sub $s2,$s3,$s4 EXIT: #Furtherinstructionsbelow

UsingBranchesforLoops
while(a[i]==k)i++;

#s0isa,s1isi,s2isk BEGIN: sll $t0,$s1,2 add $t0,$t1,$s0 lw $t1,0($t0) bne $t1,$s2,EXIT addi $s1,$s1,1 j BEGIN EXIT: #Furtherinstructionsbelow

TestingOtherBranchConditions

slt <dst>,<reg1>,<reg2>

slt==setlessthan <dst>issetto1if<reg1>islessthan<reg2>,0otherwise

slti <dst>,<reg1>,<immediate> Howabout<=or>or>=comparisons? Canbefollowedbyabneorbeqinstruction Note:register0intheregisterfileisalwaysZERO

Denoted$zerointheassemblylanguage Programsuse0incomparisonoperationsveryfrequently

Whynotsinglebltorbltiinstruction?

ForLoop:AnExample
for(i=0;i<10;i++){a[i]=0;}

#s0isi,s1isa addi $s0,$zero,0 BEGIN: slti $t0,$s0,10 beq $t0,$zero,EXIT sll $t1,$s0,2 add $t2,$t1,$s1 sw 0($t2),$zero j BEGIN EXIT: #Furtherinstructionsbelow