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phase-locked loop

def ini ti on

A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-


driven oscillator that is constantly adjusted to match in phase (and thus lock on) the
frequency of an input signal. In addition to stabilizing a particular communications
channel

Design fundamentals

Figure 1. Feedback System

Figure 2. Phase locked loop

Parameter Definition

The Laplace Transform permits the representation of the time response f(t) of a system in
the complex domain F(s). This response is twofold in nature in that it contains both
transient and steady state solutions. Thus, all operating conditions are considered and
evaluated. The Laplace transform is valid only for positive real time linear parameters;
thus, its use must be justified for the PLL which includes both linear and nonlinear
functions. This justification is presented in Chapter Three of Phase Lock Techniques by
Gardner.

Using servo theory, the following relationships can be


obtained.2

These parameters relate to the functions of a PLL as shown


in Figure 2.

The phase detector produces a voltage proportional to the phase difference between the
signals qi and qo/N. This voltage upon filtering is used as the control signal for the
VCO/VCM (VCM – Voltage Controlled Multivibrator). Since the VCO/VCM produces a
frequency proportional to its input voltage, any time variant signal appearing on the
control signal will frequency modulate the VCO/VCM. The output frequency is

From another source much simpler:

Outline
1•Basic PLL system
2•Basic circuit block
3–Phase detector
4•Analog mixer
5•Digital 3 state Phase Frequency Detector
6•Charge pump circuit
7–Filter
8–Voltage Controlled Oscillator
9•Pull-in process
0•System characteristics (frequency and time response)
10–With 1st order filter
11–With Lag-Lead filter
12•Delay Locked Loop
13•Clock recovery circuits
14•Frequency synthesizer
Application Area:
11.Internal clock generation in LSI locked to external clock
22.Frequency Synthesizer for communication systems
33.Clock recovery for communication systems and data storage systems
44.FM demodulation

Frequency Synthesizer

Clock Recovery

PLL is a feedback system to match the input signal phase and the output
signal phase.
Through this process, frequencies of these signals become
equal completely.
WAVEFORM IN PLL SYSTEM
Analog phase detector (mixer type)

3 state Phase Frequency Detector


This 3 state phase detector is currently most widely
used.
Because it has a ability for frequency detect.
Dead Zone in PFD
The most serious issue of PFD is dead zone at a
small phase deviation.
This causes a large jitter and a phase noise.