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Flow
Wipro Technologies
Innovative Solutions, Quality Leadership
EagleWison FPGA Design Flow
Architecture
WIPRO's FPGA Design Centre leverages on domain expertise in telecommunica
tions, networking and embedded systems, to define the functional architecture of
the design. This, coupled with the FPGA /ASIC Design expertise, enables the team
to come out with efficient optimized architecture, which can easily fit into the se
lected FPGA, meeting the timing and other criteria).
! Definition of FPGA architecture: Data and Control Flow, On-chip buses, Buffering
strategies, Register implementation, clocking and synchronization schemes, IO
definition, functional / physical partitioning, integration of soft/hard IP blocks.
EagleWise ASIC Design Handbook along with ETCH (Early Timing Closure
Hacker.) & FACT (FPGA Area Closure Tracker focusing on Architecture/Design
Optimization techniques catering to FPGA Designs) enables “best practices”
framework by capturing guidelines on Architecture, design partitioning, RTL
coding, low power designs, high performance designs etc. These guidelines
enable the chosen architecture to achieve the performance goals with no or
minimum number of iterations.
! Selecting the FPGA device based on Systematic approach. FPGA Device Selection
Guide provides set of guidelines and considerations
! FACT Methodology for controllability over FPGA resources right from architecture
stage. It provides a comprehensive set of area estimation guidelines coupled
with a tracker to control FPGA area within budget. It aids the designer with an
exhaustive collection of area optimization techniques
! Assigning the I/Os, obeying the electrical DRC and to ease out the Board Layout.
I/O Planning makes use of in-house tools to generate top level RTL with dummy
logic and vendor specific tools, to do the pin assignments and DRC checking.
! Based on the pin assignment, FPGA Schematic Part Symbols are generated
automatically using in-house scripts.
FPGA Configuration Strategy is planned as per the system requirement.
Logic Design
! Checklists are used for reviewing the design and checklists cover various
aspects like Timing, Area, I/O assignments etc.
! Proven ETCH methodology (Early Timing Closure Hacker) for early timing
closure of FPGA designs. The principle behind ETCH is that of Design for
Timing Closure. ETCH provides powerful set of Design guidelines for timing
closure norms, guidelines and techniques.
! Directory structure that is suitable for design, verification, synthesis and FPGA
fitting.
! Special relationship with tool vendors helps to support peak tool demand
Verification Planning
! Early identification of verification strategy
! All levels of verification planned: block level, multi-block module level, Full
Chip/ FPGA level. Depending on the need, system level as well as hard
ware-software co-verification is also planned.
! Traceability matrix to link verification test cases with each attribute of design
under test
RTL Coding
! Coding in Verilog or VHDL
! HDL Coding Guidelines (as defined in the EagleWise ASIC Design Hand
book) to ensure consistent style of coding
! Coding Tips from FACT & ETCH to achieve the best design performance.
! Mandatory code purification using SCOUR, Wipro's own linting and having
interface to HDL lint tools like ExploreRTL. Linting is performed to weed out
coding problems of synthesizability, testability, simulation-synthesis mis
match, and coding guidelines violations.
Verification Design
! Design of Verification Environment and test cases
Verification Coding
! High level abstraction using languages like C, Vera, Specman etc. that
allows faster development of test cases
Functional Verification
! Unit Level Verification using simple HDL Based environment. Usage of Unit
Level Test Plan and Code Coverage metrics as exit criteria.
! Code coverage framework called HDLCov (based on tools like HDL Score,
Verification navigator) to run code coverage of Design Under Test
! Use of metrics (test completeness, earned value, defect arrival trend, etc.) to
enable decision making and resource planning
! Industry standard synthesis tools like Synplify, FPGA Compiler and Vendor
specific Fitting tools are used.
! Familarity with leading FPGA vendors like Xilinx, ALTERA & LUCENT
! Usage of Industry standard tools like Amplify (Floor planning & Synthesis),
Synplify and FPGA Compiler
! FACT & ETCH provides some tool specific optimization techniques.
! Vendor specific fitting tools are made use of, for this purpose
! Testing and Debugging is done as per system level test plan to validate the
FPGA Design.