338

Third-Order Phase-Locked Loops using Dual LOOPS with Improved Stability

Minoru Kamata, Takashi Shono, t Takahiko Saba, Iwao Sasase, and $Shinsaku M o r i
Dept. of Electrical Engineering, Keio University 3- 14-1 Hiyoshi, Kohoku, Yokohama, 223 Japan E-mail:kamata@mori.elec.keio.ac.j p tDept. of Electrical and Computer Engineering, Nagoya Institute of Technology $Dept. of Electrical and Electronics Engineering, Nippon Institute of Technology

Abstract- A third-order PLL has an instability problem. It is known that the system of dual loops improves the instability and suppresses a steady-state error of the third-order PLL. A conventional third-order PLL using dual loops is implemented by digital equipment. Since the digital PLL cannot be used at high frequency band in satellite communications because of limitation of the operational frequency, the conventional third-order PLL using dual loops are unavailable such an environment. In this paper, we propose a new third-orderPLL using dual loops which are implemented by analog equipment. We investigate the transient response and the steadystate behavior of the proposed PLL due to the frequency ramp transition. Results show the steady-state phase error of the proposed PLL is suppressed. Furthermore, we show the stability of the proposed PLL is better than that of the typical third-order PLL.

I. INTRODUCTION
Phase-locked loops (PLLs) have been played an important role in communication systems, such as for bit timing estimation, demodulation, and frequency synthesis. Typical applications of the PLL can be found in analog modulators and demodulators. When a received signal of the PLL has frequency step transition, a perfect second-order PLL which suppresses the steady-state error has been generally used [1],[2]. In mobile communication systems, an input signal of the PLL has not only the frequency step transition, but also the frequency ramp transition because of Doppler shift and multipath fading. In addition, the second-order PLL must track carrier frequency offset in transmission systems. However, a perfect second-order PLL cannot suppress the steady-state phase error in environments where the received signal has the frequency ramp transition. Therefore a third-order PLL is required in wireless communications with the large fre-

quency transition. One of the standard third-order PLLs is a perfect thirdorder PLL which consists of two active filters. However, perfect third-order PLL is unstable when a loop gain is lower than the threshold [2]. To improve instability of the third-order PLL, a thirdorder PLL with dual loops was proposed in [3]. Since the dual-loop is superior to the perfect second-order PLL in transient response[4], the third-order PLL with dual loops is stable against any loop gain, and can suppress the steadystate phase error. However, the third-order PLL with dual loops need to be implemented by the digital equipment, because voltage-controlled oscillator (VCO) g a n factor of the first loop should be equivalent to that of the second loop. If the VCO gain factor of the first loop is different from that of the second one, the steady-state error becomes infinite and the PLL cannot get to synchronize. Since it is impossible to make the VCO gain factors in the analog PLL the same value, the conventional third-order PLL using dual loops cannot be implemented by the analog equipment. In satellite communications in which subcarrier is transmitted at high-frequency band, PLL cannot be implemented by digital equipment because of high operational frequency. Thus the analog third-order PLL is required in satellite communications in which there is frequency ramp transition. There is also need for the analog third-order PLL to improve stability and to suppress the steady-state error like the digital system. In this study, we propose a new third-order PLL using d u d loops with improved stability which is implemented by the analog equipment. At first, we establish the closed-loop transfer function of the proposed PLL. As a result, we can obtain steady-state phase error when input signals have frequency ramp transition. Next, to investigate transient behavior, we use Runge-Kutta-Gill method to the loop equation. We can evaluate transient behavior of the proposed PLL. Finally, we evaluate the stability of the proposed PLL

0-7803-3905- 3/97/$1O.OO@ 1997 IEEE

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where
1-1

= RIC,

72

= R2C.

The closed-loop transfer function H ( s )is

: PD gain factor

: :
:

Figure 1: A equivalent block diagram of the proposed PLL.

:

by the Routh-Hurwitz criterion and by the root locus plot. 11. SYSTEM MODEL

in the first loop (Vhad), VCO gain factor in the first loop (radsN), PD gain factor in the second loop (Vlrad), VCO gain factor in the second loop (radlsN), loop gain in the first loop (radh), loop gain in the second loop (rads), time constant of the filter (sec).

IV. STEADY-STATE PHASE ERROR

A equivalent block diagram of the proposed PLL is shown in Fig. 1. In the first loop, phase error is not filtered by any loop filter. First loop has no filter, the second loop has an active filter. So the output of a phase detector (PD) in the first loop is directly added to the output of the loop filter in the second loop. The output of the VCO in the second loop is practically the output signal of the proposed PLL. Though the proposed PLL has the active filter in the first loop, the conventional third-order PLL using dual loops has it in the second loop. As described above, a system model of the proposed third-order PLL with dual loop is different from that of the conventional third-order PLL.
111. TRANSFER FUNCTION OF THE PLL
x

Next, the steady-state behavior of the proposed PLL is discussed. Let us consider the steady-state error resulting from a step change of input phase, AB, frequency, Aw, and acceleration, R. So the input signal (in the frequency domain) is given as follows:

ei,(s)
4~
=
-

Aw

+ S.

A0

(4)

The phase error is obtained from ( 3 ) , and(4) as

(-+-+-).
s3

[I - ~ ( s ) i e ~ , ( s ) q s3 + KQ, (Kv, - K&)TI s2 (S + K1)(71s2 K27-2~ K2) + + R Aw A0

$2

In this section, we carry out linear analysis of the proposed PLL under assumption that there is no noise and PD characteristic is liner. We can write the closed-form transfer function of the proposed loop according to the fundamental loop equations, provided that loop filter in the second loop is an active filter. The transfer function E ( s ) of a LPF used in this analysis is given by

(5)

The phase error in (5) is evaluated by means of the finalvalue theorem of Laplace transform. The steady-state phase error is given as

1 +72s F ( s ) = -,
7 1s

According to (6), the steady-state phase error of the proposed PLL depends on acceleration, R of the input signal.

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Table 2: Parameters of the proposed PLL. lame I : I ne steaay-state pnase error or various r u s .

Perfect secondorder PLL

#

Phase error (in the frequency domain) Steady-state phase error S . -R sz + Ks +Kzl s3
0.1

0.25MHzN 0.001 sec 0.001 sec

Perfect third-

order PLL
#

Conventional third-order PLL using dual loops

-0.4

Proposed third-order PLL using dual loops

0.001

0.002

0.003

0.004

0.005

time (sec)
Figure 2: Transient phase error due to a step in frequency.

Therefore if R is zero, the steady-state error will be zero regardless of the values of A0 and Aw. Table 1 shows the steady-state phase error of various PLLs. In addition, # in Table 1 are derived from [ 11, [2]. When VCO gain factor in the first loop, Kw , is equivalent to that of the second loop, K v , , the steady-state error of the proposed PLL becomes zero. In case of,the third-order PLL with dual loops implemented by the digital equipment, if the VCO gain factor of the first loop is different from that of the second one, the steady-state error becomes infinite and therefore the PLL cannot get to synchronize.
V. TRANSIENT RESPONSE

- = R-Kg2-+K$,--+K$,-4
dt2 dt
72

dz

71

d4 dt

1
71

(8)

We investigate the transient response of the proposed PLL. Although the transient response is obtained by the inverse Laplace transform of (51, use numerical calculation we by the method of Runge-Kutta-Gill for simplicity. Replacing s of ( 3 ) by d/dt, we can obtain the following two differential equation relative to the phase error, #J.
.dz - =

Table 2 shows the parameters of the transient response for the numerical calculation. The frequency step response is shown in Fig. 2, where initial frequency ramp, initial frequency step, and initial phase error are all zero. The ratio of VCO gain in the first loop, Kv, to loop gain in the second loop, K h is 0.98. From Fig. 2 it is apparent that there is no steady-state error resulting from a step change of frequency, Aw. In addition, since transient response due to the frequency step is independent of the ratio Kv, /Kv,, we only show Fig. 2 in case the ratio is 0.98. Next, the frequency ramp response is shown in Fig. 3. When a received signal of the proposed PLL has frequency ramp transition, the steadystate phase error exists. If we can set the ratio Kv,/Kv, close to zero, we can suppress the steady-state error to be almost zero. VI. STABILITY We consider stability of the proposed PLL by using Routh-Hunvitz Criterion. The stability condition II is expressed as follows:

dt

Rt+Aw- Kb,Kv,z

(7)

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0.002

9 &
-8-

0.0015

g
6,

0.001

2 c a

0.0005

I
0
0.001 0.002

0.003

0.004

0.005

time (sec)
Figure 3: Transient phase error due to a ramp in frequency. Figure 4: Root locus plot of the proposed PLL.

n=

K*{KlKV, +KlK2(?) + &($)I

K 1

+K2(3

(9)

ACKNOWLEDGMENTS This work is partly supported by Ministry of Education, The Telecommunication Advancement Foundation, and International Communications Foundation.

Since every variable of the equation is positive, we can find that the system of the proposed PLL is stable. We show transient response and stability of the proposed loop graphically by using root-locus plot. In the conventional third-order PLL, if the locus enters the right half-plane for low values of gain, the loop is unstable. This is in contrast to the first order loops and second-order loops, which are unconditionally stable for all values of gain [2]. Figure 4 shows the root-locus plot of the proposed loop. So the locus of the proposed PLL does not exist in the right half-plane, the stability of the loop is independent of the loop gain, K1 and K2, and the proposed PLL is stable in every condition. As a result, we can find the proposed PLL is superior to the conventional third-order PLL at stability.

REFERENCES
[ 13 A. J. Viterbi, Principles of Coherent Communications,

McGraw-Hill, 1966.

[2] Floyd M. Gardner, Phaselock Techniques, 2nd ed., John Wiley & Sons, 1979.
[3] Shin-ichiro Nakajima, Masafumi Hagiwara and Masao Nakagawa, Robust third-order DPLL against input frequencyjuctuation IEICE Trans., vol. J71-A No. 2, pp. 418-425, 1988.(in Japanese)
[4] Taiichiro Kurita and Shinsaku Mori, Pelformance of a dual-phase-lock LOOPIEICE Trans., vol. J63-A NO.9, pp. 545-561, 1980.(in Japanese)

VII. CONCLUSION
In this paper, we have proposed new third-order PLL with improved stability. The proposed system consists of dual loops in which that the second loop has active filter, and can be implemented of analog system. At first, we obtain the closed-loop transfer function of the proposed PLL, and derive steady-state phase error when input signal has frequency ramp transition. Next, we consider the transient response by numerical calculation and evaluate transient behavior of the proposed PLL. Finally, we evaluate the stability of the proposed PLL by the Routh-Hurwitz criterion and by the root-locus plot. It is shown that the proposed PLL is stable in every condition.