A 2-GHz CMOS LC-Tuned VCO

using Switched-Capacitors to
Compensate for Bond Wire
Inductance Variation

Nathan Sneed
University of California, Berkeley

December 21, 2000

 i

Contents
INTRODUCTION 1
OSCILLATORS IN RADIO TRANSCEIVERS 3
2.1 Frequency Translation and Channel Selection.........................................................3
2.2 Important Performance Specifications.....................................................................5
2.2.1 Phase Noise..........................................................................................................................5
2.2.2 Power Consumption.............................................................................................................7

LC-TUNED OSCILLATORS 9
3.1 Oscillator Overview .................................................................................................9
3.1.1 Two-Port (Feedback) View ................................................................................................10
3.1.2 One-Port (Negative Resistance) View................................................................................11
3.2 Phase Noise............................................................................................................11
3.2.1 One-Port View....................................................................................................................11
3.2.2 Two-Port View ...................................................................................................................13
3.2.3 Characterization .................................................................................................................14
3.2.4 Tank Q................................................................................................................................14
3.2.5 Leeson’s Model..................................................................................................................16

VOLTAGE-CONTROLLED OSCILLATOR DESIGN 19

4.1 Topology and Design Procedure ............................................................................19
4.1.1 Active circuit......................................................................................................................20
4.1.2 Bond Wire as Inductor .......................................................................................................25
4.1.3 Capacitor Array and Varactor ............................................................................................27
4.1.4 Tank Q................................................................................................................................32
4.2 Specific Design Description...................................................................................35
4.2.1 Capacitor Array and Varactor ............................................................................................35
4.2.2 Tank Q................................................................................................................................38
4.2.3 Active Circuit.....................................................................................................................38
4.2.4 Complete Schematic ..........................................................................................................43
4.3 Simulation Results .................................................................................................43
4.3.1 Frequency Tuning ..............................................................................................................43
4.3.2 Output Voltage ...................................................................................................................45
4.3.3 Phase Noise........................................................................................................................46
4.3.4 Summary ............................................................................................................................48

CONCLUSION 49
REFERENCES 51
 1

CHAPTER 1

Introduction

A critical building block of almost any wireless or wireline transceiver is the local oscilla-

tor (LO). When used with a mixer, the LO allows frequency translation and channel selec-

tion of radio frequency (RF) signals. The LO is typically implemented as a phase-locked

loop (PLL), wherein a voltage-controlled oscillator (VCO) is phase-locked to a high-sta-

bility crystal oscillator. A VCO is basically comprised of a gain element and a resonator.

The resonator determines the oscillation frequency, and when it is composed of energy-

storing inductors and capacitors, it is often referred to as an LC tank. A voltage-controlled

varactor diode allows the oscillation frequency of the VCO to be varied.

The most critical performance specification for an oscillator is phase noise. In a

receiver, the phase noise of the LO limits the ability to detect a weak signal in the presence

of a strong signal in an adjacent channel. In a transmitter, phase noise results in energy

being transmitted outside of the desired band. To help minimize phase noise, we need

high-Q (low-loss) inductors and capacitors.

2
As the demand for smaller, cheaper, and more power-efficient mobile wireless trans-

ceivers continues to increase, manufacturers strive to integrate as much of the transceiver’s

circuitry onto a single piece of silicon. However, it has been difficult to integrate high-Q

and tight-tolerance inductors in a standard, and thus inexpensive, IC fabrication process. A

desirable approach takes advantage of the self-inductance of bond wires, which are neces-

sary to connect the silicon IC to the package leads. However, fabrication processes can

result in bond wire length variation of up to ±40% from the desired length, and hence also

from the desired inductance. Since we need to achieve some nominal oscillation fre-

quency, the effect of this bond wire length variation must be eliminated.

This report focuses on the design of a 2-GHz CMOS LC VCO which uses an array of

switched capacitors to tune out the inductance variation caused by bond wire length varia-

tion. The switch configuration needed to achieve nominal oscillation frequency would be

determined and set during manufacturing. Two cross-coupled PMOS devices are used for

the oscillator’s gain element. The switches are implemented with 0.18-µm channel-length

NMOS devices. For this technique to provide any advantage, the LC-tank Q must not suf-

fer appreciably due to the channel on-resistances of the NMOS switches. Fortunately, it

does not, as will be shown with hand calculations and Spectre simulations.
 3

CHAPTER 2

Oscillators in Radio
Transceivers

Oscillators play a critical role in communication systems, providing the periodic signals

needed for the timing of digital circuits and for frequency translation. While “oscillator”

can mean anything that exhibits periodically time-varying characteristics, we are con-

cerned with the type that provides an electrical signal (voltage or current) at a specific fre-

quency when supplied only with DC power. When used for frequency translation, we

often refer to an oscillator as the local oscillator (LO), as opposed to oscillators used as

clocks for timing digital circuits. While LOs and clocks can be derived from the same

basic oscillator, we will focus on the function, performance, and design of oscillators used

as LOs for frequency translation in radio transceivers.

2.1 Frequency Translation and Channel Selection

The front-end of a typical receiver is shown in Fig. 2.1, where the mixer and LO are used

to downconvert the incoming radio frequency (RF) signal to a lower, intermediate fre-

quency (IF). Since the IF frequency is fixed, we select the channel of interest by varying
4

RF IF
LNA

LO

Figure 2.1 Simplified receiver block diagram.

Phase
Detector VCO
Reference Loop
Input Output
Filter

÷M

Figure 2.2 Phase-locked loop.

the frequency of the LO. Assuming a low-side LO is being used (the LO frequency is

lower than the RF frequency), the IF frequency is given by:f IF = f RF – f LO.

The LO is often implemented as a phase-locked loop (PLL). A typical PLL is made up

of a voltage-controlled oscillator (VCO), a low-pass loop filter, a phase detector, and a fre-

quency divider, as shown in Fig. 2.2. A PLL is used because it forces the output frequency

to be exactly equal to the frequency of the input signal. With the addition of a frequency

divider in the loop, frequency multiplication can be achieved. If the divider has value M,

then the output frequency will be M times the input frequency. Furthermore, if the divider

value is adjustable, we can generate different LO frequencies by simply changing M.

Thus, a fixed, low-frequency (~10 MHz) reference oscillator can be used to generate mul-

tiple LO frequencies in the low-GHz range.

 5
Within the so-called loop bandwidth of the PLL, the output contains noise characteris-

tics of the reference signal, the phase detector, the loop filter, the divider, and the VCO.

Outside the loop bandwidth, the output only contains the noise characteristics of the VCO.

Therefore, the spectral purity of the VCO influences that of the LO, which in turn impacts

the spectrum of the downconverted RF signal.

Having identified the role of the VCO in a transceiver, the rest of the report shall focus

on the performance and design of a VCO. Since a VCO is just an oscillator whose fre-

quency can be controlled by varying a voltage, the terms “VCO” and “oscillator” can be

considered synonymous for the remainder of this report.

2.2 Important Performance Specifications

The most critical specification for any oscillator is its spectral purity, usually characterized

by phase noise. Since many wireless transceivers such as mobile phones are battery-pow-

ered, we also strive to minimize power consumption. There is a trade-off between phase

noise and power consumption up to a point, beyond which increased power consumption

cannot be tolerated by practical devices.

2.2.1 Phase Noise

Ideally, the spectrum of an oscillator is an impulse located at a single frequency. However,

in any practical oscillator, the spectrum has power distributed around the desired oscilla-

tion frequency ω0, in addition to power located at harmonic frequencies, as shown in Fig.

2.3. This undesirable power distribution around the desired oscillation frequency is known

as phase noise. The origins of phase noise will be discussed in Section 3.2.
6

Power
Density

ω
ω0 2ω0 3ω0

Figure 2.3 Practical oscillator spectrum.

RF
Interfering
Signal

Desired
Signal
ω

LO

IF
Interfering
Signal
Desired
Signal
ω

Figure 2.4 SNR degradation due to phase noise.

To understand the negative effect of phase noise, consider the receiver front-end of

Fig. 2.1. As shown in Fig. 2.4, when trying to receive a signal in one channel in the pres-

ence of a stronger signal in an adjacent channel, the phase noise of the LO is modulated

onto the stronger signal at IF, thereby reducing the signal-to-noise ratio (SNR) of the

desired signal at IF. This phenomenon is often referred to as reciprocal mixing, and limits

how close together channels can be placed [1]. Similarly, in a transmitter, LO phase noise
 7
is modulated onto the desired signal, resulting in unwanted energy being transmitted out-

side of the desired band.

2.2.2 Power Consumption

As will be shown in Section 3.2, phase noise is inversely proportional to the power dissi-

pated in the resistive part of the resonant LC tank. This seems to suggest that an arbitrarily

small phase noise can be achieved by simply increasing the bias current, but there are

practical limitations as to how small phase noise can be made.

As bias current is increased, so is the VCO’s output voltage amplitude. However, any

CMOS transistor has a maximum voltage that cannot be exceeded without permanent

damage. Also, in the usual situation where the n-well in a PMOS device is tied to the

power supply, the drain cannot exceed the power supply voltage by more than about 0.6

volts before the drain-well diode is turned on, resulting in clipping of the output voltage.

As a result, bias current is usually limited by the process. Moreover, since the VCO is

likely to be incorporated in a battery-powered transceiver, we would like to minimize cur-

rent consumption to maximize battery life.

8
 9

CHAPTER 3

LC-Tuned Oscillators

In this chapter, we will focus on the analysis of oscillators whose frequency of oscillation

is determined by the resonant frequency of parallel LC tank. CMOS ring oscillators are an

easy-to-integrate alternative, but they exhibit inferior phase noise performance for a given

power dissipation [2] and thus are not considered in this report.

3.1 Oscillator Overview

An electrical oscillator generates a periodically time-varying signal when only supplied

with DC power. Any oscillator can usually either be viewed as a single, two-port, feedback

circuit or as two one-port circuits connected together. Which viewpoint we chose is often a

matter of preference or convenience, and depends on the circuit in question. However,

some active circuits such as tunnel-diodes are inherently one-port [1].

10

Si(s) a(s) So(s)

+
+

f(s)

Figure 3.1 Ideal linear feedback model.

3.1.1 Two-Port (Feedback) View

Consider the linear feedback model shown in Fig. 3.1. The overall transfer function from

input to output is given by

So( s ) a(s)
------------- = ------------------------------ (3.1)
Si( s ) 1 – a(s) f (s)

We note that this system can have a non-zero output without any input as long as

a(s) f (s) = 1 (3.2)

which is known as the Barkhausen criterion. The quantity a ( s ) f ( s ) is often called the

loop gain.

For (3.2) to be satisfied, the magnitude of the loop gain must be equal to one and the

phase shift around the loop must be equal to zero. As will be described in Section 4.1.1,

we typically design for an initial loop gain magnitude greater than one and rely on nonlin-

earities in the amplifier to reduce the magnitude to exactly one in steady-state operation.

Assuming a ( s ) has zero phase shift, we can implement f ( s ) as a resonator having zero

phase shift at the desired oscillation frequency. Such a resonator is often realized with a

parallel LC tank.
 11

Active
Resonator Circuit

RT –Ra

Figure 3.2 One-port view of an oscillator.

3.1.2 One-Port (Negative Resistance) View

Another way to view an oscillator is given in Fig. 3.2. The oscillator is broken up into two

one-port networks: an active circuit and a resonator. To achieve steady-state oscillation,

the equivalent parallel resistance RT of the resonator must be exactly balanced by a nega-

tive resistance –Ra produced by the active circuit. When this condition is satisfied, the cir-

cuit becomes lossless, the equivalent parallel resistance becomes infinite, and oscillation

results. Essentially, any energy dissipated in RT is replenished with energy introduced by

the active circuit [1].

3.2 Phase Noise

As described in Section 2.2.1, any practical oscillator exhibits phase noise. As with oscil-

lators, there are one-port and two-port views of phase noise.

3.2.1 One-Port View

An equivalent one-port model of an LC oscillator is shown in Fig. 3.3. All noise sources in

the circuit are combined into a single current source, i n ( ω ) , with mean square noise cur-
12

L C RT Active
in(ω)
Circuit

–Ra

Figure 3.3 One-port model of an LC oscillator.

2
rent density i n ⁄ ( ∆ω ) . Assuming linear time-invariant behavior, total noise power den-

sity P n ( ω ) ⁄ ( ∆ω ) can be calculated as

2
Pn ( ω ) in
--------------- = -------- ⋅ Z ( ω ) (3.3)
∆ω ∆ω

and includes the effects of the noise on both phase and amplitude [2]. Since practical oscil-

lators have some mechanism for limiting amplitude, amplitude noise is suppressed. There-

fore, the total noise power density is only due to phase noise, and is typically half the value

given in (3.3). It also should be pointed out that the above is based on a linear time-invari-

ant approach, and any practical oscillator is neither linear nor time-varying. As a result,

low-frequency flicker (or 1 ⁄ f ) noise is modulated onto the carrier. Nonetheless, (3.3) is a

good first-order estimate of phase noise [2].

This LTI process of conversion of noise current to phase noise is depicted in Fig. 3.4.

Note the importance of the tank’s frequency response in determining the shape of the

phase noise sidebands [2].

Two ways to decrease phase noise are suggested by (3.3) and Fig. 3.4. First, we should

minimize the number of noise sources in the oscillator. Since active devices are major con-

tributors of noise, we should use as few transistors as possible. Second, the tank’s magni-
 13

2
i
n
------
∆ω

|ZT(ω)| RT

Pn ( ω )
----------------
∆ω

Figure 3.4 Conversion of noise current to phase noise.

tude response Z ( ω ) should be made as narrow as possible, as will be discussed in

Section 3.2.4.

3.2.2 Two-Port View

Returning to the two-port model shown in Fig. 3.1, we now consider f ( s ) to be a parallel

RLC tank as shown in Fig. 3.5a. The magnitude and phase responses of such a network

are given in Fig. 3.5b. As discussed in Section 3.1.1, we need zero degrees net phase shift

around the feedback loop (any integer multiple of 360 degrees). Since noise sources in the

oscillator circuit will cause temporary phase shifts in the feedback loop, the instantaneous

oscillation frequency will be changing such that the tank produces a compensating phase

shift, keeping the total phase shift around the loop equal to zero. Thus, phase noise can

also be viewed as short-term instability in the frequency of oscillation [2].

14

ZT L C RT

(a)

ZT
∠Z T
RT +90º

–90º
ω
ω0 ω0

(b)

Figure 3.5 (a) Parallel RLC tank. (b) Magnitude and phase response.

3.2.3 Characterization

Phase noise is usually characterized by a quantity called single sideband noise spectral

density, denoted L{∆ω}and defined as

P 1Hz ( ω 0 + ∆ω )
L { ∆ω } = 10 ⋅ log -------------------------------------- (3.4)
Ps

where P 1Hz ( ω 0 + ∆ω ) represents the single sideband power measured in a 1-Hz band-

width and located at a frequency offset ∆ω from the oscillation frequency ω 0 . P s repre-

sents the total signal power. A typical plot of L{∆ω}is shown in Fig. 3.6. Note the

existence of regions of various slopes, as discussed in [2].

3.2.4 Tank Q

In Section 3.2.1, we saw how the frequency response of the RLC tank largely determines

the shape of the phase noise sidebands. To reduce the phase noise, we would like the mag-
 15

L { ∆ω }
1
-----
3
f

1
-----
2
f
1
---
f

Figure 3.6 General appearance of single-sideband phase noise.

nitude response of the tank to be as sharp as possible (i.e. have a very narrow bandwidth).

A measure of the sharpness of a tank’s magnitude response is its quality factor, or simply

its Q. We will look at three equivalent definitions of Q which are relevant to oscillators [1].

The first definition of Q is based on the magnitude response of the tank. Given the res-

onant frequency ω 0 and the 3-dB bandwidth ω 3dB , we have

ω0
Q = ------------------
- (3.5)
2 ⋅ ω 3dB

Thus, for a fixed ω 0 , Q increases as the 3-dB bandwidth decreases, corresponding to a

sharpening of the peak in the magnitude response.

The next definition of Q incorporates the phase response at the resonant frequency and

is defined as

ω
Q = -----0- dφ (3.6)
2 dω

To understand the usefulness of this definition, recall the necessary condition of zero net

phase shift in the feedback loop at the oscillation frequency. Any deviation in oscillation

frequency develops a phase shift which violates this condition, thus forcing the oscillation
16
frequency back to ω 0 . The definition of Q in (3.6) reveals that higher Q corresponds to

higher phase slope, and thus stronger opposition to any deviation in oscillation from ω 0 .

The last definition of Q is

Es
Q = 2π  ------ (3.7)
 E d

where E s is the peak energy stored in L or C per cycle and E d is the energy dissipated in

R per cycle. We can use this definition to compute the Q of a parallel RLC tank as

QT = RT ⁄ ( ω0 L ) = ω0 RT C (3.8)

In addition, the definition of (3.7) is useful for calculating the Q of a network that is more

complicated than a parallel RLC tank.

3.2.5 Leeson’s Model

A well-known phase noise model known as Leeson’s model was derived using a linear

time-invariant approach, and predicts the following for L { ∆ω } :

 2FkT ω0 2 ω 3 
L { ∆ω } = 10 ⋅ log  -------------- ⋅ 1 +  ---------------- ⋅  1 + -------------
1⁄ f 

(3.9)
P  2Q∆ω   ∆ω
 s 

In (3.9), F is an empirically-determined parameter; k is Boltzmann’s constant; T is temper-

ature in kelvins; P s is the average power dissipated in the equivalent parallel resistance of

the tank; ω 0 is the oscillation frequency; Q is the quality factor of the tank; ∆ω is the off-
2
set from the oscillation frequency; and ω is the corner frequency between the 1 ⁄ f
1⁄ f
3

3
and 1 ⁄ f regions (as shown in Fig. 3.6) [2].

Examining (3.9), we note that phase noise is inversely proportional to the average

power dissipated in the tank resistance. This implies that phase noise performance can be
 17
improved by increasing the oscillation voltage amplitude. Second, we see that phase noise

is inversely proportional to the square of Q. Hence, as previously discussed, we should

strive to achieve the maximum Q possible.

18
 19

CHAPTER 4

Voltage-Controlled Oscillator
Design

A 2-GHz voltage-controlled oscillator (VCO) has been designed in a 0.18-µm CMOS pro-

cess. The VCO uses switched capacitors to tune out the bond wire inductance variation

that occurs as a result of fabrication. This chapter covers the design process and SpectreRF

simulation results.

4.1 Topology and Design Procedure

An oscillator is composed of two basic blocks: an active circuit and a resonator. For a

VCO, a varactor is also needed for continuous frequency tuning. In addition, this design

includes a capacitor array for discrete frequency tuning, which is used to compensate for

bond wire inductance variation. This section discusses the specific circuits chosen to

implement these functions.

20

VDD

M0 M1

M2 M3

Vout1 Vout2

Tank Tank

Figure 4.1 PMOS differential oscillator.

4.1.1 Active circuit

For the active part of the oscillator, a differential topology using cross-coupled PMOS

FETs was chosen, as shown in Fig. 4.1. Advantages of a differential topology include: (1)

rejection of common-mode supply and substrate noise; (2) differential output (good for

driving Gilbert mixers); (3) convenient high-frequency IC realization. There are no signif-

icant disadvantages for an IC realization of a differential oscillator [3].

PMOS transistors were chosen over NMOS due to their superior noise characteristics.

The disadvantage of using PMOS devices is the additional bias current needed to achieve

the same transconductance gm as an identically-sized NMOS device. However, the addi-

tional power dissipation was considered acceptable.

Minimum channel-length devices (0.18 µm) were used to minimize parasitic drain

capacitance due to M2 and M3. Since the tank will be connected to the drains of these

devices, their drain capacitances will affect the oscillation frequency. Although these

capacitances can be taken into account during the design of the varactor and capacitor
 21

M2 M3

Rin

it vt

(a)

it

vt -vt
2 2

(b)

Figure 4.2 (a) Test circuit to determine negative resistance. (b) Differential-mode half-circuit of
(a).

array, we would like to minimize them in order to maximize the frequency tuning range

for a given varactor capacitance range.

Taking a one-port view of the VCO, the active circuit shown in Fig. 4.1 represents a

small-signal negative resistance between the output terminals Vout1 and Vout2. The value of

the resistance can be computed by placing a test voltage source vt between the output ter-

minals, as shown in Fig. 4.2a [9]. Note that because the oscillator operates in purely differ-

ential mode, the sources of M2 and M3 do not experience any (small-signal) voltage
22

M2 M3

RT C L L C RT

Figure 4.3 Small-signal AC equivalent for feedback analysis.

variation, and are thus shown grounded. Analyzing the differential-mode half-circuit

shown in Fig. 4.2b reveals that

v 2
R in = ----t = – ------ (4.1)
it gm

where gm is the transconductance of a single device. To ensure oscillation, we must make

R in ≥ – 2R T , where RT is the equivalent parallel resistance of a single-ended tank (two sin-

gle-ended tanks in series comprise the differential tank). This implies that we need

1
g m ≥ ------ (4.2)
RT

Now consider the small-signal AC equivalent of the oscillator with a parallel RLC

tank, as shown in Fig. 4.3. Using a feedback approach on this circuit, the small-signal loop

gain Al as a function of s is found to be

2
Al ( s ) = [ gm Z T ( s ) ] (4.3)

where gm is the transconductance of a single device and Z T ( s ) is the tank impedance. At

the resonant frequency of the tank, (4.3) reduces to

2
Al = ( gm RT ) (4.4)
 23
For a small-signal loop gain of one, we see that the conditions given by (4.2) and (4.4)

are equivalent. Typically, gm is chosen to set Al to a value from three to five, resulting in

right-hand-plane poles and ensuring oscillation start-up [3]. In addition, the Barkhausen

criterion says that the steady-state large-signal loop gain must be identically one to sustain

oscillation. This is represented as

2
( G mL R T ) = 1 , (4.5)

where GmL is the large-signal transconductance of M2 and M3. Combining (4.4) and (4.5),

we arrive at the steady-state amplitude condition [3]:

G mL 1
---------
- = --------- (4.6)
gm Al

The voltage amplitude at the oscillator’s output is determined by nonlinear behavior in

the FETs, and is given by the fundamental of drain current I1 multiplied by RT. Because

the cross-coupled topology forces one FET’s drain-source voltage, VDS, to be equal to the

other FET’s gate-source voltage, VGS, the FETs experience all three regions of operation

(cutoff, saturation, and triode) during any oscillation period. Due to this complicated

behavior, computer simulations have been performed and curves have been generated (not

by the author, however) that allow determination of the FET sizes and bias currents via an

iterative process. These curves are shown in Figs. 4.4 and 4.5, where V0 is the peak sinuso-

idal output voltage amplitude, V A – V T = I L ⁄ k 1, IL is the DC bias current through a sin-

1 W
gle FET, k 1 = --- µC ox ----- , VA is equal to VGS without oscillation, VT is threshold voltage,
2 L
and I1 is the fundamental drain current amplitude [3].

The general procedure for using these plots begins with simulations to determine k1

for different channel widths. Given the load RT, the fundamental drain current amplitude I1
24

Figure 4.4 Computer-generated curves to determine biasing and sizes of cross-coupled FETs

necessary to achieve a desired V0 can be calculated. Also, for a desired Al, (4.6) gives the

required G mL ⁄ g m . Then iterating on Fig. 4.4, we find the V A – V T = I L ⁄ k 1 needed to

achieve this G mL ⁄ g m . With this V A – V T , Fig. 4.5 is used to get I 1 ⁄ I L . Finally, a unique

device width and bias current will simultaneously satisfy the values found for I 1 ⁄ I L and

I L ⁄ k1 .
 25

Figure 4.5 Computer-generated curves to determine biasing and sizes of cross-coupled FETs

4.1.2 Bond Wire as Inductor

As discussed in Chapter 3, low phase noise corresponds to high tank Q. Typically, the Q of

the tank’s inductor is the limiting factor in overall tank Q. Standard chip-to-package bond

wires are used as the inductors in this VCO design due to an expected Q of at least 20 at 2

GHz [4]. An integrated alternative is to use spiral inductors, but their low Q (less than ten)

makes them undesirable.

Any bond wire inductor has a series resistance associated with it. This resistance is

directly related to the resistivity of the metal, as well as the skin effect at high frequencies
26
[10]. The Q of an inductor with a series resistance R s can be determined using the defini-

tion of (3.7), and is given by

QL = ( ω0 L ) ⁄ Rs (4.7)

It is shown in [6] that for values of Q greater than ten (the situation here), we can convert

series resistance R s into an equivalent parallel resistance R p . with the following relation-

ship:

2
R p = QL ⋅ Rs (4.8)

For a typical bond wire, the inductance to resistance ratio is constant. Thus, no matter

what the value of L, Q L does not change. However, for larger values of L, the series resis-

tance R s increases. Since we desire high equivalent parallel resistance, (4.8) suggests that

we choose the largest value for L possible.

How large L can be made is limited by the maximum length of a bond wire, which var-

ies depending on a number of factors. According to [4], a typical length is 5 mm. Since the

rule of thumb for bond wire inductors is 1 nH/mm, a nominal value of 5 nH was chosen

for L.

While their high Q is attractive, the main problem with using bond wire inductors is

the length—and hence inductance—variation that occurs during fabrication. The worst

variation that can be expected is ±40% [5]. Since we need to design for a nominal oscilla-

tion frequency, this variation needs to be “tuned out” somehow. As will be described

below, an array of switched capacitors is well-suited for this task.

 27

Cv,min – Cv,max Ca,min – Ca,max Cp

Figure 4.6 Tank capacitances.

4.1.3 Capacitor Array and Varactor

Because the oscillation frequency is determined by the tank’s resonant frequency

ω 0 = 1 ⁄ ( LC ) , the tank capacitance C can be adjusted to compensate for variation in

bond wire inductance L. Due to the large inductance variation, a large capacitance range is

needed, ruling out the use of only a varactor for compensation. The solution described in

this report uses a switched-capacitor array and varactor together to form the capacitive

portion of the tank. As illustrated in Fig. 4.6 the tank capacitance is formed by a varactor

diode capacitance that varies from C v, min to C v, max , a capacitor array that varies from

C a, min to C a, max , and a parasitic capacitance C p . In essence, this structure provides

coarse (stepped) tuning via the capacitor array and fine (continuous) tuning via the varac-

tor. Continuous tuning is required when the VCO is used in a phase-locked loop.

To determine how to size the capacitors, switches, and varactor, we start with the

desired continuous tuning range, f min to f max, and inductance range, L min to L max . The

widest range of total tank capacitance needed to tune from f min to f max corresponds to the

lowest inductance value L min (a result of the nonlinear relationship between inductance
28
and capacitance for a given resonant frequency). The minimum and maximum capacitance

values that define this range are given by:

Lmin 2 –1
C t, min = [ ( 2π ⋅ f max ) ⋅ L min ] (4.9)

Lmin 2 –1
C t, max = [ ( 2π ⋅ f min ) ⋅ L min ] (4.10)

Because the tuning from f min to f max needs to be continuous, the varactor must be
Lmin Lmin
able to tune over the difference ( C t, max – C t, min ) . Given the varactor tuning voltage limi-

tations imposed by the maximum signal voltage swing, simulations are used to determine

maximum change in varactor capacitance per unit area ∆C va . Once this process-depen-

dent parameter is determined, the minimum required varactor area can be calculated as

Lmin Lmin
C t, max – C t, min
A v, min = ------------------------------------
- (4.11)
∆C va

In practice, Av should be chosen larger than the value given by (4.11) to give the varactor a

wider capacitance range and to ensure some capacitance overlap between different capaci-

tor array settings. However, Cv,min increases as Av increases, due to characteristics of the

varactor. An upper bound on the minimum total tank capacitance is given by

2 –1
C t, min = C a, min + C v, min + C p ≤ [ ( 2π ⋅ f max ) ⋅ L max ] (4.12)

and represents the case of maximum inductance Lmax and tuning to fmax. Hence, Av must

be chosen larger than (4.11), but small enough so that the corresponding Cv,min will satisfy

(4.12). Also note that the varactor area required to tune across an arbitrary fmin and fmax

may result in a value for Cv,min that exceeds the limit of (4.12), in which case the range of

fmin to fmax and/or the range of Lmin to Lmax will need to be reduced.
 29

Cmm 2Cmm 2n-1Cmm

VSW1 VSW2 VSW8

W 2W 2n-1W
0.18 Cdd 2Cdd 2n-1Cdd
0.18 0.18

Figure 4.7 General binary-weighted capacitor array.

For the minimum inductance Lmin, the maximum capacitance available from the array

Ca,max and the minimum varactor capacitance Cv,min are required to achieve fmax. Thus, to
Lmin
achieve C t, min as calculated above, Ca,max is determined by:

Lmin
C a, max = C t, min – C v, min – C p (4.13)

where C p is the parasitic drain capacitance of the active device. Once the active portion of

the oscillator is designed, simulations can be used to determine C p .

When at the maximum inductor value L max , the total tank capacitance must be able to

adjust to a low enough value to achieve the maximum oscillation frequency f max. There-

fore, C a, min is given by

2 –1
C a, min = [ ( 2π ⋅ f max ) ⋅ L max ] – C v, min – C p (4.14)

At this point, the physical implementation of the varactor (its area) has been deter-

mined, but not the physical implementation of the capacitor array. The general binary-

weighted capacitor array is shown in Fig. 4.7, where Cmm represents the capacitance of a

metal-metal capacitor and Cdd represents parasitic drain capacitance. To maintain a con-

stant Q for each switch/capacitor pair when the switches are on, as each capacitor size

doubles, the channel on-resistance must halve. Therefore, the NMOS switch widths are

also binary-weighted (since channel resistance is inversely proportional to channel width),

30
and consequentially, the parasitic drain capacitances associated with each switch are

binary-weighted too. To completely specify the array, we must determine the number of

switch/capacitor pairs n, the switch width W, and the metal-metal capacitor value C mm to

enable an adjustment range from C a, min to C a, max .

In the case when all of the switches are off, each element of the array consists of a

metal-metal and parasitic drain capacitance in series, giving the minimum capacitance of

the array:

 1 1  –1  1 1  –1  1 1  –1
C a, min = ----------- + --------- + -------------- + ------------ + … +  ----------------------
- + --------------------- (4.15)
 C mm C dd  2C mm 2C dd  2 n – 1 C mm 2 n – 1 C dd

When all switches are on, each parasitic drain capacitance is essentially shorted out by a

switch, giving the maximum capacitance of the array:

n
C a, max = ( 2 – 1 )C mm (4.16)

Since the values of Ca,min and Ca,max are known, we would like to solve (4.15) and (4.16)

simultaneously to get expressions for Cmm and Cdd. Doing so results in:

C a, max
C mm = ----------------
n
(4.17)
2 –1

C a, max ⋅ C a, min
C dd = ---------------------------------------------------------------
n
- (4.18)
( 2 – 1 ) ( C a, max – C a, min )

Finally, we use the value for Cdd found with (4.18) to determine the switch width W. Since

drain capacitance per unit channel width, denoted Cddw, is approximately constant for a

given channel length, we have

W = C dd ⁄ C ddw (4.19)
 31

Lmin
C t, min
∆Cv

Lmin
C t, min + C s t e p
∆Cv

Col

Figure 4.8 Effect of capacitance array step size on continuous tuning range.

The only remaining array parameter to be determined is n, the number of elements in

the array. Recall that most capacitance range is required when the inductance is Lmin,

given by (4.9) and (4.10). This range must be covered by the varactor once the array steps

from its minimum value Ca,min to ( C a, min + C step ) , where Cstep is the array step size

given by:

C a, max – C a, min
C step = --------------------------------------
n
- (4.20)
2 –1

As illustrated by Fig. 4.8, between these two array capacitance values, there is a range of

capacitance overlap Col that either capacitor array setting can accommodate by adjusting

the varactor (note that ∆C v = C v, max – C v, min ). In order to ensure that the range defined

in (4.9) and (4.10) does not straddle Col, thereby preventing continuous tuning, Col must
Lmin Lmin
be made larger than ( C t, max – C t, min ) . The upper bound on Cstep is therefore:

Lmin Lmin
C step ≤ ∆C v + C t, min – C t, max (4.21)

Using the result of (4.21) in (4.20), a minimum value for n can be found.
32

Lmax Cmm 2Cmm 2n-1Cmm

Cv

RLmax Cdd 2Cdd 2n-1Cdd

Figure 4.9 Tank when all switches are off.

4.1.4 Tank Q

The proposed benefit of using a switched-capacitor array is to allow high-Q bond wires to

be used for tank inductance. However, the advantages of using high-Q inductors must not

be negated by a low-Q capacitor array. Therefore, this section discusses the impact of the

channel on-resistances of the switches on the tank Q, represented by QT.

First consider the case when the inductor is at its maximum value Lmax and the lowest

array capacitance Ca,min is needed. This situation corresponds to all switches off, and the

resulting tank is shown in Fig. 4.9. For Q L > 10 , we can convert the series resistance
2
RLmax to a parallel resistance by multiplying by Q L , giving

2
RT Q L R Lmax
QT = -----------------
- = ---------------------
- = QL (4.22)
ω 0 L max ω 0 L max

Thus, the tank Q is simply equal to the inductor Q since none of the capacitors contribute

any loss (recall that we assume inductor Q is independent of inductance for a bond wire).

Now consider the other extreme when the inductor is at its minimum value Lmin and

the highest array capacitance Ca,max is needed. This situation corresponds to all switches

being on, and results in the lowest tank Q for any switch setting (because all n channel on-
 33

Lmin Cmm 2Cmm 2n-1Cmm

Cv
Ron Ron
RLmin Ron
2 2n-1

(a)

2
2 2 Q C R on
Lmin Q L R Lmin Cv Cmm Q C R on 2n-1C mm
2n-1

(b)

Lmin (2n-1)Cmm + Cv RT

(c)

Figure 4.10 (a) Tank when all switches on. (b) Equivalent circuit of (a) for Q > 10. (c) Simplified
version of (b).

resistances are present). The resulting tank circuit is shown in Fig. 4.10a. Recall that QC is

the same for each switch/capacitor pair as a result of the binary weighting and is given by:

1
Q C = --------------------------- (4.23)
ω 0 R on C mm

To compute the Q of the circuit in Fig. 4.10a, we multiply each resistance in series with a
2
capacitor by Q C to convert to an equivalent parallel resistance, giving the circuit of Fig.

4.10b. Combining all resistance and capacitance results in the circuit of Fig. 4.10c, where

RT is given by

2 2 2
Q C R on Q C R on Q C R on
RT =
2
Q L R Lmin || 2
Q C R on || ---------------
- || … || ---------------
- = Q L ω 0 L min
|| ---------------
- (4.24)
2 n–1 n
2 2 –1
34
Using (4.24), we can calculate minimum tank Q (when inductance is at as Lmin and all

switches are on):

2
RT Q L Q C R on
Q T , min = ----------------- = -------------------------------------------------------------------
- (4.25)
ω 0 L min n
( 2 – 1 )Q L ω 0 L min + Q C R on
2

To put (4.25) in a more convenient form, we start with the square-law relationship for Ron:

W –1
R on = µC ox ----- ( V GS – V t ) (4.26)
l

As (4.26) shows, to minimize the channel resistance of a switch in the on state, we use the

maximum VGS allowable (usually VDD). However, because (4.26) is based on a square-law

assumption that may deviate significantly from reality, it is best to simulate Ron to deter-

mine a factor to replace µC ox ( V GS – V t ) . We will denote this factor k, defined by:

W
k = R on ⋅ ----- (4.27)
l

Now we can transform (4.25) into a formula only containing the basic parameters

Ca,min, Ca,max, Lmin, QL, Cddw, ω0, and k. Using the relationships of (4.7), (4.17), (4.18),

(4.19), (4.23), (4.25), and (4.27), and after some algebraic manipulation, we arrive at the

following expression for minimum tank Q as a function of switch channel length l:

C a, min Q L
Q T , min ( l ) = ------------------------------------------------------------------------------------------------------------------------------
3
- (4.28)
C a, min + C a, max ( C a, max – C a, min )C ddw L min Q L ω 0 lk

Note that (4.28) is not dependent on n, the number of capacitors in the array. Once we con-

sider a specific oscillator design and IC process, we will use (4.28) to generate plots of

QT,min vs. l for various inductor tolerances.

 35

4.2 Specific Design Description

Using the topology and design procedures discussed in Section 4.1, a 2-GHz VCO has

been implemented and simulated in a 0.18-µm CMOS process. The basic design goal was

to successfully use a switched-capacitor array to tune out ±40% bond wire inductance

variation around a nominal value of 5 nH, while maximizing the continuous frequency

tuning range.

4.2.1 Capacitor Array and Varactor

The first step in designing the varactor is to determine the available voltage control range.

For the thin-oxide 0.18-µm channel length devices used in this design, the maximum ter-

minal-to-terminal voltage is 1.95 V. According to the design rules for this process, a

greater voltage will likely result in permanent damage to the device. Considering the oscil-

lator topology of Fig. 4.1, we note that the gate of M2 experiences the drain voltage of

M3, and vice-versa. Also note that the single-ended output voltage will swing symmetri-

cally above and below ground (positive and negative) since it is taken across an inductor

connected to ground. Hence, each FET’s gate and drain experience equal and opposite

voltages, and therefore the peak (single-ended) output voltage must be less than half of the

1.95-V maximum, or 975 mV. To allow some margin for safety, we will design for a peak

(single-ended) output voltage of 900 mV. Then, to ensure that the varactor is never for-

ward-biased, its control voltage VC must be greater than 300 mV (assuming a 600-mV

diode turn-on voltage). If we also assume that the maximum supply voltage available is

1.8 V, VC can therefore vary from 300 mV to 1.8 V.

36
Y x 10
varacdata
740.00
720.00
700.00
680.00
660.00

Cap/Area (aF/um^2)
640.00
620.00
600.00
580.00
560.00
540.00
520.00
500.00
480.00
X
0.00 1.00

Reverse bias voltage (V)

Figure 4.11 Simulated varactor characteristics.

Simulations were performed to determine the capacitance per unit area of the p+/n-

well diode used as the varactor, and the results are shown in Fig. 4.11. From this data, we

can determine the change in capacitance per unit area ∆C va as the control voltage varies

from 300 mV to 1.8 V, giving

2
∆C va = 0.171 fF/µm . (4.29)

Considering ±2% continuous tuning about 2 GHz, we have

f min = 1.96 GHz (4.30)

f max = 2.04 GHz (4.31)

 37
Also recall that the most varactor capacitance range is needed for L min = 3 nH . Then

from (4.9) and (4.10)

Lmin
C t, min = 2.03 pF (4.32)

Lmin
C t, max = 2.20 pF (4.33)

2
From (4.11) we get the minimum varactor area A v, min = 987 µm . To get slightly more

tuning range out of the varactor and keeping the restriction of (4.12) in mind, we increase

the area to

2
A v = 1020 µm (4.34)

From the varactor characteristics shown in Fig. 4.11, this varactor area corresponds to

C v, min = 0.496 pF (4.35)

C v, max = 0.671 pF (4.36)

Assuming a parasitic drain capacitance Cp of 0.1 pF (determined by simulation), (4.13)

and (4.14) give

C a, max = 1.44 pF (4.37)

C a, min = 0.274 pF (4.38)

From (4.20) and (4.21), the minimum number of capacitor array elements is calculated to

be

n = 8 (4.39)

Then (4.17) and (4.18) give

C mm = 5.62 fF (4.40)

C dd = 1.33 fF (4.41)
38
Finally, simulation determined that C ddw = 1.28 fF/µm , and so (4.19) gives

W = 1.0 µm (4.42)

4.2.2 Tank Q

With all tank parameters calculated as above for tuning out ±40% bond wire inductance

variation, the minimum tank Q can now be found. Using a VGS of 1.8 V to turn on the

switches, k defined in (4.27) was determined through simulation to be 4300 Ω. For a 2-

GHz oscillation frequency, assuming Q L = 20 , and using minimum channel length (0.18

µm) devices for the switches, (4.28) results in Q T , min = 11.8 . Since spiral inductors typ-

ically have Q’s of less than ten, the switched capacitor array approach is an improvement.

For inductance variations less than ±40%, less switched capacitance is required, and

there will be an improvement in minimum tank Q. Still considering ±2% continuous tun-

ing about 2 GHz, the tank design procedure of Section 4.1.3 can be repeated for different

inductor tolerances. For each inductor tolerance, we would then have a different set of tank

parameters to plug into (4.28), and hence a different plot of QT,min vs. l. This was done for

the additional inductor tolerances ±10%, ±20%, and ±30%, and for bond wire Qs of 20,

40, and 60. The results are shown in Fig. 4.12. Note that these curves are specific to the

0.18-µm process considered here.

4.2.3 Active Circuit

One side effect of using a switched-capacitor array is that the actual tank impedance pre-

sented to the oscillator is not known during the design. Depending on the switch setting, a

range of equivalent parallel tank resistances are possible. This presents a minor complica-
 39

X Graph
Y Inductor Tolerance
L
+/- 10%
19.00 L L K
L +/- 20%
L M
18.00 L +/- 30%
L O
K
K
+/- 40%
17.00
K
16.00 K
K
15.00 M K
Minimum Q
M
14.00
M
13.00 M

12.00 M
O M
11.00 O

10.00 O

9.00 O
O
8.00
O
X x 10-3
200.00 300.00 400.00
Switch channel length (nm)

(a)
X Graph
Y InductorTolerance
Inductor Tolerance
L
+/- 10%
36.00 L K
L +/- 20%
34.00 L M
L +/- 30%
L O
32.00 L +/- 40%
K
30.00 K
28.00 K

26.00 K
K
Minimum Q

24.00 M K
M
22.00
M
20.00
M
18.00 M
16.00 O M
O
14.00
O
12.00 O
O
10.00 O
X x 10-3
200.00 300.00 400.00
Switch channel length (nm)

(b)

Figure 4.12 Minimum tank Q vs. switch channel length for 0.18-µm process, 2-GHz oscillation
frequency, and (a) QL=20; (b) QL=40.
40

X Graph
Y Inductor Tolerance
L
+/- 10%
L K
50.00 L +/- 20%
L M
+/- 30%
L O
45.00 L +/- 40%
L
K
40.00 K
K
Minimum Q

35.00
K
K
30.00 M K
M

25.00 M
M
20.00 M
O M
O
15.00 O
O
O
10.00 O
X x 10-3
200.00 300.00 400.00
Switch channel length (nm)
(c)

Figure 4.12 (c) Minimum tank Q vs. switch channel length for 0.18-µm process, 2-GHz
oscillation frequency, and QL=60.

tion since knowledge of the load is integral to designing the oscillator to achieve a desired

output voltage swing and small-signal loop gain. By considering the two extremes of the

array (all switches on and all switches off), we can find a compromising solution.

In the case when all switches are off, the inductance is L max = 7 nH . We are assum-

ing Q L = 20 . The equivalent parallel resistance of the tank is maximum for this case, and

is given by:

R T , max = Q L ω 0 L max = 1760 Ω (4.43)

When all switches are on, the inductance is L min = 3 nH . The on-resistance of the small-

est switch was determined through simulation with V GS = 1.8 V :

R on = 750 Ω (4.44)
 41
With switches on, each capacitor has the same Q:

1
Q C = --------------------------- = 18.9 (4.45)
ω 0 R on C mm

Finally, the equivalent parallel resistance of the tank for this case is given by (4.24):

R T , min = 438 Ω (4.46)

From (4.43) and (4.46), we see that the minimum and maximum tank resistances differ by

a factor of four.

Assume the active circuit is designed with enough gm to achieve a peak output voltage

of 900 mV and a small-signal loop gain of three into a load of RT,max. Then by (4.4), when

the load is RT,min, the small-signal loop gain Al will be reduced by a factor of

R T , max 2
 ----------------
- = 16 (4.47)
 R T , min 

Clearly, this is not a viable solution since Al could be as low as 3/16, meaning the oscilla-

tor would never start up. Now consider designing for a load of RT,min. In this case, if the

load happened to be RT,max, then the peak output voltage would be four times 900 mV,

exceeding the maximum voltage rating for the devices. The compromise is to design the

active circuit to produce 900 mV peak output voltage for a load of RT,max, but for a small-

signal loop gain that is 16 times the minimum desired loop gain of three. Thus, following

the design procedure outlined in Section 4.1.1, bias current and device channel widths

were determined to achieve A l = 3 ⋅ 16 = 48 and 900-mV peak output voltage into a

load of 1760 Ω. The result is I D = 425 µA and W = 35 µm .

A simple current mirror was used as the bias circuit, as shown in Fig. 4.1. We would

like the sources of M2 and M3 to see a high impedance looking into the drain of M1 to
42
degenerate their noise. For a given bias current, this is achieved by increasing the channel

length of M1 as much as possible while still keeping the device in saturation [7]. For

small-signal operation, the noise contribution of M1 would not be considered because it

divides equally between each side of the differential pair and does not appear at the differ-

ential outputs. The oscillator differential pair, however, is operating in a large-signal, non-

linear, and time-variant fashion. Therefore, the noise from M1 cannot be ignored.

Although flicker noise is low-frequency, the nonlinear behavior of the oscillator modulates

it onto the output signal, resulting in increased phase noise [1]. Since flicker noise is given

by

2 K 1
v n = ---------------- --- , (4.48)
WlC ox f

we can see that not only does increasing M1’s channel length reduce the noise of M2 and

M3 via degeneration, but it also acts to reduce its own flicker noise.

The channel width of M1 should be chosen as small as possible to reduce its parasitic

drain capacitance, but large enough to keep M1 in saturation (both in order to keep the

drain impedance high). This implies biasing M1 on the border between triode and satura-

tion (i.e. such that V GS – V th = V DS ). Since the sizes and bias currents of M2 and M3

have already been chosen, the bias voltage at the source connection of M2 and M3 is fixed,

and thus M1’s VDS is fixed. As a result, a unique W/l ratio for M1 exists that will place it

on the triode/saturation border.

A trade-off clearly exists since we would like a long channel length, a small channel

width, and a constant W/l ratio. Periodic noise simulations were performed using

SpectreRF for various W and l values (keeping W/l constant) to determine the size of M1
 43
that results in the minimum noise at a 3-MHz offset from the 2-GHz carrier frequency.

This particular offset frequency was chosen since it is a critical specification for GSM [8].

The optimum values were found to be W = 40 µm and l = 1 µm .

4.2.4 Complete Schematic

Fig 4.13 shows a schematic of the complete VCO design. The entire capacitor array is not

shown due to size constraints, but the capacitances and switch widths follow a binary pro-

gression (i.e. 1, 2, 4, 8,..., 128). Also note that RL depends on the value of L, and is set such

that Q L = 20 .

4.3 Simulation Results

SpectreRF 4.4.6 was used to perform periodic steady-state (PSS) and periodic noise

(PNOISE) analyses on the oscillator of Fig. 4.13.

4.3.1 Frequency Tuning

To determine the continuous tuning range available at the inductor extreme of 3 nH, all

switches were turned on by applying 1.8 V to their gates. PSS analyses were then per-

formed with the varactor control voltage VC at 0.3 V and 1.8 V. The resulting tuning range

is 1.955 GHz to 2.038 GHz, not quite achieving the desired fmax of 2.04 GHz. With the

inductor set to 7 nH, all switches were turned off by grounding their gates, and PSS analy-

ses were run for the two varactor extremes. In this case, a tuning range of 1.848 GHz to

2.044 GHz was achieved.

 44
1.8 V

4 40
1 1

85 µA

35 35
0.18 0.18

Vout1 Vout2

Cmm 2Cmm 128Cmm L L Cmm 2Cmm 128Cmm

VC

VSW1 VSW2 VSW8 VSW1 VSW2 VSW8

W 2W 128W W 2W 128W
0.18 0.18 0.18 RL RL 0.18 0.18 0.18

Figure 4.13 Complete VCO schematic

 45

(a)

(b)

Figure 4.14 (a) Single-ended output waveforms with all switches on. (b) Single-ended output
waveforms with all switches off.

4.3.2 Output Voltage

Transient analyses were performed for each inductor extreme. The single-ended output

voltage waveforms are shown in Figs. 4.14a and 4.14b. The peak differential output volt-

age with all switches off is 1.83 V, close to the desired value of 1.8 V. The output drops to

380 mV with all switches on, due to the decreased tank resistance. Although the tank
46
resistance only changes by a factor of four, we observe the output voltage drop by a factor

of almost five. This is a result of the active devices operating in a different nonlinear

regime with less drain current fundamental than designed for in Section 4.2.3.

4.3.3 Phase Noise

Periodic noise analyses were performed at each inductor extreme. Total output noise den-

sity as a function of frequency for each case is shown in Figs. 4.15a and 4.15b. With this

noise data and the output voltage amplitude data from Section 4.3.2, single-sideband

phase noise was computed as follows:

2 ( RMS noise voltage density ) dBc

L = 20 ⋅ log ----------------------------------------------------------------------------- ----------- (4.49)
Peak differential output voltage Hz

The phase noise at a 3-MHz offset frequency with the inductor at 3 nH and all switches on

is –126 dBc/Hz. With the inductor at 7 nH and all switches off, the phase noise at a 3-MHz

offset is –131 dBc/Hz.

It is worth noting that there is only a 5-dB difference in phase noise between the cases

of all switches on and all switches off. A purely linear time-invariant approach to phase

noise, as represented by (3.9), suggests that phase noise would change by a factor of

2
 R T , max Q T , max  1759 20 2 
L max – L min ≈ 20 log  ----------------- ⋅ ----------------
- = 20 log  ------------ ------------2 = 21 dB (4.50)
 R T , min Q 2T , min   438 11.8 

To get to the root of this discrepancy, the noise due to individual devices was examined.

According to the periodic noise analysis, M1 is the dominant noise contributor at a 3-MHz

offset by approximately an order of magnitude in the all-switches-off case. Furthermore,

at a 3-MHz offset, M1’s noise contribution in the all-switches-off case is greater than in
 47
Periodic Noise Analysis noise : freq = 2.03889 GHz + (1 Hz > 10 MHz)
V/sqrt(Hz)
out
1e+01

1e+00

1e-01

1e-02

1e-03

1e-04

1e-05

1e-06

1e-07
Hz
sweep
1e+02 1e+05

(a)freq = 2.04157 GHz + (1 Hz -> 10 MHz)

Periodic Noise Analysis `pnoise':
V/sqrt(Hz)
1e+03 out

1e+02

1e+01

1e+00

1e-01

1e-02

1e-03

1e-04

1e-05

1e-06

1e-07
Hz sweep
1e+02 1e+05

(b)

Figure 4.15 (a) Output noise voltage density with all switches on. (b) Output noise voltage
density with all switches off.

the all-switches-on case by about two orders of magnitude. Given the high tank Q of 20

with all switches off, this result is odd and questionable. Either the difference in output
48
voltage amplitude between the extreme switch cases results in M2 and M3 operating in a

much different nonlinear regime, thus significantly affecting how much of M1’s noise

appears at the output, or the simulation is unreliable. In either case, this unexpected phase

noise result cannot be attributed to the capacitor array, which is the primary focus of this

report.

4.3.4 Summary

A summary of the VCO performance is shown in Table 4.1.

Table 4.1: Summary of results

Allowable Bond Wire Inductance Range 3 nH – 7 nH

Minimum Continuous Tuning Range 1.955 GHz – 2.038 GHz
Minimum Peak Differential Output Voltage 380 mV
Maximum Peak Differential Output Voltage 1.83 V
Maximum Phase Noise @ 3-MHz Offset –126 dBc/Hz
(result questionable)
Supply Voltage 1.8 V
Supply Current 925 µA
Total Power Consumption 1.67 mW
 49

CHAPTER 5

Conclusion

An integral component of almost any wireless or wireline transceiver is the VCO. Low-

phase-noise, integrated VCOs are readily implemented using bond wires for the tank’s

inductance, but their variation in inductance must be tuned out in order to maintain a nom-

inal oscillation frequency. This report demonstrates the feasibility of using an array of

switched-capacitors to provide the necessary compensation.

A procedure was outlined for designing the varactor, the capacitor array, and the active

devices for a differential CMOS oscillator topology. A 2-GHz VCO was designed in a

0.18-µm process. The goal was to compensate for up to ±40% inductance variation while

providing ±2% continuous-frequency tuning.

An important consideration in this approach is how the on-resistances of the switches

affect the Q of the tank. An equation was derived which relates the minimum tank Q to the

process and capacitor array parameters. For the specific VCO design, a minimum Q of

11.8 was achieved. In addition, for the specific 0.18-µm process considered here, plots of
50
minimum-Q vs. switch channel length were generated for inductor tolerances of ±10%,

±20%, ±30%, and ±40%.

SpectreRF was used to verify the VCO design. The desired continuous-frequency tun-

ing range was nearly achieved for all inductance values, while periodic noise simulations

predicted worse phase noise than expected. However, simulations also revealed that noise

from the tail current source dominates by an order of magnitude in the all-switches-off

case (when the tank Q is 20). Such an unexpected result can only be attributed to either the

oscillator’s nonlinearity or inaccurate simulation results, but it is not due to the switched-

capacitor technique per se.

In summary, a switched-capacitor array can effectively compensate for the inductance

variation of bond wires without significantly degrading tank Q. Even for a poor inductance

tolerance of ±40%, this technique appears to have an advantage over VCO designs which

use spiral inductors. As minimum channel lengths and hence channel resistances decrease,

this technique may eventually allow the design of completely integrated VCOs with lower

phase noise than can be achieved using off-chip inductors.

 51

References

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