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Instruction cycle
An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from bootup to when the computer is shut down.
Circuits used
The circuits used in the CPU during the cycle are: Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next... Memory Address Register (MAR) - holds the address of a memory block to be read from or written to Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory Instruction register (IR) - a temporary holding ground for the instruction that has just been fetched from memory Control Unit (CU) - decodes the program instruction in the IR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources Arithmetic logic unit (ALU) - performs mathematical and logical operations The time period during which one instruction is fetched from memory and executed when a computer is given an instruction in machine language. There are typically four stages of an instruction cycle that the CPU carries out: 1) Fetch the instruction from memory. 2) "Decode" the instruction. 3) "Read the effective address" from memory if the instruction has an indirect address. 4) "Execute" the instruction.
Instruction cycle
Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle:
Instruction cycle
Fetch cycle
Step 1 of the Instruction Cycle is called the Fetch Cycle. These step are the same for each instruction. The fetch cycle processes the instruction from the instruction word which contains an opcode.
Instruction cycle
Decode
Step 2 of the instruction Cycle is called the decode. The opcode fetched from the memory is being decoded for the next steps and moved to the appropriate registers.
Execute cycle
Step 4 of the Instruction Cycle is the Execute Cycle. These steps will change with each instruction. The first step of the execute cycle is the Process-Memory. Data is transferred between the CPU and the I/O module. Next is the Data-Processing uses mathematical operations as well as logical operations in reference to data. Central alterations is the next step, is a sequence of operations, for example a jump operation. The last step is a combined operation from all the other steps.
(Increment the PC for next cycle at the same time) The registers used above, besides the ones described earlier, are the Memory Address Register (MAR) and the Memory Data Register (MDR), which are used (at least conceptually) in the accessing of memory. Often, the MDR is expressed as the MBR (Memory Buffer Register). Fetch and execute example (written in RTL - Register Transfer Language): PC=0x5AF , AC=0x7EC3 , M[0x5AF]=0x932E , M[0x32E]=0x09AC , M[0x9AC]=0x8B9F. T0 : AR = 0x5AF (PC) T1 : IR = 0x932E (M[AR]) , PC=0x5BO T2 : DECODE = ADD opCode 0x932E , AR=0x32E , I=1. (Indirect instruction) T3 : AR = 0x9AC (M[AR]) T4 : DR = 0x8B9F T5 : AC = 0x8B9F + 0x7EC3 = 0x0A62, E = 1 (carry out) , SC = 0 Summary: this example is for an ADD Instruction which made Indirect where: T0-T1 is the Fetch operation. T2 is the operation code Decode. T3 Indirect Memory reference T4-T5 Execute ADD operation
Instruction cycle
References
[1] Bosky Agarwal (2004). "Instruction Fetch Execute Cycle" (http:/ / www. cs. montana. edu/ ~bosky/ cs518/ ife/ IFE. pdf). . Retrieved 2010-07-09.
License
Creative Commons Attribution-Share Alike 3.0 Unported //creativecommons.org/licenses/by-sa/3.0/