VHDL Interview Question(s)

What are the two key concepts in the simulation semantics oI VHDL and how does each concept help
VHDL simulation produce waveIorms that match the behaviour that we expect?
2 What is the advantage oI RTL simulation in comparison to simulation as deIined by the VHDL standard?
3 What is the disadvantage oI RTL simulation in comparison to simulation as deIined by the VHDL
standard?
4 or each oI the architectures muruku muruku 4, answer the Iollowing questions
4 INSTRUCTIONS:
s the code legal VHDL?
2 I the code is legal VHDL:
nswer whether the behaviour oI the signal z has the same behaviour as in the
main architecture oI sumit
nswer whether the code is synthesizable
I the code is synthesizable, answer whether it adheres to good coding practices
I the the code is not legal, not synthesizable, or does not Iollow good coding practices, explain why
entity sumit is
port (
a, b, clk : in stdlogic;
z : out stdlogic
);
end schreyer;

architecture main oI sumit is
signal m : stdlogic;
begin
process ( clk )
begin
iI risingedge( clk ) then
m a or b; end iI; end process; process ( clk ) begin iI risingedge( clk ) then z not m; end iI; end process; end
main;
uruku 1
4 architecture muruku oI sumit is
signal m : stdlogic;
begin
process ( clk )
begin
iI risingedge( clk ) then
m a or b; z not m; end iI; end process; end muruku;
2 uruku_X
4 architecture murukuX oI sumit is
signal m, p : stdlogic;
begin
process ( clk )
begin
iI risingedge( clk ) then
m a or b; end iI; end process; process ( clk ) begin iI risingedge( clk ) then z p; end iI; end
process; p not m; end murukuX;
3 uruku_2
4 architecture muruku2 oI sumit is
signal m, p : stdlogic;
begin
iI (a or b) `` generate
m ``; end generate; iI (a or b) `0` generate m `0`; end generate; process ( clk ) begin iI
risingedge( clk ) then p m; end iI; end process; process ( clk ) begin iI risingedge( clk ) then
z not p; end iI; end process; end muruku2;
4 uruku_3
4 architecture muruku3 oI sumit is
begin
process
begin
wait until risingedge(clk);
wait until risingedge(clk);
z not (a or b); end process; end muruku3;
5 uruku_4
4 architecture muruku4 oI sumit is
signal m, p : stdlogic;
begin
process ( clk )
begin
iI risingedge( clk ) then
m a or b; end iI; end process; process ( clk ) begin iI risingedge( clk ) then p m; end iI; end
process; z not p; end muruku4;
QUESTS

what s diIIerence b/w blocking and non blocking assignments?
where will u use it?

ans: blocking stmt
these stmt blocks the other stmt Irom being executedie Iirst these stmt gets executed beIore it lets other stmt
execute
2on blocking stmt
these stmt executes all parallelywithe designated delayes

2 what s racing condition?

when s and r, then both the signals Iight against each other to determine the outputiI this occurs output oI the
is not determined

how to overcome?

we can reduce the noise
2 (i think we can put master-slave )

3 iI u replace latch enable signal by clock wat will be the diIIerence?
(i think iI we put clock ,then power consumption will be more)

4 how latch takes less power and II takes more power?
(clock routing may take power)

5 what's diIIrence b/w mealy and moore ckt?

mealy
it has less number oI states
it more prone to noise
moore
it has more number oI states
it is less prone to noise

6 how to overcome metastability?
by adding another
see our S-by smith

7 iI u have "case" stmt and "iI" stmt, and iI "case" s good Ior synthesis then wat s advantage oI "iI" stmt?

inside case stmt expression cannot be used like

case (xx*5y-0)

(x): z5;
(y): I0;
end case;

8 how will u write d II using variables alone?(VHDL question)
(i don't know)
but i think using variable and signals we can write D

9 design a some gates using mux
reIer any digital book
0 draw a state diagram Ior sequence detector
reIer any digital book

how to overcome racing condition?
(see the previous answer)
2 Ior a small example draw simlation time Ior non blocking assignment, blocking assignment
(reIer the previous link)

3 some questions on interIacing

4 draw a simple circuit oI D using pass gate transistor
reIer any S book

5 which universal gate do u preIer(D or R)?
ans: D gate
6 why?
ans: it takes less power,(i think less arear)

7 draw the schematic oI D gate
see the book

8 what determines drive strangth oI a gate?
width oI the gate determines drive strength oI the gate
9 what s clock skew?
when clock s routed through the chip it is subjected to parasitic capacitance,so the current is absorbed by the
circuit, so clock is delayed by some amountwhich is called clock skew
skew-- means delay
eqn:- rr*cr(cc2) like that (see any S book)

20 how to reduce the Irequency by halI?(very very important question!!!)

ans i know:
just put a T
iI u put a T u reduce the Ireq by halI
iI u put 2 power n , u reduce the Irequency by n times
they may ask u to code it in Verilog or VHDL

2 how to double the Irequency by two times
14) ulfference beLween verllog and vhdl?

CompllaLlon
vPuL MulLlple deslgnunlLs (enLlLy/archlLecLure palrs) LhaL reslde ln Lhe same sysLem flle may be
separaLely complled lf so deslred Powever lL ls good deslgn pracLlce Lo keep each deslgn unlL ln lLs own
sysLem flle ln whlch case separaLe compllaLlon should noL be an lssue

verllog 1he verllog language ls sLlll rooLed ln lLs naLlve lnLerpreLaLlve mode CompllaLlon ls a means of
speedlng up slmulaLlon buL has noL changed Lhe orlglnal naLure of Lhe language As a resulL care musL
be Laken wlLh boLh Lhe compllaLlon order of code wrlLLen ln a slngle flle and Lhe compllaLlon order of
mulLlple flles SlmulaLlon resulLs can change by slmply changlng Lhe order of compllaLlon

uaLa Lypes
vPuL A mulLlLude of language or user deflned daLa Lypes can be used 1hls may mean dedlcaLed
converslon funcLlons are needed Lo converL ob[ecLs from one Lype Lo anoLher 1he cholce of whlch daLa
Lypes Lo use should be consldered wlsely especlally enumeraLed (absLracL) daLa Lypes 1hls wlll make
models easler Lo wrlLe clearer Lo read and avold unnecessary converslon funcLlons LhaL can cluLLer Lhe
code vPuL may be preferred because lL allows a mulLlLude of language or user deflned daLa Lypes Lo be
used

verllog Compared Lo vPuL verllog daLa Lypes a re very slmple easy Lo use and very much geared
Lowards modellng hardware sLrucLure as opposed Lo absLracL hardware modellng unllke vPuL all daLa
Lypes used ln a verllog model are deflned by Lhe verllog language and noL by Lhe user 1here are neL
daLa Lypes for example wlre and a reglsLer daLa Lype called reg A model wlLh a slgnal whose Lype ls
one of Lhe neL daLa Lypes has a correspondlng elecLrlcal wlre ln Lhe lmplled modeled clrculL Cb[ecLs
LhaL ls slgnals of Lype reg hold Lhelr value over slmulaLlon delLa cycles and should noL be confused wlLh
Lhe modellng of a hardware reglsLer verllog may be preferred because of lLs slmpllclLy

ueslgn reusablllLy
vPuL rocedures and funcLlons may be placed ln a package so LhaL Lhey are avall able Lo any deslgn
unlL LhaL wlshes Lo use Lhem

verllog 1here ls no concepL of packages ln verllog luncLlons and procedures used wlLhln a model musL
be deflned ln Lhe module 1o make funcLlons and procedures generally accesslble from dlfferenL module
sLaLemenLs Lhe funcLlons and procedures musL be placed ln a separaLe sysLem flle and lncluded uslng
Lhe `lnclude compller dlrecLlve

13) WhaL are dlfferenL sLyles of verllog codlng l mean gaLelevelconLlnuous level and oLhers explaln ln
deLall?

16) Can you Lell me some of sysLem Lasks and Lhelr purpose?

$dlsplay $dlsplayb $dlsplayh $dlsplayo $wrlLe $wrlLeb $wrlLeh $wrlLeo
1he mosL useful of Lhese ls $dlsplay1hls can be used for dlsplaylng sLrlngs expresslon or values of
varlables
Pere are some examples of usage
$dlsplay(Pello onl)
ouLpuL Pello onl
$dlsplay($Llme) // currenL slmulaLlon Llme
ouLpuL 460
counLer 4b10
$dlsplay( 1he counL ls b counLer)
ouLpuL 1he counL ls 0010
$reseL reseLs Lhe slmulaLlon back Lo Llme 0 $sLop halLs Lhe slmulaLor and puLs lL ln lnLeracLlve mode
where Lhe
user can enLer commands $flnlsh exlLs Lhe slmulaLor back Lo Lhe operaLlng sysLem


17) Can you llsL ouL some of enhancemenLs ln verllog 2001?

ln earller verslon of verllog we use or Lo speclfy more Lhan one elemenL ln senslLlvlLy llsL ln verllog
2001 we can use comma as shown ln Lhe example below
// verllog 2k example for usage of comma
always [ (l1l2l3l4)

verllog 2001 allows us Lo use sLar ln senslLlve llsL lnsLead of llsLlng all Lhe varlables ln 8PS of combo
loglcs 1hls removes Lypo mlsLakes and Lhus avolds slmulaLlon and synLhesls mlsmaLches
verllog 2001 allows porL dlrecLlon and daLa Lype ln Lhe porL llsL of modules as shown ln Lhe example
below
module memory (
lnpuL r
lnpuL wr
lnpuL 70 daLa_ln
lnpuL 30 addr
ouLpuL 70 daLa_ouL
)


18)WrlLe a verllog code for synchronous and asynchronous reseL?

Synchronous reseL synchronous means clock dependenL so reseL musL noL be presenL ln senslLlvlLy dlsk
eg
always [ (posedge clk )

begln lf (reseL)
end
Asynchronous means clock lndependenL so reseL musL be presenL ln senslLlvlLy llsL
Lg
Always [(posedge clock or posedge reseL)
begln
lf (reseL)
end

19) WhaL ls pll?why ls lL used?

rogrammlng Language lnLerface (Ll) of verllog PuL ls a mechanlsm Lo lnLerface verllog programs wlLh
programs wrlLLen ln C language lL also provldes mechanlsm Lo access lnLernal daLabases of Lhe
slmulaLor from Lhe C program
Ll ls used for lmplemenLlng sysLem calls whlch would have been hard Lo do oLherwlse (or lmposslble)
uslng verllog synLax Cr ln oLher words you can Lake advanLage of boLh Lhe paradlgms parallel and
hardware relaLed feaLures of verllog and sequenLlal flow of C uslng Ll

20) 1here ls a Lrlangle and on lL Lhere are 3 anLs one on each corner and are free Lo move along sldes of
Lrlangle whaL ls probablllLy LhaL Lhey wlll colllde?

AnLs can move only along edges of Lrlangle ln elLher of dlrecLlon leL's say one ls represenLed by 1 and
anoLher by 0 slnce Lhere are 3 sldes elghL comblnaLlons are posslble when all anLs are golng ln same
dlrecLlon Lhey won'L colllde LhaL ls 111 or 000 so probablllLy of noL colllslon ls 2/81/4 or colllslon
probablllLy ls 6/83/4
DiIIerentiate between nter assignment Delay and nertial Delay
What are the diIIerent State machine Styles ? Which is better ? Explain disadvantages and
advantages
What is the diIIerence between the Iollowing lines oI code ?
O reg #0 reg2 ;
O reg3 # 0 reg4 ;
What is the value oI Var aIter the Iollowing assignment ?
reg Var;
initial begin
Var "-"
end
n the below code, ssume that this statement models a Ilop with async reset n this,
how does the synthesis tool, Iigure out which is clock and which is reset s the statements within
the always block is necessary to Iind out this or not ?

1 module which_clock (x,y,q,d);
2 input x,y,d;
3 output q;
4 reg q;
5
6 always @ (posedge x or posedge y)
7 if (x)
8 q <= 1'b0;
9 else
10 q <= d;
11
12 endmodule
What is the output oI the two codes below ?
1 module quest_for_out();
2
3 integer i;
4 reg clk;
5
6 initial begin
7 clk = 0;
8 #4 $finish;
9 end
10
11 always #1 clk = ! clk;
12
13 always @ (posedge clk)
14 begin : FOR_OUT
15 for (i=0; i < 8; i = i + 1) begin
16 if (i == 5) begin
17 disable FOR_OUT;
18 end
19 $display ("Current i : %g",i);
20 end
21 end
22 endmodule


1 module quest_for_in();
2
3 integer i;
4 reg clk;
5
6 initial begin
7 clk = 0;
8 #4 $finish;
9 end
10
11 always #1 clk = ! clk;
12
13 always @ (posedge clk)
14 begin
15 for (i=0; i < 8; i = i + 1) begin : FOR_IN
16 if (i == 5) begin
17 disable FOR_IN;
18 end
19 $display ("Current i : %g",i);
20 end
21 end
22 endmodule

Why cannot initial statement be synthesizeable ?
onsider a 2: mux; what will the output be iI the Select (sel) is "X" ?


What is the diIIerence between blocking and nonblocking assignments ?
What is the diIIerence between wire and reg data type ?
Write code Ior async reset D-lip-lop
Write code Ior 2: UX using diIIerent coding methods
Write code Ior a parallel encoder and a priority encoder
What is the diIIerence between and ?
What is deIparam used Ior ?
What is the diIIerence between unary and logical operators ?
What is the diIIerence between tasks and Iunctions ?
What is the diIIerence between transport and inertial delays ?
What is the diIIerence between casex and case statements ?
What is the diIIerence between $monitor and $display ?
What is the diIIerence between compiled, interpreted, event based and cycle based
simulators ?
What is code coverage and what are the diIIerent types oI code coverage that one does ?