Datasheet

Freescale Semiconductor Data Sheet: Product Preview
Document Number: K60P144M100SF2 Rev. 1, 11/2010
Features Operating Characteristics Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V Temperature range (ambient): -40 to 105C
Performance Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces Up to 512 KB program flash memory on nonFlexMemory devices Up to 256 KB program flash memory on FlexMemory devices Up to 256 KB FlexNVM on FlexMemory devices 4 KB FlexRAM on FlexMemory devices Up to 128 KB RAM Serial programming interface (EzPort) FlexBus external bus interface Clocks 1 to 32 MHz crystal oscillator 32 kHz crystal oscillator Multi-purpose clock generator
System peripherals 10 low-power modes to provide power optimization based on application requirements Memory protection unit with multi-master protection 16-channel DMA controller, supporting up to 64 request sources External watchdog monitor Software watchdog Low-leakage wakeup unit
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. 20102010 Freescale Semiconductor, Inc. Preliminary
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Supports the following: MK60N256VLQ100, MK60X256VLQ100, MK60N512VLQ100, MK60N256VMD100, MK60X256VMD100, MK60N512VMD100
K60 Sub-Family Data Sheet
K60P144M100SF2
Security and integrity modules Hardware CRC module to support fast cyclic redundancy checks Hardware random-number generator Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms 128-bit unique identification (ID) number per chip Human-machine interface Low-power hardware touch sensor interface (TSI) General-purpose input/output Analog modules 16-bit SAR ADC with PGA (x64) 12-bit DAC Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Voltage reference Timers Programmable delay block Eight-channel motor control/general purpose/PWM timers Two-channel quadrature decoder/general purpose timers IEEE 1588 timers Periodic interrupt timers 16-bit low-power timer Carrier modulator transmitter Real-time clock
Communication interfaces Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability USB full-/low-speed On-the-Go controller with on-chip transceiver Controller Area Network (CAN) module SPI modules I2C modules UART modules Secure Digital host controller (SDHC) I2S
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K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................5 1.1 Determining valid orderable parts......................................5 2 Part identification......................................................................5 2.1 Description.........................................................................5 2.2 Format...............................................................................5 2.3 Fields.................................................................................5 2.4 Example............................................................................6 3 Terminology and guidelines......................................................6 3.1 Definition: Operating requirement......................................6 3.2 Definition: Operating behavior...........................................7 3.3 Definition: Attribute............................................................7 6 Peripheral operating requirements and behaviors....................20 6.1 Core modules....................................................................20 6.1.1 6.1.2 Debug trace timing specifications.........................20 JTAG electricals....................................................21
6.2 System modules................................................................24 6.3 Clock modules...................................................................24 6.3.1 6.3.2 MCG Specifications...............................................24 Oscillator Electrical Characteristics.......................26 6.3.2.1 6.3.2.2 Oscillator DC Electrical Specifications 26 Oscillator frequency specifications......27
3.4 Definition: Rating...............................................................8 3.5 Result of exceeding a rating..............................................8 3.6 Relationship between ratings and operating
requirements......................................................................8 3.7 Guidelines for ratings and operating requirements............9 3.8 Definition: Typical value.....................................................9
3.9 Typical Value Conditions...................................................10 4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10 4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11 5 General.....................................................................................12
5.1 Nonswitching electrical specifications...............................12 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5
Voltage and Current Operating Requirements......12 LVD and POR operating requirements.................13 Voltage and current operating behaviors..............14
Power mode transition operating behaviors..........14 Power consumption operating behaviors..............15 5.1.5.1 Diagram: Typical IDD_RUN operating behavior...............................................17
5.1.6 5.1.7 5.1.8
EMC radiated emissions operating behaviors.......18 Designing with radiated emissions in mind...........19 Capacitance attributes..........................................19
5.2 Switching electrical specifications.....................................19 5.3 Thermal specifications.......................................................19 5.3.1 5.3.2 Thermal operating requirements...........................20 Thermal attributes.................................................20 6.6.2 6.6.3
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6.3.3 6.3.3.1 6.3.3.2 6.4.1 6.4.1.1 6.4.1.2 6.4.1.3 6.4.1.4 6.4.1.5 6.4.2 6.4.3 6.6.1 6.6.1.1 6.6.1.2 6.6.1.3 6.6.1.4 6.6.3.1
32kHz Oscillator Electrical Characteristics............28 32kHz Oscillator DC Electrical Specifications......................................28 32kHz Oscillator Frequency Specifications......................................28
6.4 Memories and memory interfaces.....................................29 Flash (FTFL) Electrical Characteristics.................29 Flash Timing Parameters Program and Erase............................................29
Flash Timing Parameters Commands..........................................29 Flash (FTFL) Current and Power Parameters..........................................31
Reliability Characteristics....................31 Write Endurance to FlexRAM for EEPROM.............................................32
EzPort Switching Specifications............................33 Flexbus Switching Specifications..........................34
6.5 Security and integrity modules..........................................36 6.6 Analog...............................................................................36 ADC electrical specifications.................................36 16-bit ADC operating conditions..........37 16-bit ADC electrical characteristics....39 16-bit ADC with PGA operating conditions............................................42 16-bit ADC with PGA characteristics...43
CMP and 6-bit DAC electrical specifications.........44 12-bit DAC electrical characteristics.....................45 12-bit DAC operating requirements.....45

3
6.6.3.2 6.6.4
12-bit DAC operating behaviors..........46
6.8.7 6.8.8
SDHC Specifications.............................................56 I2S Switching Specifications.................................57
Voltage Reference Electrical Specifications..........48
6.7 Timers................................................................................49 6.8 Communication interfaces.................................................49 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 Ethernet Switching Specifications.........................50 USB electrical specifications.................................51 USB DCD Electrical Specifications.......................51 USB Voltage Regulator Electrical Specifications. .52 DSPI Switching Specifications for Low-speed Operation..............................................................52 6.8.6 DSPI Switching Specifications (High-speed
6.9 Human-machine interfaces (HMI)......................................59 6.9.1 6.9.2 General Switching Specifications..........................59 TSI Electrical Specifications..................................59
7 Dimensions...............................................................................60 7.1 Obtaining package dimensions.........................................60 8 Pinout........................................................................................61 8.1 K60 Signal Multiplexing and Pin Assignments..................61 8.2 K60 Pinouts.......................................................................66 9 Revision History........................................................................68
mode)....................................................................54
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Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK60 and MK60.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field Q K## M Qualification status Kinetis family Flash memory type Description Values M = Fully qualified, general market flow P = Prequalification K60 N = Program flash only X = Program flash and FlexMemory Table continues on the next page...
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Terminology and guidelines Field FFF Description Program flash memory size 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB Values
T PP
Temperature range (C) Package identifier
V = 40 to 105 FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) FX = 64 QFN (9 mm x 9 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm) MB = 81 MAPBGA (8 mm x 8 mm) LL = 100 LQFP (14 mm x 14 mm) ML = 104 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MF = 196 MAPBGA (15 mm x 15 mm) MJ = 256 MAPBGA (17 mm x 17 mm) 50 = 50 MHz 72 = 72 MHz 100 = 100 MHz 120 = 120 MHz 150 = 150 MHz
CCC
Maximum CPU frequency (MHz)
Packaging type
2.4 Example
This is an example part number: MK60N512VMD100
3 Terminology and guidelines

3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
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R = Tape and reel (Blank) = Trays

Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed:
Symbol VDD Description 1.0 V core supply volt age 0.9 Min. 1.1 Max. V Unit
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements:
Symbol IWP Description Min. Max. Unit Digital I/O weak pullup/ 10 pulldown current 130 A
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol CIN_D Description Input capacitance: digi tal pins Min. 7 Max. pF Unit
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3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: Operating ratings apply during operation of the chip. Handling ratings apply when the chip is not powered.
This is an example of an operating rating:

Symbol VDD Description 1.0 V core supply volt age 0.3
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Min. Max. 1.2 V
The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
Operating rating
3.4.1 Example
Unit
3.5 Result of exceeding a rating

40 Failures in time (ppm) 30
20
10
Measured characteristic
K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.

8
Preliminary
3.6 Relationship between ratings and operating requirements

g tin h or an dlin g in rat g( mi n.) ing ui req in. (m nt me re ) ui req ax (m nt me re .) h or g dlin an ( ing rat x.) ma g g tin
Op
era
Op
t era
era Op
tin
era Op
Fatal range
- Probable permanent failure
Limited operating range

- No permanent failure - Possible decreased life - Possible incorrect operation
Normal operating range

- No permanent failure - Correct operation
Limited operating range

- No permanent failure - Possible decreased life - Possible incorrect operation
Fatal range
- Probable permanent failure
Handling range
- No permanent failure
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Description Min. 10 70 Typ. 130 Max. A
3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:
Never exceed any of the chips ratings. During normal operation, dont exceed any of the chips operating requirements. If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that: Lies within the range of values specified by the operating behavior Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol IWP Unit Digital I/O weak pullup/pulldown current

Preliminary
Ratings
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions:
5000 4500 4000 3500 IDD_STOP (A) 3000 2500 2000 1500 1000 500 0 0.90 TJ
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as specified):
Symbol TA VDD Description Value Unit Ambient temperature 3.3 V supply voltage 25 3.3 C V
4 Ratings
10
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105 C 25 C 40 C 0.95 1.00 1.05 1.10 VDD (V)
150 C

Ratings
4.1 Thermal handling ratings

Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. 55 Max. 150 260 245 Unit C C Notes 1 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings

Symbol MSL Description Moisture sensitivity level
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Min. Max. 3 Unit Min. Max. Unit V V -2000 -500 -100 +2000 +500 +100 mA Min. 0.3 0.3 0.3 Max. 3.8 185 5.5 VDD + 0.3 Table continues on the next page...
Notes 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings

Symbol VHBM VCDM ILAT Description
Notes 1 2
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 85C
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings

Symbol VDD IDD VDIO VAIO Description Digital supply voltage Digital supply current Digital input voltage (except RESET, EXTAL, and XTAL) Analog, RESET, EXTAL, and XTAL input voltage Unit V mA V V

Preliminary
11
General Symbol ID VDDA IDDA VUSB_DP VUSB_DM VREGIN VBAT VRAM VRFVBAT Description Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage Analog supply current1 USB_DP input voltage USB_DM input voltage USB regulator input RTC battery supply voltage VDD voltage required to retain RAM Min. 25 VDD 0.3 TBD 0.3 0.3 0.3 0.3 1.2 Max. 25 VDD + 0.3 TBD 3.63 3.63 6.0 3.8 Unit mA V mA V V V V V V
VBAT voltage required to retain the VBAT register file
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current.
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and Current Operating Requirements

Symbol VDD VDDA Description Min.
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TBD
Table 1. Voltage and current operating requirements

Max. 3.6 3.6 0.1 0.1 1.71 1.71 0.1 0.1
Unit V V V V
Notes
Supply voltage
Analog supply voltage
VDD VDDA VDD-to-VDDA differential voltage VSS VSSA VSS-to-VSSA differential voltage VIH Input high voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V VIL Input low voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V VHYS Input hysteresis
0.7 VDD 0.75 VDD
V V
0.06 VDD Table continues on the next page...
0.35 VDD 0.3 VDD
V V V

12
Preliminary
General
Table 1. Voltage and current operating requirements (continued)

Symbol IIC Description DC injection current single pin VIN > VDD VIN < VSS DC injection current total MCU limit, includes sum of all stressed pins VIN > VDD VIN < VSS 0 0 2 0.2 mA mA 1 0 0 25 5 mA mA Min. Max. Unit Notes 1
5.1.2 LVD and POR operating requirements

Symbol VPOR VLVDH Description Min.
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Table 2. LVD and POR operating requirements
Typ. 1.1 TBD TBD Max. TBD TBD V V 2.56 TBD TBD TBD TBD 2.70 2.80 2.90 3.00 60 TBD TBD TBD TBD TBD TBD TBD V V V V V TBD TBD TBD TBD 1.80 1.90 2.00 2.10 TBD TBD TBD TBD V V V V Table continues on the next page...
1. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).
Unit
Notes
Falling VDD POR detect voltage
Falling low-voltage detect threshold high range (LVDV=01)
Low-voltage warning thresholds high range VLVW1 VLVW2 VLVW3 VLVW4 VHYS VLVDL Level 1 falling (LVWV=00) Level 2 falling (LVWV=01) Level 3 falling (LVWV=10) Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis high range Falling low-voltage detect threshold low range (LVDV=00) Low-voltage warning thresholds low range
mV
VLVW1 VLVW2 VLVW3 VLVW4
Level 1 falling (LVWV=00) Level 2 falling (LVWV=01) Level 3 falling (LVWV=10) Level 4 falling (LVWV=11)

Preliminary
13
General
Table 2. LVD and POR operating requirements (continued)

Symbol VHYS VBG tLPO Description Low-voltage inhibit reset/recover hysteresis low range Bandgap voltage reference Internal low power oscillator period factory trimmed 1. Rising thresholds are falling threshold + VHYS TBD TBD Min. Typ. 40 1.00 1000 TBD TBD Max. Unit mV V s Notes
5.1.3 Voltage and current operating behaviors

Symbol VOH Description Min.
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Table 3. Voltage and current operating behaviors
Max. Unit VDD 0.5 VDD 0.5 V V VDD 0.5 VDD 0.5 V V 100 mA 0.5 0.5 V V 30 0.5 0.5 V V 100 1 1 50 mA A A k
Notes
Output high voltage high drive strength 2.7 V VDD 3.6 V, IOH = -10mA
1.71 V VDD 2.7 V, IOH = -3mA
Output high voltage low drive strength 2.7 V VDD 3.6 V, IOH = -2mA
1.71 V VDD 2.7 V, IOH = -0.6mA IOHT VOL Output high current total for all ports
Output low voltage high drive strength 2.7 V VDD 3.6 V, IOL = 10mA 1.71 V VDD 2.7 V, IOL = 3mA
Output low voltage low drive strength 2.7 V VDD 3.6 V, IOL = 2mA
1.71 V VDD 2.7 V, IOL = 0.6mA IOLT IIN IOZ RPU and RPD Output low current total for all ports Input leakage current (per pin) Hi-Z (off-state) leakage current (per pin)
Internal weak pullup and pulldown resistors
1. Measured at VIL max and VDD min

14
Preliminary
General
5.1.4 Power mode transition operating behaviors

In the table below, all specifications except tPOR, assume the following clock configuration: CPU and system clocks = 100MHz Bus and FlexBus clocks = 50 MHz Flash clock = 25 MHz
Table 4. Power mode transition operating behaviors
Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8V to execution of the first instruction across the operating temperature range of the chip. RUN VLLS1 RUN RUN VLLS1 VLLS1 RUN Min. Max. 300 Unit s Notes 1
RUN VLLS2 RUN RUN VLLS2 VLLS2 RUN
RUN VLLS3 RUN RUN VLLS3 VLLS3 RUN RUN LLS RUN RUN LLS LLS RUN
RUN STOP RUN RUN STOP STOP RUN RUN VLPS RUN RUN VLPS VLPS RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
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4.1 s s 123.8 4.1 s s 49.3 4.1 s s 49.2 4.1 5.9 s s 4.1 4.2 s s 4.1 5.8 s s

15
General
5.1.5 Power consumption operating behaviors

Table 5. Power consumption operating behaviors
Symbol IDD_RUN Description Run mode current all peripheral clocks disa bled, code executing from flash @ 1.8V @ 3.0V IDD_RUN Run mode current all peripheral clocks ena bled, code executing from flash @ 1.8V @ 3.0V 55 56 TBD TBD mA mA 3 40 42 TBD TBD mA mA 2 Min. Typ. Max. Unit Notes 1
IDD_RUN_M Run mode current all peripheral clocks ena bled and peripherals active, code executing from AX flash @ 1.8V @ 3.0V IDD_WAIT IDD_STOP IDD_VLPR IDD_VLPR IDD_VLPW IDD_VLPS IDD_LLS IDD_VLLS3
Wait mode current at 3.0 V all peripheral clocks disabled Stop mode current at 3.0 V
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85 85 TBD TBD TBD TBD TBD TBD TBD TBD TBD 15 1.4 1.25 TBD 1.05 30 12 A A 8 6 TBD TBD TBD TBD TBD A A 4 2 550 A A nA
mA mA mA mA mA mA mA 5 6 7 4
Very-low-power run mode current at 3.0 V all peripheral clocks disabled Very-low-power run mode current at 3.0 V all peripheral clocks enabled Very-low-power wait mode current at 3.0 V
Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V
Very low-leakage stop mode 3 current at 3.0 V 128KB RAM devices 64KB RAM devices
IDD_VLLS2 IDD_VLLS1 IDD_VBAT
Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current when CPU is not accessing RTC registers at 3.0 V
1. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 2. 100MHz core and system clock, 50MHz bus and FlexBus clocks, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 3. 100MHz core and system clock, 50MHz bus and FlexBus clocks, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clocks. MCG configured for FEI mode. 5. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash.

16
Preliminary
General 6. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 7. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled.
5.1.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions: MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks disabled except FTFL LVD disabled, USB regulator disabled No GPIOs toggled Code execution from flash
Figure 1. Run mode supply current vs. core frequency all peripheral clocks disabled
The following data was measured under these conditions: MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks enabled but peripherals are not in active operation LVD disabled, USB regulator disabled
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Preliminary
17
General
No GPIOs toggled Code execution from flash
Figure 2. Run mode supply current vs. core frequency all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors

Symbol VRE1 VRE2 VRE3 VRE4 Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 Frequency band (MHz) 0.1550 50150 150500 5001000 0.151000
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Table 6. EMC radiated emissions operating behaviors
Typ. TBD TBD TBD TBD TBD Unit dBV
Notes 1, 2
VRE_IEC_SAE IEC and SAE level
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated CircuitsTEM/ Wideband TEM (GTEM) Cell Method.

18
Preliminary
General 2. VDD = 3 V, TA = 25 C, fOSC = 16 MHz (crystal), fBUS = 20 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated CircuitsTEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind

1. To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for EMC design.
5.1.8 Capacitance attributes

Symbol CIN_A CIN_D Description
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Table 7. Capacitance attributes
Min. Max. 7 7
Unit pF pF
Input capacitance: analog pins Input capacitance: digital pins
5.2 Switching electrical specifications

Symbol Description
Table 8. Device clock specifications

Min. Normal run mode
Max.
Unit
Notes
fSYS fBUS FB_CLK fFLASH
System and core clock Bus clock
100 50 50 25
MHz MHz MHz MHz
FlexBus clock Flash clock
VLPR mode fSYS fBUS FB_CLK fFLASH System and core clock Bus clock FlexBus clock Flash clock 2 2 2 1 MHz MHz MHz MHz
5.3 Thermal specifications

Preliminary
19
Peripheral operating requirements and behaviors
5.3.1 Thermal operating requirements

Table 9. Thermal operating requirements
Symbol TJ TA Description Die junction temperature Ambient temperature Min. 40 40 Max. 125 105 Unit C C
Board type
Singlelayer (1s) Four-layer (2s2p) Singlelayer (1s) Four-layer (2s2p)
Symbol
RJA RJA RJMA RJMA RJB RJC JT
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Description 144 LQFP 144 Unit MAPBGA
C/W Thermal resistance, junction to ambient (natural convection) 52 50 Thermal resistance, junction to ambient (natural convection) 44 30 C/W Thermal resistance, junction to ambient (200 ft./ min. air speed) 43 38 41 27 C/W C/W Thermal resistance, junction to ambient (200 ft./ min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case 33 17 C/W 11 10 C/W Thermal characterization parameter, junction to package top outside center (natural convection) 2 2 C/W
5.3.2 Thermal attributes
Notes
1 1 1 1 2 3 4
6 Peripheral operating requirements and behaviors

6.1 Core modules
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental ConditionsNatural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental ConditionsForced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental ConditionsNatural Convection (Still Air).
1.

20
Preliminary
6.1.1 Debug trace timing specifications

Table 10. Debug trace operating behaviors
Symbol Tcyc Twl Twh Tr Tf Ts Th Description Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Data setup Data hold Min. Max. Unit MHz ns ns ns ns ns ns Frequency dependent 2 2 3 2 3 3
TRACE_CLKOUT TRACE_D[3:0]
6.1.2 JTAG electricals

Symbol Description Operating voltage J1
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Figure 3. TRACE_CLKOUT specifications
Ts Th Ts Th
Figure 4. Trace data specifications
Table 11. JTAG electricals

Min. 2.7 Max. 3.6 Unit V MHz 0 0 1/J1 Table continues on the next page... 25 50 ns
TCLK frequency of operation JTAG and CJTAG Serial Wire Debug
J2
TCLK cycle period

Preliminary
21
Table 11. JTAG electricals (continued)

Symbol J3 Description TCLK clock pulse width JTAG and CJTAG Serial Wire Debug J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high-Z 20 10 20 0 3 30 30 4 4 ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit ns
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time
TRST setup time (negation) to TCLK high
TCLK (input)
22
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16 1 100 8
J2 J3 J3 J4 J4
Figure 5. Test clock input timing

TCLK
J5 J6
Data inputs
J7
Input data valid
Data outputs
J8
Output data valid
Data outputs
Data outputs
TCLK
TDI/TMS
TDO
TDO
J11
TDO
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J7 Output data valid
Figure 6. Boundary scan (JTAG) timing
J9
J10
Input data valid
J11
Output data valid
J12
Output data valid
Figure 7. Test Access Port timing

23
TCLK
J14 J13
TRST
Figure 8. TRST timing
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG Specifications

Symbol fints_ft fints_t tirefsts fdco_res_t Description
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Table 12. MCG specifications
Min. Typ. Max. 32.768 31.25 39.0625 4 TBD s 0.1 0.3 0.2 0.5 + 0.5 - 1.0 0.5 TBD 3.5 3.875 3 4 4.125 5 Table continues on the next page...
6.2 System modules
Unit kHz kHz
Notes
Internal reference frequency (slow clock) facto ry trimmed at nominal VDD and 25C Internal reference frequency (slow clock) user trimmed Internal reference (slow clock) startup time
Resolution of trimmed DCO output frequency at fixed voltage and temperature using SCTRIM and SCFTRIM
%fdco
fdco_res_t Resolution of trimmed DCO output frequency at fixed voltage and temperature using SCTRIM only fdco_t fdco_t
%fdco
Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 70C Internal reference frequency (fast clock) factory trimmed at nominal VDD and 25C Internal reference frequency (fast clock) user trimmed
%fdco %fdco
fintf_ft fintf_t
MHz MHz

24
Preliminary
Table 12. MCG specifications (continued)

Symbol tirefstf floc_low floc_high Description Internal reference startup time (fast clock) Loss of external clock minimum frequency RANGE = 00 Loss of external clock minimum frequency RANGE = 01, 10, or 11 FLL fdco_t DCO output fre quency range user trimmed and DMX32=0 Low range (DRS=00) 640 fints_t Mid range (DRS=01) 1280 fints_t 40 41.94 50 MHz 20 20.97 25 MHz 1, 2 Min. (3/5) x fints_t (16/5) x fints_t Typ. TBD Max. TBD Unit s kHz kHz Notes
fdco_t_DMX3 DCO output fre quency range 2 reference = 32,768Hz and DMX32=1
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Mid-high range (DRS=10 192)0 fints_t 60 62.91 75 High range (DRS=11) 2560 fints_t 80 83.89 100 Low range (DRS=00) 732 fints_t 23.99 Mid range (DRS=01) 1464 fints_t 47.97 Mid-high range (DRS=10) 2197 fints_t 71.99 High range (DRS=11) 2929 fints_t 95.98 TBD TBD TBD TBD 1 ps ps PLL 48.0 2.0 1.49 4.47 400 TBD 100 4.0 2.98 5.97 0.15 + 1075(1/ fpll_ref) ps ps % %
MHz
MHz
MHz
MHz
MHz
MHz
Jcyc_fll Jacc_fll tfll_acquire
FLL period jitter
FLL accumulated jitter of DCO output over a 1s time window FLL target frequency acquisition time
ms
fvco fpll_ref Jcyc_pll Jacc_pll Dlock Dunl tpll_lock
VCO operating frequency PLL reference frequency range PLL period jitter PLL accumulated jitter over 1s window Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time
MHz MHz 6, 7 6,7
ms
1. The resulting system clock frequencies should not exceed their maximum specified values.

Preliminary
25
Peripheral operating requirements and behaviors 2. 3. 4. 5. This specification includes the 2% precision of the internal reference frequency (slow clock). The resulting clock frequency must not exceed the maximum specified clock frequency of the device. This specification was obtained at TBD frequency. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 7. This specification was obtained at internal frequency of TBD. 8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
This section provides the electrical characteristics of the module. 6.3.2.1

Symbol VDD33OSC IDDOSC
Oscillator DC Electrical Specifications

Description Min.
Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH)

Typ. Max. 3.6 Unit V Notes 3.3 V supply voltage 1.71
Supply current low-power mode 32 kHz 1 MHz 4 MHz 8 MHz
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500 100 200 300 700 1.2 1.5 nA A A A A Table continues on the next page... 25 200 400 800 1.5 3 4 A A A A
6.3.2 Oscillator Electrical Characteristics
16 MHz 24 MHz 32 MHz IDDOSC
mA mA 1
Supply current high gain mode 32 kHz 1 MHz 4 MHz 8 MHz 16 MHz 24 MHz 32 MHz
mA mA mA 2, 3 2,3
Cx Cy
EXTAL load capacitance XTAL load capacitance

26
Preliminary
Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH) (continued)
Symbol RF Description Feedback resistor low-frequency, low-power mode Feedback resistor low-frequency, high-gain mode Feedback resistor high-frequency, low-power mode (1 8 MHz, 8 32 MHz) Feedback resistor high-frequency, high-gain mode (1 8 MHz, 8 32 MHz) RS Series resistor low-frequency, low-power mode Min. Typ. 10 1 Max. Unit M M M M k k k Notes 2,3
Series resistor low-frequency, high-gain mode Series resistor high-frequency, low-power mode Series resistor high-frequency, high-gain mode 1 MHz resonator 2 MHz resonator 4 MHz resonator 8 MHz resonator
16 MHz resonator 20 MHz resonator 32 MHz resonator Vpp
Peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode Peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode Peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode Peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode
1. VDD33OSC=3.3 V, Temperature =27 C, Cx/Cy=20 pF 2. See crystal or resonator manufacturer's recommendation 3. RF and Cx,Cy are integrated in low-frequency, low-power mode and must not be attached externally
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200 6.6 3.3 0 0 0 0 0 k k k k k k k V V V V 0.6 0.75 VDD33OSC VDD33OSC 0.6 0.75 VDD33OSC VDD33OSC

27
6.3.2.2
Oscillator frequency specifications
Table 14. Oscillator frequency specifications, (VDD33OSC = VDD33OSC (min) to VDD33OSC (max), TA = TL to TH)
Symbol fosc_lo fosc_hi_1 fosc_hi_2 tdc_extal tcst Description Oscillator crystal or resonator frequency low frequency mode Oscillator crystal or resonator frequency high frequency mode (low range) Oscillator crystal or resonator frequency high frequency mode (high range) Input clock duty cycle (external clock mode) Min. 32 1 8 40 Typ. 50 Max. 40 8 32 60 Unit kHz MHz MHz % Notes
Crystal start-up time 32 kHz low-frequency, low-power mode Crystal start-up time 32 kHz low-frequency, high-gain mode
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TBD 800 4 3 ms ms ms ms Min. 1.71 Typ. 100 2.5 15 0.6 3.6
1, 2, 3
Crystal start-up time 8 MHz high-frequency, low-power mode Crystal start-up time 8 MHz high-frequency, high-gain mode
1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal start up time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.
6.3.3 32kHz Oscillator Electrical Characteristics

This section describes the module electrical characteristics. 6.3.3.1
32kHz Oscillator DC Electrical Specifications
Table 15. 32kHz Oscillator Module DC Electrical Specifications (VSSOSC= 0 VDC) (TA = TL to TH)
Symbol VBAT RF Cpara Cload Vpp Description Supply voltage Internal feedback resistor Parasitical capacitance of EXTAL32 and XTAL32 Internal load capacitance (programmable) Peak-to-peak amplitude of oscillation Max. Unit V M pF pF V

28
Preliminary
6.3.3.2
32kHz Oscillator Frequency Specifications
Table 16. 32kHz oscillator frequency specifications (VDD33OSC = VDD33OSC (min) to VDD33OSC (max), TA = TL to TH)
Symbol fosc_lo tstart Description Oscillator crystal Crystal start-up time Min. Typ. 32 1000 Max. Unit kHz ms 1, 2 Notes
1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) Electrical Characteristics
This section describes the electrical characteristics of the FTFL module. 6.4.1.1 Flash Timing Parameters Program and Erase
The following characteristics represent the amount of time the internal charge pumps are active and do not include command overhead.
Table 17. NVM program/erase timing characteristics
Min. Typ. 20 20 Max. TBD 100 800
Symbol thvpgm4 thversscr thversblk
Description
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s ms ms 160
Unit
Notes
Longword Program high-voltage time Sector Erase high-voltage time Erase Block high-voltage time
1 1
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol trd1blk trd1sec2k tpgmchk
Flash Timing Parameters Commands

Table 18. Flash command timing characteristics
Description Read 1s Block execution time Read 1s Section execution time (2 KB flash sec tor) Program Check execution time Min. Table continues on the next page... Typ. Max. 1.4 40 35 Unit ms s s Notes

Preliminary
29
Table 18. Flash command timing characteristics (continued)

Symbol trdrsrc tpgm4 tersblk tersscr tpgmsec2k trd1all trdonce tpgmonce tersall tvfykey tpgmpart tsetram32k tsetram256k Description Read Resource execution time Program Longword execution time Erase Flash Block execution time Erase Flash Sector execution time Program Section execution time (2 KB flash sec tor) Read 1s All Blocks execution time Read Once execution time Min. Typ. 50 160 20 TBD Max. 35 TBD 800 100 TBD 2.8 35 Unit s s ms ms ms ms s s 1 2 2 Notes 1
Program Once execution time
Erase All Blocks execution time
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50 TBD 320 1600 35 ms s 175 TBD TBD TBD ms ms ms TBD TBD Byte-write to FlexRAM for EEPROM operation 100 TBD TBD 1.5 s TBD TBD TBD TBD ms ms ms ms TBD 2.5 Word-write to FlexRAM for EEPROM operation 100 TBD TBD TBD TBD TBD TBD 1.5 TBD 2.5 s ms ms ms ms Longword-write to FlexRAM for EEPROM operation Table continues on the next page...
2 1
Verify Backdoor Access Key execution time
Program Partition for EEPROM execution time
Set FlexRAM Function execution time for 32 KB of EEPROM backup Set FlexRAM Function execution time for 256 KB of EEPROM backup
teewr8bers teewr8b32k teewr8b64k
Byte-write to erased FlexRAM location execution time Byte-write to FlexRAM execution time (32 KB EEPROM backup) Byte-write to FlexRAM execution time (64 KB EEPROM backup)
teewr8b128k Byte-write to FlexRAM execution time (128 KB EEPROM backup) teewr8b256k Byte-write to FlexRAM execution time (256 KB EEPROM backup)
teewr16bers
Word-write to erased FlexRAM location execu tion time
teewr16b32k Word-write to FlexRAM execution time (32 KB EEPROM backup) teewr16b64k Word-write to FlexRAM execution time (64 KB EEPROM backup) teewr16b128k Word-write to FlexRAM execution time (128 KB EEPROM backup) teewr16b256k Word-write to FlexRAM execution time (256 KB EEPROM backup)

30
Preliminary
Table 18. Flash command timing characteristics (continued)

Symbol teewr32bers Description Longword-write to erased FlexRAM location exe cution time Min. Typ. 200 TBD TBD TBD TBD Max. TBD TBD 2.7 TBD 3.7 Unit s ms ms ms ms Notes
teewr16b32k Longword-write to FlexRAM execution time (32 KB EEPROM backup) teewr16b64k Longword-write to FlexRAM execution time (64 KB EEPROM backup) teewr32b128k Longword-write to FlexRAM execution time (128 KB EEPROM backup) teewr32b256k Longword-write to FlexRAM execution time (256 KB EEPROM backup)
1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3
Flash (FTFL) Current and Power Parameters

Description
Symbol IDD_PGM
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Table 19. Flash (FTFL) current and power parameters
Typ. 10
Unit mA
Worst case programming current in program flash
6.4.1.4
Symbol
Reliability Characteristics
Description
Table 20. NVM reliability characteristics

Min. Typ.1 Program Flash 5
Max.
Unit
Notes
tnvmretp10k tnvmretp1k tnvmretp100 nnvmcycp
Data retention after up to 10 K cycles Data retention after up to 1 K cycles
TBD TBD TBD TBD
years years years
2 2 2 3
10 15
Data retention after up to 100 cycles Cycling endurance
10 K Data Flash
cycles
tnvmretd10k tnvmretd1k tnvmretd100 nnvmcycd
Data retention after up to 10 K cycles Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance
5 10 15 10 K FlexRAM as EEPROM
TBD TBD TBD TBD
years years years cycles
2 2 2 3
tnvmretee100 Data retention up to 100% of write endurance
TBD
years
Table continues on the next page...

Preliminary
31
Table 20. NVM reliability characteristics (continued)

Symbol tnvmretee10 tnvmretee1 Description Data retention up to 10% of write endurance Data retention up to 1% of write endurance Min. 10 15 35 K 315 K 1.27 M 10 M 80 M Typ.1 TBD TBD TBD TBD TBD TBD TBD Max. Unit years years writes writes writes writes writes Notes 2 2 4 4 4 4 4
nnvmwree16 Write endurance with an EEPROM backup to FlexRAM ratio of 16 nnvmwree128 Write endurance with an EEPROM backup to FlexRAM ratio of 128 nnvmwree512 Write endurance with an EEPROM backup to FlexRAM ratio of 512 nnvmwree4k Write endurance with an EEPROM backup to FlexRAM ratio of 4096 nnvmwree32k Write endurance with an EEPROM backup to FlexRAM ratio of 32,768
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618. 2. Data retention is based on Tjavg = 55C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40C Tj 125C 4. Write endurance represents the number of writes to FlexRAM at -40C Tj 125C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum value assumes all byte-writes to FlexRAM.
6.4.1.5
Write Endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFL to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size are used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used.
Writes_subsystem = EEPROM 2 EEESPLIT EEESIZE EEESPLIT EEESIZE Write_efficiency nnvmcycd
where Writes_subsystem minimum writes to FlexRAM for subsystem (each subsystem can have different endurance)
32
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Preliminary
EEPROM allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command EEESPLIT FlexRAM split factor for subsystem; entered with the Program Partition command EEESIZE total allocated FlexRAM based on DEPART; entered with Program Partition command Write_efficiency 0.25 for 8-bit writes to FlexRAM 0.50 for 16-bit or 32-bit writes to FlexRAM
6.4.2 EzPort Switching Specifications

Table 21. EzPort switching specifications
Num Description Operating voltage Table continues on the next page... Min. 2.7 Max. 3.6 Unit V
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Figure 9. EEPROM backup writes to FlexRAM
33
nnvmcycd data flash cycling endurance
Table 21. EzPort switching specifications (continued)

Num EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 Description EZP_CK frequency of operation (all commands except READ) EZP_CK frequency of operation (READ command) EZP_CS negation to next EZP_CS assertion EZP_CS input valid to EZP_CK high (setup) EZP_CK high to EZP_CS input invalid (hold) EZP_D input valid to EZP_CK high (setup) EZP_CK high to EZP_D input invalid (hold) EZP_CK low to EZP_Q output valid (setup) Min. 2 x tEZP_CK 5 5 2 5 0 Max. fSYS/2 fSYS/8 12 Unit MHz MHz ns ns ns ns ns ns ns ns
EZP_CK low to EZP_Q output invalid (hold) EZP_CS negation to EZP_Q tri-state
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
6.4.3 Flexbus Switching Specifications

All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency.
34
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12
EP3 EP4 EP2 EP9 EP7 EP8 EP5 EP6
Figure 10. EzPort Timing Diagram

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values.
Table 22. Flexbus switching specifications
Num Description Operating voltage Frequency of operation FB1 FB2 FB3 FB4 FB5 Clock period Address, data, and control output valid Address, data, and control output hold Data and FB_TA input setup Data and FB_TA input hold Min. 2.7 20 TBD 0 Max. 3.6 50 11.5 Unit V Mhz ns ns ns ns ns 1 1 2 2 Notes
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA.
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_CSn
FB_OEn
FB_BE/BWEn
FB4
AA=1
FB_TA
FB_TSIZ[1:0]
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8.5 0.5
FB5 FB3 Address FB4 FB2 Address Data
AA=1 AA=0
FB5
AA=0
TSIZ
Figure 11. FlexBus read timing diagram

35

FB1
FB_CLK
FB3
FB_A[Y]
FB2
Address
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins (ADCx_DP0, ADCx_DM0, ADC, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DP3). The ADCx_DP2 and ADCx_DM2 ADC inputs are used
36
Pr el im in ar y
AA=1 AA=0
FB4
FB5
AA=1 AA=0
TSIZ
Figure 12. FlexBus write timing diagram
Preliminary
as the PGA inputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 25 and Table 26. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1
Symbol VDDA VDDA VSSA VREFH VREFL VADIN CADIN
16-bit ADC operating conditions

Table 23. 16-bit ADC operating conditions
Description Supply voltage Supply voltage Ground voltage ADC reference voltage high Conditions Absolute Delta to VDD (VDDVDDA) Delta to VSS (VSSVSSA) Min. 1.71 -100 -100 1.13 Typ.1 0 0 Max. 3.6 +100 +100 VDDA VSSA Unit V mV mV V V V 2 2 Notes
Reference volt age low Input voltage Input capaci tance
RADIN
Input resistance
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VDDA VSSA 8 4 VSSA VREFL VREFH 10 5 16 bit modes 8/10/12 bit modes pF 2 5 k Table continues on the next page...

37
Table 23. 16-bit ADC operating conditions (continued)

Symbol RAS Description Analog source resistance Conditions 16 bit modes fADCK > 8MHz fADCK = 48MHz fADCK < 4MHz 13/12 bit modes fADCK > 16MHz fADCK > 8MHz fADCK = 48MHz fADCK < 4MHz 0.5 1 2 5 k k k k 0.5 1 2 k k k Min. Typ.1 Max. Unit Notes External to MCU Assumes ADLSMP=0
fADCK
ADC conversion clock frequency
1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference.
38
Pr el im in ar y
11/10 bit modes fADCK > 8MHz 2 5 k k k k k fADCK = 48MHz fADCK < 4MHz 10 5 9/8 bit modes fADCK > 8MHz fADCK < 8MHz 10 ADLPC=0, ADHSC=1 16 bit modes 13 bit modes 1.0 1.0 TBD TBD MHz MHz ADLPC=0, ADHSC=0 16 bit modes 13 bit modes 1.0 1.0 1.0 1.0 8.0 MHz MHz MHz MHz 12.0 5.0 8.0 ADLPC=1, ADHSC=1 16 bit modes 13 bit modes ADLPC=1, ADHSC=0 16 bit modes 13 bit modes 1.0 1.0 2.5 5.0 MHz MHz

SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT
Z ADIN
SIMPLIFIED CHANNEL SELECT CIRCUIT
Z AS R AS V ADIN V AS C AS
Pad leakage due to input protection
R ADIN
ADC SAR ENGINE
6.6.1.2
Symbol IDDA
16-bit ADC electrical characteristics

Description Conditions1 Min.
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)

Typ.2 215 340 470 610 Max. Supply current ADLPC=1, ADHSC=0 ADLPC=1, ADHSC=1 ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1
Pr el im in ar y
INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN
R ADIN
C ADIN
Figure 13. ADC input impedance equivalency diagram
Unit A A A A A
Notes ADLSMP= 0 ADCO=1
Supply current
Stop, reset, module off ADLPC=1, ADHSC=0 ADLPC=1, ADHSC=1 ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1
0.01 2.4 4.0 5.2 6.2
0.8
fADACK
ADC asynchro nous clock source
TBD TBD TBD TBD
TBD TBD TBD TBD
MHz MHz MHz MHz
tADACK = 1/ fADACK
Sample Time
See Reference Manual chapter for sample times
Conversion Time See Reference Manual chapter for conversion times Table continues on the next page...

Preliminary
39
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol TUE Description Total unadjusted error Conditions1 16 bit differential 16 bit single-ended 13 bit differential 12 bit single-ended 11 bit differential 10 bit single-ended 9 bit differential 8 bit single-ended DNL Differential nonlinearity 16 bit differential 13 bit differential 11 bit differential 9 bit differential Min. Typ.2 14.0 13.0 1.5 TBD 0.8 TBD 0.5 0.5 2.5 2.5 0.7 0.7 0.5 0.2 0.2 Max. TBD TBD TBD TBD TBD TBD 1.0 1.0 TBD TBD TBD TBD TBD TBD 0.5 0.5 LSB3 Max hard ware aver aging (AVGE = %1, AVGS = %11) Unit LSB3 Notes Max hard ware aver aging (AVGE = %1, AVGS = %11)
INL
Integral non-line arity
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16 bit single-ended 12 bit single-ended 10 bit single-ended 8 bit single-ended 16 bit differential 13 bit differential 11 bit differential 9 bit differential TBD -6 to +2.5 -2 to +12 1.0 1.0 0.5 0.5 0.3 0.3 4.0 4.0 0.7 0.7 0.4 0.4 0.2 0.2 16 bit single-ended 12 bit single-ended 10 bit single-ended 8 bit single-ended 16 bit differential 13 bit differential 12 bit single-ended 11 bit differential 10 bit single-ended 9 bit differential 8 bit single-ended TBD TBD TBD TBD 0.5 0.5 TBD TBD TBD TBD 0.5 0.5 16 bit single-ended Table continues on the next page...
LSB3
Max aver aging
EZS
Zero-scale error
LSB3
VADIN = VSSA

40
Preliminary
Symbol EFS Description Full-scale error Conditions1 16 bit differential 16 bit single-ended 13 bit differential 12 bit single-ended 11 bit differential 10 bit single-ended 9 bit differential 8 bit single-ended EQ Quantization er ror 16 bit modes Min. Typ.2 0 to +10 0 to +14 1.0 TBD 0.4 0.4 0.2 0.2 -1 to 0 Max. TBD TBD TBD TBD 0.5 0.5 LSB3 Unit LSB3 Notes VADIN = VDDA
ENOB
Effective number 16 bit differential mode of bits Avg=32 Avg=16 Avg=8 Avg=4 Avg=1
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13 bit modes 0.5 TBD TBD TBD TBD TBD 13.6 14.1 13.2 TBD TBD TBD TBD TBD TBD TBD 16 bit single-ended mode Avg=32 Avg=16 Avg=8 Avg=4 Avg=1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD See ENOB 6.02 ENOB + 1.76 dB 16 bit differential mode Avg=32 16 bit single-ended mode Avg=32 TBD TBD dB -94 TBD dB TBD TBD 95 TBD dB dB 16 bit single-ended mode Avg=32 Table continues on the next page...
bits bits bits bits bits
bits bits bits bits bits
SINAD THD
Signal-to-noise plus distortion Total harmonic distortion
SFDR
Spurious free dy 16 bit differential mode namic range Avg=32

Preliminary
41
Symbol EIL Description Input leakage er ror Conditions1 Min. Typ.2 IIn RAS Max. Unit mV Notes IIn = leak age cur rent (refer to the MCU's voltage and cur rent oper ating rat ings)
VTEMP25
Temp sensor voltage
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. 1 LSB = (VREFH - VREFL)/2N 4. Input data is 1 kHz sine wave.
6.6.1.3
Symbol VDDA VREFPGA VADIN RPGA
16-bit ADC with PGA operating conditions

Description Conditions Min. Typ.1
Pr el im in ar y
25C to 105C TBD TBD 25C
Temp sensor slope
40C to 25C
TBD
mV/C mV/C mV
Table 25. 16-bit ADC with PGA operating conditions

Max. 3.6 Absolute 1.71
Unit V V V
Notes
Supply voltage
PGA ref voltage Input voltage
VREFOUT VREFOUT VREFOUT VSSA TBD TBD TBD TBD TBD TBD 1.25 VDDA TBD TBD TBD TBD TBD TBD
2, 3
Input impedance
Gain = 1, 2, 4, 8 Gain = 16, 32 Gain = 64
64 32 16
RPGAD
Differntial input impedance
Gain = 1, 2, 4, 8 Gain = 16, 32 Gain = 64
128 64 32 100
IN+ to IN-
RAS TS
Analog source resistance ADC sampling time
Gain = 16, 32 Gain = 64
4 5
1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREFOUT) 3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output of the VREF module, the VREF module must be disabled.

42
Preliminary
Peripheral operating requirements and behaviors 4. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency
6.6.1.4
Symbol IDDA_PGA ILKG G
16-bit ADC with PGA characteristics

Table 26. 16-bit ADC with PGA characteristics
Description Supply current Leakage current Gain2 PGA disabled Conditions Min. TBD Typ.1 590 <1 1 2 Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.5 4 Unit A A dB dB dB dB dB dB dB dB Notes
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PGAG=0 PGAG=1 PGAG=2 PGAG=3 TBD TBD TBD TBD TBD TBD TBD 3.9 TBD TBD 29.9 TBD PGAG=4 PGAG=5 PGAG=6 16-bit modes < 16-bit modes kHz kHz dB 40 Gain=1 TBD TBD Gain=1 TBD TBD TBD TBD dB dB Gain=64 Gain=1 Gain=64 Gain=1 Gain=1 Gain=64 0.2 TBD 10 TBD TBD TBD TBD TBD mV s ppm/C ppm/C ppm/C %/V %/V TBD TBD TBD TBD TBD TBD Table continues on the next page...
RAS < 100
GA BW
Gain error
RAS < 100
Input signal band width Power supply re jection ration
PSRR
VDDA= 3V 100mV, fVDDA= 50Hz, 60Hz VCM= 500mVpp, fVCM= 50Hz, 100Hz Gain=1, ADC Averaging=32 3 0 to 50C
CMRR
Common mode rejection ratio
VOFS TGSW dG/dT
Input offset volt age Gain switching settling time Gain drift over temperature Offset drift over temperature Gain drift over supply voltage
dVOFS/dT dG/dVDDA
0 to 50C, ADC Averaging=32 VDDA from 1.71 to 3.6V

Preliminary
43
Table 26. 16-bit ADC with PGA characteristics (continued)

Symbol EIL Description Input leakage er ror Conditions All modes Min. Typ.1 IIn RAS Max. Unit mV Notes IIn = leakage current (refer to the MCU's voltage and current op erating ratings) VPP,DIFF Maximum differ ential input signal swing Signal-to-noise ratio Total harmonic distortion Gain=1 Gain=64 Gain=1 Gain=64 Gain=1 Gain=64 [(VREFPGA 2.33) - 0.2] / (2 Gain) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 8.3 V 4
THD
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57.7 87.3 85.3 dB dB dB dB dB 92.42 92.54 12.3 12.7 8.4 8.7 Gain=1, Average=4 Gain=1, Average=8 bits bits bits bits bits bits bits bits bits bits bits dB Gain=64, Average=4 Gain=64, Average=8 Gain=1, Average=32 Gain=2, Average=32 Gain=4, Average=32 Gain=8, Average=32 13.4 13.1 12.6 11.8 11.1 10.2 9.3 Gain=16, Average=32 Gain=32, Average=32 Gain=64, Average=32 See ENOB 6.02 ENOB + 1.76
SNR
dB
Average=32
Average=32, fin=100Hz Average=32, fin=100Hz
SFDR
Spurious free dy namic range Effective number of bits
ENOB
SINAD
Signal-to-noise plus distortion ra tio
1. Typical values assume VDDA =3.0V, Temp=25C, fADCK=6MHz unless otherwise stated. 2. Gain = 2PGAGx 3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC sampling rate and time of the switching). 4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting.

44
Preliminary
6.6.2 CMP and 6-bit DAC electrical specifications

Table 27. Comparator and 6-bit DAC electrical specifications
Symbol VDD IDDHS IDDLS IDDOFF VAIN VAIO VH Description Supply voltage Supply current, High-speed mode (EN=1, PMODE=1, VDDA >= VLVI_trip) Supply current, low-speed mode (EN=1, PMODE=0) Supply current, OFF Mode (EN=0,) Analog input voltage Analog input offset voltage Min. 1.71 VSS 0.3 Typ. Max. 3.6 200 20 100 VDD 20 Unit V A A nA V mV
Analog comparator hysteresis HYSTCTR = 00 HYSTCTR = 01 HYSTCTR = 10 HYSTCTR = 11
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5 10 20 30 VDD 0.5 0.5 20 50 120 420 120 250 TBD 8 0.5 0.3 0.5 0.3
mV mV mV mV V V ns ns ns A LSB1 LSB
VCMPOh VCMPOl tDHS tDLS
Output high Output low
Propagation delay, high-speed mode (EN=1, PMODE=1) Propagation delay, low-speed mode (EN=1, PMODE=1) Analog comparator initialization delay
IDAC6b INL DNL
6-bit DAC current adder (enabled) 6-bit DAC integral non-Llnearity
6-bit DAC differential non-linearity
1. 1 LSB = Vreference/64
6.6.3 12-bit DAC electrical characteristics

6.6.3.1
Symbol VDDA VDACR TA
12-bit DAC operating requirements

Desciption Supply voltage Reference voltage Temperature
Table 28. 12-bit DAC operating requirements

Min. 1.71 1.15 40 Table continues on the next page... Max. 3.6 3.6 105 Unit V V C 1 Notes

Preliminary
45
Table 28. 12-bit DAC operating requirements (continued)

Symbol CL IL Desciption Output load capacitance Output load current Min. Max. 100 1 Unit pF mA Notes 2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
6.6.3.2
Symbol n
12-bit DAC operating behaviors

Description Resolution
Table 29. 12-bit DAC operating behaviors

Min. 12 1 0 Typ. Max. 12 Unit b Notes
IDDA_DACLP Supply current low-power mode
IDDA_DACH Supply current high-speed mode

P
tDACLP tDACHP tCCDACLP tCCDACHP Vdacoutl Vdacouth INL DNL DNL VOFFSET EG PSRR TCO TGE AC Rop
Full-scale settling time (0x080 to 0xF7F) lowpower mode
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150 700 200 30 5 A A s s s s 100 15 TBD 100 VDACR 100 3 VDACR 8 1 1 0.5 0.5 0.4 0.1 60 Table continues on the next page... TBD TBD 0.8 0.6 90 TBD 250 dB
1 1 1 1
Full-scale settling time (0x080 to 0xF7F) highpower mode Code-to-code settling time (0xBF8 to 0xC08) low-power mode Code-to-code settling time (0xBF8 to 0xC08) high-speed mode DAC output voltage range low high-speed mode, no load, DAC set to 0x000
mV mV 2 3 4 5 5
DAC output voltage range high high-speed mode, no load, DAC set to 0xFFF
Integral non-linearity error high speed mode Differential non-linearity error VDACR > 2 V
LSB LSB LSB
Differential non-linearity error VDACR = VRE FO (1.15 V) Offset error Gain error Power supply rejection ratio, VDDA > = 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Offset aging coefficient Output resistance load = 3 k
%FSR %FSR
V/C ppm of FSR/C V/yr

46
Preliminary
Table 29. 12-bit DAC operating behaviors (continued)

Symbol SR Description Slew rate -80h F7Fh 80h High power (SPHP) Low power (SPLP) CT BW Channel to channel cross talk 3dB bandwidth High power (SPHP) Low power (SPLP) 1. 2. 3. 4. 5. 550 40 1.2 0.05 1.7 0.12 -80 dB kHz Min. Typ. Max. Unit V/s Notes
Settling within 1 LSB The INL is measured for 0+100mV to VDACR100 mV The DNL is measured for 0+100 mV to VDACR100 mV The DNL is measured for 0+100mV to VDACR100 mV with VDDA > 2.4V Calculated by a best fit curve from VSS+100 mV to VREF100 mV
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Figure 14. Typical INL error vs. digital code
47
6.6.4 Voltage Reference Electrical Specifications
Symbol VDDA TA CL
Description
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Figure 15. Offset at half scale vs. temperature Table 30. VREF full-range operating requirements
Min. Max. 3.6 105 100 1.71 40 Unit V C nF
Notes
Supply voltage Temperature Output load capacitance
Table 31. VREF full-range operating behaviors

Symbol Vout Vout Vdrift Description Voltage reference output with factory trim Voltage reference output without factory trim Temperature drift (Vmax -Vmin across the full temperature range) Min. TBD 1.15 Typ. 1.2 Max. TBD 1.24 7 Unit V V mV See Fig ure 16 Notes

48
Preliminary
Table 31. VREF full-range operating behaviors (continued)

Symbol Tc Ac Ioff Ibg Itr Description Temperature coefficient Aging coefficient Powered down current (off mode, VREFEN = 0, VRSTEN = 0) Bandgap only (MODE_LV = 00) current Tight-regulation buffer (MODE_LV =10) current Load regulation (MODE_LV = 10) current Tstup DC Buffer startup time Min. 100 Typ. TBD Max. TBD TBD 0.10 75 1.1 100 TBD TBD TBD Unit ppm/C ppm/year A A mA V/mA s Notes
Line regulation (power supply rejection)
Symbol TA
Description
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60 dB
mV
Table 32. VREF limited-range operating requirements

Min. 0 Max. 50
Unit C
Notes
Temperature
Table 33. VREF limited-range operating behaviors

Min. Max. TBD TBD
Symbol Vout
Description
Unit A
Notes
Voltage reference output with factory trim
TBD
Figure 16. Typical output vs.temperature
TBD
Figure 17. Typical output vs. VDD
6.7 Timers
See General Switching Specifications.
6.8 Communication interfaces

Preliminary
49
6.8.1 Ethernet Switching Specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII Signal Switching Specifications
The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices.
Symbol MII1 Description
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Table 34. Ethernet MII mode signal timing
Min. Max. 25 35% 65% 35% 65% 5 5 25 35% 65% 35% 65% 2 25
MII6 MII5
Unit MHz RXCLK period RXCLK period ns ns MHz TXCLK period TXCLK period ns ns
RXCLK frequency
RXCLK pulse width high
MII2
RXCLK pulse width low
MII3 MII4 MII5
RXD[3:0], RXDV, RXER to RXCLK setup RXCLK to RXD[3:0], RXDV, RXER hold TXCLK frequency
TXCLK pulse width high
MII6
TXCLK pulse width low
MII7 MII8
TXCLK to TXD[3:0], TXEN, TXER invalid TXCLK to TXD[3:0], TXEN, TXER valid
TXCLK (input)
MII8 MII7 Valid data
TXD[n:0]
TXEN
Valid data
TXER
Valid data
Figure 18. MII transmit signal timing diagram

50
Preliminary

MII2 MII1
RXCLK (input)
MII3 MII4
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
6.8.1.2
RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices.
Table 35. Ethernet RMII mode signal timing
Min. Num RMII1 RMII2 RMII3 RMII4 RMII7 RMII8 Description Max. 50 Unit MHz RMII_CLK period RMII_CLK period ns ns ns ns
EXTAL frequency (RMII input clock RMII_CLK) RMII_CLK pulse width high RMII_CLK pulse width low
RXD[1:0], CRS_DV, RXER to RMII_CLK setup RMII_CLK to RXD[1:0], CRS_DV, RXER hold RMII_CLK to TXD[1:0], TXEN invalid RMII_CLK to TXD[1:0], TXEN valid
6.8.2 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
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Figure 19. MII receive signal timing diagram
35% 35% 4 2 4 65% 65% 15

51
6.8.3 USB DCD Electrical Specifications

Table 36. USB DCD specifications
Symbol VDP_SRC VLGC IDP_SRC IDM_SINK RDM_DWN VDAT_REF Description USB_DP source voltage (up to 250 A) Threshold voltage for logic high USB_DP source current USB_DM sink current D- pulldown resistance for data pin contact detect Data detect voltage Min. TBD 0.8 7 50 14.25 0.25 Typ. TBD 10 100 TBD Max. TBD 2.0 13 150 24.8 0.4 Unit V V A A k V
6.8.4 USB Voltage Regulator Electrical Specifications

Symbol VREGIN IDDon IDDstby IDDoff ILOADrun ILOADstby VReg33out Description Min. 2.7 Typ.
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Table 37. USB voltage regulator electrical specifications
Max. 5.5 V 120 A A nA TBD 500 120 TBD 3 3.3 2.2 290 3.6 3.6 8.16 100 395 V V V F TBD 2.3 1.76 1 185 TBD TBD
Unit
Notes
Input supply voltage
Quiescent current Run mode, load current equal zero
Quiescent current Standby mode, load cur rent equal zero Quiescent current Shutdown mode Maximum load current Run mode
mA mA 1
Maximum load current Standby mode
Regulator output voltage Input supply (VRE GIN) > 3.6 V Run mode Standby mode
Pass-through mode COUT ESR ILIM External output capacitor External output capacitor equivalent series re sistance Current limitation threshold
m mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

52
Preliminary
6.8.5 DSPI Switching Specifications for Low-speed Operation

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
Table 38. Master Mode DSPI Timing (Low-speed mode)
Num Operating voltage Frequency of operation DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 Description Min. 1.71 Max. 3.6 12.5 Unit V MHz ns ns ns ns ns ns ns ns Notes 1
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid DSPI_SCK to DSPI_PCSn output hold DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced.
DSPI_PCSn
DSPI_SCK (CPOL=0) DSPI_SIN
DSPI_SOUT
Num Operating voltage Frequency of operation DS9
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4 x tBCLK (tSCK/2) - 4 (tSCK/2) - 4 (tSCK/2) - 4 -2 (tSCK/2) + 4 10 15 0
DS3 DS2 DS1 DS4 DS7 DS8 First data Data Last data DS5 DS6 First data Data Last data
Figure 20. DSPI Classic SPI Timing Master Mode Table 39. Slave Mode DSPI Timing (Low-speed Mode)
Description Min. 1.71 8 x tBCLK Table continues on the next page... Max. 3.6 6.25 Unit V MHz ns
DSPI_SCK input cycle time

Preliminary
53
Table 39. Slave Mode DSPI Timing (Low-speed Mode) (continued)

Num DS10 DS11 DS12 DS13 DS14 DS15 DS16 Description DSPI_SCK input high/low time DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSIP_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven Min. (tSCK/2) - 4 0 5 15 Max. (tSCK/2) + 4 20 15 15 Unit ns ns ns ns ns ns ns
DSPI_SS
DSPI_SCK (CPOL=0) DSPI_SOUT
DSPI_SIN
6.8.6 DSPI Switching Specifications (High-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
Table 40. Master Mode DSPI Timing (High-speed mode)
Num Operating voltage Frequency of operation DS1 DS2 DS3 DSPI_SCK output cycle time DSPI_SCK output high/low time DSPI_PCSn to DSPI_SCK output valid Table continues on the next page... Description Min. 2.7 2 x tBCLK (tSCK/2) 2 (tSCK/2) 2 Max. 3.6 25 (tSCK/2) + 2 Unit V MHz ns ns ns
54
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Figure 21. DSPI Classic SPI Timing Slave Mode

Table 40. Master Mode DSPI Timing (High-speed mode) (continued)

Num DS4 DS5 DS6 DS7 DS8 Description DSPI_SCK to DSPI_PCSn output hold DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold Min. (tSCK/2) 2 2 TBD 0 Max. 8.5 Unit ns ns ns ns ns
DSPI_SCK (CPOL=0) DSPI_SIN
DSPI_SOUT
Num
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DSPI_PCSn
Figure 22. DSPI Classic SPI Timing Master Mode
Table 41. Slave Mode DSPI Timing (High-speed mode)

Description Min. 2.7
Max. 3.6
Unit V MHz ns ns ns ns ns ns ns ns
Operating voltage
Frequency of operation DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16
12.5
DSPI_SCK input cycle time
4 x tBCLK
DSPI_SCK input high/low time
(tSCK/2) 2 0 2 7
(tSCK/2 + 2 TBD 14 14
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven

Preliminary
55
DSPI_SS
DS10 DS9
DSPI_SCK (CPOL=0) DSPI_SOUT

DS13 DS15 DS12 First data DS14 First data Data Last data DS11 Data Last data DS16
DSPI_SIN
6.8.7 SDHC Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.
Table 42. SDHC switching specifications
Min. Card input clock Num Symbol Description Max. Unit
SD1
fpp fpp fpp fOD
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Figure 23. DSPI Classic SPI Timing Slave Mode
Clock frequency (low speed) 0 0 0 0 7 7 400 25 20 Clock frequency (SD\SDIO full speed) Clock frequency (MMC full speed) Clock frequency (identification mode) Clock low time 400 3 3 Clock high time Clock rise time Clock fall time SDHC output delay (output valid) -5 6.5 SDHC input setup time SDHC input hold time 5 0
kHz MHz MHz kHz ns ns ns ns
SD2 SD3 SD4 SD5
tWL tWH
tTLH tTHL
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 SD8 tTHL tTHL ns ns

56
Preliminary

SD3 SD2 SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7 SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
6.8.8 I2S Switching Specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below.
Table 43. I2S master mode timing
Num Description Min. 2.7 Max. 3.6 Unit V ns MCLK period ns BCLK period ns ns ns ns ns ns
Operating voltage S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
I2S_MCLK cycle time
I2S_MCLK pulse width high/low I2S_BCLK cycle time I2S_BCLK pulse width high/low I2S_BCLK to I2S_FS output valid I2S_BCLK to I2S_FS output invalid I2S_BCLK to I2S_TXD valid I2S_BCLK to I2S_TXD invalid I2S_RXD/I2S_FS input setup before I2S_BCLK I2S_RXD/I2S_FS input hold after I2S_BCLK
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Figure 24. SDHC timing
2 x tSYS 45% 5 x tSYS 45% -2.5 -3 20 0 55% 55% 15 15

57

S1 S2 S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4 S5
S4 S6
I2S_FS (output)
S9 S10
I2S_FS (input)
S7 S8
S7 S8
I2S_TXD
I2S_RXD
Num
Description
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Figure 25. I2S timing master mode Table 44. I2S alave mode timing
Min. 2.7 Max. 3.6 8 x tSYS 45% 10 3 55% 0 20 10 2
S11 S12 S12 S15 S16 S13 S14 S15 S15 S16 S17 S18
S9
S10
Unit V ns MCLK period ns ns ns ns ns ns
Operating voltage S11 S12 S13 S14 S15 S16 S17 S18
I2S_BCLK cycle time (input)
I2S_BCLK pulse width high/low (input) I2S_FS input setup before I2S_BCLK I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid I2S_RXD setup before I2S_BCLK I2S_RXD hold after I2S_BCLK
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
S16
I2S_TXD
I2S_RXD
Figure 26. I2S timing slave modes

58
Preliminary
6.9 Human-machine interfaces (HMI)

6.9.1 General Switching Specifications
These general purpose specifications apply to all signals configured for GPIO, SCI, FlexCAN, CMT, I2C, and IEEE 1588 timer signals.
Table 45. General switching specifications
GPIO pin interrupt pulse width (digital glitch filter disa bled) Synchronous path GPIO pin interrupt pulse width (digital glitch filter disa bled, analog filter enabled) Asynchronous path GPIO pin interrupt pulse width (digital glitch filter disa bled, analog filter disabled) Asynchronous path External reset pulse width (digital glitch filter disabled) Mode select (EZP_CS) hold time after reset deasser tion Port rise and fall time (high drive strength) Slew disabled Slew enabled
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1.5 100 16 ns ns TBD 2 12 36 ns ns 32 36 ns ns
Symbol
Description
Min.
Max.
Unit
Notes 1 2
2
Bus clock cycles
Bus clock cycles 3
Port rise and fall time (low drive strength) Slew disabled Slew enabled 1. 2. 3. 4.
The greater synchronous and asynchronous timing must be met. This is the shortest pulse that is guaranteed to be recognized. 75pF load 15pF load
6.9.2 TSI Electrical Specifications

Table 46. Touch Sensing Input module specifications
Symbol VDDTSI CELE fREFmax Description Operating voltage Target electrode capacitance range Reference oscillator frequency Min. 1.71 1 Typ. 20 5.5 Max. 3.6 500 TBD Unit V pF MHz 1 Notes

Preliminary
59
Dimensions
Table 46. Touch Sensing Input module specifications (continued)

Symbol fELEmax CREF VDELTA IREF IELE Pres5 Pres20 Pres100 Max Sens20 MaxSens Res TCon20 ITSI_RUN ITSI_LP Description Electrode oscillator frequency Internal reference capacitor Oscillator delta voltage Reference oscillator current source base current Electrode oscillator current source base current Electrode capacitance measurement precision Electrode capacitance measurement precision Electrode capacitance measurement precision Max sensitivity @ 20pF electrode Maximum sensitivity Resolution Min. TBD TBD TBD TBD Typ. 0.5 1 600 1 1 TBD TBD TBD Max. TBD TBD TBD TBD TBD TBD TBD TBD 600 24 16 Unit MHz pF mV A A % % % 2 3 4 5 6 7 8 Notes
Response time @ 20pF
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0.15 0.326 0.326 fF fF 0.006 30 s TBD 1 A A TBD 98ASS23177W 98ASA00222D
bits 9
Current added in run mode
Low power mode current adder
1. The TSI module is functional with capacitance values outside of this range. However, optimal performance is not guaranteed. 2. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current 3. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current 4. Measured with a 5pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 8; Iext = 16 5. Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 2; Iext = 16 6. Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 16, NCSC = 3; Iext = 16 7. 6.2ms scan time 8. 1pF electrode capacitance with 4.96ms scan time 9. Time that takes to do one complete measurement of the electrode. Sensitivity resolution of 0.0133pF
7 Dimensions
7.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for the drawings document number:
If you want the drawing for this package 144-pin LQFP 144-pin MAPBGA Then use this document number

60
Preliminary
Pinout
8 Pinout
8.1 K60 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
L5 M5
NC NC
A10 NC B10 NC C10 NC D3 D2 D1 E4 E5 F6 E3 E2 E1 F4 F3 F2 F1 G4 G3 E6 F7 H3 H1 H2 ADC1_SE4a ADC1_SE5a ADC1_SE6a ADC1_SE7a VDD VSS DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED VDD VSS VSS USB0_DP USB0_DM
Pr el im in ar y
NC NC NC NC NC ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA ADC1_SE5a PTE1 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL ADC1_SE6a PTE2 SPI1_SCK SPI1_SIN UART1_CTS _b SDHC0_DCL K ADC1_SE7a PTE3 UART1_RTS _b SDHC0_CMD VDD VSS PTE4 PTE5 PTE6 SPI1_PCS0 SPI1_PCS2 SPI1_PCS3 UART3_TX SDHC0_D3 UART3_RX SDHC0_D2 UART3_CTS _b I2S0_MCLK I2S0_CLKIN PTE7 PTE8 PTE9 PTE10 PTE11 PTE12 VDD VSS VSS USB0_DP USB0_DM UART3_RTS _b UART5_TX UART5_RX UART5_CTS _b UART5_RTS _b I2S0_RXD I2S0_RX_FS I2S0_RX_BC LK I2S0_TXD I2S0_TX_FS I2S0_TX_BC LK
144 144 QFP BGA
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort

61
Pinout 144 144 QFP BGA 21 22 23 24 25 26 27 G1 G2 J1 J2 K1 K2 L1 Default VOUT33 VREGIN ADC0_DP1 ADC0_DM1 ADC1_DP1 ADC1_DM1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 VDDA VREFH VREFL VSSA ADC1_SE16 ADC0_SE16 VREF_OUT DAC0_OUT DAC1_OUT XTAL32 EXTAL32 VBAT VDD VSS ADC0_SE17 ADC0_SE18 DISABLED DISABLED DISABLED JTAG_TCLK/ TSI0_CH1 SWD_CLK/ EZP_CLK JTAG_TDI/ EZP_DI TSI0_CH2 ALT0 VOUT33 VREGIN ADC0_DP1 ADC0_DM1 ADC1_DP1 ADC1_DM1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
29
M1
30
M2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
H5 G5 G6 H6 K3 J3 M3 L3 L4 M7 M6 L6 M4 K5 K4 J4 H4 J5
51
J6
Pr el im in ar y
PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 VDDA VREFH VREFL VSSA ADC1_SE16 VREF_OUT ADC0_SE16 DAC0_OUT DAC1_OUT XTAL32 EXTAL32 VBAT VDD VSS ADC0_SE17 ADC0_SE18 PTE24 PTE25 PTE26 PTE27 PTE28 PTA0 UART0_CTS _b UART0_RX FTM0_CH5 JTAG_TCLK/ EZP_CLK SWD_CLK JTAG_TDI EZP_DI CAN1_TX CAN1_RX UART4_TX UART4_RX UART4_CTS _b UART4_RTS _b ENET_1588_ CLKIN EWM_OUT_b EWM_IN RTC_CLKOU USB_CLKIN T PTA1 FTM0_CH6
28
L2
PGA0_DM/ ADC0_DM0/ ADC1_DM3

62
Preliminary
Pinout 144 144 QFP BGA 52 K6 Default JTAG_TDO/ TRACE_SW O/EZP_DO JTAG_TMS/ SWD_DIO NMI_b/ EZP_CS_b JTAG_TRST VDD VSS DISABLED ADC0_SE10 ADC0_SE11 DISABLED DISABLED DISABLED CMP2_IN0 CMP2_IN1 VDD ALT0 TSI0_CH3 ALT1 PTA2 ALT2 UART0_TX ALT3 FTM0_CH7 ALT4 ALT5 ALT6 ALT7 JTAG_TDO/ TRACE_SW O JTAG_TMS/ SWD_DIO NMI_b RMII0_RXER/ CMP2_OUT MII0_RXER I2S0_RX_BC JTAG_TRST LK EZP_CS_b EzPort EZP_DO
53 54 55 56 57 58 59 60 61 62 63 64 65 66
K7 L7 M8 E7 G7 J7 J8 K8 L8 M9 L9 K9 J9
TSI0_CH4 TSI0_CH5
PTA3 PTA4 PTA5
UART0_RTS _b
FTM0_CH0 FTM0_CH1 FTM0_CH2
L10 DISABLED
67 68 69 70 71 72 73 74 75 76 77 78 79 80
L11 DISABLED K10 DISABLED K11 ADC1_SE17 E8 G8 VDD VSS
M12 EXTAL M11 XTAL L12 RESET_b K12 DISABLED J12 J11 J10 DISABLED DISABLED DISABLED
H12 DISABLED H11 DISABLED
Pr el im in ar y
PTA6 FTM0_CH3 ADC0_SE10 PTA7 FTM0_CH4 ADC0_SE11 PTA8 FTM1_CH0 FTM1_QD_P HA PTA9 FTM1_CH1 MII0_RXD3 FTM1_QD_P HB PTA10 FTM2_CH0 MII0_RXD2 FTM2_QD_P HA PTA11 FTM2_CH1 MII0_RXCLK FTM2_QD_P HB CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ MII0_RXD1 I2S0_TXD CMP2_IN1 PTA13 CAN0_RX FTM1_CH1 RMII0_RXD0/ MII0_RXD0 I2S0_TX_FS PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ DV/ MII0_RXDV I2S0_TX_BC LK PTA15 SPI0_SCK UART0_RX RMII0_TXEN/ MII0_TXEN I2S0_RXD PTA16 SPI0_SOUT SPI0_SIN UART0_CTS _b RMII0_TXD0/ MII0_TXD0 I2S0_RX_FS ADC1_SE17 PTA17 UART0_RTS _b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK VDD VSS EXTAL XTAL RESET_b PTA24 PTA25 PTA26 PTA27 PTA28 PTA29 MII0_TXD2 MII0_TXCLK MII0_TXD3 MII0_CRS MII0_TXER MII0_COL FB_A29 FB_A28 FB_A27 FB_A26 FB_A25 FB_A24 PTA18 PTA19 FTM0_FLT2 FTM1_FLT0 FTM_CLKIN0 FTM_CLKIN1 LPT0_ALT1
VSS
TRACE_CLK OUT
TRACE_D3 TRACE_D2
TRACE_D1
TRACE_D0
FTM1_QD_P HA
FTM1_QD_P HB
I2S0_CLKIN

63
Pinout 144 144 QFP BGA 81 Default ALT0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 ALT1 PTB0 ALT2 I2C0_SCL ALT3 FTM1_CH0 ALT4 RMII0_MDIO/ MII0_MDIO RMII0_MDC/ MII0_MDC ENET0_1588 _TMR0 ENET0_1588 _TMR1 ENET0_1588 _TMR2 ALT5 ALT6 FTM1_QD_P HA FTM1_QD_P HB FTM0_FLT3 FTM0_FLT0 FTM1_FLT0 FTM2_FLT0 ALT7 EzPort
H10 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 H9 ADC0_SE9/ ADC1_SE9/ TSI0_CH6
82
PTB1
I2C0_SDA
FTM1_CH1
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
G12 ADC0_SE12/ ADC0_SE12/ PTB2 TSI0_CH7 TSI0_CH7 G11 ADC0_SE13/ ADC0_SE13/ PTB3 TSI0_CH8 TSI0_CH8 G10 ADC1_SE10 G9 ADC1_SE11 ADC1_SE10 ADC1_SE11 PTB4 PTB5
I2C0_SCL I2C0_SDA
UART0_RTS _b UART0_CTS _b
F12 ADC1_SE12 F11 ADC1_SE13 F10 DISABLED F9 DISABLED
E12 ADC1_SE14 E11 ADC1_SE15 H7 F5 E9 VSS VDD TSI0_CH10
E10 TSI0_CH9 D12 TSI0_CH11 D11 TSI0_CH12 D10 DISABLED D9 DISABLED C12 DISABLED C11 DISABLED
B12 ADC0_SE14/ ADC0_SE14/ PTC0 TSI0_CH13 TSI0_CH13 B11 ADC0_SE15/ ADC0_SE15/ PTC1 TSI0_CH14 TSI0_CH14 A12 ADC0_SE4b/ ADC0_SE4b/ PTC2 CMP1_IN0/ CMP1_IN0/ TSI0_CH15 TSI0_CH15 A11 CMP1_IN1 H8 A9 D8 VSS VDD DISABLED DISABLED CMP1_IN1 VSS VDD PTC4 PTC5 PTC3
106 107 108 109 110
64
Pr el im in ar y
ENET0_1588 _TMR3 ADC1_SE12 PTB6 FB_AD23 ADC1_SE13 PTB7 FB_AD22 FB_AD21 FB_AD20 FB_AD19 PTB8 PTB9 UART3_RTS _b SPI1_PCS1 UART3_CTS _b UART3_RX UART3_TX ADC1_SE14 PTB10 SPI1_PCS0 FTM0_FLT1 ADC1_SE15 PTB11 SPI1_SCK FB_AD18 FTM0_FLT2 VSS VDD TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_BC LK I2S0_TX_FS FB_AD15 FTM2_QD_P HA TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 FB_OE_b FTM2_QD_P HB CMP0_OUT CMP1_OUT PTB20 SPI2_PCS0 FB_AD31 PTB21 SPI2_SCK FB_AD30 PTB22 PTB23 SPI2_SOUT SPI2_SIN SPI0_PCS4 SPI0_PCS3 SPI0_PCS2 SPI0_PCS5 PDB0_EXTR G UART1_RTS _b UART1_CTS _b UART1_RX I2S0_TXD FTM0_CH0 FTM0_CH1 FB_AD29 FB_AD28 FB_AD14 FB_AD13 FB_AD12 CMP2_OUT SPI0_PCS1 FTM0_CH2 FB_CLKOUT SPI0_PCS0 SPI0_SCK UART1_TX FTM0_CH3 LPT0_ALT2 FB_AD11 FB_AD10 CMP1_OUT CMP0_OUT

Pinout 144 144 QFP BGA 111 112 113 114 115 116 117 118 119 120 121 122 123 C8 B8 A8 D7 C7 B7 A7 D6 C6 B6 A6 Default CMP0_IN0 CMP0_IN1 ALT0 CMP0_IN0 CMP0_IN1 ALT1 PTC6 PTC7 ALT2 SPI0_SOUT SPI0_SIN I2S0_MCLK I2S0_CLKIN ALT3 PDB0_EXTR G ALT4 ALT5 FB_AD9 FB_AD8 FB_AD7 FTM2_FLT0 ALT6 ALT7 EzPort
ADC1_SE4b/ ADC1_SE4b/ PTC8 CMP0_IN2 CMP0_IN2 ADC1_SE5b/ ADC1_SE5b/ PTC9 CMP0_IN3 CMP0_IN3 ADC1_SE6b/ ADC1_SE6b/ PTC10 CMP0_IN4 CMP0_IN4 ADC1_SE7b DISABLED DISABLED DISABLED DISABLED VSS VDD DISABLED ADC1_SE7b PTC11 PTC12 I2C1_SCL I2C1_SDA
I2S0_RX_BC FB_AD6 LK I2S0_RX_FS I2S0_RXD UART4_RTS _b FB_AD5 FB_RW_b FB_AD27
124
D5
DISABLED
125
C5
DISABLED
126
B5
DISABLED
127
A5
DISABLED
128 129 130 131 132 133 134 135
D4 C4 B4 A4 A3 A2 F8
ADC0_SE5b DISABLED DISABLED DISABLED ADC0_SE6b ADC0_SE7b VDD
M10 VSS
Pr el im in ar y
PTC13 UART4_CTS _b FB_AD26 PTC14 PTC15 UART4_RX UART4_TX FB_AD25 FB_AD24 VSS VDD PTC16 CAN1_RX UART3_RX ENET0_1588 FB_CS5_b/ _TMR0 FB_TSIZ1/ FB_BE23_16 _BLS15_8_b PTC17 CAN1_TX UART3_TX ENET0_1588 FB_CS4_b/ _TMR1 FB_TSIZ0/ FB_BE31_24 _BLS7_0_b PTC18 UART3_RTS _b ENET0_1588 FB_TBST_b/ _TMR2 FB_CS2_b/ FB_BE15_8_ BLS23_16_b PTC19 UART3_CTS _b ENET0_1588 FB_CS3_b/ FB_TA_b _TMR3 FB_BE7_0_B LS31_24_b FB_ALE/ FB_CS1_b/ FB_TS_b PTD0 SPI0_PCS0 UART2_RTS _b ADC0_SE5b PTD1 PTD2 PTD3 PTD4 ADC0_SE6b ADC0_SE7b VSS VDD PTD5 PTD6 SPI0_SCK SPI0_SOUT SPI0_SIN SPI0_PCS1 SPI0_PCS2 SPI0_PCS3 UART2_CTS _b UART2_RX UART2_TX UART0_RTS _b UART0_CTS _b UART0_RX FTM0_CH4 FTM0_CH5 FTM0_CH6 FB_CS0_b FB_AD4 FB_AD3 FB_AD2 FB_AD1 FB_AD0 EWM_IN EWM_OUT_b FTM0_FLT0

65
Pinout 144 144 QFP BGA 136 137 138 139 140 141 142 143 144 A1 C9 B9 B3 B2 B1 C3 C2 C1 Default DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED ALT0 ALT1 PTD7 PTD8 PTD9 PTD10 PTD11 PTD12 PTD13 PTD14 PTD15 SPI2_PCS0 SPI2_SCK SPI2_SOUT SPI2_SIN SPI2_PCS1 ALT2 CMT_IRO I2C0_SCL I2C0_SDA ALT3 UART0_TX UART5_RX UART5_TX UART5_RTS _b UART5_CTS _b SDHC0_CLKI N SDHC0_D4 SDHC0_D5 SDHC0_D6 SDHC0_D7 ALT4 FTM0_CH7 ALT5 ALT6 FTM0_FLT1 FB_A16 FB_A17 FB_A18 FB_A19 FB_A20 FB_A21 FB_A22 FB_A23 ALT7 EzPort
8.2 K60 Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section.
66
Pr el im in ar y
Pinout
PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 PTC19 PTC18 PTC17 PTC16 PTC15 PTC14 PTC13 PTC12 PTC11 PTC10 PTD9 PTD8 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC9 PTC8 PTC7 PTC6 111 PTC5 110 PTC4 109 108 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 72 73 VDD VDD 122 VSS VSS 121
141
142
132
131
139
135
129
125
119
138
136
128
126
118
140
130
144
143
137
134
133
127
124
123
120
117
116
115
114
PTE0 PTE1 PTE2 PTE3 VDD VSS PTE4 PTE5 PTE6 PTE7 PTE8 PTE9 PTE10 PTE11 PTE12 VDD VSS VSS
113
112
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VDD VSS PTC3 PTC2 PTC1 PTC0 PTB23 PTB22 PTB21 PTB20 PTB19 PTB18 PTB17 PTB16 VDD VSS PTB11 PTB10 PTB9 PTB8 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PTA29 PTA28 PTA27 PTA26 PTA25 PTA24 RESET_b PTA19
107
USB0_DP USB0_DM
VOUT33 VREGIN ADC0_DP1 ADC0_DM1
ADC1_DP1 ADC1_DM1 PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA1_DM/ADC1_DM0/ADC0_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
VDDA VREFH VREFL VSSA
ADC1_SE16 ADC0_SE16
Pr el im in ar y
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 37 38 39 59 60 61 62 63 64 65 66 67 68 69 70 EXTAL32 PTA1 PTA9 PTA10 VSS 71 VBAT PTE24 PTA2 DAC1_OUT PTE28 PTA13 PTA5 PTE25 DAC0_OUT PTE27 PTA14 XTAL32 PTA16 PTA17 PTA0 PTA6 PTA7 VDD PTA8 VREF_OUT VDD PTE26 PTA11 PTA12
Figure 27. K60 144 LQFP Pinout Diagram

Preliminary
PTA15
PTA18
PTA3
PTA4
VDD
VSS
VSS
67
Revision History
1 2 3 4 5 6 7 8 9 10 11 12
PTD7
PTD6
PTD5
PTD4
PTD0
PTC16
PTC12
PTC8
PTC4
NC
PTC3
PTC2
PTD12
PTD11
PTD10
PTD3
PTC19
PTC15
PTC11
PTC7
PTD9
NC
PTC1
PTC0
PTD15
PTD14
PTD13
PTD2
PTC18
PTC14
PTC10
PTC6
PTD8
NC
PTB23
PTB22
PTE2
PTE1
PTE0
PTD1
PTC17
PTC13
PTC9
PTC5
PTB21
PTB20
PTB19
PTB18
Pr el im in ar y
PTE4 PTE3 VDD VDD VDD VDD PTB17 PTB16 PTB11 PTE8 PTE7 VDD VSS VSS VDD PTB9 PTB8 PTB7 PTE12 PTE11 VREFH VREFL VSS VSS PTB5 PTB4 PTB3 VSS PTE28 VDDA VSSA VSS VSS PTB1 PTB0 PTA29 ADC0_SE16 PTE27 PTA0 PTA1 PTA6 PTA7 PTA13 PTA27 PTA26 ADC1_SE16 PTE26 PTE25 PTA2 PTA3 PTA8 PTA12 PTA16 PTA17 DAC0_OUT DAC1_OUT NC VBAT PTA4 PTA9 PTA11 PTA14 PTA15 VREF_OUT PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA19 3 4 5 6 7 8 9 10 11
PTE6
PTE5
PTB10
PTE10
PTE9
PTB6
VOUT33
VREGIN
PTB2
USB0_DP
USB0_DM
PTA28
ADC0_DP1
ADC0_DM1
PTA25
ADC1_DP1/
ADC1_DM1
PTA24
PGA0_DP/ ADC0_DP0/ ADC1_DP3
PGA0_DM/ ADC0_DM0/ ADC1_DM3
RESET_b
PGA1_DP/ M ADC1_DP0/ ADC0_DP3 1
PGA1_DM/ ADC1_DM0/ ADC0_DM3 2
PTA18
12
Figure 28. K60 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 47. Revision History
Rev. No. 1 Date 11/2010 Substantial Changes Initial public revision

68
Preliminary
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Pr el im in ar y
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Freescale Semiconductor Data Sheet: Product Preview

Document Number: K60P144M100SF2 Rev. 1, 11/2010

Supports the following: MK60N256VLQ100, MK60X256VLQ100, MK60N512VLQ100, MK60N256VMD100, MK60X256VMD100, MK60N512VMD100

K60 Sub-Family Data Sheet

3.9 Typical Value Conditions...................................................10 4 Ratings......................................................................................10

4.1 Thermal handling ratings...................................................10 4.2 Moisture handling ratings..................................................11

4.3 ESD handling ratings.........................................................11

4.4 Voltage and current operating ratings...............................11 5 General.....................................................................................12

5.1 Nonswitching electrical specifications...............................12 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5

5.1.6 5.1.7 5.1.8

Freescale Semiconductor, Inc.

Reliability Characteristics....................31 Write Endurance to FlexRAM for EEPROM.............................................32

EzPort Switching Specifications............................33 Flexbus Switching Specifications..........................34

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary

12-bit DAC operating behaviors..........46

SDHC Specifications.............................................56 I2S Switching Specifications.................................57

Voltage Reference Electrical Specifications..........48

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Temperature range (C) Package identifier

Maximum CPU frequency (MHz)

This is an example part number: MK60N512VMD100

3 Terminology and guidelines

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary

Terminology and guidelines

3.2 Definition: Operating behavior

3.3 Definition: Attribute

Freescale Semiconductor, Inc.

Terminology and guidelines

3.4 Definition: Rating

This is an example of an operating rating:

3.5 Result of exceeding a rating

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.

Freescale Semiconductor, Inc.

Terminology and guidelines

3.6 Relationship between ratings and operating requirements

Limited operating range

Normal operating range

Limited operating range

3.7 Guidelines for ratings and operating requirements

3.8 Definition: Typical value

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.

3.9 Typical Value Conditions

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary

4.1 Thermal handling ratings

4.2 Moisture handling ratings

4.3 ESD handling ratings

Electrostatic discharge voltage, human body model

4.4 Voltage and current operating ratings

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.

VBAT voltage required to retain the VBAT register file

5.1 Nonswitching electrical specifications

5.1.1 Voltage and Current Operating Requirements

Table 1. Voltage and current operating requirements

Analog supply voltage

0.7 VDD 0.75 VDD

0.06 VDD Table continues on the next page...

0.35 VDD 0.3 VDD

K60 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.

Freescale Semiconductor, Inc.

Table 1. Voltage and current operating requirements (continued)

5.1.2 LVD and POR operating requirements

Falling VDD POR detect voltage