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78K/0 Series
Instructions
Document No. U12326EJ4V0UM00 (4th edition) Date Published October 2001 N CP(K)
Printed in Japan
1995
[MEMO]
IEBus is a trademark of NEC Corporation. Caution: Purchase of NEC I 2C components conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4
Regional Information
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Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of 78K/0 Series products and to design and develop its application systems and programs.
Purpose
This manual is intended to give users an understanding of the various kinds of instruction functions of 78K/0 Series products.
Organization
This manual is broadly divided into the following sections. CPU functions Instruction set Explanation of instructions
It is assumed that readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To check the details of the functions of an instruction whose mnemonic is known: Refer to APPENDICES B and C. To check an instruction whose mnemonic is not known but whose general function is known: Find the mnemonic in CHAPTER 4 INSTRUCTION SET and then check the detailed functions in CHAPTER 5 EXPLANATION OF INSTRUCTIONS. To learn about the various kinds of 78K/0 Series product instructions in general: Read this manual in the order of CONTENTS. To learn about the hardware functions of 78K/0 Series products: See the separate users manuals.
Conventions
Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ................. XXXX or XXXXB Decimal .............. XXXX Hexadecimal ...... XXXXH
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Common to 78K/0 Series
Document Name Users Manual Instructions Application Note
Note
Note Some subseries may not be covered. Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
CONTENTS
CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
MEMORY SPACE ............................................................................................................... 12 Memory Spaces ................................................................................................................12 Internal Program Memory (Internal ROM) Space .......................................................... 12 Vector Table Area ............................................................................................................. 12 CALLT Instruction Table Area ......................................................................................... 12 CALLF Instruction Entry Area ......................................................................................... 12 Internal Data Memory (Internal RAM) Space .................................................................. 12 Special Function Register (SFR) Area ............................................................................ 13 External Memory Space ................................................................................................... 13 IEBusTM Register Area ...................................................................................................... 13
2.2 2.3
3.2
4.2
CHAPTER 5 EXPLANATION OF INSTRUCTIONS ................................................................................. 46 5.1 8-Bit Data Transfer Instructions ...................................................................................... 48 5.2 16-Bit Data Transfer Instructions .................................................................................... 51 5.3 8-Bit Operation Instructions ............................................................................................ 54 5.4 16-Bit Operation Instructions .......................................................................................... 63 5.5 Multiply/Divide Instructions ............................................................................................ 67 5.6 Increment/Decrement Instructions ................................................................................. 70 5.7 Rotate Instructions ...........................................................................................................75 5.8 BCD Adjust Instructions .................................................................................................. 82 5.9 Bit Manipulation Instructions .......................................................................................... 85 5.10 Call Return Instructions ................................................................................................... 93 5.11 Stack Manipulation Instructions ................................................................................... 101 5.12 Unconditional Branch Instruction ................................................................................ 105 5.13 Conditional Branch Instructions ................................................................................... 107 5.14 CPU Control Instructions ..............................................................................................116 APPENDIX A REVISION HISTORY .....................................................................................................123 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) ............................................. 124 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) ...................... 126
10
LIST OF FIGURES
Title
Page
Program Counter Configuration .............................................................................................................. 14 Program Status Word Configuration ....................................................................................................... 14 Stack Pointer Configuration .................................................................................................................... 16 Data to Be Saved to Stack Memory ....................................................................................................... 16 Data to Be Reset from Stack Memory .................................................................................................... 16 General-Purpose Register Configuration ............................................................................................... 18
LIST OF TABLES
Title
Page
General-Purpose Register Absolute Address Correspondence Table ..................................................... 17 Operand Identifiers and Description Methods .......................................................................................... 32
11
CHAPTER 1
MEMORY SPACE
12
(3) RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products in the 78K/0 Series to which internal expansion RAM is allocated. (5) RAM for LCD display There are some products in the 78K/0 Series to which RAM for LCD display is allocated. This RAM can also be used as an ordinary RAM area.
13
CHAPTER 2 REGISTERS
2.1.2 Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 2-2. Program Status Word Configuration
7 IE Z RBS1 AC RBS0 0 ISP 0 CY
14
CHAPTER 2 REGISTERS
(1) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. This flag is reset (0) upon DI instruction execution or interrupt request acknowledgment and is set (1) upon execution of the EI instruction. (2) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (3) Register bank select flags (RBS0 and RBS1) These are 2-bit flags used to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SBL RBn instruction execution is stored. (4) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (5) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, vectored interrupt requests specified as low priority by the priority specification flag register (PR) are disabled for acknowledgment. Actual acknowledgment for interrupt requests is controlled by the state of the interrupt enable flag (IE). (6) Carry flag (CY) This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
15
CHAPTER 2 REGISTERS
2.1.3 Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 2-3. Stack Pointer Configuration
15 SP 0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 2-4 and 2-5. Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution. Figure 2-4. Data to Be Saved to Stack Memory
Interrupt and BRK instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Lower half register pairs Upper half register pairs SP SP _ 2 SP _ 2 SP _ 1 SP PC7-PC0 PC15-PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7-PC0 PC15-PC8 PSW
PUSH rp instruction
SP SP + 1 SP SP + 2
SP SP + 1 SP + 2
PC7-PC0 PC15-PC8
SP SP + 1 SP + 2 SP SP + 3
16
CHAPTER 2 REGISTERS
17
CHAPTER 2 REGISTERS
16-bit processing FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H 15 0 7 RP0 RP1 RP2 RP3
8-bit processing R7 R6 R5 R4 R3 R2 R1 R0 0
16-bit processing FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H 15 0 7 AX BC DE HL
8-bit processing H L D E B C A X 0
18
CHAPTER 2 REGISTERS
19
CHAPTER 3 ADDRESSING
20
CHAPTER 3 ADDRESSING
3.1.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instructions can be branched to all memory spaces. The CALLF !addr11 instruction is branched to the area of 0800H to 0FFFH. [Illustration] CALL !addr16, BR !addr16 instruction
15 PC
8 7
7 6
3 CALLF
15 PC 0 0 0 0
11 10 1
8 7
21
CHAPTER 3 ADDRESSING
3.1.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. When the CALLT [addr5] instruction is executed, table indirect addressing is performed. Executing this instruction enables the value to be branched to all memory spaces referencing the address stored in the memory table of 40H to 7FH. [Illustration]
7 Instruction code 1 6 1 5 ta40 1 0 1
15 Effective address 0 0 0 0 0 0 0
8 0
7 0
6 1
1 0 0
Effective address+1
High addr.
15 PC
22
CHAPTER 3 ADDRESSING
3.1.4 Register addressing [Function] The register pair (AX) contents to be specified by an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A 0 7 X 0
15 PC
23
CHAPTER 3 ADDRESSING
[Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing.
24
CHAPTER 3 ADDRESSING
3.2.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the instruction codes. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified by 3 bits in the instruction code. [Operand format]
Identifier r rp X, A, C, B, E, D, L, H AX, BC, DE, HL Description
r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL). [Description example] MOV A, C; When selecting the C register for r
Instruction code 0 1 1 0 0 0 1 0
25
CHAPTER 3 ADDRESSING
3.2.3 Direct addressing [Function] Direct addressing directly addresses the memory indicated by the immediate data in the instruction word. [Operand format]
Identifier addr16 Description Label or 16-bit immediate data
Instruction code
OP code
00H
FEH
[Illustration]
7 OP code addr16 (lower) addr16 (upper) 0
Memory
26
CHAPTER 3 ADDRESSING
3.2.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte fixed space FE20H to FF1FH. An internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the entire SFR area. Ports that are frequently accessed in a program, a compare register of the timer/event counter and a capture register of the timer/event counter are mapped in the area FF00H through FF1FH, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format]
Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only)
[Description example] MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H
Instruction code 0 0 0 1 0 0 0 1 OP code
30H (saddr-offset)
[Illustration]
7 OP code saddr-offset 0
When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1.
27
CHAPTER 3 ADDRESSING
3.2.5 Special-function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format]
Identifier sfr sfrp Special function register name 16-bit-manipulatable special function register name (even address only) Description
20H (sfr-offset)
[Illustration]
7 OP code sfr-offset
28
CHAPTER 3 ADDRESSING
3.2.6 Register indirect addressing [Function] Register indirect addressing addresses memory with register pair contents specified as an operand. The register pair to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register pair specification in instruction codes. [Operand format]
Identifier
[Illustration]
15 DE D
8 7 E 7 Memory
29
CHAPTER 3 ADDRESSING
3.2.7 Based addressing [Function] 8-bit immediate data is added to the contents of the HL register pair as a base register and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified by the register bank select flag (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier
Description [HL+byte]
3.2.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the HL register pair as a base register and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flag (RBS0 to RBS1). Addition is performed by expanding the B or C register as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier
30
CHAPTER 3 ADDRESSING
3.2.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables addressing of the internal high-speed RAM area only. [Description example] In the case of PUSH DE
Instruction code 1 0 1 1 0 1 0 1
31
CHAPTER 4
INSTRUCTION SET
This chapter lists the instructions in the 78K/0 Series instruction set. The instructions are common to all 78K/0 Series products.
4.1 Operation
For the operation list for each product, refer to the users manual of each product. 4.1.1 Operand identifiers and description methods Operands are described in the Operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $ and [ ] are key words and are described as they are. Each symbol has the following meaning. #: Immediate data specification !: Absolute address specification $: Relative address specification [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 4-1. Operand Identifiers and Description Methods
Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbolNote Special-function register symbols (16-bit manipulatable register even addresses only)Note FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3
Note FFD0H to FFDFH are not addressable. Remark Refer to the users manual of each product for the symbols of special function registers.
32
4.1.2 Description of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( ): A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing in progress Memory contents indicated by address or register contents in parentheses Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data
addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 4.1.3 Description of flag operation column (Blank): Unchanged 0: 1: : R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
33
4.1.4 Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 4.1.5 Instructions listed by addressing type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
34
#byte
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
None
MOV XCH
MOV
MOV XCH
MOV
INC DEC
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV
DBNZ
DBNZ
INC DEC
PUSH POP
[DE] [HL]
MOV
MULU DIVUW
Note
Except r = A.
35
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX ADDW SUBW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW #word AX rpNote sfrp saddrp !addr16 SP None
Note
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand 1st Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1` SET1 CLR1 SET1 CLR1 SET1 CLR1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
36
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
AX
!addr16
!addr11
[addr5]
$addr16
CALL BR
CALLF
CALLT
BR BC BNC BZ BNZ
Compound Instructions
BT BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
37
Immediate data corresponding to bit 8-bit immediate data corresponding to byte 16-bit address lower 8-bit offset data corresponding to saddr sfr 16-bit address lower 8-bit offset data Signed twos complement data (8 bits) of relative address distance between the start and branch addresses of the next instruction 11 bits of immediate data corresponding to addr11 5 bits of immediate data corresponding to addr5
38
Mnemonic
Operands B1 1 0 1 0 0 R2 R1 R0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 1 0 0 R2 R1 R0 0 1 1 1 0 R2 R1 R0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 B2 Data
Operation Code B3 B4
Saddr-offset Sfr-offset
Data Data
Saddr-offset Saddr-offset Sfr-offset Sfr-offset Low addr Low addr High addr High addr Data
High addr
0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0
Note Except r = A.
39
Instruction Group
Mnemonic
Operands B1 rp,#word saddrp,#word sfrp,#word AX,saddrp saddrp,AX AX,sfrp sfrp,AX AX,rp rp,AX AX,!addr16 !addr16,AX
Note 1 Note 1
Operation Code B2 Low byte Saddr-offset Sfr-offset Saddr-offset Saddr-offset Sfr-offset Sfr-offset B3 High byte Low byte Low byte High byte High byte B4
0 0 0 1 0 P1 P0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 0 P1 P0 0 1 1 0 1 0 P1 P0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
Note 1
AX,rp A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
Note 2
0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1 1 0 1 0 1 0 0 0
Note 2
ADDC
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0
40
Mnemonic
Operands B1 B2 Data
Operation Code B3 B4
SUB
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
Note
0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0
Saddr-offset
Data
0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0
Note
SUBC
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 0
Note
AND
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
0 0 1 1 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0
Note Except r = A.
41
Mnemonic
Operands B1 B2 Data
Operation Code B3 B4
OR
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
Note
0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0
Saddr-offset
Data
0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0
Note
XOR
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
0 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0
Note
CMP
A,#byte saddr,#byte A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C]
0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0
Note Except r = A.
42
Mnemonic
Operands B1 B2
1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 1 0
0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 R2 R1 R0 1 0 0 0 0 0 0 1 0 1 0 1 0 R2 R1 R0 1 0 0 1 0 0 0 1 1 0 0 0 0 P1 P0 0 1 0 0 1 0 P1 P0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 Saddr-offset Saddr-offset
DEC
r saddr
INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD Adjust Bit Manipulation ADJBA ADJBS MOV1
CY,saddr.bit CY,sfr.bit CY,A.bit CY,PSW.bit CY,[HL].bit saddr.bit,CY sfr.bit,CY A.bit,CY PSW.bit,CY [HL].bit,CY
0 1 1 1 0 0 0 1 0 B2 B1 B0 0 1 0 0 0 1 1 1 0 0 0 1 0 B2 B1 B0 1 1 0 0 0 1 1 0 0 0 0 1 1 B2 B1 B0 1 1 0 0
Saddr-offset Sfr-offset
AND1
43
Mnemonic
Operands B1 B2
OR1
0 1 1 1 0 0 0 1 0 B2 B1 B0 0 1 1 0 0 1 1 1 0 0 0 1 0 B2 B1 B0 1 1 1 0 0 1 1 0 0 0 0 1 1 B2 B1 B0 1 1 1 0
XOR1
SET1
0 1 1 1 0 0 0 1 0 B2 B1 B0 1 0 1 0 0 1 1 0 0 0 0 1 1 B2 B1 B0 1 0 1 0 0 B2 B1 B0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 B2 B1 B0 0 0 1 0 0 B2 B1 B0 1 0 1 1 Saddr-offset
CLR1
Sfr-offset
SET1 CLR1 NOT1 Call Return CALL CALLF CALLT BRK RET RETB RETI Stack Manipulation POP PUSH
High addr
ta40
MOVW
44
Mnemonic
Operands B1 B2
BR
!addr16 $addr16 AX
1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 0
0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 jdisp jdisp jdisp jdisp Saddr-offset jdisp Sfr-offset jdisp jdisp jdisp Saddr-offset Sfr-offset jdisp jdisp jdisp jdisp jdisp
0 0 1 1 0 0 0 1 0 B2 B1 B0 0 1 1 0 0 0 1 1 0 0 0 1 0 B2 B1 B0 1 1 1 0 1 B2 B1 B0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 B2 B1 B0 0 1 1 0
BF
BTCLR
jdisp jdisp
jdisp
DBNZ
CPU control
RBn
0 1 1 0 0 0 0 1 1 1 RB1 1 RB0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0
45
CHAPTER 5
EXPLANATION OF INSTRUCTIONS
This chapter explains the instructions of 78K/0 Series products. Each instruction is described with a mnemonic, including description of multiple operands. The basic configuration of instruction description is shown on the next page. For the number of instruction bytes and the instruction codes, refer to the users manual of each product and CHAPTER 4 INSTRUCTION SET, respectively. All the instructions are common to 78K/0 Series products.
46
DESCRIPTION EXAMPLE
Mnemonic
MOV
MOV dst, src: Indicates the basic description format of the instruction. dst src: Indicates instruction operation using symbols. Indicates operands that can be specified by this instruction. Refer to 4.1 Operation for the description of each operand symbol.
Mnemonic
Operand(dst,src) r, #byte
Mnemonic
Operand(dst,src) A, PSW
MOV
MOV
~ A, saddr ~
saddr, A
~ ~ ~ ~
~ [HL], A ~
A, [HL+byte]
~ ~ ~ ~
~ PSW, #byte ~
[Flag]
~ [HL+C], A ~
Indicates the flag operation that changes by instruction execution. Each flag operation symbol is shown in the conventions.
Z AC CY
Conventions
Symbol Blank 0 1 X R Description Unchanged Cleared to 0 Set to 1 Set or cleared according to the result Previously saved value is restored
[Description]: Describes the instruction operation in detail. The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. [Description example] MOV A, #4DH; 4DH is transferred to the A register.
47
48
MOV
Operand(dst,src) r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte
Note Note
Mnemonic MOV
Operand(dst,src) A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL+byte] [HL+byte], A A, [HL+B] [HL+B], A A, [HL+C] [HL+C], A
Note Except r = A
[Description] The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. No interrupts are acknowledged between the MOV PSW, #byte instruction/MOV PSW, A instruction and the next instruction. [Description example] MOV A, #4DH; 4DH is transferred to the A register.
49
XCH
Operand(dst,src)
Note
Mnemonic XCH
[Flag]
Z AC CY
[Description] The 1st and 2nd operand contents are exchanged. [Description example] XCH A, FEBCH; The A register contents and address FEBCH contents are exchanged.
50
51
MOVW
Operand(dst,src) rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp
Mnemonic MOVW
[Flag]
Z AC CY
[Description] The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. [Description example] MOVW AX, HL; The HL register contents are transferred to the AX register. [Caution] Only an even address can be specified. An odd address cannot be specified.
52
XCHW
Operand(dst,src) AX, rp
Note
[Flag]
Z AC CY
[Description] The 1st and 2nd operand contents are exchanged. [Description example] XCHW AX, BC; The memory contents of the AX register are exchanged with those of the BC register.
53
54
ADD
Mnemonic ADD
Note Except r = A
[Flag]
Z AC CY
[Description] The destination operand (dst) specified by the 1st operand is added to the source operand (src) specified by the 2nd operand and the result is stored in the CY flag and the destination operand (dst). If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the addition generates a carry out of bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0). If the addition generates a carry for bit 4 out of bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0). [Description example] ADD CR10, #56H; 56H is added to the CR10 register and the result is stored in the CR10 register.
55
ADDC
Mnemonic ADDC
Note Except r = A
[Flag]
Z AC CY
[Description] The destination operand (dst) specified by the 1st operand, the source operand (src) specified by the 2nd operand and the CY flag are added and the result is stored in the destination operand (dst) and the CY flag. The CY flag is added to the least significant bit. This instruction is mainly used to add two or more bytes. If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the addition generates a carry out of bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0). If the addition generates a carry for bit 4 out of bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0). [Description example] ADDC A, [HL+B]; The A register contents and the contents at address (HL register + (B register)) and the CY flag are added and the result is stored in the A register.
56
SUB
Mnemonic SUB
Note Except r = A
[Flag]
Z AC CY
[Description] The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand and the result is stored in the destination operand (dst) and the CY flag. The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination operand (dst). If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the subtraction generates a borrow out of bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0). If the subtraction generates a borrow for bit 3 out of bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0). [Description example] SUB D, A; The A register is subtracted from the D register and the result is stored in the D register.
57
SUBC
Mnemonic SUBC
Note Except r = A
[Flag]
Z AC CY
[Description] The source operand (src) specified by the 2nd operand and the CY flag are subtracted from the destination operand (dst) specified by the 1st operand and the result is stored in the destination operand (dst). The CY flag is subtracted from the least significant bit. This instruction is mainly used for subtraction of two or more bytes. If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the subtraction generates a borrow out of bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0). If the subtraction generates a borrow for bit 3 out of bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0). [Description example] SUBC A, [HL]; The (HL register) address contents and the CY flag are subtracted from the A register and the result is stored in the A register.
58
AND
Mnemonic AND
Note Except r = A
[Flag]
Z AC CY
[Description] Bit-wise logical product is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst). If the logical product shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). [Description example] AND FEBAH, #11011100B; Bit-wise logical product of FEBAH contents and 11011100B is obtained and the result is stored at FEBAH.
59
OR
Mnemonic OR
Note Except r = A
[Flag]
Z AC CY
[Description] The bit-wise logical sum is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst). If the logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). [Description example] OR A, FE98H; The bit-wise logical sum of the A register and FE98H is obtained and the result is stored in the A register.
60
XOR
Mnemonic XOR
Note Except r = A
[Flag]
Z AC CY
[Description] The bit-wise exclusive logical sum is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst). Logical negation of all bits of the destination operand (dst) is possible by selecting #0FFH for the source operand (src) with this instruction. If the exclusive logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). [Description example] XOR A, L; The bit-wise exclusive logical sum of the A and L registers is obtained and the result is stored in the A register.
61
CMP
Mnemonic CMP
Note Except r = A
[Flag]
Z AC CY
[Description] The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand. The subtraction result is not stored anywhere and only the Z, AC and CY flags are changed. If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the subtraction generates a borrow out of bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0). If the subtraction generates a borrow for bit 3 out of bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0). [Description example] CMP FE38H, #38H; 38H is subtracted from the contents at address FE38H and only the flags are changed (comparison of contents at address FE38H and the immediate data).
62
63
ADDW
[Flag]
Z AC CY
[Description] The destination operand (dst) specified by the 1st operand is added to the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst). If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the addition generates a carry out of bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared (0). As a result of addition, the AC flag becomes undefined. [Description example] ADDW AX, #ABCDH; ABCDH is added to the AX register and the result is stored in the AX register.
64
SUBW
[Flag]
Z AC CY
[Description] The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand and the result is stored in the destination operand (dst) and the CY flag. The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination operand (dst). If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the subtraction generates a borrow out of bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared (0). As a result of subtraction, the AC flag becomes undefined. [Description example] SUBW AX, #ABCDH; ABCDH is subtracted from the AX register contents and the result is stored in the AX register.
65
CMPW
[Flag]
Z AC CY
[Description] The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand. The subtraction result is not stored anywhere and only the Z, AC and CY flags are changed. If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the subtraction generates a borrow out of bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared (0). As a result of subtraction, the AC flag becomes undefined. [Description example] CMPW AX, #ABCDH; ABCDH is subtracted from the AX register and only the flags are changed (comparison of the AX register and the immediate data).
66
67
MULU
Operand(src)
[Flag]
Z AC CY
[Description] The A register contents and the source operand (src) data are multiplied as unsigned data and the result is stored in the AX register. [Description example] MULU X; The A register contents and the X register contents are multiplied and the result is stored in the AX register.
68
DIVUW
Operand(dst)
[Flag]
Z AC CY
[Description] The AX register contents are divided by the destination operand (dst) contents and the quotient and the remainder are stored in the AX register and the destination operand (dst), respectively. Division is executed using the AX register and destination operand (dst) contents as unsigned data. However, when the destination operand (dst) is 0, the X register contents are stored in the C register and AX becomes 0FFFFH. [Description example] DIVUW C; The AX register contents are divided by the C register contents and the quotient and the remainder are stored in the AX register and the C register, respectively.
69
70
INC
Operand(dst)
saddr
[Flag]
Z AC CY
[Description] The destination operand (dst) contents are incremented by only one. If the increment result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the increment generates a carry for bit 4 out of bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0). Because this instruction is frequently used for increment of a counter for repeated operations and an indexed addressing offset register, the CY flag contents are not changed (to hold the CY flag contents in multiplebyte operation). [Description example] INC B; The B register is incremented.
71
DEC
Operand(dst)
saddr
[Flag]
Z AC CY
[Description] The destination operand (dst) contents are decremented by only one. If the decrement result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). If the decrement generates a carry for bit 3 out of bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0). Because this instruction is frequently used for decrement of a counter for repeated operations and an indexed addressing offset register, the CY flag contents are not changed (to hold the CY flag contents in multiplebyte operation). If dst is the B or C register or saddr, and it is not desired to change the AC and CY flag contents, the DBNZ instruction can be used. [Description example] DEC FE92H; The contents at address FE92H are decremented.
72
INCW
Operand(dst)
[Flag]
Z AC CY
[Description] The destination operand (dst) contents are incremented by only one. Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC and CY flag contents are not changed. [Description example] INCW HL; The HL register is incremented.
73
DECW
Operand (dst)
[Flag]
Z AC CY
[Description] The destination operand (dst) contents are decremented by only one. Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z, AC and CY flag contents are not changed. [Description example] DECW DE; The DE register is decremented.
74
75
ROR
ROR dst, cnt (CY, dst7 dst 0, dst m1 dstm) one time
Operand(dst,cnt)
[Flag]
Z AC CY
[Description] The destination operand (dst) contents specified by the 1st operand are rotated to the right just once. The LSB (bit 0) contents are simultaneously rotated to MSB (bit 7) and transferred to the CY flag.
CY
[Description example] ROR A, 1; The A register contents are rotated one bit to the right.
76
ROL
ROL dst, cnt (CY, dst0 dst 7, dstm+1 dstm) one time
Operand(dst,cnt)
[Flag]
Z AC CY
[Description] The destination operand (dst) contents specified by the 1st operand are rotated to the left just once. The MSB (bit 7) contents are simultaneously rotated to LSB (bit 0) and transferred to the CY flag.
CY
[Description example] ROL A, 1; The A register contents are rotated to the left by one bit.
77
RORC
Rotate Right with Carry Byte Data Rotation to the Right with Carry
RORC dst, cnt (CY dst 0, dst 7 CY, dstm1 dst m) one time
Operand(dst,cnt)
[Flag]
Z AC CY
[Description] The destination operand (dst) contents specified by the 1st operand are rotated just once to the right with carry.
CY 7 0
[Description example] RORC A, 1; The A register contents are rotated to the right by one bit including the CY flag.
78
ROLC
Rotate Left with Carry Byte Data Rotation to the Left with Carry
ROLC dst, cnt (CY dst 7, dst 0 CY, dstm+1 dstm ) one time
Operand(dst,cnt)
[Flag]
Z AC CY
[Description] The destination operand (dst) contents specified by the 1st operand are rotated just once to the left with carry.
CY 7 0
[Description example] ROLC A, 1; The A register contents are rotated to the left by one bit including the CY flag.
79
ROR4
ROR4 dst A3-0 (dst) 3-0, (dst)7-4 A 3-0, (dst)3-0 (dst) 7-4
Operand(dst) [HL]
Note
Note Specify an area other than the SFR area as operand [HL].
[Flag]
Z AC CY
[Description] The lower 4 bits of the A register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the right. The higher 4 bits of the A register remain unchanged.
7 A
4 3
0 dst
43
[Description example] ROR4 [HL]; Rightward digit rotation is executed with the memory contents specified by the A and HL registers.
After Execution
1010
0101
0011
1100
80
ROL4
Operand(dst) [HL]
Note
Note Specify an area other than the SFR area as operand [HL].
[Flag]
Z AC CY
[Description] The lower 4 bits of the A register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the left. The higher 4 bits of the A register remain unchanged.
7 A
4 3
0 dst
43
[Description example] ROL4 [HL]; Leftward digit rotation is executed with the memory contents specified by the A and HL registers.
A 7 Before Execution 4 0001 3 0010 0 7 (HL) 4 0100 3 1000 0
After Execution
0001
0100
1000
0010
81
82
ADJBA
CY
[Description] The A register, CY flag and AC flag are decimally adjusted from their contents. This instruction carries out an operation having meaning only when the BCD (binary coded decimal) data is added and the addition result is stored in the A register (in all other cases, the instruction carries out an operation having no meaning). See the table below for the adjustment method. If the adjustment result shows that the A register contents are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
Condition A3 to A0 9 AC = 0 A3 to A 0 10 AC = 0 AC = 1 A7 to A 4 9 and CY = 0 A7 to A4 10 or CY = 1 A7 to A4 < 9 and CY = 0 A7 to A 4 9 or CY = 1 A7 to A 4 9 and CY = 0 A7 to A4 10 or CY = 1 Operation A A, CY 0, AC 0 A A+01100000B, CY 1, AC 0 A A+00000110B, CY 0, AC 1 A A+01100110B, CY 1, AC 1 A A+00000110B, CY 0, AC 0 A A+01100110B, CY 1, AC 0
83
ADJBS
CY
[Description] The A register, CY flag and AC flag are decimally adjusted from their contents. This instruction carries out an operation having meaning only when the BCD (binary coded decimal) data is subtracted and the subtraction result is stored in the A register (in all other cases, the instruction carries out an operation having no meaning). See the table below for the adjustment method. If the adjustment result shows that the A register contents are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
Condition AC = 0 CY = 0 CY = 1 AC = 1 CY = 0 CY = 1 Operation A A, CY 0, AC 0 A A01100000B, CY 1, AC 0 A A00000110B, CY 0, AC 0 A A01100110B, CY 1, AC 0
84
85
MOV1
Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
Mnemonic MOV1
[Flag] dst = CY
Z AC CY
PSW.bit
Z AC CY
[Description] Bit data of the source operand (src) specified by the 2nd operand is transferred to the destination operand (dst) specified by the 1st operand. When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is changed. [Description example] MOV1 P3.4, CY; The CY flag contents are transferred to bit 4 of port 3.
86
AND1
Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
[Flag]
Z AC CY
[Description] Logical product of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst). The operation result is stored in the CY flag (because of the destination operand (dst)). [Description example] AND1 CY, FE7FH.3; Logical product of FE7FH bit 3 and the CY flag is obtained and the result is stored in the CY flag.
87
OR1
Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
[Flag]
Z AC CY
[Description] The logical sum of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst). The operation result is stored in the CY flag (because of the destination operand (dst)). [Description example] OR1 CY, P2.5; The logical sum of port 2 bit 5 and the CY flag is obtained and the result is stored in the CY flag.
88
XOR1
Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
[Flag]
Z AC CY
[Description] The exclusive logical sum of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst). The operation result is stored in the CY flag (because of the destination operand (dst)). [Description example] XOR1 CY, A.7; The exclusive logical sum of the A register bit 7 and the CY flag is obtained and the result is stored in the CY flag.
89
SET1
dst = CY
Z AC CY 1
[Description] The destination operand (dst) is set (1). When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is set (1). [Description example] SET1 FE55H.1; Bit 1 of FE55H is set (1).
90
CLR1
dst = CY
Z AC CY 0
[Description] The destination operand (dst) is cleared (0). When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is cleared (0). [Description example] CLR1 P3.7; Bit 7 of port 3 is cleared (0).
91
NOT1
Operand(dst)
[Flag]
Z AC CY
[Description] The CY flag is inverted. [Description example] NOT1 CY; The CY flag is inverted.
92
93
CALL
[Operand]
Mnemonic CALL Operand(target) !addr16
[Flag]
Z AC CY
[Description] This is a subroutine call with a 16-bit absolute address or a register indirect address. The start address (PC+3) of the next instruction is saved in the stack and is branched to the address specified by the target operand (target). [Description example] CALL !3059H; Subroutine call to 3059H
94
CALLF
[Operand]
Mnemonic CALLF Operand(target) !addr11
[Flag]
Z AC CY
[Description] This is a subroutine call which can only be branched to addresses 0800H to 0FFFH. The start address (PC+2) of the next instruction is saved in the stack and is branched in the range of addresses 0800H to 0FFFH. Only the lower 11 bits of an address are specified (with the higher 5 bits fixed to 00001B). The program size can be compressed by locating the subroutine at 0800H to 0FFFH and using this instruction. If the program is in the external memory, the execution time can be decreased.
95
CALLT
CALLT [addr5] (SP1) (PC+1)H, (SP2) (PC+1)L, SP PCH PCL SP2, (00000000, addr5+1) (00000000, addr5)
[Operand]
Mnemonic CALLT Operand([addr5]) [addr5]
[Flag]
Z AC CY
[Description] This is a subroutine call for call table reference. The start address (PC+1) of the next instruction is saved in the stack and is branched to the address indicated with the word data of a call table (the higher 8 bits of address are fixed to 00000000B and the next 5 bits are specified by addr5). [Description example] CALLT [40H]; Subroutine call to the word data addresses 0040H and 0041H.
96
BRK
BRK (SP1) PSW, (SP2) (PC+1)H, (SP3) (PC+1)L, IE SP PCH PCL 0, SP3, (3FH), (3EH)
[Description] This is a software interrupt instruction. PSW and the next instruction address (PC+1) are saved to the stack. After that, the IE flag is cleared (0) and the saved data is branched to the address indicated with the word data at the vector address (003EH). Because the IE flag is cleared (0), the subsequent maskable vectored interrupts are disabled. The RETB instruction is used to return from the software vectored interrupt generated with this instruction.
97
RET
[Description] This is a return instruction from the subroutine call made with the CALL, CALLF and CALLT instructions. The word data saved to the stack returns to the PC, and the program returns from the subroutine.
98
RETI
[Description] This is a return instruction from the vectored interrupt. The data saved to the stack returns to the PC and the PSW, and the program returns from the interrupt service routine. This instruction cannot be used for return from the software interrupt with the BRK instruction. None of interrupts are acknowledged between this instruction and the next instruction to be executed. The NMIS flag is set to 1 by acknowledgment of a non-maskable interrupt, and cleared to 0 by the RETI instruction. [Caution] When the return from non-maskable interrupt servicing is performed by an instruction other than the RETI instruction, the NMIS flag is not cleared to 0, and therefore no interrupts (including non-maskable interrupts) except software interrupts can be acknowledged.
99
RETB
[Description] This is a return instruction from the software interrupt generated with the BRK instruction. The data saved in the stack returns to the PC and the PSW, and the program returns from the interrupt service routine. None of interrupts are acknowledged between this instruction and the next instruction to be executed.
100
101
PUSH
Push Push
PUSH src When src = rp (SP1) srcH, (SP2) src L, SP SP2 When src = PSW (SP1) src SP SP1
[Operand]
Mnemonic PUSH PSW rp Operand(src)
[Flag]
Z AC CY
[Description] The data of the register specified by the source operand (src) is saved to the stack. [Description example] PUSH AX; AX register contents are saved to the stack.
102
POP
Pop Pop
POP dst When dst = rp dst L (SP), dstH (SP+1), SP SP+2 When dst = PSW dst (SP) SP SP+1
[Operand]
Mnemonic POP PSW rp Operand(dst)
PSW
Z R AC R CY R
[Description] Data is returned from the stack to the register specified by the destination operand (dst). When the operand is PSW, each flag is replaced with stack data. None of interrupts are acknowledged between the POP PSW instruction and the subsequent instruction. [Description example] POP AX; The stack data is returned to the AX register.
103
[Flag]
Z AC CY
[Description] This is an instruction to manipulate the stack pointer contents. The source operand (src) specified by the 2nd operand is stored in the destination operand (dst) specified by the 1st operand. [Description example] MOVW SP, #FE1FH; FE1FH is stored in the stack pointer.
104
105
BR
BR target PC target
[Flag]
Z AC CY
[Description] This is an instruction to branch unconditionally. The word data of the target address operand (target) is transferred to PC and branched. [Description example] BR AX; The AX register contents are branched as the address.
106
107
BC
BC $addr16 PC PC+2+jdisp8 if CY = 1
Operand($addr16) $addr16
[Flag]
Z AC CY
[Description] When CY = 1, data is branched to the address specified by the operand. When CY = 0, no processing is carried out and the subsequent instruction is executed. [Description example] BC $300H; When CY = 1, data is branched to 0300H (with the start of this instruction set in the range of addresses 027FH to 037EH).
108
BNC
Operand($addr16) $addr16
[Flag]
Z AC CY
[Description] When CY = 0, data is branched to the address specified by the operand. When CY = 1, no processing is carried out and the subsequent instruction is executed. [Description example] BNC $300H; When CY = 0, data is branched to 0300H (with the start of this instruction set in the range of addresses 027FH to 037EH).
109
BZ
BZ $addr16 PC PC+2+jdisp8 if Z = 1
Operand($addr16) $addr16
[Flag]
Z AC CY
[Description] When Z = 1, data is branched to the address specified by the operand. When Z = 0, no processing is carried out and the subsequent instruction is executed. [Description example] DEC B BZ $3C5H; When the B register is 0, data is branched to 03C5H (with the start of this instruction set in the range of addresses 0344H to 0443H).
110
BNZ
Operand($addr16) $addr16
[Flag]
Z AC CY
[Description] When Z = 0, data is branched to the address specified by the operand. When Z = 1, no processing is carried out and the subsequent instruction is executed. [Description example] CMP A, #55H BNZ $0A39H; If the A register is not 0055H, data is branched to 0A39H (with the start of this instruction set in the range of addresses 09B8H to 0AB7H).
111
BT
Operand(bit,$addr16) saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
b(Number of bytes) 3 4 3 3 3
[Flag]
Z AC CY
[Description] If the 1st operand (bit) contents have been set (1), data is branched to the address specified by the 2nd operand ($addr16). If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent instruction is executed. [Description example] BT FE47H.3, $55CH; When bit 3 at address FE47H is 1, data is branched to 055CH (with the start of this instruction set in the range of addresses 04DAH to 05D9H).
112
BF
Operand(bit,$addr16) saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
b(Number of bytes) 4 4 3 4 3
[Flag]
Z AC CY
[Description] If the 1st operand (bit) contents have been cleared (0), data is branched to the address specified by the 2nd operand ($addr16). If the 1st operand (bit) contents have not been cleared (0), no processing is carried out and the subsequent instruction is executed. [Description example] BF P2.2, $1549H; When bit 2 of port 2 is 0, data is branched to address 1549H (with the start of this instruction set in the range of addresses 14C6H to 15C5H).
113
BTCLR
Branch if True and Clear Conditional Branch and Clear by Bit Test (Byte Data Bit = 1)
Operand(bit,$addr16) saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
b(Number of bytes) 4 4 3 4 3
[Description] If the 1st operand (bit) contents have been set (1), they are cleared (0) and branched to the address specified by the 2nd operand. If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent instruction is executed. When the 1st operand (bit) is PSW.bit, the corresponding flag contents are cleared (0). [Description example] BTCLR PSW.0, $356H; When bit 0 (CY flag) of PSW is 1, the CY flag is cleared to 0 and branched to address 0356H (with the start of this instruction set in the range of addresses 02D4H to 03D3H).
114
DBNZ
[Operand]
Mnemonic DBNZ Operand(dst,$addr16) B, $addr16 C, $addr16 saddr, $addr16 b(Number of bytes) 2 2 3
[Flag]
Z AC CY
[Description] One is subtracted from the destination operand (dst) contents specified by the 1st operand and the subtraction result is stored in the destination operand (dst). If the subtraction result is not 0, data is branched to the address indicated with the 2nd operand ($addr16). When the subtraction result is 0, no processing is carried out and the subsequent instruction is executed. The flag remains unchanged. [Description example] DBNZ B, $1215H; The B register contents are decremented. If the result is not 0, data is branched to 1215H (with the start of this instruction set in the range of addresses 1194H to 1293H).
115
116
SEL RBn
Operand(RBn)
[Flag]
Z AC CY
[Description] The register bank specified by the operand (RBn) is made a register bank for use by the next and subsequent instructions. RBn ranges from RB0 to RB3. [Description example] SEL RB2; Register bank 2 is selected as the one for use by the next and subsequent instructions.
117
NOP
No Operation No Operation
NOP no operation
CY
118
EI
EI IE 1
CY
[Description] The maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (IE) to (1)). No interrupts are acknowledged between this instruction and the next instruction. If this instruction is executed, vectored interrupt acknowledgment from another source can be disabled. For details, refer to Interrupt Functions in the users manual of each product.
119
DI
DI IE 0
CY
[Description] Maskable interrupt acknowledgment by vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)). No interrupts are acknowledged between this instruction and the next instruction. For details of interrupt servicing, refer to Interrupt Functions in the users manual of each product.
120
HALT
CY
[Description] This instruction is used to set the HALT mode to stop the CPU operation clock. The total power consumption of the system can be decreased with intermittent operation by combining this mode with the normal operation mode.
121
STOP
CY
[Description] This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system. Power consumption can be minimized to only leakage current.
122
APPENDIX A
REVISION HISTORY
The following table shows the revision history of the previous editions. The Applied to: column indicates the chapters of each edition in which the revision was applied.
Edition 2nd Major Revision from Previous Edition Addition of the following versions: Applied to: Throughout
123
APPENDIX B
[8-bit data transfer instructions] MOV ... 49 XCH ... 50 [16-bit data transfer instructions] MOVW ... 52 XCHW ... 53
[Rotate instructions] ROR ... 76 ROL ... 77 RORC ... 78 ROLC ... 79 ROR4 ... 80 ROL4 ... 81 [BCD adjust instructions]
[8-bit operation instructions] ADJBA ... 83 ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ... 62 [16-bit operation instructions] ADDW ... 64 SUBW ... 65 CMPW ... 66 CALL ... 94 [Multiply/divide instructions] MULU ... 68 DIVUW ... 69 [Increment/decrement instructions] INC ... 71 DEC ... 72 INCW ... 73 DECW ... 74 PUSH ... 102 POP ... 103 MOVW SP, src ... 104 MOVW AX, SP ... 104 CALLF ... 95 CALLT ... 96 BRK ... 97 RET ... 98 RETI ... 99 RETB ... 100 [Stack manipulation instructions] [Call return instructions] MOV1 ... 86 AND1 ... 87 OR1 ... 88 XOR1 ... 89 SET1 ... 90 CLR1 ... 91 NOT1 ... 92 [Bit manipulation instructions] ADJBS ... 84
124
[Unconditional branch instruction] BR ... 106 [Conditional branch instructions] BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ...114 DBNZ ... 115 [CPU control instructions] SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ... 122
125
APPENDIX C
[A] ADD ... 55 ADDC ... 56 ADDW ... 64 ADJBA ... 83 ADJBS ... 84 AND ... 59 AND1 ... 87
[H] HALT ... 121 [I] INC ... 71 INCW ... 73 [M]
[B] MOV ... 49 BC ... 108 BF ... 113 BNC ... 109 BNZ ... 111 BR ... 106 BRK ... 97 BT ... 112 BTCLR ... 114 BZ ... 110 [C] [O] CALL ... 94 CALLF ... 95 CALLT ... 96 CLR1 ... 91 CMP ... 62 CMPW ... 66 POP ... 103 [D] DBNZ ... 115 DEC ... 72 DECW ... 74 DI ... 120 DIVUW ... 69 [E] EI ... 119 RET ... 98 RETB ... 100 RETI ... 99 ROL ... 77 ROLC ... 79 ROL4 ... 81 ROR ... 76 RORC ... 78 ROR4 ... 80 PUSH ... 102 [R] [P] OR ... 60 OR1 ... 88 NOP ... 118 NOT1 ... 92 [N] MOVW ... 52 MOVW AX, SP ... 104 MOVW SP, src ... 104 MOV1 ... 86 MULU ... 68
126
[S] SEL RBn ... 117 SET1 ... 90 STOP ... 122 SUB ... 57 SUBC ... 58 SUBW ... 65 [X] XCH ... 50 XCHW ... 53 XOR ... 61 XOR1 ... 89
127
[MEMO]
128
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