Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 23

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
THE PROBLEM A two-dimensional video image is transferred between processing modules by passing one pixel at a time qualied by horizontal and vertical blank pulses. Example
(shown for 4x4 image) X-> Y-> 0 4 8 12 1 5 9 13 2 6 10 14 3 7 11 15

HB

VB

Clk Pixel HB VB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 24

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
THE PROBLEM (CONTINUED) The task is to write a VHDL module that accepts the incoming video stream, stores it in a RAM, calculates a histogram from the input data, and locates the 50th percentile of the histogram. A functional block diagram and processing timeline are as follows: CPU Source Video Source Clock Source
Address, Data, Write Enable, Data Strobe

Project Module histogram

video HB VB

Input Decoder

control

Histogram Calc

control

Readout Control

data

clk clk2x A D WE CS A D WE CS

Video RAM
video frame video readin clear hist RAM calculate histogram

Histogram RAM
percentile readout hist readout video readin clear hist RAM

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 25

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
WHAT WE NEED TO DO.... Implement the following functions Input Decoder / Video RAM Controller Accepts video stream, horizontal and vertical blanks, and generates RAM address, data, write enable, and chip select (data strobe) signals to store the incoming video into a RAM At the beginning of the video stream, clears the histogram accumulation RAM After the video stream has been stored in the video RAM, generates RAM address, data, write enable, and chip select (data strobe) signals to read the video into a RAM Sequences out the histogram data, calculates the 50-percentile point, and presents the percentile point to output 50-percentile point is dened as the point (value) in the histogram at which 50% or more of the pixel intensities fall at or below it
DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED. Slide 26

Histogram Calculation / Histogram RAM controller -

Readout Controller / Percentile Determination -

February 12, 1998

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
ILLUSTRATION

255 VIDEO PIXEL DATA STREAM = 0 0 0 1 2 4 6 5 7 4 2 0 0 0

255 HISTOGRAM RAM BIN COUNTS

7 INTENSITY PIXEL COUNTS (Histogram Data) 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13

7 6 5 4 3 2 1 0 0 50-percentile 1 2 3 4 5 6 7 8 PIXEL INTENSITY (Histogram Address) 9 255

TIME (IN PIXEL INTERVALS)

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 27

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
INTERFACE SPECIFICATIONS

All external interfaces shall be std_logic or std_logic_vector The Module shall contain an external active-low reset (resetLowIn), and two external clocks, 10 MHz and 20MHz (clkIn and clk2xIn respectively) The Module shall contain a CPU programming interface consisting of: a 24-bit address bus (cpuAddrIn) a bidirectional 16-bit data bus (cpuDataBi) a 1-bit active-low Write Enable (cpuWriteEnLowIn) a 1-bit active-low Data Strobe (cpuDataStrobeLowIn) an 8-bit address bus (vidAddrOut) an 8-bit bidirectional data bus (vidDataBi) a 1-bit active-low Write Enable (vidWriteEnLowOut) a 1-bit active-low Chip Select (vidChipSelLowOut)

The Module shall contain a Video RAM interface consisting of: -

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 28

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
INTERFACE SPECIFICATIONS - CONTINUED

The Module shall contain a Histogram RAM interface consisting of: an 8-bit address bus (histAddrOut) an 8-bit bidirectional data bus (histDataBi) a 1-bit active-low Write Enable (histWriteEnLowOut) a 1-bit active-low Chip Select (histChipSelLowOut)

The Module shall contain an 8-bit data output (statDataOut) and a data valid gate (statDataValidOut) which shall be asserted during the output sequencing The Module shall accept 8-bit video data (pixelDataIn), an active-high horizontal blank (horizBlankIn), and an active-high vertical blank (vertBlankIn)

596B Students only:

The Module shall contain an active-low End-Of-Frame interrupt to the CPU (eofIntLowOut)

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 29

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
FUNCTIONAL SPECIFICATIONS : ALL STUDENTS

Input image size shall be a maximum of 16 x 16 pixels The Module shall contain a CPU programmable threshold value. Every incoming pixel whose value exceeds the threshold value shall be replaced by the threshold value in the histogram determination. The Histogram RAM shall be cleared at the beginning of each video frame, prior to accumulation of the histogram.

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 30

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
ADDITIONAL SPECIFICATIONS : 596 STUDENTS ONLY

The Module shall contain a CPU programmable Pause ag Module function shall be suspended during each video frame in which the Pause ag is set at the beginning of the frame Assertion of the Pause ag shall not interrupt processing of the current video frame The Video RAM and the Histogram shall be accessible for Read and Write to the CPU during any frame in which the Pause ag is set The Module shall supply an End-Of-Frame interrupt to the CPU The interrupt shall be asserted when the last statistics value has been read out and shall remain asserted until an Interrupt Acknowledge is received. An Interrupt Acknowledge shall consist of a Write of 0 to the Interrupt Acknowledge address, followed by a Write of 1 to the same address

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 31

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
SAMPLE TIMING

clkIn statDataOut statDataValidOut eofIntLowOut clkIn cpuAddrIn vidAddrOut histAddrOut cpuDataBi vidDataBi histDataBi cpuWriteEnLowIn vidWriteEnLowOut histWriteEnLowOut cpuDataStrobeLowIn vidChipSelLowOut histChipSelLowOut
V ALID V ALID bin 0 bin 1 bin 2 bin 255 50 %

V ALID

V ALID

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 32

Digital System Design with VHDL Final Project Notes

ProjectNotes_97.doc

FINAL PROJECT
CPU MEMORY MAP

ADDRESS 00,0000 - 7F,FFFFh 80,0000h 80,0001h 80,0002h 80,0003 - 9F,FFFFh A0,0000 - A0,00FFh A0,0100 - BF,FFFFh C0,0000 - C0,00FFh C0,0100 - FF,FFFFh

MEMORY FUNCTION

reserved for internal CPU use

VIDEO THRESHOLD REGISTER PAUSE FLAG END-OF-FRAME INTERRUPT ACKNOWLEDGE REGISTER

reserved
VIDEO RAM

reserved
HISTOGRAM RAM

reserved

February 12, 1998

DAVID M. CLARK REVISION 001 COPYRIGHT 1996 DAVID MICHAEL CLARK. ALL RIGHTS RESERVED.

Slide 33