REPORT: VHDL PRACTICE No 1.

Luis Enrique Pichardo Torres.

Ing. Mechatronics 3A

INTRODUCTION. In this report we are going to see some examples of building and representation of some logic gates in VHDL. This practice is going to improve our understanding and learning about how to design models of logic gates and simple or complex circuits in this language. The VHDL can describe the behavior and structure of electronic systems, but is particularly suited as a language to describe the structure and behavior of digital electronic hardware designs or conventional digital circuits. Each circuit was simulated in Sonata software and verified if it works and show the result as a signal in a screen. OBJETIVE. Students have to learn and understand the design of models for logic gates using VHDL. Using the simulation of each model of gate programmed to verify its functionality. THEORICAL SUPPORT. A digital system is described by its inputs and outputs and the relationship between them. In the case of VHDL on the one hand describe the appearance of the circuit: inputs and outputs, and secondly how to relate the inputs and the outputs. The appearance outside, how many input and output ports have is what I call entity. And the description of the behavior of the circuit architecture, any architecture must be associated with an entity. An entity is an abstraction of a circuit, either from a one complex system mail or a simple logic gate. The entity describes only the external form of circuit, it lists the inputs and outputs of the design. Always appears the definition of libraries and packages before the definition of the entity. For example, we have the next logic circuit:

The library.

The entity.

The circuits functionality must be specified with a VHDL construct called an architecture. All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral while another might be a structural description of the design. The architecture to the example above is the next: The architecture.

In VHDL, a bus is a special kind of signal that may have its drivers turned off. An attribute is data that are attached to VHDL objects or predefined data about VHDL objects. Examples are the current drive capability of a buffer or the maximum operating temperature of the device. A generic is VHDLs term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into the entity with generics. A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes. Now that we know some definitions we can start with the first buildings in VHDL language. This simple process should do a specific operation and the result is showing us as a signal in the software as we made in the practice. To conclude we have the final sentences for the example above.

Also we should to know some definitions to understand the process that we are going to analyze and see in the next levels. A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design. A package is a collection of commonly used data types and subprograms used in a design. Think of a package as a toolbox that contains tools used to build designs. This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers. The term bus usually brings to mind a group of signals or a particular method of communication used in the design of hardware.

An other concept is the test bench, A testbench is used to verify the functionality of a design. The testbench allows the design to verify the functionality of the design at each step in the HDL synthesis-based methodology.

The testbench provides the necessary input stimulus to the DUT and examines the output from the DUT. Just compile it and run in the simulation software and we can verify with a table of truth it is necessary if the circuit program works how we expected. DEVELOPMENT. According to each example we are going to use the same entity and test bench so is not necessary rewrite them. Just change the name of the code or logic gate that we are using. Part 1.

Test bench.
-----------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -----------------------------------------------Entity Comp_AND_tb is End Entity Comp_AND_tb; Architecture io of Comp_AND_tb is

--The component defines the interface with the. Component Comp_AND is Port ( a: in bit; b: in bit; c: out bit ); End Component Comp_AND; --Signal declaration signal x: bit; signal y: bit; signal z: bit; begin --Port map from the Comp_AND entity with the declared signals g1: Comp_AND port map( a=>x, b=>y, c=>z); --Time definition for the input signals --x y y x<= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns, '0' after 400 ns; y<= '0', '1' after 230 ns; End Architecture io;

The student will simulate the logic gates OR, AND and NOT, to write the code given and each gate. AND gate.
-----------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -----------------------------------------------Entity Comp_AND is Declaration form the input and output pins Port ( a: in bit; b: in bit; c: out bit ); End Entity Comp_AND; Architecture Excercise1 of Comp_AND is

Begin --Logic operation from the AND gate with a transport delay --of 20 ns to deliver the result c<=a and b after 20 ns; End Architecture Excercise1;

So we have the next signal an we can verify the result with a table of truth according to AND gate.

Part 2.

OR gate. As I told, we use the same entity and the same test bench to do this simulation, only changes the ANDs for ORs. Also we can compare the table of truth with the output signal in the next picture.

The student will design the models of the NOR gates, NAND, and XOR to write a VHDL program for each gate. There will be a program modeled for each gate. NOR gate. I realized the same process, change the variable for one NOR and simulate the operation. And we have the next image with its respective table of truth.

NOT gate. In this part of the practice, we must to make a little change with the entity and the test bench. I omit one of the inputs because the NOT gate works with one input and deliver one output so I cancelled the input a. The next image represent the function NOT after do it in VHDL language, the table of truth says us that the signal of output is correct. NAND gate. The simulation shows us the correctly work of the program respect with the table of truth behind.

variables no represent connections or memory states. What is an Entity? XOR gate. Finally we have the XOR gate, as all circuits only we have to change the name of the variable or gate in the example of test bench and the entity in the begin of the development part. We have the next result in the simulation. An entity is an abstraction of a circuit, either from a complex system mail or a simple logic gate. The entity describes only the external form of circuit; it lists the inputs and outputs of the design.

What is Architecture? An architecture describes the operation of the entity to which it refers, within the architecture will have to describe the operation of the entity that is associated using statements and expressions of VHDL. Are used to represent a complete description of a design.

Explain the Behavior of a component in the test bench. Knowledge questions What is a signal on VHDL? The signals represent memory elements or connections and if they can be synthesized, put another way, every object of our VHDL code be declared as signal corresponds to a cable or a memory element in our circuit. The component represents the relation between the entity and the program, so its behavior is like an interface in VHDL language.

Which is the purpose of the test bench? The purpose of the test bench is contains procedures to create instructions, read, parse and execute the stimulus file. The test bench provides the necessary input stimulus to the DUT and examines the output from the DUT

What is a variable on VHDL? CONCLUSION. The variable contains a single value that can be changed during the simulation with an assignment statement. The variable generally used as indices, mainly in loop instructions, or to take values that will shape components. The To conclude the VHDL allows us to model digital systems. Besides allows the description of digital electronic systems at any level of abstraction, also the probability of error is greatly reduced as well as the design time. I understood and learned how

to do and simulate simple circuits and I can verify them with the mathematic method or tables of truth, combining all tools that I learn in class. BIBLIOGRAPHY. Brown, Stephen and Vranesic, Zvonko (2009) Fundamentals of Digital Logic with VHDL Design 3rd Edition. McGraw-Hill, U.S.A. Perry, Douglas (2002) VHDL: Programming by Example 4th Edition. McGraw-Hill, U.S.A. IEEE (2002) IEEE Standard VHDL Language Reference Manual U.S.A.