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VLSI DESIGN 4
Course code GU Credits ECTS Credits Prerequisite courses 6DHX 20 10 Electronic Systems Design 3 (3YHW) (Electronic Circuit Design 3 (3YGW) and Silicon Devices and Technology 3 (4DJW) are recommended, and are required if advancing to VLSI Design 5) Dr E Wasige (telephone 8662, email E.Wasige) Prof D Cumming (telephone 5233, email: D.Cumming) 20 1 Description of course 1. VLSI Design 35 lectures and 4 tutorials Aims To introduce both digital and analogue VLSI design, from the physical level through to the systems level. Objectives Knowledge and Understanding Categorise different CMOS design styles and critically evaluate their respective merits. Prcis the effect of scaling rules on CMOS system operation and classify the models used to describe the operation of CMOS gates in analogue and digital design. Explain the operation of common analogue and digital microelectronic subsystems, from basic inverters and switches to multiplier units, op-amps and data converters. Identify the requirements needed to obtain accurate models of analogue systems, and explain why such models are important. Chip assembly. Evaluate the benefits of using a hardware description language in digital design and explain the syntax, structure and usage of VHDL. Register transfer level design. Summarise the issues involved in functional and timing verification of VLSI systems and explain the various low level checks applied to a design before final fabrication. Design techniques for high frequency analogue integrated circuits. Modelling and simulation used in real design Design of a wide range of analogue-to-digital converters. Typical implementations in switched-capacitor CMOS, and bipolar technologies. Limitations and error correction techniques. Skills Determine an appropriate choice of target architecture, design flow and CAD tools for a given system design problem. Design a range of microelectronic subsystems, or make an Department of Electronics and Electrical Engineering

Teaching staff (the first has overall responsibility) Approximate size of class Semester

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appropriate choice of subsystem from available design libraries. Translate a high level system design description into synthesisable VHDL code. Extract scalable device models from experimental characteristics and employ them in the design of analogue systems. Syllabus Silicon technology: Fabrication, operation and advantages of CMOS technology. CMOS scaling rules, Moores Law. Cross section and layout of CMOS inverter. Component design libraries, leaf cells and phantoms. CMOS layout design rules and design rules check (DRC) methods. Device simulation at switch and gate levels. SPICE models 1,2,3, BSIM3. DRAM Technology. Digital microelectronic circuits and subsystems: Design styles for CMOS circuits. And-Or-Invert (AOI) logic, pass gate logic, dynamic logic. Comparison of static and dynamic logic styles. Latches and memory. Architectures of more complex logic functions. Bit slicing and pipelining. Adder circuits (including mirror and Manchester carry). Shift registers. Radix-2 array multipliers. Analogue microelectronic circuits and subsystems: Simple CMOS analogue building blocks current mirror, inverting amplifier, source follower, cascoding techniques, differential pair and gain stages. Basic Op-Amp design two stage CMOS op-amp, feedback, stability and compensation. Analogue layout considerations matching issues, transistor layout, capacitor and resistor matching. Analogue-to-digital conversion: Integrating converters, successive-approximation converters, algorithmic converter, flash converter, two-step converter, interpolating converter, folding converter (with and without interpolation), pipelined converter, time-interleaved converter. Oversampling converters quantisation noise, oversampling. Noise-shaped delta-sigma converter first order, second order, high order. Decimation filters. Various architectures. Bandpass converters. Practical considerations - stability, idle tones, dithering. Multi-bit converters. Digital-to-analogue conversion: Resistor string converters; binary-scaled converters, R-2R, charge-redistribution; thermometer-code converters; hybrid converters. High Level Design: Hardware description languages. Language standards. VHSIC hardware description language (VHDL). Levels of description behavioural, structural, register transfer level (RTL). Simulation tools. Testbench creation and functional simulation/verification. Delay models. Timing verification. Static timing analysis. Optimisation of synthesis process based on timing constraints. Implementation: Target architectures ASIC, FPGA, SOG. Overview of design flow / design methodologies. Layout and floorplanning. I/O placement, Pad-rings, power and ground placement. Place and route. Clock placement and routing. Department of Electronics and Electrical Engineering

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2. Laboratory Mixed signal design exercise Aims To provide; Experience in the use of design automation and modelling tools, and design methodologies. The opportunity to perform practical design of both analogue and digital systems. Objectives Knowledge and Understanding Break down a VSLI design problem into constituent tasks, identifying appropriate CAD tools to facilitate each task. Develop synthesisable VHDL code to solve a design problem, and to verify the solution. Skills Use a range of modern CAD tools to design and test analogue and digital systems. Syllabus Practical introduction to computer aided design (CAD) tools. Design, simulation and layout of an analog subsystem. Recommended books Authors M J S Smith N H E Weste & K Eshraghian W Wolf A S Sedra & K C Smith D A Johns & K W Martin D T Comer Title, edition Application Specific Integrated Circuits Principles of CMOS VLSI Design Modern VLSI Design Microelectronic Circuits 5th Ed Publisher Addison Wesley Addison Wesley Prentice Hall Oxford Univ. Press John Wiley and Sons Array Year ISBN Cost 1995 0201500221 29 1993 1994 2004 019542527 38 0201533766 40 Code B C C C

Analog Integrated 1996 0471144487 40 B Circuit Design Introduction to 1994 0963804901 C Mixed Signal VLSI Codes : A = compulsory; B = strongly recommended; C = recommended; D = wider reading Study times Type Lectures and tutorials Laboratories and laboratory reports Tutorial sheets Review and consolidation of course material Final revision and examination Hours 39 30 20 70 30

Department of Electronics and Electrical Engineering

Course information These times are a rough estimate of the work required by a typical student. There will be variations between individuals, but you will run the risk of failure if you spend significantly less time on this course than these guidelines suggest. Assessment % 10 90 Type Laboratory Degree Examination Details Report on an analog design assignment 2 hour paper

The degree examinations are held in weeks 13 to 14; no resit is available.

Department of Electronics and Electrical Engineering