Code No: 07A4EC02

R07

Set No. 2

II B.TECH IIII B.Tech II Semester Regular Examinations,May 2010 - 2010 SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY
LINEAR AND DIGITAL IC APPLICATIONS Common to Instrumentation And Control Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Classify the lters and explain the characteristics of each one of them. (b) Draw the rst order low-pass Butterworth lter and analyze the same by deriving the gain and phase angle equation. [8+8] 2. (a) What is the phase-Locked loop? Briey explain the roles of Low-pass lter and VCO in PLL. (b) Explain an application in which the 555 timer can be used as Astable multivibrator. [8+8] 3. (a) Write short notes on dierent types of ROM. (b) Write short notes on Clocked D ip op.

4. (a) Give the design procedure of a compensating network for an Op-amp which uses 10V supply voltages. Assume necessary data. (b) In the circuit of gure 4, R1 =100 , RF = 4.7K , CMRR=90 db. If the amplitude of the induced 60-Hz noise at the output is 5mV (rms). Calculate the amplitude of the common-mode input voltage Vcm . RL = 1K [8+8]

w w

jn .

w tu

r o

.c ld

m o

[8+8]

Figure 4 5. (a) Explain the operation of a counter type of Analog to Digital converter. (b) Specify the modications necessary in the circuit for a time varying analog input voltage. (c) Calculate the conversion time for a full scale input incase of a 12-bit counter type Analog to Digital converter driven by 2MHz clock. [8+4+4] 6. (a) Draw the circuit of two input NAND gate with totem-pole output and do the static analysis when output is HIGH & Output is low. 1

Code No: 07A4EC02

R07

Set No. 2

(b) Explain why two totem pole outputs cant be tied together. (c) With neat circuit explain the concept of open collector O/P with pull-up. resistor. [6+6+4] 7. (a) What is Gyrator circuit? Explain its operation with a neat circuit diagram. (b) What is a sample and hold circuit? Why is it needed? With neat circuit diagram, describe the operation of an Op-amp based sample and hold circuit. [6+10] 8. (a) Using two 74138 decoders design a 4 to 16 decoder? (b) Design a CMOS transistor circuit that has the functional behavior F (Z) = (A + B)(B + C). [8+8]

w w

jn .

w tu

r o

.c ld

m o

Code No: 07A4EC02

R07

Set No. 4

II B.TECH IIII B.Tech II Semester Regular Examinations,May 2010 - 2010 SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY LINEAR AND DIGITAL IC APPLICATIONS Common to Instrumentation And Control Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Dene input oset voltage and CMRR as applied to Op-amp ICs. (b) Explain how the above parameters can be measured?

2. (a) What is a voltage follower? What are its features and applications? (b) What do you mean by sampling? (c) Explain basic circuit for sample and hold circuit.

3. (a) Explain sinking current and sourcing current of TTL output? Which of the above parameters decide the fan out and how? (b) Distinguish between static and dynamic power dissipation of a CMOS circuit? Derive the expression for dynamic power dissipation? [8+8] 4. (a) Describe how frequency division and multiplication can be achieved using a Phase Locked Loop. (b) Draw the circuit of a PLL AM detector and explain its operation.

5. (a) Explain with the help of neat diagram the simple structure of MOS ROM. (b) Design MOD 5 synchronous counter. 6. (a) Draw the logic diagram of 74283 IC and explain the operation? (b) Write short notes on BCD to binary converter? [8+8] [8+8]

7. (a) Explain the operation of a multiplying DAC and mention its applications. (b) A 12-bit D to A converter has a full-scale range of 15 volts. Its maximum dierential linearity error is 1/2 LSB. i. What is the percentage resolution? ii. What are the minimum and maximum possible values of the increment in its output voltage? [8+8] 8. (a) Explain the term Frequency Scaling with suitable example. (b) Design a I order wide band-pass lter with fL =200 Hz. fH =1 KHz and a passband gain=4. Draw the frequency response and calculate ?Q? factor for the 'Q' lter. (Assume necessary data) [6+10]

w w

jn .

w tu

rl o

.c d

m o

[8+8]

[8+3+5]

[12+4]

Code No: 07A4EC02

R07

Set No. 1

II B.TECH IIII B.Tech II Semester Regular Examinations,May 2010 - 2010 SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY LINEAR AND DIGITAL IC APPLICATIONS Common to Instrumentation And Control Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Write short notes on the operation of any two: (a) Quadrature oscillator. (b) Voltage controlled oscillator. (c) Wien - bridge oscillator.

2. (a) List out various types of D/A converter and A/D converters and compare their merits and demerits. (b) Give the schematic circuit of successive approximations A/D converter and explain its operations. [8+8] 3. (a) Give the block diagram of PLL and explain about each block in detail. (b) Dene the following terms with reference to PLL. i. Lock range. ii. Capture range. iii. Pull-in-time.

4. (a) Compare dierent logic families and mention their advantages and disadvantages? (b) Which is the fastest non-saturated logic gate? Draw the circuit and explain its functions. [8+8] 5. (a) What is cross over distortions and how it is eliminated in dierential amplier? (b) Explain dierent methods of external frequency compensation in an Op-amp. (c) Design an amplier with a gain of +5 using one Op-amp ( make necessary assumptions). [4+6+6] 6. (a) Design a 3 input 5output multiplexer? Write the truth table and draw the logic 5-bit diagram. (b) Write short notes on full subtractor. 7. (a) Design a 4-bit binary synchronous counter using 7474? (b) Draw the circuit and explain the crystal controlled clock generators. [8+8] [8+8]

w w

jn .

w tu

r o

.c ld

m o

[5+5+6] [16]

[10+6]

8. (a) Explain with a neat circuit diagram the working of voltage to current converter with oating load and grounded. 4

Code No: 07A4EC02

R07

Set No. 1

(b) Design a circuit to convert a 4 mA to 20mA input current to 0V to 10V output voltage. The circuit is powered from 15V regulated supplies. (Assume necessary data) [10+6]

w w

jn .

w tu

r o

.c ld

m o

Code No: 07A4EC02

R07

Set No. 3

II B.TECH IIII B.Tech II Semester Regular Examinations,May 2010 - 2010 SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY
LINEAR AND DIGITAL IC APPLICATIONS Common to Instrumentation And Control Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What is the name of the circuit that is used to detect the peak value of the non sinusoidal input waveforms. Draw its circuit and explain its operation. (b) Draw any one multivibrator circuit using Op-amp and explain its operation and derive relevant expression for its time period. [6+10] 2. (a) Broadly classify the integrated circuits for a wide range of applications. (b) What is a practical Op-amp? Draw its equivalent circuit.

(c) In an Op-amp, V2 = 0 (inverting terminal input). What is the voltage at V1 (non-inverting terminal input) for an output of 5V if AOL = 50000. [6+6+4] 3. Write short notes on:

(a) Dual-slope A/D converter.

(b) Charge balancing type Analog to Digital converter. 4. (a) Give the logic diagram of 74147 and explain its truth table? (b) Write short notes on half subtractor? 5. (a) Draw the logic diagram of binary counter and explain its operation?

(b) Draw the internal structure of synchronous SRAM and explain the operation? [8+8] 6. (a) Draw the circuit of a Totem-pole TTL NAND gate ? What is the purpose of using a diode at the output stage? Explain its operation and verify the truth table. (b) When do we use open-collector TTL gate? (c) Which is the fastest logic gate and why? 7. (a) Write short notes on : i. Balanced Modulator. ii. Voltage Controlled Oscillator. iii. Digital Phase Detector. (b) Give any one applications of PLL and explain it in detail. [4+4+4+4] [8+4+4]

w w

jn .

w tu

r o

.c ld

m o

[8+8]

[8+8]

8. (a) Design a II order Butterworth Low-pass lter for a cut o frequency of 1KHz and for a given normalized polynomial of S 2 +1.414S+1. Assume necessary data. 6

Code No: 07A4EC02

R07

Set No. 3

(b) In the above circuit given (gure 8(b)ii) if the integrator components are R1 =120 K and C1 = 0.01F,R3 = 6.8 K R2 = 1.2K, determine i. Peak-to-peak triangular output amplitude. ii. The frequency of triangular wave. [8+8]

Figure 8(b)ii

w w

jn .

w tu

r o

.c ld

m o