The Rambus Memory System
James A. Gasbarro
Rambus Inc.
Abstract
This paper describes a revolutionary new technology
for building high-performance DRAM memory systems
that operate up to I O times faster than conventional sys-
tems. With only a 9-bit wide interface, devices are capable
oftransferring data at over 500 MBytes per second. This
technology is implemented using standard CMOS process,
package, and printed circuit fabrication techniques and is
suitable for cost sensitive volume applications.
1.0 Introduction
During the last two decades, DRAM technology has
changed dramatically. While device densities have
increased by nearly six orders of magnitude, DRAM
access times have only improved by EO factor of 10. Over
the same period microprocessor performance has jumped
by a factor of 100. This has created a significant perfor-
mance gap between computing elements and their associ-
ated memory devices. This gap has been traditionally
filled by relatively expensive application specific memo-
ries, such as SRAM caches for processors, or multiport
VRAMs for graphics subsystems. Rambus Inc. has devel-
oped a new high-bandwidth DRAM interface that can sup
ply the data rates needed for advanced multimedia and
graphics computing applications with substantialcost sav-
ings.
BusData[B:Ol
I I I I I I
BusCtrl, BusEnable
ClkFromMaster
ClkToMaster I I I I I I I I I
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Figure 1: Master and Slaves Connect to Terminated Transmission
0-8186-7102-5/95 $04.00 0 1995 IEEE
2.0 The Rambus Channel
The RambusTMChannel is a high-speed memory inter-
face that operates up to 10 times faster than conventional
DRAM interfaces. The Channel uses a small number of
very high speed signals to carry all address, data, and con-
trol information, greatly reducing the pin count and hence
cost, while maintaining high performance levels. The
Channel is a byte wide bus that operates at over 500
MBytes/sec. Multiple Channels can be operated in parallel
to achieve even higher throughput.
A Rambus Channel contains 13 controlled impedance,
matched transmission lines: 9 data, 2 clock, and 2 control.
As shown in the Figure 1, the Channel has a bus topology
with the master device (microprocessor or ASIC control-
ler) at one end, terminators at the other end, and slaves
@DRAMsm) in between.
Several key features of the system can be noted from
the figure. The &st important feature is the master, which
is located at one end of the bus. In the Rambus protocol,
direct data transfers occur only between master and slave
devices, not between slaves. This allows signals to be ter-
minated at only one end of the Channel, resulting in con-
siderable savings in U 0 power dissipation. In operation,
data driven by the master propagates past all slaves, allow-
ing all slaves to correctly sense the data. The matched ter-
minator prevents any reflections. Data driven by a slave
initially propagates in both directions along the bus at half
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I I I I
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the voltage swing. The wavefront travelling toward the
terminator stops when it reaches the terminating resis-
tance. The signal travelling toward the master, on the other
hand, encounters an open circuit. This causes the wave-
front to double in amplitude, supplying full logic level
inputs to the master.
Output drivers on the Channel are current source driv-
ers, rather than the more common voltage source drivers.
Current source drivers present a high impedance to the
waveform reflecting from the master end of the bus. This
prevents secondary reflections from occurring due to the
active slave driver. Thus, the worst case bus settling time
is 2 Tf(Tf is the time-of-flight on the bus) when the slave
nearest the terminator is transmitting. The worst case data
delivery time however, between any master-slave pair is
only 1 Te
A second feature of the Channel topology is the clock
distribution scheme. The clock routing begins at the slave
end of the Channel and propagates to the master end as
ClkToMaster, where it loops back as ClkFromMaster to
the slave end and terminates. This clock topology allows
clock and data to always travel in the same direction to
minimize skew. A slave always sends data to the master
synchronously with ClkToMaster, and the master always
sends data to the slaves synchronously with ClkFromMas-
ter. Because the transmission lines are matched, the clock
and data signals remain synchronized as they travel to
their destination.
In a Rambus Channel, both edges of the clock are used
for data transfer. Thus 500 MByte/sec operation is attained
with only a 250 MHz clock source. This limits the maxi-
mum toggle rate for any signal, data or clock to 250 MHz.
All high-speed signals on the Channel operate with volt-
age swings of about 800 mV, and are driven with con-
trolled rise-time drivers. These features combine to
minimize electromagnetic interference problems.
3.0 Packaging
The slave packaging is crucial to maintaining a uniform
transmission line environment for the Channel. Since there
can be many RDRAMs in a system, the stub introduced by
the leads of the device must be kept as small as possible.
RDRAMs are designed such that the internal bonding pads
of the die are pitch matched to the Channel traces on the
printed circuit board (PCB). This allows the leadframe to
have a uniform length of about 2 mm, which in turn
enables pin parasitics of less than 2 pf and 3 nH.
95
PCBs carrying Rambus Channel signals are designed
using standard FR-4construcition techniques. The micro-
strip transmission lines are targeted for 50 ohm nominal
impedance. Due to the capacitive loading effect of the
RDRAMs, the loaded impedance can be as small as 20
ohms.
The Rambus Interface is a special logic block contained
in any device that connects to the Channel. The interface is
implemented in the same standard CMOS processes that
are in common use for today's ASICs and DRAMS. Con-
tained in the interface are two delay-locked loops for
deskewing transmit and receive clocks, as well as level
converters and shift register logic to convert the external
low-swing, byte-wide 500 Mllz bus to an internal8-byte-
wide CMOS bus that operates at 62.5 MHz. In an ASIC,
the interface appears as a diffused cell in the pad ring. The
ASIC designer only has to deid with the lower speed bus,
and does not need to know the details of the low-speed to
high-speed transformation.
In the RDRAM, the interface is located along one edge
of the die and replaces the existing DRAM U 0 structures.
The DRAM core is of conventional design, with an inter-
nal CAS cycle time of 16 ns. [n addition to the bus trans-
formation function, the RDRAM interface also contains
the registers and logic necessary to implement the bus pro-
tocol.
4.0 Transactions
Channel transactions are initiated with a Request
Packet by the Master, as shown in Figure 2. The Request
Packet contains the address of the R D M M and memory
location to be accessed, as well as byte-count and opcode
fields. For a write request, the write data immediately fol-
lows the request. For reads, the access time from request
to the first data word is 28 ns. Up to 256 bytes of data can
be streamed in a single transaction.
Read Ra Read Data
Write Rq Write Dada
Figure 2: Channlel Transactions
 Each RDRAM is broken down into two independent
banks of memory. Each of these banks has a 2 KByte
cache line associated with it that is built out of large sense
amplifier arrays. These caches work by holding the last
accessed row of their associated bank in the sense amplifi-
ers allowing further accesses to the same row of memory
to result in cache hits. With the row already stored in the
cache, data can be accessed with very low latency. Each
RDRAM added to a system adds two cache lines to the
memory system helping to increase cache hit rates.
A cache miss results when a row is accessed that is not
currently stored in one of the cache lines When this hap-
pens, the requesting master is sent a Negative Acknowl-
edge packet indicating the requested row is not yet
available. The RDRAM then loads the requested row into
the cache line and waits for the master to submit a retry of
the previous request.
Address mapping hardware is provided to increase
cache hit rates by allowing system designers to easily per-
form n-way RDRAM interleaving. In a non-interleaved
memory system, contiguous blocks of addresses follow
each other in sequence in one D R A M which is then fol-
lowed by the next RDRAM. By using address mapping,
contiguous blocks of addresses are split across several
RDRAMs, and therefore across several cache lines. In a
typical system containing, for example, eight RDRAMs,
m i s s rates could be expected to be as low as 5%.
5.0 Concurrency
Read and write transactions to RDFtAMs are not lim-
ited to simple sequential operations. Non-contiguous
blocks of memory can be accessed through the use of the
read and write non-sequential operations. With these com-
mands, multiple eight-byte blocks of data within a DRAM
cache line can be accessed in a non-sequential fashion.
The address for the next data block is transmitted as a
serial address packet on one of the control signals. Succes-
sive serial address packets continue to specify new
addresses within the cache while data is continuously
transferred until the access is complete. Non-sequential
accesses are useful in applications such as graphics,where
data is often accessed in a localized but non-linear fashion,
or in main memory applications when performing func-
tions such as write gathering.
Concurrent transactions can be used to optimize
RDRAM utilization in high performance applications by
taking advantage of available Channel bandwidth during
cache miss latency periods. When a m i s s in one RDRAM
takes place, that device will be busy loading a new row
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into one of its cache lines. Other than that, the Channel
and all other RDRAMs will still be available for use.
Instead of waiting for the first D R A M to finish loading
its cache, a transaction to another RDRAM can be initi-
ated.
This can be used in various ways. In system where
memory accesses can be queued, a transaction can take
place for any pending access residing in a different
D R A M . When that transaction is complete, the first
transaction can be retried.
&touching can be used in systems where memory
accesses are predictable, such as video applications. This
is done when an application is finished with a particular
RDRAM and about to access a different one. If the next
access to the original RDRAM is known in advance, a
dummy transaction can be first generated to cause a row
m i s s and prepare it for its next access. Transactions to
other devices can then take place while a cache fill is tak-
ing place. When the original device is next accessed, the
required row of data will already be loaded in the cache
line and a cache hit will occur.
6.0 System level
At the system level, the Rambus architecture has a
number of important advantages over conventional mem-
ory system approaches. In the graphics arena, for example,
only one 16Mb DRAM is needed for building a high reso-
lution frame buffer. Commodity DRAMScannot supply
the bandwidth needed with only one device. A single
RDRAM though, can supply all the bandwidth needed for
display refresh and still have a large fraction of the total
available for display update. In main memory applica-
tions, memory granularity is a big issue due to system
cost. Conventional memory systems use multiple devices
in parallel to meet the bandwidth needs of the processor.
This implies that incremental memory cost is two to four
times more than what can be had using RDRAIvfs, which
can be added in units of a single DRAM. With 8 MByte
chips just a few years away, this will soon become a criti-
cal issue.
7.0 Conclusion
The new technology introduced by the Rambus Chan-
nel and the RDRAM represent a substantial leap forward
in processor to memory interconnect. This technology will
enable a host of new applications where high bandwidth
and low cost are the driving factors.
Rambus and RDRAM are trademarks of Rambus Inc.