Proceedings of the 30th European Solid-State Circuits Conference

September 20 - September 24, 2004, Leuven, Belgium, pp. 83-86

60 GHz Transceiver Circuits in SiGe:C

BiCMOS Technology
Wolfgang Winkler, Johannes Borngräber, Hans Gustat, Falk Korndörfer

IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany

Phone: +49-(0)-335-5625-150 E-mail: wwinkler@ihp-microelectronics.com

Abstract analog part of the system without having to deal with

complexity, throughput and power consumption of
This paper presents the design and measurement of key high-data rate digital processing.
circuit building blocks for a high-data-rate transceiver in - The bandwidth available in the 61 GHz ISM band is
the 60 GHz band. The adopted modulation scheme is 500 MHz. Thus, bandwidth efficiency is less important
ASK for simple configuration with high data rate. The compared to lower frequency bands.
circuits presented are: LNA, oscillator, mixer, modulator - In a bandwidth-efficient modulation scheme like
and demodulator. The circuits are fabricated in a OFDM, the A/D converter (ADC) is a major problem.
0.25 µm SiGe:C BiCMOS technology. With the required low power consumption and
throughput in mind, it is difficult to design an ADC
that would suit the system needs.
1. Introduction In summary, ASK seems well suited for a first-
generation 60 GHz transceiver, due to simplicity and
power efficiency. Later implementations will certainly
Traditionally, multimedia content is transferred with
make use of more sophisticated modulation schemes.
wired transmission systems. Because of the limited data
The transmit path of the transceiver consists of a
rates, conventional WLAN systems cannot take over this
61.25 GHz fundamental mode oscillator, a switch and a
task. That’s why new wireless transmission systems with
power amplifier. Between the modulator and the power
data rates > 150 Mb/s are under investigation [1]. In [2] a
amplifier a filter is inserted to reduce spurs. The receiver
wireless transceiver module at 60 GHz is presented
path consists of a low noise amplifier (LNA), a mixer, a
showing a data-rate as high as 1.25 Gb/s. The chip set
56 GHz oscillator, a variable gain amplifier and an ASK
consists of different MMICs based on 0.15 µm
demodulator. The circuit blocks in dashed boxes in
AlGaAs/InGaAs heterojunction FET technology.
Figure 1 are described in this paper.
For future low-cost systems it is required to realize the
.
full transceiver in a silicon-based technology on a single
chip or at least with a low chip-count. With the modern
CMOS, bipolar and BiCMOS technologies developed in
the last few years it seems certain to make true this goal
in short term [3].
This paper presents the design and measurement of key
circuits for the implementation in a high data-rate
60 GHz transceiver. At the present state, the circuits are
completed for on-wafer measurement.

2. Circuit Design

A. Transceiver Architecture
Figure 1 shows the block diagram of the proposed
transceiver. It is based on amplitude shift keying
modulation principle (ASK). The reasons for the
selection of this modulation technique are the following. Figure 1 : Transceiver block diagram
- ASK is a very simple modulation scheme allowing
designing and demonstrating a 60 GHz transceiver in a
relatively short time-scale. It allows focusing on the
 B. Low Noise Amplifier
The three-stage LNA circuit is shown in Figure 2 and
Figure 3. One task of the LNA design was to get
unconditional stability for both on-wafer measurements
and for the use of the amplifier in test board modules
together with the other receiver components. Especially
the use of bond wires for the connection of the ground
potential (and the associated inductance) causes serious
stability problems if a single-ended configuration is used.
That’s why all the stages are designed in differential
configuration. The input and output are trafo-coupled.
The transformer coupling is useful in two ways. First, it
acts as a balun for connection to a single-ended antenna.
Second, the primary and secondary windings of the
transformer are tuned to gat a bandpass characteristic.
With this, an additional input filter in the RX path can be
omitted and this function is integrated in the LNA.
The circuit of one single stage of the LNA is shown in
Figure 3. It is a differential stage with inductive load and
with matching network at the output.
Figure 2 : 60 GHz LNA.
Figure 3 : Circuit of one stage of differential LNA.
C. Oscillators
The transceiver architecture of Figure 1 requires two
oscillators working at different frequencies. One is for
the transmit path at the centre of the ISM band at
61.25 GHz. The other frequency in the receive path is the
transmit frequency reduced by the intermediate
frequency (IF). The circuit principle of both oscillators is
based on a modified Colpitts principle in a symmetric
configuration of negative-resistance type as shown in
Figure 4 [4]. With the symmetric circuit the signal
interference via the silicon substrate is reduced in
comparison to a single-ended version.
The diodes and resistors in the circuit are used to define
the operating point of the transistors. The tank is a
symmetric circuit of the Inductors L1 and the MIM
capacitor C1. The base-emitter capacitors CBE of the
bipolar transistor acts in parallel to the MIM capacitors
C1. For explanation, the tank can be divided into two half
circuits separated by the symmetry line shown in Figure
4. In operation, the oscillator-halves are working in the
odd mode, such that the outputs are 180º out of phase.
The nodes of the tank indicated by the symmetry line are
fixed at virtual ground for the fundamental tone.
The inductors L1 are designed as arms of a single loop of
metal layer 4 (Aluminium with 2 µm thickness and
10 µm width). The simulated inductance is 85 pH per
arm. The capacitor C2 is a varicap formed by an n-
channel MOS device. In order to get a wide range of
capacitance variation the device is working in the whole
range from depletion to accumulation. The voltage for
frequency-control is applied to the n-well of the
structure. With VCtrl becoming more positive, the MOS
structure is driven into depletion and the capacitance will
be reduced. The output of the oscillator core is connected
to an amplifier in the case of the receive path. The
oscillator of the transmit path is directly connected to the
amplifier with switch (Figure 1).
Figure 4 : Circuit of the LC oscillators used in the receive
and the transmit path.
D. Mixer
The mixer circuit is a balanced Gilbert cell with
symmetric LO and RF inputs. The differential output is
connected to the VGA giving the differential signal to
the demodulator.
E. ASK Modulator
The modulator circuit consists of bipolar transistors and
a MOS transistor (Figure 5). It is a symmetric common-
base amplifier with the base connected to the drain of an
n-channel MOS transistor. The gate of the MOS
transistor is connected to the data input. With low
voltage level at the input the MOS transistor is switched
off and the common-base circuit acts as an amplifier
transferring the RF to the power amplifier. With high-
level at the input the MOS transistor is switched on and
the base-emitter voltage approaches zero. In this manner
the amplifier is switched off and the power amplifier
input is isolated from the oscillator. The advantage of the
circuit is the shielding function of the bipolar base region
so that a good isolation can be expected.
3. Measurement Results
The circuits were fabricated in the IHP 0.25 µm SiGe:C
BiCMOS technology. The bipolar transistors of this
technology have a maximum transit frequency fT of
200 GHz and also a maximum frequency of oscillation
fmax of 200 GHz. In the circuits mainly bipolar transistors
and passives were used. The only MOS transistor so far
is the switch in the modulator circuit. Figure 7 shows
photos of the presented circuits. The oscillators were
characterized using an on-wafer test-system with GS-
probes. The supply voltage of the oscillators and mixer is
3V and the voltage of the switch, demodulator and the
LNA is 2.5 V.

a) b)
Figure 5 : RF switch for modulation of the RF signal.

F. Demodulator
The amplitude-shift keying demodulation uses a full-
wave rectifier together with a lowpass filter (LPF)
corresponding to the maximum data rate of 1Gb/s. The
block diagram is shown in Figure 6. Full-wave
rectification is easily achieved using both differential
inputs. The diode function is implemented using high-
performance transistors, resulting in wide input
frequency range (3-30 GHz) giving large IF flexibility. c)
d)
However, the summation is a differential-to-single-ended
conversion. To regenerate the differential mode, the
output of an additional common-mode block (CMB) acts
as the corresponding inverted signal. A subsequent
differential amplifier provides sufficient gain for bit
slicing.

e)
Figure 6 : ASK demodulator block diagram.
Figure 7 : Chip Photo of a) LNA, b) mixer, c) oscillator of
the receive-path, d) oscillator and switch in the
transmit-path, e) receiver test structure.
The LNA was measured on wafer with a 110 GHz vector
network analyser. The maximum gain is 9.6 dB. The
gain-maximum is reached at 61 GHz, which is exactly
the target frequency of the requested ISM band (Figure
8). The LNA has a bandpass characteristic resulting from
the tuned transformers at input and output. With this
characteristic, no additional bandpass filter is needed.
Figure 8 : Gain curves of the 60 GHz LNA.
The transmit path was measured by applying a
rectangular waveform to the data input of the modulator
while the integrated oscillator generates the RF power.
Figure 9 shows the output of the switch measured with
an oscillograph. The signal at the data input has a
frequency of 200 MHz. The output amplitude is
210 mVpp. The output frequency of the oscillator is
65 GHz. This frequency is too high in comparison to the
target of 61.25 GHz. A redesign of this oscillator is
required.
Figure 9 : Signal of the oscillator with switching the
output on and off.
The LC oscillator in the receive path has a tuning range
from 56 GHz to 60 GHz. The chosen IF frequency for
the VGA and the demodulator is 4 GHz. Figure 10 shows
the tuning curve of the VCO.
Figure 10 : Tuning curve of the LC oscillator in the
receiver.
4. Summary and Conclusions
Key circuit blocks for 60 GHz high data-rate transceiver
system were successfully designed and fabricated in a
SiGe:C BiCMOS technology. The adopted modulation
scheme was ASK for simple configuration with high data
rate.
The measurement results show 9.6 dB gain of the LNA
at 61 GHz, 4 GHz tuning range of the oscillator in the
receiver with a centre frequency of 58 GHz and an ASK
modulator with good isolation properties and 210 mVpp
output voltage. Further measurements and a redesign is
in progress.
Acknowledgements
The authors acknowledge the IHP technology team for
chip fabrication and the modelling team for supplying
accurate models of the devices.
References
[1] P. Smulders, “Exploiting the 60GHz band for local
wireless multimedia access: prospects and future
directions,” IEEE Communications Magazine,
pp.140-147, Jan. 2002, pp. 118-121.
[2] K. Ohta et al., “Wireless 1.25 Gb/s transceiver
module at 60GHz band,” ISSCC Dig. Tech. Papers,
pp. 298-299, Feb. 2002.
[3] S. Reynolds et al., “60 GHz transceiver circuits in
SiGe bipolar technology,” ISSCC Dig. Tech. Papers,
pp. 442-443, Feb. 2004.
[4] W.Winkler et al., “60 GHz and 76 GHz oscillators in
0.25 µm SiGe:C BiCMOS“, IEEE Int. Solid-State
Circuits Conf., February 2003, pp. 454-455.