Introduction to VHDL

Covers VHDL modeling of basic building blocks of combinational logic. From the designer viewpoint of using VHDL to write a textbased description of a digital circuit for design entry, presynthesis simulation, and logic synthesis. VHDL is a industry standard language for modelling digital circuits. Original version (1987) - IEEE standard 1076. Revised standard IEEE 1164 (1993). Originally intended for design documentation and simulation.

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VHDL Keywords and Constructs

Constructs for VHDL Entity declaration Entity circuit is port (
a : in std_logic; b : out std_logic; c : in std_logic_vector(3 downto 0); d : out std_logic_vector(0 to 7) ); end circuit; signal inta : std_logic; signal intb : std_logic_vector (3 downto 0); signal counter : integer range -127 to 127; variable temp: std_logic_vector(0 to 7) constant C : std_logic_vector (3 downto 0) := 000;

Internal signals, variables, constants

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Constructs for Component instantiation

VHDL
architecture sys_arch of system1 is component comp1 port( a : std_logic; b : std_logic ) ; end component; begin U_comp1: comp1 port map (A, B); end sys_arch; Dataout <= Datain;

Concurrent signal assignment Sequential block process ( a )

begin end process;

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Constructs for Control flow a)If b)if else

VHDL
if (en = 1) then f <= x1; end if; if (sel = 0) then f <= x1; g <= x2; else f <= x2; g <= x1; end if;

c)case

case y is when 00 => f <= stateA; when 01 => f <= stateB; when others => f <= stateC; end case;

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VHDL Design Unit

A digital circuit or system is called a design entity, or just entity. It has two blocks: The entity declaration, which specifies the input and output connections (ports) to the hardware The architecture, which defines the behaviour of the hardware entity being designed (or each words, provides the circuit details).

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Entity Entity declaration

entity entity_name is port ( signal_name : end entity_name;

[mode]

type_name );

Architecture

architecture architecture_name of entity_name is [type; signal; constant; component declarations] [attribute specifications] begin {component instantiation statement;} {concurrent assignment statement;} {process statement;} {generate statement;} end [architecture_name];

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VHDL Data Object & Types

Three

data objects are used to represent information in VHDL programs. Signals Variables Constants Signals provide wires (connections) in the circuit. An architecture assigns value to an output signal through a signal assignment statement denoted by the symbol '<='. E.g.,
x

<= 1; -- binary value 1 is assigned to x x <= u + y; -- value of (u + y) is assigned to x

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The values of signals can correspond to different data TYPEs, such as INTEGER, REAL, BIT, and nonnumeric sets. Data types are characterized by a name, a set of values, and a set of operations. VHDL data types that are predefined include:

TYPE INTEGER TYPE TYPE TYPE TYPE REAL BOOLEAN BIT CHARACTER

IS RANGE -2,147,483,647 TO 2,147,483,647

i.e., -(2**31-1) to (2**31-1)

IS RANGE -1.0E+38 TO 1.0E+38 IS (FALSE, TRUE) IS ('0', '1') IS (..., 'A','B',...,'a', 'b',..., '0', '1',...)
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VHDL also contain new types useful in modelling digital hardware. To accurately model the operation of digital circuits, values other than '0' or '1' are also needed for a logic bit. Data type STD_LOGIC include nine values, namely U, X, 0, 1, Z, W, L, H, and ''. U is un-initialized X is forced unknown Z is tri-state or high impedance L and H are weak '0' and weak '1', respectively '' is dont care.

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STD_LOGIC_VECTOR data type contains a vector (or onedimensional array) of STD_LOGIC bits. A one-bit value is assigned to a signal using single quotes, as in 0 or 1. A STD_LOGIC_VECTOR is assigned to a vector using double quotes, as in 00. A VHDL program with STD_LOGIC data types should include, at the beginning of the program, the statements: LIBRARY ieee; USE ieee.std_logic_1164.all; Othe packages - std_logic_arith (signed and unsigned), std_logic_signed (signed), and std_logic_unsigned (unsigned).
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Operators in VHDL
Highest precedence Operator Class Miscellaneous Multiplying Sign Adding Relational Logic Operator
NOT *, / +, +, -, & (concatenate) =, /=, <, <=, >, >= AND, OR, NAND, NOR, XOR, XNOR

Lowest Precedence

Operators in the same category do not have precedence over one another.
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x1 AND x2 AND x3 OR x4

Since there is no precedence among any Boolean operators, the above expressionto imply the Boolean expression x1x2x3 + x4

Parentheses should be used freely to ensure correct interpretation of the logic expression. (x1 AND x2 AND x3) OR x4

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HDL Modelling of Digital Circuits

Different circuit complexities (e.g., simple modules to complete systems) require different kinds of specification or levels of abstraction. Three modelling styles in HDL-based design of digital systems Structural modeling Dataflow modeling Behavioural modeling

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Structural modelling using primitives and lower-level module instantiation. This modelling allows for the hierarchical modular design approach in design. It is used to describe a schematic or logic diagram. The functionality of the design is hidden inside the components. Dataflow modelling output signals are specified in terms of input signal transformation. This style is similar to Boolean equations. This model-ling style allows a digital system to be designed in terms of its function. Behavioural modelling describes the function or expected behaviour of the design in an algorithmic manner. This style is the closest to a natural language description of the circuit functionality.
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Dataflow Modelling
func2 x1 x2 x3 Logic Function f

VHDL entity func2 is port ( x1, x2, x3 : in std_logic; f : out std_logic); end func2; architecture LogicFunc of func2 is begin f <= (not x1 and not x2 and x3) or (x1 and not x2 and not x3) or (x1 and not x2 and x3) or (x1 and x2 and not x3); end LogicFunc;

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A half-adder description using concurrent statements

VHDL entity HA is port (a, b : in std_logic; s, c : out std_logic); end HA; architecture Dataflow of HA is begin s <= a xor b; Cout <= a and b end Dataflow;

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A full-adder description using concurrent statements

VHDL 1 entity fulladder is 2 port (Cin, x, y : in std_logic; 3 s, Cout : out std_logic); 4 end fulladd; 5 6 architecture LogicFunc of fulladder is 7 begin 8 s <= x xor y xor Cin; 9 Cout <= (x and y) or (Cin and x) or (Cin and y) 10 end LogicFunc;

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Notes on Concurrent/ Continuous signal assignment statements

In VHDL, a concurrent signal assignment statement is used to assign a value to a signal. Different types of concurrent statements: simple signal assignment selected signal assignment conditional signal assignment The order in which these statements appear in the architecture body does not affect the semantics of the VHDL code. The statements are executed concurrently whenever any one of the values on the RHS changes.

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Besides concurrent statements, there are also sequential statements. Sequential statements are evaluated in the order in which they appear in the code. Must be contained in a process block - More discussion later.

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Structural Modelling

Modular design of full-adder using half-adders A full-adder circuit, FA, is described in a hierarchical modular approach, using the half-adder module, HA. The figure below shows the functional block diagram of the full-adder modular design. In VHDL structural modelling, component instantiation (concurrent statements) is used. A component instantiation statement associates the signals in the instantiated component (HA, in this case) with the ports of the design entity (FA in this case).
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VHDL entity FA is port ( cin, a, b : in std_logic; sum, cout : out std_logic); end FA; architecture Structural_FA of FA is signal s1, s2, s3 : std_logic; component HA port (a, b : in std_logic; sum, cout : out std_logic); end component; begin u1: HA port map ( a, b, s1, s2 ); u2: HA port map ( s1, cin, sum, s3 ); cout <= s2 or s3; end Structural_FA;

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Behavioural Modelling

At higher levels of design abstraction, a digital module is often modelled behaviourally, i.e., the function or operation of the module is described in an algorithmic manner. In behavioural modelling, the VHDL code will contain statements that are executed sequentially in a predefined order (or procedure). The order of the sequential (or procedural) statements in the VHDL code is important and may affect the semantics of the code. In VHDL, these sequential statements are defined using a PROCESS statement inside an architecture body.
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PROCESS Statement

Besides the typical signal assignment statement, there are three variants of sequential statements: IF-THEN-ELSE statement CASE statement LOOP statement. When there is a change in the value of any signal in the processs sensitivity list, then the process block becomes active. Once activated, statements in the process are evaluated in sequential order.

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Any signal assignments inside the process block are not visible outside the process until all the statements in the process have been evaluated. For multiple VHDL assignments to the entity circuit25 is port ( a, b : in std_logic; same signal, only z : out std_logic); the last one is used. end circuit25;

architecture Behav of circuit25 begin process (a, b) begin z <= 0 ; if a = b then z <= 1 ; end if; end process; end Behav;

is

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Behavioural Modelling of Basic Combinational Logic

Using IF-THEN-ELSE construct

2:1 MUX a b 0 f 1 sel z

entity mux2to1 is port ( a, b, s : in std_logic; z : out std_logic); end mux2to1; architecture behav of mux2to1 is begin process (a, b, s) begin if s = 0 then z <= a ; else z <= b ; end if ; end process; end behav;
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s f: if s = 0 then z = a else z = b

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Multiplexer with vectored signals.

entity LogicCircuit is port ( a, b : in std_logic_vector(3 downto 0); s : in std_logic; z : out std_logic_vector(3 downto 0) ); end LogicCircuit; architecture behav of LogicCircuit is begin process (a, b, s) begin if s = 0 then z <= a ; else z <= b ; end if ; end process; end behav;

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Another method
process (sel, x1, x2) begin f <= x1; if sel = 1 then f <= x2; end if; end process;

The statement f <= x1 is evaluated first and be the default. Only when f <= x2, the second assignment overrides the default f assignment.

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Implied Memory

Due to no default value (or no ELSE clause) f would retain its present value when the IF condition is not satisfied. f = self + selx2 A.k.a implied latch
process (sel, x1, x2) begin if sel = 1 then f <= x2; end if; end process;

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Using CASE-WHEN construct

The CASE-WHEN statement is written akin to a truth table. The final WHEN clause sets a default value. Consider a 2-to-4 Decoder, with Enable signal The VHDL constructs IF-THEN-ELSE and CASE-WHEN statements are sequential statements, and therefore must be contained in process blocks.

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Concurrent WITH-SELECT-WHEN and WHEN-ELSE Constructs

VHDL also provides an alternative way to describe these logic circuits using concurrent statements. The WITH-SELECT-WHEN statement above provides selective signal assignment. The WHEN conditions must specify mutually exclusive values of the selection signal The WHEN-ELSE statement provides selective VHDL conditional signal assignment. the WHEN condition can specify any simple expression.

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Examples

entity mux is port (a, b, c, d : in std_logic_vector (3 downto 0); s : in std_logic_vector (1 downto 0); x : out std_logic_vector (3 downto 0)); end mux; architecture archmux of mux is begin with s select x <= a when 00 , b when 01 , c when 10 , d when others; end archmux;

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entity mux is port (a, b, c, d : in std_logic_vector (3 downto 0); s : in std_logic_vector (1 downto 0); x : out std_logic_vector (3 downto 0)); end mux; architecture archmux of mux is begin x <= a when (s = 00) else b when (s = 01) else c when (s = 10) else d ; end archmux;

Higher priorities for WHEN conditions with higher order of appearance.

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Tri-state buffer

Besides 0 and 1, there is a third signal value is Z When a gates output is in a high-impedance state, it is as though the gate were disconnected from the output. Gates that can be placed in such a state are called tri-state gates, which output one of three values: 0, 1, and Z.
OE Din Dout

Din X 0 1

OE Dout 0 1 1 Z 0 1

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The code
entity tristatebuffer is port (Din, OE : in std_logic; Dout : out std_logic); end tristatebuffer; architecture circuit of tristatebuffer is begin Dout <= Din when OE = 1 else Z ; end circuit;

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