Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees

Boyan Semerdjiev and Dimitrios Velenis

Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago, IL 60616 Email: semeboy@iit.edu, velenis@ece.iit.edu

Abstract Scaling of the on-chip feature size down into the deep submicron range has emphasized the importance of interconnect delay variations due to capacitive coupling. A methodology for reducing crosstalk noise on tree-structured interconnects is proposed in this paper. An algorithm is implemented to compute the optimal sequence of shielding insertion along a capacitively coupled interconnect tree. The reduction in crosstalk is veried through simulation and compared to alternative shielding schemes, considering the availability of limited shielding resources. It is demonstrated that the reduction in interconnect delay variations achieved by the proposed methodology is consistently higher. Furthermore, it is shown that delay variations between two critical nodes in a tree can also be reduced by the same shielding insertion approach.

I. I NTRODUCTION The scaling of the on-chip feature size within the deep submicron range has shifted the design effort of integrated circuits towards enhancing the performance of on-chip interconnect lines. As interconnect wires become thinner and more densely routed, the wire capacitance to ground is decreased and coupling capacitance among the lines increases [1]. Crosstalk noise induced by signal switching events on capacitively coupled interconnects can cause the delay of a signal to deviate from its target value [2], [3]. Signal delay variations along a critical path of a system can cause a wrong data to be latched within a register, thereby causing a circuit to malfunction. To compensate for the effects of delay variations, the timing constraints in a system are relaxed and the maximum operating frequency is reduced [4]. Therefore, alleviating the effects of coupling capacitance among interconnects is a critical task for reducing delay variations and enhancing the circuit performance. Several methods can be utilized to reduce the effects of crosstalk noise on coupled interconnect lines. Increasing the spacing among interconnect wires reduces the amount of coupling and the variations in signal delay [5]. This approach, however, reduces the interconnect routing density and therefore the functionality of an integrated system. Alternatively, the routing of power and ground lines among signal propagating wires can effectively decrease capacitive coupling and reduce the effects that introduce crosstalk noise [3]. The

insertion of these power and ground supply lines is called interconnect shielding. The utilization of interconnect shielding depends upon the available resources of power and ground lines. The primary effort in this paper is focused on optimizing the application of shielding lines, considering the resource constraints. The proposed methodology can be applied to any tree interconnect structure in order to reduce the signal delay variations at a tree node. In this paper, the application of shielding on clock trees is considered for reducing the effects of crosstalk noise on the clock signal arriving at critical registers. The proposed shield insertion methodology is presented in Section II. An algorithm that implements the proposed methodology is described in Section III. The developed algorithm is utilized to determine the application of shielding in a set of tree structured interconnects. The resulting reduction in signal delay variations is presented in Section IV. Furthermore, the proposed methodology is used in Section V to determine the insertion of shielding when two critical nodes are considered within a tree. Finally, some conclusions are presented in Section VI. II. PATH S HIELDING ALONG T REE S TRUCTURED I NTERCONNECTS In this paper crosstalk noise along clock tree structures is considered. The clock signal is generated at the source of the tree and propagates to the clocked registers located at the leafnodes of the tree. The unique route along the tree between the clock signal source and a register node is dened as the path between the source and that node. All the other segments on the clock tree that are not on the path to a node are specied as branches. A critical node on the tree represents a register of a critical path. Variations of the clock signal delay to that node can violate the timing constraints at the register and cause a system malfunction. The entire tree structure is considered to be coupled with interconnect lines routed in parallel to the tree segments. It is assumed that all the coupled lines switch together at the same time with the clock signal, therefore introducing the largest amount of crosstalk on the clock tree. The effects of crosstalk noise among interconnect lines are described using the aggressor-victim model. A signal transition on an aggressor line affects the propagation of a signal along a victim line. In the discussion that follows the clock tree

is considered the victim interconnect structure. The parasitic capacitance per unit length for a coupled interconnect wire is determined by two primary components, the capacitance to the ground substrate, and the coupling capacitance to adjacent lines. The total line capacitance is

The maximum delay variation at a critical node of the tree is expressed by the difference in the signal delay when the lines switch in the same and opposite directions. When the shielding segment is placed closer to the source of the tree,

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Initially, the insertion of shielding along the direct path between the signal source and a critical tree node is considered. The distributed interconnect resistance and capacitance is segments of unit size. It is assumed that modelled using only one unit segment within the clock tree is shielded on the path from the source to the critical node, as illustrated in Figure 1. Two posible locations are considered for shielding insertion, one closer to the source as shown in Figure 1(a), and one closer to the critical node, as illustrated in Figure 1(b). The effect of the shielding placement on the variation of signal delay at the critical node is evaluated next, considering that the clock tree and the aggressor line can switch both in the same and in opposite directions. The case where both the aggressor line and the clock tree switch in the same direction is considered rst. In this case the

Alternatively, in the case that the aggressor line and the clock tree switch in opposite directions, the effective capacitance of the non-shielded segment is , which is higher than . Therefore, the delay of the clock signal is greater when the non-shielded segment is placed closer to the critical node and multiplied with the greater common path resistance factor. In this case, the effect of shielding to the signal delay is (3)

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where is the ground substrate capacitance, is the coupling capacitance between wires, and is a constant that depends upon the signal switching conditions on the coupled lines [6]. If two capacitively coupled interconnect lines switch in the same direction at the same time then the value of is zero and the coupling capacitance component is cancelled. If the lines switch in opposite directions, then and the effective coupled capacitance is maximum. This case represents the worst-case delay of a signal along the victim line. If the aggressor line does not switch, the value of is one. This variation in the effective capacitance of an interconnect wire due to crosstalk causes variations in the signal propagation delay along a line. Interconnect shielding can alleviate the effects of crosstalk and reduce the delay variations of interconnect signals. A quiescent power ( ) or ground line is routed between the two coupled lines, forcing the value of factor to become one and eliminating the variations of the component. Therefore, the total effective capacitance of a shielded signal line is constant: . It is demonstrated that interconnect shielding is an efcient method to reduce crosstalk noise. In order to completely eliminate the noise effects along a clock tree, power supply wires are required to be routed parallel to the entire tree structure which may not be feasible. In a practical design, the available shielding resources are sufcient for covering only a portion of the clock tree. The shielding methodology presented in this paper optimizes the placement of limired shielding resoures in order to minimize the effects of crosstalk noise at a critical node within a tree. The basic concept of this methodology is presented next.

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effective capacitance of the non-shielded wire segment will be which is less than the capacitance of the shielded segment: . Using the Elmore delay model [7] to evaluate the clock signal delay at the critical node results in a higher delay value when the shielded segment is placed closer to the node, as shown in Figure 1(b). The greater delay is due to the greater common path resistance factor multiplied with the component in the tree illustrated in Figure 1(b) compared with the tree shown in Figure 1(a). Therefore, when both lines switch in the same direction the signal delay is less when shielding is applied closer to the source of the tree (2)

the maximum delay variation at the critical node is

(4)

When the shielding segment is placed closer to the critical node, the maximum delay variation is

model provides exactly the same delay values for both shielding locations, since the branch capacitances are multiplied by the same resistive coefcient. More accurate delay values at a critical node of the tree can be obtained with the use of the lognormal delay metric [8][11] given by:

Considering the expressions (2) and (3) it can be shown that (6)

It is shown by expression 6 that the variations in signal delay are greater when the shielding is applied further away from the critical nodes of the clock tree. Therefore, inserting shielding lines closer to a critical node in a clock tree results in greater efciency in the utilization of the shielding resources. B. Shielding placement along the tree branches Furthermore, the effect of shielding at a tree branch segment upon the delay variation of the clock signal arriving at a critical node is investigated. A tree branch is considered a line segment that does not belong in the path from the clock source to a critical node. A unit wire segment along a branch of a clock tree is shielded on two different locations, as shown in Figure 2. The shielded segment can be closer to the direct path from the source to a critical node as shown in Figure 2(a), or farther away, as illustrated in Figure 2(b).
branch

where represents the Elmore delay and characterizes the second moment of the tree circuit at the critical node. represents the signal delay to the critical node. Using this approach, it is shown that the signal delay at the critical node of the clock tree is higher for the circuit shown in Figure 2(a), compared with the circuit illustrated in Figure 2(b). Therefore, when both the clock tree and the aggressor lines switch in the same direction, the effect of shielding location on a branch is

Alternatively, when the aggressor lines and the clock tree switch in opposite directions, the delay at a critical node is smaller when the branch shielding is applied closer to the direct path to that node. Therefore, for opposite switching interconnects:

Clock Source

Direct Path Critical Node

branch

The maximum delay variation at a critical node of the tree is expressed by the difference between the signal delay when the lines switch in the same and opposite directions. When shielding is placed closer to the direct path to the critical node, the delay variation at that node is

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Non-shielded line segment

(a) Close-to-Path Shielding

When the shielding segment is placed farther on the branch, the delay variation is

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Direct Path Critical Node

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(b) Far-from-Path Shielding

Fig. 2. Shielding placement along a tree branch, with respect to the direct path from source to a critical node

The effect of the shielding placement on the variation of the signal delay at the critical node is evaluated next. Initially it is assumed that the clock tree and the aggressor lines are switching in the same direction. Applying the Elmore delay

Therefore, it is demonstrated that the variations in signal delay are less when shielding on a branch is applied at a closer location to the direct path from the tree source to a critical node. Considering the analysis of shielding on the direct path that was discussed earlier, it can be concluded that the closer the application of shielding is to a critical tree node, the greater the reduction of the delay variations at that node. This is the basic concept of the proposed shielding methodology that enhances the shielding efciency on tree structured interconnects. An algorithm that implements this approach is described in the next section.

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III. S HIELDING I NSERTION A LGORITHM It is demonstrated in section II that the effectiveness of interconnect shielding on reducing delay variation at a critical node is enhanced when shielding is applied in the close proximity of that node. An algorithm that implements this concept is developed and presented in this section. This algorithm determines the optimum segments of a tree that should be shielded in order to achieve the greatest reduction in signal delay variations at a specic node. Constraints in the availability of shielding resources are also considered within the proposed approach and they are expressed as the maximum percentage of the tree structure that can be shielded. The position of a critical node within a tree is the preferred location to begin the application of shielding. The entire tree structure is subdivided into unit length segments. Shielding is applied iteratively at single unit segment steps from the location of the critical node towards the source of the tree. The set of possible unit segments that can be shielded in a single iteration is dened as the shielding frontier. In the rst iteration of the algorithm the shielding frontier is the wire segment adjacent to the critical node. In every iteration the frontier advances by one unit segment towards the source of the tree. When a branch node within the tree is reached, the segments on both downstream directions of the branch node are inserted in the frontier. In the next iteration two segments are candidates for shield insertion. To determine which one is the best candidate, the reduction in delay variation at the critical node is calculated assuming that each one of the frontier segments is shielded. The segment resulting in the greatest reduction in delay variation is selected and the segment(s) downstream are added to the frontier. An example of the application of the algorithm on a tree structure is illustrated in Figure 3. In the tree circuit shown in
D B (Shielded) A

Figure 3(a) the shielding sequence was initiated at the critical node and has propagated toward the source of the tree. There are three segments , , and in the frontier. The reduction in the delay variation at the critical node is calculated assuming that each one of the segments , , and are shielded. It is assumed that the shielding of segment produces the greatest reduction in delay variation. Therefore, segment is shielded and the downstream segment is inserted in the frontier, as shown in Figure 3(b). The shielding of segments , , and in the frontier is evaluated again and segment is selected, as illustrated in Figure 3(c). After segment is shielded, segments and are inserted in the frontier. In the following step segment is selected for shielding among segments , , , and , as shown in Figure 3(d). At the end of this step the frontier set contains the nodes , , , and . The lognormal delay metric [8] is utilized within the algorithm to determine the reduction in the delay variation when the shielding of each candidate segment is considered. Calculating the rst and second moments at the critical node has a quadratic dependence on the total number of unit length segments in the tree. The rst and second moments can potentially be calculated for every unit segment in the tree. Therefore, the complexity of the algorithm is , where is the total number of unit segments. The pseudocode of the algorithm is listed in Figure 4. Notice in Figure 4 that the algorithm terminates when either the frontier set is empty (i.e. the entire tree is shielded), or when all the available shielding resources are utilized.

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(a) Step 1 - Three segments in the frontier

(b) Step 2 - Segment is shielded and is added to the frontier

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IV. S HIELDING A PPLICATION R ESULTS The developed algorithm is applied to a set of interconnect tree structures in order to evaluate the effect of the proposed path-and-branch shielding methodology on the signal delay variations at a critical tree node. The proposed approach

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TABLE I A PPLICATION OF PATH - AND - BRANCH AND DIRECT- PATH SHIELDING FOR REDUCING DELAY UNCERTAINTY AT A
CRITICAL NODE

1 2 3 4 5 6 7 8

2 9 7 6 8 8 4 5

3 17 13 11 15 15 7 9

9.8 9.2 5.6 10 10 10 10 7

287.0 231.6 83.0 230.9 112.3 157.1 240.4 144.4

166.3 152.1 56.7 111.7 46.9 87.8 105.4 85.6 Avg. Reduction

42.1% 34.3% 31.7% 51.6% 58.2% 44.1% 56.2% 40.7% 44.9%

154.8 134.6 51.5 103.2 31.8 73.9 103.8 77.6 Avg. Reduction

is compared with an alternative shielding technique where shielding is applied only along the direct path between the critical node and the signal source. The developed shielding application algorithm is modied in order to implement the alternative method, by advancing the shielding frontier only along the direct path from the critical node to the tree source. For both methodologies, limited shielding resources are considered. Shielding can be applied only along 30% of the total tree length. An example of the proposed path-and-branch shielding methodology and the alternative direct-path shielding approach is illustrated in Figures 5(a) and 5(b) respectively.

simulation are compared with the values obtained by the algorithm using the lognormal delay metric, and the results are listed in Table II. As shown in Table II, the utilization of the lognormal delay metric provides in general accurate results with an error below 4%. There is only a single case where the error between the simulated and calculated delay variations value is increased up to 9.2%.
TABLE II C OMPARISON OF DELAY VALUES OBTAINED BY SIMULATION AND THE
LOGNORMAL METRIC

Circuit 1 2
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Scenario No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var No-Shield Var 30% Shield Var

Algorithm (ps) 284.1 170.5 231.1 132.6 82.8 51.4 227.1 99.3 114.5 32.2 155.4 71.4 236.3 99.6 142.8 75.7

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3 4 5 6

(a) Path-and-Branch Shielding

(b) Direct-Path Shielding

7 8

Fig. 5. Examples of the path-and-branch and direct-path shielding approaches

Eight different interconnect tree structures are considered for application of the shielding methodologies. The interconnects are implemented on metal 4 layer using TSMC technology [12]. The total length of the tree structures is between and . The length of the direct path between the critical node and the tree source is between and . For each tree structure, the delay variation at the critical node when no shielding is applied, together with the reduction in noise achieved by the two shielding methodologies is listed in Table I. It is shown in Table I that the application of direct-path shielding along 30% of the interconnect tree reduces the signal delay variations at a critical node by 44.9% on average. Furthermore, the application of the proposed path-and-branch shielding increases the reduction in delay variations by up to 51% on average, for the same total shielding length. Therefore, the proposed path-andbranch methodology enhances the efciency of the utilization of shielding resources. Furthermore, the considered tree structures are simulated us1 ing Spectre and the variations in signal delay before and after the application of the shielding methodologies are calculated. The delay variation values calculated by Spectre

V. S HIELDING

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1 Spectre

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The most crucial effect of delay variations in the clock signal is the uncertainty introduced between the clock arrival times at sequentially adjacent registers connected by a combinational data path. The more strict the setup and hold time constraints of a data path are the more sensistive the timing of that data path is to clock delay variations. A small amount of clock signal delay variations can violate the timing constraints at a critical data path and cause a system malfunction. Therefore, it is signicant to reduce the delay variations of the clock signal at both the initial and the nal register of a critical path. The application of interconnect shielding on two critical nodes within a tree is considered in this section. The proposed path-and-branch shielding methodology is applied on a set of tree interconnects and the results are compared with the application of the alternative direct-path shielding approach for pairs of critical nodes. For both methodologies, limited availability of shielding resources is considered. Shielding can only be applied along 30% of the total tree length. In the case of the direct-path shielding method,

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Circuit No.

No. of Terminals

No. of Segments

Total Length (mm)

No Shielding (ps)

Direct-Path (ps) % Reduction

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Path-and-Branch (ps) % Reduction 46.1% 41.9% 38.0% 55.3% 71.7% 53.0% 56.8% 46.3% 51.1%

Simulation (ps) 287.0 154.8 231.6 134.6 83.0 51.5 230.9 103.2 112.3 31.8 157.1 73.9 240.4 103.8 144.4 77.6

% Error 1.0 9.2 0.2 1.5 0.2 0.2 1.7 3.9 1.9 1.2 1.1 3.5 1.7 4.2 1.1 2.5

TABLE III R EDUCTION IN THE SUM OF DELAY VARIATIONS AT TWO CRITICAL NODES
Circuit No. 1 2 3 4 5 6 No. of Terminals 8 5 6 8 8 4 No. of Segments 15 9 11 15 15 7 Total Length (mm) 10 7 10 10 10 10 No Shielding (ps) 325.3 251.3 327.2 293.4 216.2 324.7 Direct-Path (ps) % Reduction 34.3% 36.0% 35.2% 34.4% 32.4% 35.1% 34.6%

213.8 160.8 212.0 192.4 146.2 210.8 Avg. Reduction

206.2 157.7 194.2 182.8 136.5 202.0 Avg. Reduction

the direct path from each node towards the source equal to 15% of the total tree length is shielded. For the proposed path-and-branch approach, both shielding frontiers advance simultaneously towards the source until 30% of the tree is shielded. If the critical nodes are close, the shielded segments may merge in a single shielded subtree and a common frontier will advance towards the signal source. An example of the two approaches used for shielding application to two critical nodes is illustrated in Figure 6.

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node segment and advancing towards the source of the tree. At every step of the algorithm the unit segment that minimizes the delay variations is selected and the shielding frontier is advanced. The proposed methodology is applied to a set of tree interconnects and the results are compared with the application of shielding along the direct path between the source and a critical node. It is shown that the approach presented in this paper enhances the efciency of shielding application by more than 6% on average. Furthermore, the effectiveness of the proposed approach is demonstrated when two critical nodes are identied in a tree and shielding is applied to reduce the signal delay variations at those nodes. R EFERENCES
[1] L. Ding, P. Mazumder, and D. Blaaw, Crosstalk noise estimation using effective coupling capacitance, Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 5, pp. 645648, May 2002. [2] L. Ding, D. Blaaw, and P. Mazumder, Efcient crosstalk noise modeling using aggressor and tree reductions, Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 595600, November 2002. [3] J. Zhang and E. G. Friedman, Effect of shield insertion on reducing crosstalk noise between coupled interconnects, in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2. n.p., May 2004, pp. 529532. [4] C. V. Kashyap, C. J. Alpert, and A. Devgan, An effective capacitance based delay metric for rc interconnect, Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 229234, November 2000. [5] X. Huang, Y. Cao, D. Sylvester, S. Lin, T. King, and C. Hu, Rlc signal integrity analysis of high-speed global interconnects, International Electron Device Meeting (IEDM), pp. 731734, December 2000. [6] T. Sakurai, Closed-form expressions for interconnection delay, coupling and crosstalk on vlsis, IEEE Transactions on Electron Devices, vol. 40, no. 1, pp. 118124, January 1993. [7] W. C. Elmore, The transient response of damped linear networks with particular regard to wideband ampliers, Applied Physics, vol. 19, pp. 5563, January 1948. [8] C. J. Alpert, F. Liu, C. V. Kashyap, and A. Devgan, Delay and slew metrics using the lognormal distribution, in Proceedings of the Design Automation Conference. n.p., June 2003, pp. 382385. [9] P. R. OBrien and T. L. Savarino, Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation, Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 512515, November 1989. [10] C. J. Alpert, F. Liu, C. V. Kashyap, and A. Devgan, Closed-form delay and slew metrics made easy, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 12, pp. 1661 1669, December 2004. [11] C. J. Alpert, A. Devgan, and C. V. Kashyap, Rc delay metrics for performance optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 5, pp. 571582, May 2001. [12] 0.18UM Logic 1P6M Salicide 1.8V/3.3V Spice Models, Taiwan Semiconductor Manufacturing Co., LTD, July 1999.

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(a) Direct-path shielding for (b) Path-and-branch shielding two nodes for two nodes Fig. 6. Path-and-branch and direct-path shielding approaches for two nodes

The resulting reduction in the sum of delay variations at the two critical nodes by the application of shielding is listed in Table III. The two shielding methodologies are applied to a total of six tree structures. As listed in Table III, the application of the direct-path shielding methodology reduces the variation of signal delay between the two nodes by 34.6%. The proposed path-and-branch approach achieves an even higher reduction in delay variation by 37.8%. Therefore, it is demonstrated that the proposed shielding methodology also increases the efciency of shielding application in the case that two critical nodes are considered within a tree. Furthermore, the reduction in signal variation simulated using Spectre is compared with the values calculated by the shield insertion algorithm using the lognormal delay metric. It is demonstrated that the calculations using the lognormal delay metric are accurate in general with a maximum error of 3.5% VI. C ONCLUSIONS A methodology that enhances the efciency of shielding application on on-chip tree interconnects is presented in this paper. Interconnect shielding is applied in iterative steps along unit length segments of a tree in order to achieve the greatest reduction in signal delay variations at a critical node. The limited availability of shielding resources is considered in the proposed approach. An algorithm is developed that implements the application of shielding starting from the critical

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Path-and-Branch (ps) % Reduction 36.6% 37.2% 40.6% 37.7% 36.9% 37.8% 37.8%