Flip-Flops

extracts Irom:
http://www.elec.uq.edu.au/~3e211/pracs/prac2/prac2.htm
Dept. of Computer Science and Electrical Engineering
The University of Queensland
St. Lucia Qld 4072 Australia
%e memory elements in a sequential circuit are called flip-flops A Ilip-Ilop circuit as two
outputs, one Ior te normal value and one Ior te complement value oI te stored bit Binary
inIormation can enter a Ilip-Ilop in a variety oI ways and gives rise to diIIerent types oI Ilip-
Ilops
397oduc9io3 - Basic Flip-Flop Ci7cui9
A Ilip-Ilop circuit can be constructed Irom two NAND gates or two NOR gates %ese Ilip-
Ilops are sown in Figure 2 and Figure 3 Eac Ilip-Ilop as two outputs, " and ", and two
inputs, set and reset %is type oI Ilip-Ilop is reIerred to as an SR flip-flop or SR latch %e
Ilip-Ilop in Figure 2 as two useIul states Wen Q1 and Q'0, it is in te set state (or 1-
state) Wen Q0 and Q'1, it is in te clear state (or 0-state) %e outputs Q and Q' are
complements oI eac oter and are reIerred to as te normal and complement outputs,
respectively %e binary state oI te Ilip-Ilop is taken to be te value oI te normal output
Wen a 1 is applied to bot te set and reset inputs oI te Ilip-Ilop in Figure 2, bot Q and Q'
outputs go to 0 %is condition violates te Iact tat bot outputs are complements oI eac
oter In normal operation tis condition must be avoided by making sure tat 1's are not
applied to bot inputs simultaneously

a) Logic diagram

-) %rut table
Figu70 2. Basic Ilip-Ilop circuit wit NOR gates

a) Logic diagram

-) %rut table
Figu70 3. Basic Ilip-Ilop circuit wit NAND gates
%e NAND basic Ilip-Ilop circuit in Figure 3(a) operates wit inputs normally at 1 unless te
state oI te Ilip-Ilop as to be canged A 0 applied momentarily to te set input causes Q to
go to 1 and Q' to go to 0, putting te Ilip-Ilop in te set state Wen bot inputs go to 0, bot
outputs go to 1 %is condition sould be avoided in normal operation
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397oduc9io3 - Clock0d SR Flip-Flop
%e clocked SR Ilip-Ilop sown in Figure 4 consists oI a basic NOR Ilip-Ilop and two AND
gates %e outputs oI te two AND gates remain at 0 as long as te clock pulse (or CP) is 0,
regardless oI te S and R input values Wen te clock pulse goes to 1, inIormation Irom te
S and R inputs passes troug to te basic Ilip-Ilop Wit bot S1 and R1, te occurrence
oI a clock pulse causes bot outputs to momentarily go to 0 Wen te pulse is removed, te
state oI te Ilip-Ilop is indeterminate, ie, eiter state may result, depending on weter te
set or reset input oI te Ilip-Ilop remains a 1 longer tan te transition to 0 at te end oI te
pulse

a) Logic diagram

-) %rut table
Figu70 4. Clocked SR Ilip-Ilop
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397oduc9io3 - D Flip-Flop
%e D Ilip-Ilop sown in Figure 5 is a modiIication oI te clocked SR Ilip-Ilop %e D input
goes directly into te S input and te complement oI te D input goes to te R input %e D
input is sampled during te occurrence oI a clock pulse II it is 1, te Ilip-Ilop is switced to
te set state (unless it was already set) II it is 0, te Ilip-Ilop switces to te clear state

a) Logic diagram wit NAND gates

-) Grapical symbol

c) %ransition table
Figu70 5. Clocked D Ilip-Ilop
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397oduc9io3 - 1K Flip-Flop
A JK Ilip-Ilop is a reIinement oI te SR Ilip-Ilop in tat te indeterminate state oI te SR type
is deIined in te JK type Inputs J and K beave like inputs S and R to set and clear te Ilip-
Ilop (note tat in a JK Ilip-Ilop, te letter J is Ior set and te letter K is Ior clear) Wen logic
1 inputs are applied to bot J and K simultaneously, te Ilip-Ilop switces to its complement
state, ie, iI Q1, it switces to Q0 and vice versa
A clocked JK Ilip-Ilop is sown in Figure 6 Output Q is ANDed wit K and CP inputs so
tat te Ilip-Ilop is cleared during a clock pulse only iI Q was previously 1 Similarly, ouput
Q' is ANDed wit J and CP inputs so tat te Ilip-Ilop is set wit a clock pulse only iI Q' was
previously 1
Note tat because oI te Ieedback connection in te JK Ilip-Ilop, a CP signal wic remains a
1 (wile JK1) aIter te outputs ave been complemented once will cause repeated and
continuous transitions oI te outputs %o avoid tis, te clock pulses must ave a time
duration less tan te propagation delay troug te Ilip-Ilop %e restriction on te pulse
widt can be eliminated wit a master-slave or edge-triggered construction %e same
reasoning also applies to te % Ilip-Ilop presented next

a) Logic diagram

-) Grapical symbol

c) %ransition table
Figu70 6. Clocked JK Ilip-Ilop
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397oduc9io3 - T Flip-Flop
%e % Ilip-Ilop is a single input version oI te JK Ilip-Ilop As sown in Figure 7, te % Ilip-
Ilop is obtained Irom te JK type iI bot inputs are tied togeter %e output oI te % Ilip-Ilop
"toggles" wit eac clock pulse

a) Logic diagram

-) Grapical symbol

c) %ransition table
Figu70 7. Clocked % Ilip-Ilop
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397oduc9io3 - T7igg07i3g of Flip-flops
%e state oI a Ilip-Ilop is canged by a momentary cange in te input signal %is cange is
called a trigger and te transition it causes is said to trigger te Ilip-Ilop %e basic circuits oI
Figure 2 and Figure 3 require an input trigger deIined by a cange in signal level %is level
must be returned to its initial level beIore a second trigger is applied Clocked Ilip-Ilops are
triggered by pulses
%e Ieedback pat between te combinational circuit and memory elements in Figure 1 can
produce instability iI te outputs oI te memory elements (Ilip-Ilops) are canging wile te
outputs oI te combinational circuit tat go to te Ilip-Ilop inputs are being sampled by te
clock pulse A way to solve te Ieedback timing problem is to make te Ilip-Ilop sensitive to
te pulse transition rater tan te pulse duration
%e clock pulse goes troug two signal transitions: Irom 0 to 1 and te return Irom 1 to 0
As sown in Figure 8 te positive transition is deIined as te positive edge and te negative
transition as te negative edge

Figu70 8. DeIinition oI clock pulse transition
%e clocked Ilip-Ilops already introduced are triggered during te positive edge oI te pulse,
and te state transition starts as soon as te pulse reaces te logic-1 level II te oter inputs
cange wile te clock is still 1, a new output state may occur II te Ilip-Ilop is made to
respond to te positive (or negative) edge transition only, instead oI te entire pulse duration,
ten te multiple-transition problem can be eliminated
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397oduc9io3 - Mas907-Slav0 Flip-Flop
A master-slave Ilip-Ilop is constructed Irom two seperate Ilip-Ilops One circuit serves as a
master and te oter as a slave %e logic diagram oI an SR Ilip-Ilop is sown in Figure 9
%e master Ilip-Ilop is enabled on te positive edge oI te clock pulse CP and te slave Ilip-
Ilop is disabled by te inverter %e inIormation at te external R and S inputs is transmitted
to te master Ilip-Ilop Wen te pulse returns to 0, te master Ilip-Ilop is disabled and te
slave Ilip-Ilop is enabled %e slave Ilip-Ilop ten goes to te same state as te master Ilip-
Ilop

Figu70 9. Logic diagram oI a master-slave Ilip-Ilop
%e timing relationsip is sown in Figure 10 and is assumed tat te Ilip-Ilop is in te clear
state prior to te occurrence oI te clock pulse %e output state oI te master-slave Ilip-Ilop
occurs on te negative transition oI te clock pulse Some master-slave Ilip-Ilops cange
output state on te positive transition oI te clock pulse by aving an additional inverter
between te CP terminal and te input oI te master

Figu70 10. %iming relationsip in a master slave Ilip-Ilop
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397oduc9io3 - Edg0 T7igg070d Flip-Flop
Anoter type oI Ilip-Ilop tat syncronizes te state canges during a clock pulse transition is
te edge-triggered Ilip-Ilop Wen te clock pulse input exceeds a speciIic tresold level,
te inputs are locked out and te Ilip-Ilop is not aIIected by Iurter canges in te inputs until
te clock pulse returns to 0 and anoter pulse occurs Some edge-triggered Ilip-Ilops cause a
transition on te positive edge oI te clock pulse (positive-edge-triggered), and oters on te
negative edge oI te pulse (negative-edge-triggered) %e logic diagram oI a D-type positive-
edge-triggered Ilip-Ilop is sown in Figure 11

Figu70 11. D-type positive-edge triggered Ilip-Ilop
Wen using diIIerent types oI Ilip-Ilops in te same circuit, one must ensure tat all Ilip-Ilop
outputs make teir transitions at te same time, ie, during eiter te negative edge or te
positive edge oI te clock pulse
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397oduc9io3 - Di70c9 3pu9s
Flip-Ilops in IC packages sometimes provide special inputs Ior setting or clearing te Ilip-
Ilop asyncronously %ey are usually called preset and clear %ey aIIect te Ilip-Ilop
witout te need Ior a clock pulse %ese inputs are useIul Ior bringing Ilip-Ilops to an intial
state beIore teir clocked operation For example, aIter power is turned on in a digital system,
te states oI te Ilip-Ilops are indeterminate Activating te clear input clears all te Ilip-Ilops
to an initial state oI 0 %e grapic symbol oI a JK Ilip-Ilop wit an active-low clear is sown
in Figure 12

a) Grapic Symbol

-) %ransition table
Figu70 12. JK Ilip-Ilop wit direct clear
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P70pa7a9io3
Prepare te Iollowing in your prac book:
Basic Flip-Flop
i Draw te logic circuit Ior an unclocked NOR gate Ilip-Ilop
ii Enter te expected timing diagram Ior signals Q and Q' in Figure 13

Figu70 13. NOR gate Ilip-Ilop timing diagram
iii Draw te logic circuit Ior an unclocked NAND gate Ilip-Ilop
iv Enter te expected timing diagram Ior signals Q and Q' in Figure 14

Figu70 14. NAND gate Ilip-Ilop timing diagram
Mas907-Slav0 Flip-Flop
i Draw te logic circuit implemented wit gates Ior te SR master-slave Ilip-Ilop in
Figure 9 Use NOR gate Ilip-Ilops
ii Enter te expected timing diagram Ior te signals Y, Y', Q, and Q' in Figure 15

Figu70 15. SR master-slave Ilip-Ilop timing diagram
Edg0 T7igg070d Flip-Flop
i Draw te logic circuit Ior te D-type positive-edge triggered Ilip-Ilop in Figure 11
ii Enter te expected timing diagram Ior te signals S, R, Q, and Q' in Figure 16

Figu70 16. D-type edge triggered Ilip-Ilop timing diagram
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P7oc0du70
Use LogicWorks to simulate te circuits tat you ave prepared Use switces Irom te I/O
library Ior te inputs and probes Irom te I/O library Ior te outputs Place signal names on
te circuit so tat te signals are visible in te timing window Create a separate drawing Ior
eac circuit
%o be sure tat your circuits don't cross te printing page boundaries, ceck te Sow Page
Outlines option Irom te Drawing,Display Options menu
Only print out te circuit and waveIorms Ior te SR master-slave Ilip-Ilop