1 - Truth table and reduced Boolean equation.

I started with first writing down the Boolean equation that describes the 2-input mux on the gate level
diagram.

Using Demorgan's theorem, I can simplify the Boolean equation.

The truth table is easily found by plugging in all possible values of A, X0, and X1 into the inputs and
recording Y.

A X1 X0 Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

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2 - Transistor Level Schematic (Virtuoso)

I decided against using symbols because of the simplicity of the circuit. Any larger than this, and I'm sure it
would be wise to work at the gate level .

Each gate was made with CMOS transistor logic.

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3 - Logic Simulation (irsim)

Converting the netlist with schm2sim.pl:

>perl schm2sim.pl

The following irsim script was used to generate inputs:

cmd.bat

stepsize 50
analyzer A X1 X0 Y
vector in A X1 X0
set in 000
s
set in 001
s
set in 010
s
set in 011
s
set in 100
s
set in 101
s
set in 110
s
set in 111
s

Finally, using IRSIM with the input script and the CMOS description file found on the TA page.
>irsim cmos.prm sch.sim -sim.cmd

The logic generated correctly describes the 2-input mutiplexer.

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4 - Hand Calculations

First step was to calculate the capacitive load for the final NAND gate. The specification call for the mux
driving 32 minimum size CMOS inverters, and a 100fF wiring cap.

Estimating the capacitive load of one CMOS inverter using only the gate capacitances for both the NMOS and
PMO S device :

Solving for final load by multiplying Cinv by 32 and adding the 100fF wiring cap:

Calculate the current required to switch the load in the allotted 600ps propagation delay.

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5 - Table of Calculations

tphl tplh tp pstat pdyn

Hand 600ps 600ps 600ps 0 700uW
Spice 598ps 650ps 598ps 720uW

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6 - Simulation Waveforms

After first simulating the circuit with the orginal calculated Wp and Wn, I realized that not taking into
account some of the parasitics caused me to underestimate the current required to charge the load.

By increasing my Wn to 660nm and my Wp to 2.22um for the last nand gate to take into account the
parasitics, I was able to meet the 600ps specification for rise time.

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7 - Layout Design

The layout design was completed successfully and passed the CRC and all design constraints.

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