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FM RECEIVER TRAINER MODEL-COM124-RX

More than 2000 Trainers

SIGMA TRAINERS AHMEDABAD (INDIA)

INTRODUCTION
This trainer has been designed with a view to provide practical and experimental knowledge of a general circuit of FM radio receiver on Single PCB of size 12"x 9.

SPECIFICATIONS

1. 2. 3. 4. 5. 6.

Power supply Audio power output Frequency range Controls Instrument required Standard Accessories

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220V Ac, 50Hz 450mW maximum. FM - 88MHz to 108 MHz. Volume and Tone controls. Standard signal generator with 1MHz carrier and 30% modulation index 1. A Training Manual 2. Connecting Patch cords.

PRACTICAL-1
BLOCK DIAGRAM & WORKING PRINCIPLE OF FM RADIO RECEIVER (1) FM Tuner section: IC1 works as a FM tuner as well as FM I.F. amplifier and detector. It consists of RF amplifier, FM Local oscillator and mixer. The FM modulated signal picked by telescopic antenna is connected to the RF amplifier in he IC1 at pin 2 through wideband tuned Circuit L54 - C58. This FM signal is amplified and then applied to a Mixer via a parallel tuned circuit (L51, C53 and C52) at pin 24. In the mixer, the signal is mixed with an Oscillator signal, which is also controlled by a parallel- tuned circuit (L52, C54 and C51) at pin 24. C51 is FM Gang capacitor. C51 and L52 are tuned to change FM oscillator frequency. The oscillator is combined with an automatic frequency control circuit-AFC-which only needs an external buffer capacitor C55 (4.7/16). Thus the FM signal is converted into 10.7 MHz FMIF signal by the mixer and oscillator. The output of the mixer is applied to an external filter consisting of FM IFT coil L53 ad capacitor C56 and C57. L53 is tuned to 10.7MHz. CF1 and CF2 are ceramic filter tuned to 10.7 Mhz FM IF frequency. (2) FM IF Amplifier: This stage is based on a single IC - IC1. It consists two stage IF amplifier. The 10.7 MHz FM IF signal from the FM mixer is connected to first FM IF amplifier at pin 18 through L53. The amplified signal is again filtered by ceramic filter CF1 (10.7S) at pin 4 and 6. The filtered signal is then applied to 2nd FM IF amplifier at pin 4. Then it is applied to FM discriminator in the IC1. The gain of this stage is @ 78dB. (3). FM Detector: A ratio detector is used for FM detection, since it gives a good measure of self-limiting. This detector is included in the IC1. Here coil L4 works as FM detector coil. (3) FM AGC: Here FM AGC signal is given to FM IF amplifiers in the IC1 and FM RF amplifier in the IC1. AGC is directly given in the IC1 for FM RF amplifier and FM IF amplifier. (4) Audio Preamplifier: Q4 (BC148A) is an audio preamplifier transistor. The detected output from D5 (OA79) is connected to volume control from POT P1 (10K Log) though tone control P7 depending upon the band selected. Pot P2 (100K) and C22 (0.1u) constitutes the tone control. The required output from the volume control is fed to the base of Q4 (BC148A) through the coupling capacitor C10 (0.1u). R10 (1M) provides the base bias to Q4. R11 (2K2) is the collector load and R12 (100E) is the mean current limiting resistor. The amplified output from the collector of Q4 is given to the driver transistor Q5 (BC148B) through the coupling capacitor C11 (0.1u). (5) Audio Driver: Q5 (BC 148B) is the driver transistor. It amplifies the output available from the preamplifier. R13 (220K) is the base-biasing resistor. The decoupling network R14 (150E) and C12 (220/10) keeps the bias free from variations and so steady. The collector of Q5 (BC 148B) is connected to the DC supply +6V through the primary of driver transformer X1, which is a step down type. It has two separate secondaries to supply two equal and phase opposite signals to the push pull output transistors Q6 (AC128) and Q7 (AC128). (6) Output: Q6 (AC128) and Q7 (AC128) works as output amplifier in push pull configuration. The signal output from the driver transformer is available at the two secondaries, which are so phased that Q6 and Q7 conduct alternately for every half cycle of the input signal. The signals fed to Q6 and Q7 are in phase opposition at any instant of 2

time. So under Class A condition during cycle of the input signal voltage when the collector current of Q6 increases because of increased bias, the collector current of Q7 decreases because of reduction in bias, and vice versa in the other half cycle. Normally a very low forward bias (0.2 V) is given so that the transistor work in Class `B' mode slightly above cut off under no signal conditions and thus minimizes crossover distortion. So under no signal condition, there is very little collector current and so very low drain on the DC supply (battery). Each transistor handles only half cycle of the signal voltage. R16 (47E), R17 (1K), R18 (47E), R19 (1K) form a potential driver across the battery of 6V. Since R16 + R17 is equal to R18 + R19, the battery is divided equally at the junction of R17 and R18 i.e. at point B. C13 (220/10) and C14 (220/10) are decoupling capacitors to short circuit the resistors for AC; so that the DC potentials at point A, B, C. remain steady even under varying signal condition. C13 and C14 have large value (220uf), Especially to serve as a short circuit to audio signal current flowing through the potential divider. C13 and C14 also act as coupling capacitors for LS.
Circuit of Q6:

The collector of Q6 is connected to +3V (Point B) through LS, which serves as the collector load. The emitter is at +6V potential, so that collector is virtually at 3V with reference to emitter, the condition that is required for working of a PNP transistor. The base is connected through the secondary winding of IDT (input driver Transformer) to the point A, which is 0.2V -Ve with reference to emitter. This is the initial forward base bias. The DC collector current flows through the LS. So this stage is common emitter amplifier getting input signal through S1 (1st secondary winding) and developing an output signal across LS. Since the C13 shorts R16, R17 for signal current, the full signal voltage is developed on the LS only.
Circuit of Q7:

In the same way, the collector of Q7 is at zero potential and the emitter through LS is connected to +3V (Point B). Since C14 short circuits R18 and R19 for signal current, the LS is the only load in the circuit. And so the whole output signal power is given to it. Input signal is fed from S2 (2nd secondary of IDT) in the base collector circuit. So this stage works as a common collector circuit. The base is connected through S2 to the point C, which provides the initial base bias for Q7.
No Signal Condition:

The two transistors Q6, Q7 are in series across the +6V as far as DC is concerned, because the battery potential is divided equally across them, and the currents are flowing in the same direction through them. Q6, Q7 and the divided potentials of the battery form actually a balanced bridge circuit and the LS gets connected across the bridge ends, and so takes no DC current. Under no signal condition, the DC currents flowing through LS are in opposite directions, and when the transistors are a matched pair, the currents are equal and cancel each other.
Signal Conditions:

Considering the AC conditions, Q6 and Q7 are connected in parallel since the emitter of Q6 and collector of Q7 are at the same potential. Since C13 and C14 are short circuit paths to signals current, the emitter of Q6, point A, B, C and collector of Q7 can be considered at the same potential as far as AC is concerned. So each transistor and the load which is common to both are in parallel and load requirement is also reduced to half that of one transistor. Again since the two transistor circuits are electrically separate, the emitter of Q6 and Collector of Q7 can be considered as same without altering the circuit operation in any way. Both the half cycles of the input signal flow through LS. (7). Power supply stage. The mains 230V AC is step downed by X'mer X2 to 9V AC in the secondary. This 9V AC is converted into 12V DC by rectifier diode D1-D4 (1N 4002) and filtering capacitor C16 (1000/10). This 12V DC is converted into regulated +6V dc by 3-pin regulator IC IC2 (7806). C15 is output ripple filtering capacitor. The +6V DC output is available at output pin of IC2 (7806). This +6V DC supply is given to the circuit.

PRACTICAL-2
ALIGNMENT OF FM RADIO RECEIVER FM IF Alignment: 1. Switch on the radio receiver and FM signal generator. 2. Set the FM signal generator at FM modulated output 10.7 MHz and connect loop antenna to it. 3. Connect AC voltmeter across LS. 4. Set the volume control fully clockwise. 5. Set the attenuator of the signal generator to maintain the output about 0.25 V on the AC voltmeter, this will prevent overloading of the receiver. 6. Set the gang capacitor of the receiver to minimum capacity or set the point of the receiver at 108 MHz on the dial. 7. Adjust the core of FM IFT for maximum response. 8. Seal cores with wax.

PRACTICAL-3
RECEPTION OF FM SIGNALS 1. Keep FM radio receiver near FM transmitter with transmitting frequency 100KHz and modulating voice audio signal. 2. Speak to mike and hear voice signal in FM receiver.