SLNO 1 2 3 4 5 6 7 8 9 10 11

DATE 11/10/2010 12/10/2011 18/10/2010 19/10/2010 25/10/2010 26/10/2010 01/11/2010 02/11/2010 08/11/2010 09/11/2010 09/11/2010

PERIOD 6,7 5,6 6,7 5,6 6,7 5,6 6,7 5,6 6,7 5 6

TOPICS Course syllabus Class policies Lecture Note #1: Introduction Review of Combinational Logic
Combinational Circuits Design

HOURS NEEDED 2 2 2 2 2 2 2 2 2 1 1 20

Five and Six variable K-Maps

Synchronous Sequential Circuits review & design

Introduction to Mealy & Moore state machines Design of sequence detectors and state machines
Analysis in combinational and sequential systems

Fault detection, Static and dynamic hazards The Design of Digital Systems Examples Total Hours

SLNO 1 2 3 4 5 6 7

DATE 18/01/2011 24/01/2011 25/01/2011 31/01/2011 01/02/2011 07/02/2011 08/02/2011

PERIOD 5,6 6,7 5,6 6,7 5,6 6,7 5,6

TOPICS Introduction to programmable Logic Families and

Tutorial

HOURS NEEDED 2 2 2 2 2 1 1 12

Classification of PLDs, SPLD,CPLD,PROM,PLA and PAL, Problems Introduction to CPLDs, Architecture of ALTERA Max 7000 CPLDs Introduction to FPGAs, Architecture of Xilinx 4000 FPGA Implementation of circuits using PROMS, PLAs and Problems practice Asynchronous sequential circuit design and problem practice Assignment work and Tutorial Total Hours

SLNO 1 2 3 4 5 6

DATE 15/11/2010 16/11/2010 22/11/2010 23/11/2010 29/11/2010 30/11/2010

PERIOD 6,7 5,6 6,7 5,6 6,7 5,6

TOPICS Introduction to HDLs and VERILOG HDL VERILOG Libraries, Modules and Architectures, Levels of Abstractions.
Verilog Description of combinational Circuits Module instances (Ex: RCA), Common Verilog pitfalls in module instantiation. Verilog operators and Gate level modeling. Delays in Verilog (Rise, Fall and Turn off), Delay Values and Behavioral modeling

HOURS NEEDED 2 2 2 2 2 2

Blocking and Non-blocking Statements and assignments and elimination of RACING Conditions.
combinational logic circuits-Verilog codes serial adders-binary multipliers-binary divider Modeling using Verilog-Flip Flops-registerscounters sequential machineCompilation and simulation of Verilog codes

7 8 9 10 11

06/12/2010 07/12/2010 13/12/2010 14/12/2010 20/12/2010

6,7 5,6 6,7 5.6 6.7

2 2 2 2 2 22

Test Bench Program Practice, Tutorials and test. Total Hours

SLNO 1

DATE 21/12/2010

PERIOD 6,7

TOPICS Introduction to asynchronous sequential machines and difference between synchronous machines. Asynchronous Sequential Circuit Design and analysis-Flow table reduction and state assignment Introduction to Fault models, Faults in Logic Circuits Stuck-at Fault Struck @ zero and Struck @ one faults Bridging Faults and Delay Fault Controllability and Observability, Problems Path sensitation method and D algorithm problems
Test Generation for Combinational Logic Circuits, Group Discussion on speed of digital systems

HOURS NEEDED 2

27/12/2010

5,6

3 4 5 6 7 8 9

28/12/2010 10/01/2011 10/01/2011 11/01/2011 11/01/2011 17/01/2011 17/01/2011

6,7 6 7 5 6 6 7

2 1 1 1 1 1 1 12

Total Hours

SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING, Kadayiruppu Department of ECE- PG M.Tech in VLSI & EMBEDDED SYATEMS
LMV 103

Advanced Digital System Design

Module 1 Combinational Circuits Design- Synchronous Sequential Circuits design-Fault detection and Analysis in combinational and sequential systems-Path sensitizing method-SPOOF method Boolean Difference Method- initial State Method Module 2 Asynchronous Sequential Circuit Design and analysis-Flow table reduction-state assignment-problem and transition table-static and dynamic hazards-essential hazards-mixed operating mode asynchronous circuits. Module 3 Study of programmable Logic Families- PLD, CPLD, FPGA, PLA. Synthesis and implementation issues Module 4 Verilog Description of combinational Circuits-arrays-Verilog operaters-Compilation and simulation of Verilog codes-Modelling using Verilog-Flip Flops-registers-counterssequential machine-combinational logic circuits-Verilog codes serial adders-binary multipliers-binary divider. Text Books : 1. Richard F Tinder, Engineering Digital Design, Mc Graw Hill, 2003. 2. Donald D Givone , Digital Principles and Design , Tata Mc Graw Hill, 2004. 3. Parag K Lala, Digital Circuit Testing and Testability ,Academic Press, 1997 4. Samir Palnitkar, Verilog HDL , Pearson Education, 1996. 5. K. Chan and S. Mourad,Digital Design Using Field Programmable Gate Array, Prentice Hall, 1994. 6. Greweal B S, Higher Engineering Mathematics, Khanna Publishers, 2005

Instructor: Asst. Prof. KARTHIK.S Office Location: Advanced Software Lab, ECE Dept, SNGCE Telephone: 252 Email: skarthikmtech@gmail.com Class Days/Time: Monday, 14:30 16:20 & Tuesday, 13:30 15:25 Classroom: W Block Pre-requisites by Topics: Digital Logic Design, Computer Architecture, Background in integrated circuit design is helpful. Must have self-motivations in learning EDA tools and Verilog HDL Course Description This course covers topics in the advanced design and analysis of digital circuits with HDL. The primary goal is to provide in depth understanding of logic and system design, synthesis, and optimization for area, speed and power consumption. The course enables students to apply their knowledge for the design of advanced digital hardware systems with corresponding EDA tools. Verilog HDL will be used for simulation and synthesis of the homework assignments and Tutorial problems. Student Learning Objectives Upon successful completion of this course, students will be able to: Design and manually optimize complex combinational and sequential digital circuits Model combinational and sequential digital circuits by Verilog HDL Design and model digital circuits with Verilog HDL at behavioral, structural, and RTL levels

Develop test benches to simulate combinational and sequential circuits Perform static and dynamic timing analysis with false paths and hazards Analyze power distribution and optimize power consumption in digital circuits
Required Texts, Readings, and EDA Tools: 1. Lecture Notes by Karthik.S

2. 4.

Donald D Givone, Digital Principles and Design , Tata Mc Graw Hill, 2004.

3. Samir Palnitkar, Verilog HDL, Pearson Education, 1996.

Parag K Lala, Digital Circuit Testing and Testability ,Academic Press, 1997

Additional Readings (optional) Any Verilog Language books/notes. Below are few on-line documents: 1. VERILOG Language reference manual

Classroom Protocol: 1. Students will put their cell phones in quiet/vibration mode during the lecture. 2. Students will not skip the lecture, class hours are for students to have questions 3. Students will come to the class on time 4. Students will work on the assignments and report by their own Assignments and Tutorial Exercises: Eight to ten assignments and exercises will be given periodically and will mostly be due in one week from the assigned date. 1. NO late submission will be accepted (absolutely!). 2. To get credit for assignments, submissions must be neat, clean, and must be done professionally and seriously. Computer Usage: Verilog Simulator, FPGA Logic Synthesis tools Additional Activities: Technical Group discussions, one to one technical discussions, Preparing answer key and Evaluation of test papers

DIGITAL SYSTEMS: No area of technology has had or is likely to continue to have more of a profound impact on our lives than digital system development. Overlap in the digital system technologies that make possible those areas we have come to take for granted. The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in large scale integration technologies and system design applications. With the advent of very large scale integration (VLSI) designs, the number of applications of integrated circuits (ICs) in highperformance computing, controls, telecommunications, image and video processing, and consumer electronics has been rising at a very fast pace. The current cutting-edge technologies such as high resolution and low bit-rate video and cellular communications provide the end-users a marvelous amount of applications, processing power and portability. This trend is expected to grow rapidly, with very important implications on VLSI design and systems design. Combinational logic basics: At any time a combinational logic circuit's output(s) depends only upon the combination of its inputs at that time. The important point is that the output is not influenced by previous inputs, or in other words the circuit has no memory. The uses to which combinational logic circuits are put can be broadly classed as: 1. data transfer circuits to control the flow of logic around a system; 2. data processing circuits that process or transform data Common examples are: multiplexers, encoders, adders, parity checkers and comparators

Two-level circuits: The circuit to implement Y= AB + BC was given in Fig. 3.1. It is shown again in Fig together with the circuit to implement the fundamental sum of products form. Since both of these circuits implement sum of products expressions they have the same basic form of AND gates to produce the required product expressions and a single AND gate to perform the summing. Such implementations are called two-level circuits since they consist of a layer of AND gates feeding a single OR gate. Consequently each input signal only has to pass through two gates to reach the output. MINIMISATION OF COMBINATIONAL LOGIC EXPRESSIONS: From the above we have seen how the operation of any combinational circuit can always be expressed in fundamental sum of products form. However, it is also clear that this is an extremely unwieldy form, both to write and implement. It is for this reason that the minimisation of combinational logic expressions is so important, allowing, as it does, circuits to be implemented in simpler forms. Minimization using Karnaugh maps: Although using a two-variable Karnaugh map for minimization is a rather trivial process it nevertheless serves to illustrate the minimization process, which as we have seen consists of combining logically adjacent fundamental product terms. We now look at examples of minimization using Karnaugh maps. Five-variable Karnaugh maps: For a five-variable map, two four-variable maps must be drawn with the fifth variable E used to index the two maps. The layout is shown in Tables below,

Example: The five-variable truth table in Table gives the outputs, X and Y, from two combinational logic circuits. Use Karnaugh maps to minimize these functions. From the Karnaugh map in Table:

X= A C+ CDE+ ABCD+ BDE+ ABDE

The product terms containing E and E are obtained solely from the Karnaugh maps for E and E respectively. Those terms not containing either E or E are for product terms obtained by rouping and looping the same fundamental product terms on both maps. For example the term A C occurs because of the quads in the top right-hand corner of the maps for both E and E. From the Karnaugh map in Table: Y= AB + CDE+ BC+ ABCD+ CDE

It may seem as if the labeling of the columns and rows of the above Karnaugh maps was chosen at random, but this is certainly not so. Then for three-variable maps, as used above, A and B will be used to index the columns and C the rows, whilst for four-variable maps C and D will be used to index the rows. Design Procedure for combinational circuit: 1. From the specifications of the circuit, determine the required number of inputs and outputs and assigned a letter symbol to each 2. Derive the truth table that defined the relationship between inputs and putouts 3. Obtain the simplified Boolean functions for each output as a function f the input variables 4. Draw the logic diagram 5. Verify the correctness of the design

HAZARDS: A hazard is a condition in a logically correct digital circuit or computer program that may lead to a logically incorrect output Static hazards: Output should stay constant, but doesnt

Static 1 hazard: Output should be a constant 1, but when one input is changed drops to 0 and then recovers to 1 Cannot occur in a POS implementation Static 0 hazard: Output should be a constant 0, but when one input is changed rises to 1 and then drops back to 0 Cannot occur in a SOP implementation Why do hazards matter? The output of a hazard-prone circuit or program depends on conditions other than the inputs and the state. The signal passed to another circuit by a hazard-prone circuit depends on exactly when the output is read. In edge-triggered logic circuits, a momentary glitch resulting from a hazard can be converted into an erroneous output. The circuit below for xy + yz has a static 1 hazard. If the input y is changed from 0 to 1, control of the output of the OR gate shifts from one AND gate to the other. Any difference in delays between the two AND gates will result in a glitch in the output of the OR

The timing diagram below shows the inputs and outputs of a circuit for xy + yz with a static 1 hazard

Static 1 hazard detection using a Karnaugh map: Reduce the logic function to a minimal sum of prime implicants. A Karnaugh map that contains adjacent, disjoint prime implicants is subject to a static 1 hazard Adjacent prime implicants: Only one variable needs to change value to move from one prime implicant to the other Disjoint prime implicants

1. No prime implicant covers cells of both of the disjoint prime implicants 2. Correspond to AND gates that must both change their outputs when a particular input is changed Hazard detection: F (x,y,z) = Sm(0,1,3,7)

Hazard elimination:

The circuit below for xy + yz has no static 1 hazard

The timing diagram below shows the inputs and outputs of a revised circuit for xy + yz with no static 1 hazard

Dynamic hazards: Dynamic hazards can occur when a signal has three or more paths through a combinational logic circuit. Their effect is to cause a signal which is expected to change state to do so, then transiently change back to the original state, before making the final transition to the expected state (e.g. the signal gives 1010 rather than just 10). The analysis of a circuit for a dynamic hazard is essentially a continuation of the 'rigorous approach' for static hazards described above. You should therefore be familiar with this material before continuing. Consider the circuit shown in Fig together with its truth table and Karnaugh map. From this implementation we get: Y= (B+C)'(AC+BC)

and note that C has three paths through the circuit" via gates l, 5; gates 2, 4, 5; and gates 3, 4, 5. Therefore there is the possibility of race conditions in three paths which may lead to a dynamic hazard.

Summary: A properly designed two-level SOP (AND-OR) circuit has no static-0 hazards. It may have static-1 hazards. A properly designed two-level POS (OR-AND) circuit has no static-1 hazards. It may have static-0 hazards. Dynamic hazards do not occur in a properly designed two-level AND-OR or OR-AND circuit. It may occur in multilevel circuits. A brute-force method of obtaining a hazard-free realization is to use the complete sum or complete product. Hazard analysis and elimination are typically needed in the design of asynchronous sequential circuits.

Sequential circuit design:

Sequential circuits are essentially combinational circuits with feedback. A block diagram of a generalized sequential circuit is shown in Fig. The generalized circuit contains a block of combinational logic which has two sets of inputs and two sets of outputs. The inputs are: A, the present (external) inputs to the circuit; y, the inputs fed back from the outputs; Z, the present (external) outputs from the combinational circuit; Y, the outputs that are fed back into the combinational circuit.

Note that the outputs, Y, are fed back via the memory block to become the inputs, y, and that y are called the 'present state' variables because they determine the current state of the circuit, with Y the 'next state' variables as they will deter- mine the next state the circuit will enter. It is often useful to think in terms of two independent combinational circuits, one each for the two sets of outputs, Z (external) and Y (internal), as shown in Fig. Both of these outputs will in general depend upon the external, A, and internal, y, (fed back) inputs.

'States' and sequential circuits: An important concept to appreciate is that sequential circuits can be considered at any time to occupy a certain 'state'. These 'states' are dependent upon the internal feedback, and in the case of asynchronous sequential circuits, the external inputs as well. At this early stage we simply note that if the memory in a circuit has i digital lines leading to and from it then it can store 2 i different patterns and hence the circuit possesses 2 ~ internal states. (We call these internal states to distinguish them from the total states of the circuit which are also dependent upon the external inputs.) This idea of the circuit possessing states is fundamental to sequential circuits since they are often designed and analyzed by the manner, or sequence, in which the available states are visited for given sequences of inputs. Asynchronous and synchronous circuits: The timing of the operation of asynchronous circuits, as the name implies, is not controlled by any external timing mechanism. Rather, as soon as changes are made at the inputs of such a circuit they take effect at the outputs. The simplest form of memory in such circuits is just a wire forming the feedback connection. Synchronous circuits are those which possess a clock of some sort which regu- lates the feedback process. Hence the timing of changes in the outputs, in response to changes at the inputs (which may have occurred sometime before), are controlled by the 'ticking' of a clock. Consequently, the timing of the operation of sequential circuits can be, and usually is, synchronised to other parts of a larger circuit. The memory in such circuits is itself made up ot" specialised logic circuits (called flip-flops) that essentially act as digital storage elements.

INTRODUCTION TO ASYNCHRONOUS SEQUENTIAL CIRCUITS: The 'memory' of previous outputs in an asynchronous sequential circuit is provided by direct feedback from the internal output(s), Y, to the internal input(s), y, of the combinational logic block (see Fig). The essence of under- standing asynchronous circuits is to realise that for the circuit to be stable the outputs generated by the input(s) must be equal (i.e. Y=y), since these two sets of signals are connected via the feedback. If this is not so then the circuit will be unstable with the output(s) (unmatched to the input(s)) acting as different input(s) and so producing new output(s) which will then be fed back again. This process will repeat until a stable condition is reached. This concept will become clearer as we analyse actual asynchronous sequential circuits. The first stage of asynchronous sequential circuit analysis is to 'break' the feed- back paths and treat the output(s) being fed back and the corresponding input(s), linked via the feedback, as separate variables. The circuit will only be stable when these signals have the same values. The conditions for which the circuit is stable are known as the 'stable states'.

(Note that for asynchronous sequential circuits these total stable states depend upon all of the inputs, i.e. both internal and external ones, and not just the values of the feedback, i.e. the present state, variables). Circuit analysis involves finding out how these stable states are both reached and related to one another, whilst design involves producing a circuit which enters the required stable states for the desired input patterns.\ Inputs and race conditions: For an asynchronous circuit to be of use it must have more than one external input (otherwise all the circuit has to respond to is a signal alternately changing its value from 0 to 1 to 0 and so on3). If two of these multiple inputs are meant to change simultaneously we know that for a real circuit this can never be guaran- teed and one of them will always change slightly before the other. The effect of this uncertainty, in which signal (and not always the same one) arrives first, is that the circuit may not operate as expected and actually end up in the 'wrong' state. This will make the circuit's operation unpredictable and hence render it useless. This problem can be overcome by making sure that only one input to the circuit changes at a time and that there is sufficient time between changes in the inputs for the circuit to stabilize. This is called fundamental mode operation, which although providing a solution does inhibit the way that the circuit can be used. ANALYSIS: stable and unstable states: Consider the circuit in Fig. below, which is simply an XOR gate with one of the inputs being the output which is fed back, so making it an asynchronous sequential circuit.

If A-0 and y- 1 then the output Y= 1, so the output produced, and fed back to the inputs, matches the input (i.e. y = Y) and the circuit is stable. Similarly, if A =0 and y=0, then Y=0, and so y= Y and the circuit is again stable. The fact that the circuit is stable means that all of the variables will remain unchanged until the input A is changed (as this is the only variable that can be accessed, i.e. the only external input). Now, if A is changed to 1 then if y=0 then Y= 1; and if y= 1 then Y=0. This will clearly lead to an unstable circuit that will continually oscillate. For example, if y-0 the output will be 1, which will be fed back to y causing the output to go to 0 which will be fed back and so cause the output to go to 1 and so on. The speed of oscillation will be determined chiefly by the time it takes the signals to propagate through the XOR gate and back along the feedback path. The Karnaugh map for Y in terms of A and y is also shown in Fig. illustrates the operation of the circuit. For the circuit to be stable Y must equal y, therefore for the top row, the circuit will only be stable when the corresponding cell of the Karnaugh map has a 0 in it (i.e. the internal output Y =0). For the bottom row the circuit will only be stable when Y= 1. We therefore see that only two stable conditions for this circuit exist. Firstly, A =0 and y=0 and secondly A-0 and y= 1, that is when A-0 (the left hand column of the Karnaugh map) as we deduced above. The Karnaugh map confirms the instability of the circuit when A = 1, since nowhere in the right-hand column (A = 1) does y= Y. All of the remaining circuit analyses are based upon the use of such Karnaugh maps. Transition table and output map: Using these Boolean equations we next draw the Karnaugh maps for Y and Z for the variables A, B and y. For this type of circuit analysis the convention is to use the external inputs to label the columns and the internal variables the rows. This gives the maps shown in Table. The one

showing the next state variable, Y, in terms of the present state variable, y, is referred to as the transition table. Flow tables: The next, crucial, stage is to decide which combinations of the three inputs repre- sent stable states for the circuit. That is for which inputs does the fed back signal, Y, correspond to the input signal, y? If these differ, then if they are 'reconnected' (since we have 'broken' the loop) clearly the circuit cannot be stable and will therefore be trying to change. State diagram: We can redraw the flow table as a state diagram which contains exactly the same information but for some purposes is more convenient. In the state diagram each state is represented by a node (a circle with a number in) with the states joined by arrows. These indicate how the circuit moves from state to state with the inputs causing the change indicated on the arrows. Example: The inputs (A, B) take the following values. Determine which states will the circuit be occupied by and illustrate this, and the output, Z, on a timing diagram. (A, B) = (0,0), ( 1,0),( 1,1 ),(0,1 ),( 1,1 ),(1,0), (0,0) Solution: For these inputs the circuit will go into states: 1, 5, 4, 2, 3, 5, 1. The timing diagram is

We have now fully analysed this circuit and can predict what state it will be in for any given sequence of inputs. So, what is its function? This is best investigated by considering under what conditions the external output, Z, becomes 1. This is when the circuit enters state 4, which is when both inputs are 1. This state can only be reached via state 5, which is entered when A = 1 and B-0. So, Z= 1 when the inputs (A,B) are (1,0) and then change directly to (1,1). In other words, the circuit detects an input sequence of (1,0), (1,1).7 This can be seen from the above example where the output goes high indicating this input sequence. Summary of analysis procedure: Now we have completed our first rigorous analysis of an asynchronous sequential circuit we can outline the analysis procedure. We will then use it to analyse two further circuits and then consider the design process. Procedure: Break the feedback loop(s). Draw the transition tables for the next state variable(s) and Karnaugh map(s) for the external output(s) in terms of the external inputs and the present state variable(s). Remember to use the external inputs to index the columns and the present state variables to index the rows. Determine which cells in the transition table give stable states, assign each of these a number and then draw the flow table. Draw the state diagram if required.

Boolean expression of outputs: From the circuit we see that:

Using these equations we can draw the Karnaugh maps for these as shown

Transition table The next stage is to determine under what conditions the circuit is stable which, by extending the argument used in the previous examples, will be when both internal inputs, x and y, match the signals being fed back to them, X and Y. In order to see this it is helpful to combine the Karnaugh maps for X and Y into the single transition table shown. The stable total states will be those cells where the values of XY match those of the variables x and y labeling the rows.

Flow table: The stable total states can then be given numbers and circled whilst the unstable states are simply labeled with the states they will lead to, as shown in Table. Note that because this circuit has two feedback signals there are four possible internal states corresponding to the four possible combinations of these variables, and hence four rows in the excitation matrix. This means that when the circuit is unstable in any cell it now has three cells (in the same column) into which it can move (with one internal input there is only one other cell in each column).

With this circuit when both A and B are 0 all unstable states lead to stable state 1; similarly in the second column when A =0 and B- 1 there is a single stable state to which all unstable states (the other three cells in this column) lead. Note that in this column, AB, rows 3 and 4 do not lead directly to the stable state, but rather get there indirectly via row 1 (since in these rows, (X, Y)(0,0)), which leads directly to state 3 (row 2). In the third column, which has inputs of both A and B being 1, there are two stable states, 4 and 6, with one each of the two unstable states leading to state 4 and 6 respectively. The fourth column, ,~B, also has two stable states, 2 and 5, but here the two feedback variable combinations giving unstable states both lead to state 5 (the one from row 4 indirectly via row 3). Hence the only way of entering state 2 is from state 1.

State diagram: Finally we can draw the state diagram (for fundamental mode operation) as shown in Fig. 5.12. There is a node for each stable state, with two arrows leading from every node (corresponding to movement to the left and right in the flow table as one of the two external input variables is changed).

Circuit operation: Having completed the basic analysis we can examine the circuit's operation under certain conditions. To do this we look at which states give an output of 1 which by comparing the flow table for the circuit and the Karnaugh map for Z can be seen to be only stable state 6. From the state diagram it can be seen that this state is only reached from state 2 when the inputs (A,B) are (1,1). However, state 2 can only be reached from state 1 with inputs of (1, 0), whilst state 1 can only be entered with inputs of (0, 0). This circuit therefore uniquely detects an input sequence of (A, B)= (0,0),(1,0) and then (1,1) to which it responds by sending the external output, Z, high. This completes the analysis, with the consequence of any input sequence capable of being found from either the flow table or state diagram.

SYNCHRONOUS SEQUENTIAL CIRCUITS:

As with asynchronous sequential circuits, the operation of synchronous sequential systems is based around the circuit moving from state to state. However, with synchronous circuits the state is determined solely by the binary pattern stored by the flip-flops within the circuit. Since each flip-flop can store a 0 or 1 then a circuit with n flip-flops has 2" possible states. Note that all states are stable since the present and next state variables are not connected directly but isolated due to the (not-transparent) flip-flops. The analysis and design of these circuits is based upon determining the next state of the circuit (and the external outputs) given the present state and the external inputs. The general form of a synchronous sequential circuit is shown in Fig. To recap, this has: external inputs, A, and outputs, Z; a combinational block which can be considered in two parts; and 'memory' in the form of flip-flops. The two parts of the combinational block serve to provide the internal outputs to the flip- flops, Y, and the external outputs, Z.

Obviously a circuit could have a simpler form and still be a synchronous sequential circuit. For instance it may have no external inputs or the external outputs may be functions of only the flipflop's outputs (the present state variables). Consideration of such simplified circuits leads to a useful way of classifying sequential synchronous circuits.

Design Procedure for sequential circuit: The word description of the circuit behavior to get a state diagram; State reduction if necessary; Assign binary values to the states; Obtain the binary-coded state table; Choose the type of flip-flops; Derive the simplified flip-flop input equations and output equations; Draw the logic diagram; General (Moore and Mealy) circuits and FSMs: The next state of a general synchronous sequential circuit is dependent not only on the present state, as in an autonomous circuit, but also on the external inputs. Such general circuits can be further subdivided into two classes which are commonly referred to as Moore and Mealy models. Introduction: FSM is an abbreviation for Finite State Machine. There are many ways to code FSMs including many very poor ways to code FSMs. This paper will examine some of the most commonly used FSM coding styles, their advantages and disadvantages, and offer guidelines for doing efficient coding, simulation and synthesis of FSM designs. Moore model: The Moore model: the outputs are functions of the present state only. The outputs are synchronous with the clocks. The Moore model describes a general synchronous sequential circuit where the external outputs are only functions of the circuit's present states (i.e. the flip-flops' outputs). Because of this in the

state diagram of such a circuit the external outputs can be linked explicitly to the nodes (i.e. states).

Mealy Machine: The Mealy model: the outputs are functions of both the present state and inputs. The outputs may change if the inputs change during the clock pulse period. The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Mealy model is the most general since not only is the next state dependent upon the present state and the external inputs, but the external outputs are also functions of both of these sets of variables. Since the external outputs also depend upon the external inputs then in the state diagram of Mealy circuits the external outputs cannot simply be associated with a node but rather must be linked to the arrows (connecting the nodes) which are labeled with the output conditions as appropriate.

State diagrams (Mealy model): We can also represent the state table graphically with a state diagram A diagram corresponding to our example state table is shown below
Present State Inputs Next State Outputs Q1 Q0 X Q1 Q0 Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 1

Always check the size of your state diagrams If there are n flip-flops, there should be 2n nodes in the diagram If there are m inputs, then each node will have 2m outgoing arrows In our example,

We have two flip-flops, and thus four states or nodes. There is one input, so each node has two outgoing arrows.

Moore State Diagram:

How to Design a Finite State Machine:

Here is an example of a designing a finite state machine, worked out from start to finish. Step 1: Describe the machine in words. In this example, well be designing a controller for an elevator. The elevator can be at one of two floors: Ground or First. There is one button that controls the elevator, and it has two values: Up or Down. Also, there are two lights in the elevator that indicate the current floor: Red for Ground, and Green for First. At each time step, the controller checks the current floor and current input, changes floors and lights in the obvious way. Step 2: Draw the FSM diagram

In this diagram, the bubbles represent the states, and the arrows represent state transitions. The arrow labels indicate the input value corresponding to the transition. For instance, when the elevator is in the Ground state, and the input is Up, the next state is First. The information in the brackets indicates the output values for the lights in each state. Step 3: Select numbers to represent states and values: Before converting the above FSM diagram to a circuit, we need to represent every value in our example as a binary number. Here is some convenient numbers to use. Ground = 0 Down = 0 Off = 0 First = 1 Up = 1 On = 1 So heres the FSM diagram with the words replaced by numbers:

Step 4: Write the truth table From the FSM diagram, its easy to read off the correct truth table.

Step 5: Draw a big picture view of the circuit Here is the finite-state machine circuit, with many details missing. The variable names have been abbreviated. The dashed boxes indicate the parts (lets call them subcircuits) that we still need to design.

All FSM circuits will have a form similar to this. Our example has two states, and so we need only one D flip-flop. An FSM with more states would need more flip-flops. Our example has one input (labeled I in the figure), but in general there may be many inputs, or none at all. Also, an FSM may not have any outputs, in which case the Output Sub-Circuit would be omitted. In our example, the Output Sub-Circuit has two outputs, R and G. To make things mpler, lets break this into two further sub-circuits: a sub-circuit that computes R, and another sub-circuit that computes G. This is shown below.

Step 6: Find Boolean expressions: For each sub-circuit that we need to design, well write a Boolean expression that expresses its output as a function of its inputs. We derive these expressions from the truth table we wrote in Step 4. There is a very general method for doing this, which well illustrate on the Next-State Sub-Circuit. The Next-State Sub-Circuit has two input I and CS, and one output, NS. From the truth table, we see that NS is 1 in exactly two cases: 1. CS = 0 and I = 1 2. CS = 1 and I = 1 So we simply write a Boolean expression that covers all and only these cases: NS = ((not CS) and I) or (CS and I) Notice that each case is represented by an AND subexpression, and the whole expression is the OR of these sub expressions. This technique can be used on a truth table of any size. Of course, this Boolean expression can be simplified. To do this, we need some rules of Boolean logic. Here are the most useful ones:

A or 1 = 1

Now we can simplify our Boolean expression: NS = ((not CS) and I) or (CS and I) = ((not CS) or CS) and I [using rule 8] = 1 and I =I [using rule 5] [using rule 3]

And so NS = I. Of course, for this simple example, this could have been easily seen just by inspecting the truth table Similarly, we find the Boolean expressions for the other sub-circuits are:

Step 7: Draw the rest of the circuit The only thing left to do is to draw the sub-circuits represented by our Boolean expressions.

FSM design procedure: Start with counters simple because output is just state simple because no choice of next state based on input

State diagram to state transition table tabular form of state diagram like a truth-table

State encoding decide on representation of states for counters it is simple: just its value

Implementation flip-flop for each state bit combinational logic based on encoding

In the case of sequential logic, the design steps are somewhat different from those of combinational logic. First, we have to deal with states. If no external inputs, a counter is a good, simple choice. Then, how states are changed is described by a state transition table, which is similar to a truth-table. To embody the state transition table, we have to choose how to encode states as well as inputs and outputs.