AX.

25 Frame Generation:
The AX.25 protocol divides the packet into seven sections as follows: 1. Flag (s) 2. Address 3. Control 4. Protocol Identifier (PID) 5. Information 6. Frame Check Sequence 7. Flag (s) This is how a UI frame looks like:

Figure 01: UI Frame FLAG: First field is the flag field which is a constant field and is used to delimit the frame. In hex its value is 0xFE and in binary it comes out to be 01111110. ADDRESS: As no digipeater is used, our address field simplifies to figure 02. It is only 112 bits long.

Figure 02: Address Field Address field contains Destination address (CQ, in this case) Source address (W2FS-4 in this case)

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Character C Q Space Space Space Space SSID

HEX Value from 43 (01000011) 51 (01010001) 20 (00100000) 20 (00100000) 20 (00100000) 20 (00100000)

Shifted Hex 86 A2 40 40 40 40 60 (10000110) (10100010) (01000000) (01000000) (01000000) (01000000) (01100000)

So we have following hex values against each character of the address field: W AE 2 64 F 8C S A6 Space 40 Space 40 SSID = 4 69 (01101001)

In each address field entry, there is a zero padded at LSB position. ASCII for Last SSID bit is set to one because there is no other address field entity next. As we are not using any repeater so address field will be only two byte long. CONTROL and PID: The control field identifies the type of frame being sent. The control fields in AX.25 are modeled after the ISO HDLC balanced operation control fields. PID field is selected from the

Figure 03: PID Field Control field is this:

Figure 04: Control Field The M bits are the unnumbered frame modifier bits. The P/F bit is the Poll/Final bit. The P/F bit is used in all types of frames. The P/F bit is used in all types of frames. The P/F bit is also used in a command (poll) mode to request an immediate reply to a frame. The reply to this poll is indicated by setting the response (final) bit in the appropriate frame. Only one outstanding poll condition per direction is allowed at a time.

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Figure 05: UI Control Field INFORMATION: Here we are using Test Corresponding hex values are 54 65 73 74

FRAME CHECK SEQUENCE: The Frame-Check Sequence (FCS) is a sixteen-bit number calculated by both the sender and the receiver of a frame. It ensures that the frame was not corrupted by the transmission medium. The Frame-Check Sequence is calculated in accordance with recommendations in the HDLC reference document, ISO 3309. Generator Polynomial ( ) Corresponding Shift Register Assembly

Figure 06: FCS Shift Register Generator Initial value used is 0xFF. Frame is passed through this assembly to get an FCS field. All frame bits are transmitted in LSB-first order except FCS field. Putting it all together we get this frame

Sp

Sp 40

Sp 40

Sp 40

SSID=0 60

W AE

2 64

F 8C

S A6

Sp 40

Sp 40

SSID=4 69

86 A2 40

Control 03
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PID F0

T 54

e 65

s 73

t 74

Prepared By: Muhammad Naeem, Zeeshan Muhammad Kabir, Kashif Iqbal

Overall frame in binary will look like this: 01111110 01100001 01000101 00000010 00000010 00000010 00000010 00000110 Flag Destination Address

01110101 00100110 00110001 01100101 00000010 00000010 10010110 11000000 00001111 Source Address 00101010 10100110 11001110 00101110 00000010 10011010 01111110 Information FCS Flag Control PID

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