International Workshop on Embedded Computing and Communication, 22, 23rd December, 2011.

Program Highlights
Guest Speaker Title: A Quick Journey through Multi-cores to Scalable Many-core Designs. Abstract: To face the ever-increasing demand for more computational power, Multi processor architectures are not only going to be massively multicore: they are going to feature heterogeneous technologies such as specialized coprocessors. Multiprocessor architectures and platforms have been introduced to extend the applicability of Moores law. There are several research efforts have recently been carried out in this domain. The design of Muli-core trades-off several important choices, such as topology selection, routing strategy selection and application mapping to network nodes. Developing a design methodology for mulitcore-based communication poses novel and exciting challenges to the design community. This talk gives a a Journey through Multi-cores to Scalable Many-core Designs.

Biography: Dr. Priya Darshan Patra, Intel USA Dr. Priyadarsan Patra is a lead architect and senior scientist variously responsible for pre-silicon Validation and post-silicon Debug and Survivability of Intel's flagship products spanning CPUs, many-integrated-core processor and SoC. He developed domino circuit synthesis and power-noisedelay tradeoff optimization for P4 class of processors. He architected and co-designed probeless post-silicon debug capability for servers. A founding member of Validation Research Lab of Intel, he led research efforts in run-time validation, resilient architecture, and early design exploration of networks-on-chip. He has recently co-authored a book on low-power design/synthesis and has received two conference best-paper nominations. Darshan serves on the committees of several IEEE conferences and mentors through SRC, GSRC programs. He is elected Senior Member of the ACM as well as the IEEE. He co-founded the International Symposium on Electronic System Design. He is on the editorial boards and boards of governors of several academic and nonprofit institutions. Priyadarsan shares a deep and joyous passion for sustainable and equitable developmentand for inventing and using technology for social progress. He is Founding Chair of the Sustainable -1-

Economic and Educational Development Society (SEEDS) and co-founded India Progressive Action Group in Austin where it won Best Student organization award for leadership in sociopolitical issues affecting South Asians. He has taught Portland-area kids for a few years as a coach, and served as a United-way Ambassador and Intel-Involved volunteer. He obtained his Bachelor of Engineering from the Indian Institute of Science and PhD in Computer Sciences from the University of Texas at Austin.

IWECC Keynote
Title: Energy-Efficient Fault Tolerant Microarchitecture for Chip Multiprocessors Abstract: Relentless scaling of silicon fabrication technology coupled with lower design tolerances are making ICs increasing susceptible to wear-out related permanent faults as well as transient faults. A well known technique for tackling both transient and permanent faults is redundant execution, specifically space redundancy, wherein a program is executed redundantly on different processors, pipelines or functional units and the results are compared to detect faults. In this presentation, we describe a power-efficien architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS)algorithm significantly reduces the power overhead of redundant execution without sacrificing performance. Using cycle accurate simulation combined with an architectural power model we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 76% with an associated mean performance overhead of only 1.2%. We also present an extension to our architecture that enables the use of cores with faulty functional units for redundant execution without a reduction in transient fault coverage. This extension enables the usage of faulty cores, thereby increasing yield and reliability with only a modest powerperformance penalty over fault-free execution.

Biography: Dr. Virendra Singh, IIT Bombay Virendra Singh obtained Ph.D in Computer Science from Nara Institute of Science and Technology (NAIST), Nara, Japan in 2005. He receive B.E and M.E in Electronics and Communication Engineering from Malaviya National Institute of Technology (MNIT), Jaipur, India. Currently, he is a faculty member at Supercomputer Education and Research Centre (SERC), Indian Institute of Science (IISc), Bangalore since May 2007. His research interests are high performance computer architecture, testing and verification of high performance processors, VLSI testing, formal verification, fault tolerant computing, embedded system design, design for reliability, and CAD of VLSI Systems. He is a member of the IEEE, the ACM, the VSI, and life member of the IETE. He -2-

is a PC member of many conferences in the area CAD and VLSI such as DATE, ETS, VLSI Design. He is a co-founder of RASDAT (Reliability Aware System Design and Test) workshop. IWECC Invited Talk Title: Spectrum Sensing for Cognitive Radios: Theory and Implementation Abstract: A cognitive system is an information processing system which is able to adapt to its environment and learn from experience. In cognitive radio (CR) concept, the devices will look for holes in the spectrum (a.k.a. spectrum sensing) and dynamically share the free spectrum with other devices (a.k.a. dynamic resource allocation). Spectrum sensing becomes a fundamental and critical task in a CR network, as the unlicensed user has to detect a licensed frequency band, and opportunistically utilizes this band without causing interference to the licensed user of the spectrum. Real-time spectral sensing of wideband signal with low complexity is a challenging task due to the high sampling rate and large bandwidth of the signal. This talk gives an overview of various signal processing aspects of spectrum sensing approaches, the need of variable resolution spectrum sensing and cooperative spectrum sensing.

Biography: Dr. K.G. Smitha, NTU, Singapore K.G. Smitha Received her B Tech degree in electrical and electronics engineering from Calicut University, India in 2002, the M.E degree from Anna university, India in 2004 and PhD degree from Nanyang Technological University in 2010. She was a lecturer in Amrita Viswavidaypeetham, Coimbatore, India from May 2004 to November 2004. Currently she is pursuing post doctoral research in School of Computer Engineering, Nanyang Technological University, Singapore. Her main research interests are in the areas of low complexity and high speed digital signal processing circuits for software radio and cognitive radio and computer arithmetic. IWECC Keynote Title: Pin-Constrained Designs of Digital Microfluidic Biochips for High-Throughput Bioassays Abstract: Digital microfluidic (DMF) biochips have emerged recently as a viable platform of implementing conventional laboratory-based biochemical procedures. These tiny chips are able to manipulate nanoliter volume of discrete fluid droplets on an electrode array via electrical actuation. However, with the increasing dimension of the array, the number of external control pins connected to the electrodes may increase significantly. Several pinconstrained biochip design techniques have -3-

been proposed earlier for controlling the electrodes through a small number of pins, a short review of which is presented in this talk in addition to new schemes.

Biography: Dr. Bhargab Bhattacharya is Assistant Director and professor at Indian Statistical Institute Kolkata. B. Bhattacharya has been on the faculty of the Indian Statistical Institute, Calcutta, since 1982. He held visiting professorship at the University of Nebraska-Lincoln, USA, and at the University of Potsdam, Germany. In the year 2005, he had been with the Department of Computer Science and Engineering, IIT Kharagpur, as VSNL Chair Professor. His research interest includes design and testing of integrated circuits, computational nanoscience, digital geometry, and image processing architecture. He has published more than 200 technical articles, and he holds 9 United States Patents. He is a Fellow ofthe Indian National Academy of Engineering,a Fellow of the National Academy of Sciences (India), and a Fellow of the IEEE. IWECC Invited Talk Title: Placement and Routing Challenges in Three dimensional Integrated Circuits Abstract: In the recent interconnect-centric design approach, the interconnect structures are increasingly consuming more power and delay budgets. 3D IC design was proposed as a plausible solution to this problem. By using this technique the number of nearest neighbors of each transistor can be increased resulting in overall decrease in total interconnect length. Switching to 3D design from the conventional 2D design has yielded several improvements in the performance of a chip. By combining multiple device layers with a high density inter-layer interconnect, 3D integration of a given circuit is likely to improve the timing as well as energy performance relative to a singlewafer implementation of the same circuit. The problem of creation of localized areas of high heat flux or hot spots becomes predominant in case of 3D ICs due to the close proximity of multiple active device layers. As a plausible solution, thermal vias are used to reduce this effect, which, in turn, increases the cost of the design as well as fabrication significantly. Hence, it has become important to consider this scenario during the physical design phase itself, i.e. primarily during the placement phase of the VLSI layout design. If placement algorithm can only tackle this problem and can generate an optimum placement with uniform thermal distribution of the modules then the total cost can be reduced significantly. Though 3D integration technique has proven itself a viable alternative for the next generation chip design but it has several challenges. One and possibly most important one in this regard is the thermal issue. There are several techniques that are being used by the researchers and designers for the reduction of this effect e.g. use of thermal vias, some external cooling methodology etc. But eventually, these efforts increase the cost rapidly. Hence, it has become important to consider this scenario during the physical design phase itself, i.e. primarily during the placement phase of the VLSI layout design. If placement algorithm can only tackle this -4-

problem and can generate an optimum placement with uniform thermal distribution of the modules then the total cost can be reduced significantly.

Biography: Dr. Prasun Ghosal, BECS, Kolkatta Prasun Ghosal is currently working as a Assistant Professor in the Department of Information Technology in Bengal Engineering & Science University, Shibpur since June, 2006. Prior to this he was a Senior Research Fellow in the same University since December, 2005. He completed his Doctoral studies the supervision of Prof. H. Rahaman, BESU, India and Prof. P. S. Dasgupta, IIMC, India. He has bagged his M. Tech. (2005) as well as B. Tech. (2002) degree from Institute of Radio Physics & Electronics, University of Calcutta, India. He is also an Honours Graduate (major in Physics) from R. K. Mission Vidyamandira, Belur (1999) under University of Calcutta. His research interests include 3D integration in VLSI Physical Design, Design of Embedded Systems, and Network-on-Chip.He is the Principal Investigator of a project on "Development of Low Cost FPGA based Embedded Systems for NoC Application" funded by AICTE (All India Council for Technical Education). He has a number of research publications in some well reputed international conferences. IWECC Invited Talk Title: Sigma-delta Based ADC Design for Multi-standard Wireless Systems Abstract: This talk will cover some of the key concepts in multi-standard ADC design. Analog-todigital Converters (ADC) have an important impact on the overall performance of signal processing systems. This research is to explore efficient techniques for the design of sigma-delta ADC, specifically for multi-standard wireless transceivers. In particular, the aim is to develop novel models and algorithms to address this problem and to implement software tools which are able to assist the designer's decisions in the system-level exploration phase. To this end, this thesis presents a framework of techniques to design sigma-delta analog-to-digital converters. We present different re-configurable sigma-delta modulator architectures, techniques for coefficient optimization and a tool box.

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Biography: Dr. Babita R. Jose, Cochin University, India Babita R. Jose received Ph.D degree in Electronics and Communication Engineering from Cochin University, India in 2010 and Masters Degree in Digital Electronics from Karnataka University, India in 1999. She also holds a M.S degree in System on Chip designs from Royal Institute of Technology (KTH), Stockholm, Sweden. Currently, she is serving as a Assistant Professor in School of Engineering, Cochin University of Science and Technology. Her interests are focused on development of System on chip architectures, Multi-standard Wireless Transceivers, Low-power design of sigma delta modulators.

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