EXPT NO :7      INTRODUCTION  TO TMS320C5X  DSP 

                                           PROCESSOR
DATE:9.09.08

THE  TEXAS  INSTRUMENTS  TMS320C5X
The TMS320C5X DSPs are general purpose 16­bit,fixed­point DSPs. Depending 
on   the   device   version,TMS320C5X   parts   include   up   to   9.5K   words   of   on­
chipprogram/data RAM, up to 16K words of ROM, a standard serial port, a time­division 
multiplexed(TDM) serial port, and a 16­bit timer. The four variations of the TMS320C5X 
are TMS320C50 (9.5K words on­chip RAM), TMS320C51 (1.5K words on­chip RAM), 
TMS320C52 (1K word on­chip RAM), and TMS320C53 (3.5K words on­chip RAM).

TMS320C5X Supports . . . 

 On­Chip Memory
 Off­Chip Memory Access
 I/O Peripheral Interface
 Direct Memory Accessing
On­Chip Memory
1K ⋅ 16­bit on­chip total RAM.
This   memory   is   available   as   data   and   program   memory.   (Some   instructions   require 
multiple locations for storage, reducing the amount of on­chip RAM availability.)

Off­Chip Memory Access
Access to off­chip memory requires a minimum of two cycles on all external memory 
writes. Nominal memory access time is 12 ns using a TMS320C52 at 80 MHz. (To access 
RAM or peripherals requires asserting the RAM’s OE signal continuously and using the 
DSP’s R/W and STRB signals for memory selection. This technique continuously drives 
the bus leading to contention and power usage issues.)

I/O Peripheral Interface
64K ⋅ 16­bit I/O Space for peripheral interfacing.
Has dedicated control lines and DSP instructions for accessing I/O space directly.

Direct Memory Accessing
An  external DMA controller interface, but DSP  operation is suspended during DMA 
transfers. Block DMA transfers require DSP intervention.
EXPT.NO: 7a STUDY OF VARIOUS ADDRESSINGMODES
DATE: 9.09.08 OF DSP

AIM
To study the various addressing modes of C5X DSP processors.

ADDRESSING MODES
C5X processors can address 64K words of program memory and 96K of data
memory. C5X supports the following six addressing modes:
1.Direct addressing.
2.Memory - mapped register addressing.
3.Indirect addressing .
4.Immediate addressing.
5.Dedicated – register addressing.
6.Circular addressing.
The details of each of these addressing modes are considered next.

DIRECT ADDRESSING
The data memory used with C5X processors is split into 512 pages
each of 128 words long. The data memory page pointer (DP) in ST 0 holds the address of
the current data memory of C5X, only lower – order 7 bits of the address are specified in
the instruction. The upper 9 bits are taken from the DP.

MEMORY – MAPPED REGISTER ADDRESSING

The RAM area in page 0 is used for storing some of the registers,
interrupt vector addresses and so on. These locations can be accessed by specifying the
actual address or by the register name.(e.g., the AR0 can either be denoted by the actual
memory location (16h) used for storing its value or by the symbol AR0).Since these
memory locations can be interchangeably used with the register names, the registers
corresponding to page 0 are reffered to as memory – mapped registers (MMRS).
With memory – mapped register addressing, the MMRS can be
modified without affecting the current page pointer value. In addition, any scratch pad
RAM (DARAM B2) location or data page 0 can also be modified.The memory –mapped
register addressing mode operates like the direct addressing mode,except that the 9 MSBS
of the address are forced to 0 instead of being loaded with the contents of the DP. This
allows the memory – mapped registers of data page 0 to be modified directly without the
overhead of changing the DP or auxiliary register. The following instructions operate in
the memory – mapped register addressing mode. Using these instructions does not affect
the contents of DP:
LAMM – load accumulator with memory – mapped register
LMMR – load memory – mapped register
SAMM – store accumulator in memory – mapped register
SMMR – store memory – mapped register
INDIRECT ADDRESSING
The ARS AR0 – AR7 are used for accessing data,using indirect
addressing mode. In the indirect addressing mode, out of the eight ARs the one which is
used for currently accessing datas denoted by register ARP. The contents of ARP can be
temporarily stored in ARB register. The indirect addressing mode of C5X permits theAR
used for the addressing to be updated automatically either after or before the operand is
fetched. Hence a separate instruction is not required to update the AR. However, if
required, the contents of an AR can be incremented or decremented by any 8 – bit
constant using SBRK and ADRK instructions(e.g., SBRK #k, ADRK #k subtracts. Adds
the constant k from/to the AR pointed by ARP)
In the indirect addressing mode, the manner in which the memory
address is computed and the manner in which theAR is altered after the instruction
depends on the instruction. This is indicated to the assembler by the symbols #, *, *+, *-,
*0+, *0-, *BR0+, *BR0-. The symbol used to indicate the indirect addressing mode and
the action taken after executing the instruction are given as follows:
Various options in the indirect addressing mode of 5X

Symbol Value of AR pointed by ARP after

Instruction execution
* AR unaltered
*+ AR incremented by 1
*- AR decremented by 1
*0+ AR incremented by the content of INDX
*0- AR decrmented by the content of INDX
*BR0+ AR incremented by the content of INDX
with reverse carry propagation
*BR0- AR decremented by the content of INDX
with reverse carry propagation

IMMEDIATE ADDRESSING
The immediate addressing mode can be used to load either a 16 – bit
constant or a constant of length 13, 9 or 7. accordingly it is reffered to as long immediate
or short immediate addressing mode. This mode is indicated by the symbol #. For e.g.,
ADD # 56h adds 56h toACC. Similarly ADD # 4567h adds 4567h to ACC.

DEDICATED – REGISTER ADDRESSING

The dedicated – register addressing mode operates like the long
immediate addressing mode, expect that the address comes from one of two special
purpose memory – mapped registers in the CPU : the block move address register
(BMAR) and the dynamic bit manipulation register (DBMR). The advantage of this
addressing mode is that the address of the block of memory to be acted upon can be
changed during execution of the program.
CIRCULAR ADDRESSSING
Many algorithms such as convolution, correlation and finite impulse
response (FIR) filters can use circular buffers in memory to implement a sliding window,
which contains the most recent data to be processed. The C5X supports two concurrent
circular buffers operating via the ARS. The following five memory – mapped registers
control the circular buffer operation:
CBSR1—Circular buffer 1 start register
CBSR2—Circular buffer 2 start register
CBER1—Circular buffer 1end register
CBER2—Circular buffer 2 end register
CBCR—Circular buffer control register
The 8-bit CBCR enables and disables the circular buffer operation. To define circular
buffers, the start and end addresses are loaded into the corresponding buffer registers
first; next, a value between the start and end registers for the circular buffer is loaded into
an AR. The corresponding circular buffer enable bit in the CBCR should be set.

RESULT
Thus the various addressing modes of C5X DSP processors were studied.
EXPT NO: 8 ADDITION OF TWO NUMBERS
DATE:9.09.08

AIM

To write a program addition of two numbers using TMS2320C5X

PROGRAM DESCRIPTION

.MMREGS,TEXT-are the assembly language syntax

LDP-data pointer pointing to the location 8000H at page 100H
LACC-load the accumulator with the data from the location 8000H
ADD- add data memory value with left shift to accumulator
SACL-store accumulator with left shift in data memory location
PROGRAM

.MMREGS
.TEXT

LDP #100H
LACC #0H
ADD #1H
SACL #2H
H: B H

OUTPUT

DATA DATA
MEMORY
ADDRESS
8000 1

RESULT
 Thus addition of two numbers is done using TMS2320C5X and the output
is verified
EXPT NO :9               TWO`S COMPLEMENT OF A NUMBER
DATE:16.09.08

AIM

To write a program two’s complement of a number using TMS2320C5X

PROGRAM DESCRIPTION
LDP- data pointer pointing to the location 8000H at page 100H
LACL-load the data memory value to the accumulator
CMPL-one`s complement of the accumulator
ADD-add data memory value with left shift to accumulator
SACL- store accumulator with left shift in data memory location
PROGRAM
.MMREGS
.TEXT
LDP #100H
LACL #5H
CMPL
ADD #1H
SACL 0000,0
H: B H

OUTPUT

DATA DATA
MEMORY
ADDRESS
8000 11
RESULT
Thus two’s complement of a number is done using TMS2320C5X and the
output is verified

EXPT NO:10 TO SOLVE A EQUATION

DATE:23.09.08

AIM
To write a program to calculate the value of the function Y=A*X1+B*X2+C*X3

PROGRAM DESCRIPTION
Load the constant A in T register. Multiply T register with X1.load T register with
constant B and add P register to the accumulator These two steps can be done by the
single instruction LTA. Multiply T register with X2.load T register with the constant C
and add P register to accumulator. We can use LTA instruction here .Multiply T register
with X3.Add the product to the accumulator .

PROGRAM
.MMREGS
.TEXT

LDP #100H
LACL #0H
LT 0000
MPY 0003H
LTA 0001H
MPY 0004H
LTA 0002H
MPY 0005H
APAC
SACL 0006,0
H: B H
INPUT
DATA DATA
MEMORY
ADDRESS
8000 1
8001 2
8002 3
8003 4
8004 5
8005 6
OUTPUT:

DATA DATA
MEMORY
ADDRESS
8006 20
RESULT
Thus two’s complement of a number is done using TMS2320C5X and the
output is verified
EXPT NO:11 LINEAR CONVOLUTION
DATE:30.09.08

AIM
To perform linear convolution using TMS2320C5X processor

PROGRAM DESCRIPTION

LAR AR1-load data memory value to ARx

LACC- load the accumulator with the data from the location 8000H
LDP- data pointer pointing to the location 8000H at page 100H
MAR-modify AR
RPT-repeat next instruction The contents of the dma,an 8 bit constant are loaded into the
repeat count register
TBLW- The contents of the pma are transferred to the dma.

PROGRAM

.MEMREGS

.TEXT
START :LDP #02H
LAR AR1,#8100H
lar ar0,#8200H
LAR AR3,#8300H
LAR AR4,#0007H
LAR AR0,#8203H
LACC #0C100H
MAR *,AR0
RPT #3H
TBLW *-

INPUT
X(n)

DATA DATA
MEMORY
ADDRESS
8000 1
 8001 3
8002 1
8003 3
INPUT
H(n)

DATA DATA
MEMORY
ADDRESS
8200 0
8201 1
8202 2
8203 1

OUTPUT

Y(n)
DATA DATA
MEMORY
ADDRESS
8300 1
8301 5
8302 8
8303 8
8304 7
8305 3
8306 0
RESULT
Thus linear convolution is performed using TMS2320C5X and the output
is verified