Midrange 8-bit PIC Microcontrollers

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 PIC stands for Peripheral Interface Controller given by Microchip Technology . These devices have been very successful in 8bit microcontrollers. The main reason is that Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the microcontroller to suit customers' requirements.
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Popularity of the 8-bit PIC microcontrollers is due to the following factors Speed: Harvard Architecture, RISC architecture. 1 machine cycle=4 clock cycles PIC executes most of the instructions at 0.2s at max. clock.
CPU architecture of PIC microcontroller

Data memory is 8-bit wide whereas program memory is 12, 14 or 16 bit wide.
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 Instruction set simplicity: The instruction set consists of just 35 instructions (as opposed to 111 instructions for 8051). Power-on-reset and brown-out reset. Brown-out-reset means when the power supply goes below a specified voltage (say 4V), it causes PIC to reset; hence malfunction is avoided. A watch dog timer (user programmable) resets the processor if the software/program ever malfunctions and deviates from its normal operation. Programmable timers and on-chip ADC. Up to 12 independent interrupt sources.
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Features

Features

PIC microcontroller has four optional clock sources.

External RC Internal RC Crystal External Clock

Power saving SLEEP mode EPROM/OTP/ROM/Flash memory option I/O port expansion capability. Free assembler and simulator support from Microchip at http://www.microchip.com/
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 Broad portfolio of more than 250 8-bit PIC microcontrollers. The only supplier to bring USB, LCD, CAN, Ethernet, and other peripherals to the 8-bit market. Where might you use a PIC? controller for appliances controller for LCDs, other devices

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Architectures of various 8-bit PIC microcontrollers Low - end PIC Architectures : - The microcontroller consisted of a simple processor executing 12-bit wide instructions with basic I/O functions. - They have limited program memory and are meant for applications requiring simple interface functions and small program & data memories. - Some of the low-end device numbers are 12C5XX 16C5X 16C505

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 Mid range PIC Architectures: -Mid range PIC architectures are built by upgrading lowend architectures with more number of peripherals, more number of registers and more data/program memory. -14 bit wide instructions -Some of the mid-range devices are 16C6X 16C7X 16F87X Program memory type is indicated by an alphabet. C = EPROM F = Flash CR = ROM

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High end architectures Otherwise known as the 18F series, this architecture overcomes some of the limitations of the midrange devices, providing for more memory (up to 128k program memory and almost 4k data memory) 16 bit wide instructions Advanced peripherals, including USB, Ethernet and CAN (controller area network)connectivity.

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8-bit PIC controller: Block diagram

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Data memory (Register Files):

Data Memory is also known as Register File. Data memory is partitioned 4 banks(bank=128 bytes) Register File consists of two portions General purpose register file (same as RAM). Special purpose register file (similar to SFR in 8051).
00H Special purpose register (32 bytes) 80H Special purpose register (32 bytes)

1FH 20H

9FH A0H

RAM 7FH Bank 0 (128 bytes) FFH

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RAM

Bank 1 (128 bytes)

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 Switching between these banks requires the RP0 and RP1 bits in the STATUS register to be configured for the desired bank when using direct addressing. The IRP bit in the STATUS register is used for indirect addressing.

Direct and Indirect Addressing of Banks MGR,RJ

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Register file(data RAM) of some midrange MCU

Some of the registers are addressable from either memory banks. E.g. STATUS register Not all locations may be implemented. Unimplemented locations will read as 0. The special purpose register file consists of input/output ports and control registers.

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program memory
Mid range MCU has 13 bits of program memory address. Hence it can address up to 8k of program memory. The program counter is 13-bit. While addressing 2k of program memory, only 11- bits are required. Hence two most significant bits of the program counter are ignored. Similarly, while addressing 4k of memory, 12 bits are required. Hence the MSB of the program counter is ignored.
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Program memory

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 On reset, the program counter is cleared and the program starts at 00H. Here a 'goto' instruction is required that takes the processor to the mainline program. When a peripheral interrupt, that is enabled, is received, the processor goes to 004H. A suitable branching to the interrupt service routine (ISR) is written at 004H. For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound.

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PIC Microcontroller Clock Mid range PIC MCU can operate up to 20MHz. One instructions cycle (Tcy) consists of four clock cycles. The Q cycle time is the same as the device oscillator cycle time (Tosc).

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Central Processing Unit ALU PICmicro MCUs contain an 8-bit ALU and an 8-bit working (W) register. The ALU is a general purpose arithmetic and logical unit. Perform 8-bit operations. One of the operand is W register and other is either a file register or immediate data. Depending upon instructions executed ALU can affect the flags.

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W register The working register is 8-bit wide. Similar to accumulator of 8051. It contains one of the source operands during the execution of instruction and may serve as the destination for the result of the operation. To move values from one register to another register, the value must pass through the W register. It is not an addressable register.

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Operation of the ALU and W Register

E.g. ADDWF FSR, 0

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STATUS register

IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

C: Carry Flag Z:Zero flag DC:Digit Carry (Auxiliary carry)

RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

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TO(Time out bit) & PD(power down bit) These two bits are used along with the SLEEP mode. To set a bit of STATUS register, bsf STATUS,05 (RP0=1) To clear a bit, bcf STATUS,05 (RP0=0) b stands for bit f stands for file register

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STATUS register of some midrange MCUs

03h-Bank 0 address 83h-Bank 1 address

RP0: Register Bank select RP0 = 1 Bank 1 RP0 = 0 Bank 0

C: Carry Flag Z:Zero flag DC:Digit Carry (Auxiliary carry)

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Program Counter
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register.
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PCLATH(Program Counter Latch) register

PCLATH is a 8-bit register which can be used to decide the upper 5bits of the program counter. PCLATH is not the upper 5bits of the program counter. PCLATH can be read from or written to without affecting the program counter. The upper 3bits of PCLATH remain zero and they serve no purpose. When PCL is written to, the lower 5bits of PCLATH are automatically loaded to the upper 5bits of the program counter,

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Loading PC

These are readable and writable register(PCL,PCLATCH).

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FSR(File selection register) address = 04H, 84H FSR is an 8-bit register used as data memory address pointer. This is used in indirect addressing mode. INDF Register (INDirect through FSR, address = 00H, 80H) INDF is not a physical register. Accessing INDF actually access the location pointed to by FSR in indirect addressing mode.

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Example showing use of INDF register to clear RAM location 20H movlw 0x20h ;move RAM location to W movwf FSR ;move W to FSR clrf INDF ; clear RAM location

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Stack
Mid-Range MCU devices have an 8-level x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed.

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PUSH operation

POP operation

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Stack overwriting
After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

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 There are no status bits to indicate stack overflow or stack underflow conditions. There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions or the vectoring to an interrupt address.

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PIC oscillator Connections

PIC microcontroller has four optional clock sources.
External RC Internal RC Crystal External Clock

These oscillator options are made available to allow a single device type the flexibility to fit applications with different oscillator requirements.

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External RC oscillator
The values of resistor & capacitor are specified in data sheets for a given oscillator frequency. For R values below 2.2 k, oscillator operation may become unstable, or stop completely. For very high R values (e.g. 1 M ), the oscillator becomes sensitive to noise, humidity , etc.. Recommended value of R is between 3 k and 100 k
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 The capacitor value is selected above 20 pF for noise and stability reasons. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic. The clock on OSC2 pin can be stopped by changing configuration bits. E.g. For 4MHz clock: R=4.7K & C=33PF
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Internal RC Oscillator
The internal RC oscillator (not on all devices) provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25C. The system clock may show variation over voltage and temperature. The calibration value that Microchip programs into the device will trim the internal oscillator to remove process variation from the oscillator frequency.
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 The value in the OSCCAL register is used to fine tune the frequency of the internal RC oscillator. The OSCCAL is special function register. The internal RC oscillator can be configured to provide a clock out signal on the OSC2/CLKOUT pin

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OSCCAL Register

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CAL3:CAL0 Trimming of Internal RC Oscillator Frequency Offset

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CALFST Positive Internal RC Oscillator Frequency Offset

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CALSLW Negative Internal RC Oscillator Frequency Offset

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Crystal oscillator
Three modes of operation -LP(Low power clocking) -XT(Standard mode) -HS(high speed) The main difference is different frequency ranges & power consumption. The user can program up to three device configuration bits (FOSC2, FOSC1 and FOSC0) to select one of these modes.
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Crystal modes
LP
Description Low

XT

HS
High frequency application. Oscillator circuits mode consumes the most current of the three crystal modes.

Standard power/frequency crystal/resonator applications. frequency. Oscillator circuits Oscillator circuits mode consumes the mode consumes the least current of the middle current of the three crystal modes. three crystal modes.

Frequency

5- 200KHz

100kHz- 4MHz

4-20 MHz

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Calibration Information
Some devices have calibration information stored in their program memory. This information is programmed by Microchip when the device is under final test. The calibration information is typically at the end of program memory. E.g. Calibration value for internal RC oscillator clock frequency, clock source selection bits (FOSC2, FOSC1 and FOSC0)

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External Clock Input

Device may be driven from an external clock, be sure to set the oscillator mode to one of the crystal modes (LP, XT, or HS).

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Instruction flow/Pipelining
Applicable for some mid range PIC MCUs. E.g. PIC16C71X An Instruction Cycle consists of four Q cycles (Q1,Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle.

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Instruction pipeline flow

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I/O Ports
Devices may have up to 7 ports. To add flexibility and functionality to a device, some pins are multiplexed with an alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.
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Ports of 16C74A

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 For most ports, the I/O pins direction (input or output) is controlled by the data direction register, called the TRIS register. TRIS<x> controls the direction of PORT<x>. A 1 in the TRIS bit corresponds to that pin being an input, while a 0 corresponds to that pin being an output. The port pins are designated by the alphabet R, followed by the respective port (viz. A, B, C, D or E) and the pin number. For example, Port-A pins are named as RA0, RA1, etc.

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Port-A (Structure of port A pin) Port-A pins RA0-RA3 and RA5 are similar. These pins function (alternate function) as analog inputs to the analog-to-digital converter.

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 TRISA register decides whether the port-pin is configured as an input or as an output (digital) pin. Setting a TRISA register bit puts the corresponding output driver in high impedance mode. In this mode, the pin can be used as a digital or analog input. Clearing a bit in the TRISA register puts the contents of the data latch on the selected pins, i.e., the pin functions as a digital output. Pins RA0-RA3 and RA5 have current sourcing capability of 25mA.

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 The alternate function of RA4 pin is Timer-0 clock input (T0CKI). RA4 pin is an open drain pin and hence requires external pull-up when configured as I/O pin. It is shown in the following figure.

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 Configuration of Port-A pins Example : Set RA0-RA3 as outputs and RA4 - RA5 as
inputs. bcf STATUS, RP0 ; clrf PORTA ; bsf STATUS, RP0 ; movlw 30H ; movwf TRISA ; Select Bank-0 Clears the data latch Select Bank-1 W 30H ( data direction ) Set RA0-RA3 as outputs, RA4-RA5 as inputs

TRISA<7:6> always read as '0'

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Port B
Port-B is an 8-bit bidirectional I/O port. The data direction in Port-B is controlled by TRISB register. Setting a bit in TRISB register puts the corresponding output in high impedance input mode. When a bit in TRISB is made zero, the corresponding pin in Port-B outputs the content of the latch (output mode).
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Each port pin has a weak internal pull-up that can be enabled by clearing bit of OPTION register (bit-7). Internal pull-up is used so that we can directly drive a device from the pins.

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 Configuration of Port-B pins Example : Set RB0-RB3 as outputs, RB4-RB6 as inputs, RB7 as output. bcf STATUS, RP0 clrf PORTB bsf STATUS, RP0 movlw 70H movwf TRISB The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

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Port B interrupt on change feature

Four of PORTBs pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded) The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB.
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 The mismatch set RB Port Change Interrupt with flag bit RBIF (INTCON<0>) & generate interrupt. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) Any read or write of PORTB. b) Clear flag bit RBIF. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on keydepression
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Port C
PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register Configuration of port c CLRF STATUS, RP0 ; Bank0 CLRF PORTC ; Initialize PORTC by clearing output data latches BSF STATUS, RP0 ; Select Bank1 MOVLW 0xCF ; Value used to initialize data direction MOVWF TRISC ; PORTC<3:0> = inputs, PORTC<5:4> = outputs, PORTC<7:6> = inputs

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Timer 0
The Timer 0 module has the following features: 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Clock source selectable to be external or internal Interrupt on overflow from FFh to 00h Edge select for external clock

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Timer0 Block diagram

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 The maximum external clocking source for timer 0 is limited to 50 MHz. Fosc/4 & external clocking frequency is divided by 2 for pre scale value of 0. E.g. Fosc=1 MHz pre scale=0 Timer 0 clock=(Fosc/4)*(1/2)=125 KHz Intially, TMR0=00h after 1 ms TMR0=125.

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Timer 0 _delay={[Timer 0_count] x prescale value x (4/Fosc)} Timer 0_Preload count=256-[Timer 0 delay x Fosc]/ [prescale value x4]

Any write to the TMR0 register will cause a 2 instruction cycle (2TCY) inhibit. That is, after theTMR0 register has been written with the new value, TMR0 will not be incremented until the third instruction cycle later.

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Timer0 Timing: Internal Clock/Prescale 1:2

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TMR0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awake the processor from SLEEP since the timer is shut-off during SLEEP.
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Timer 1
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The Timer1 Interrupt, if enabled, is generated on overflow which is latched in the TMR1IF interrupt flag bit. This interrupt can be enabled/disabled by setting/clearing the TMR1IE interrupt enable bit.

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 The operating and control modes of Timer1 are determined by the special purpose register T1CON.

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Operation of timer 1

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Timer1 can operate in one of three modes: As a synchronous timer As a synchronous counter As an asynchronous counter The operating mode is determined by clock select bit, TMR1CS (T1CON<1>), and the synchronization bit, T1SYN

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Timer1 Oscillator A crystal oscillator circuit is built in between pins T1OS1 and T1OS0. It is enabled by setting the T1OSCEN control bit (T1CON<3>). The oscillator is a low power oscillator, rated up to 200 kHz operation. It will continue to run during SLEEP

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Timer 2
Timer2 is an 8-bit timer with a pre scalar, a post scalar, and a period register. The input clock has a pre-scalar option of 1:1, 1:4 or 1:16 which is selected by bit 0 and bit 1 of T2CON register respectively. The Timer 2 module has an 8bit period register (PR2). Timer-2 increments from 00H until it is equal to PR2 and then reset to 00H on the next clock cycle.
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 PR2 is a readable and writable register. The output of TMR2 goes through a 4bit post-scalar (1:1, 1:2, to 1:16) to generate a TMR2 interrupt by setting TMR2IF. The post scalar counts the number of times that the TMR2 register matched the PR2 register.

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Timer 2 control register(T2CON)

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Watch Dog Timer(WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components.

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 The WDT will run, even If the clock on the OSC1 and OSC2 pins has been stopped, for example, by execution of a SLEEP instruction. The Watchdog Timer (WDT) is enabled/disabled by a device configuration bit. The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 WDT postscaler.

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WDT Operation
During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to . wake-up and continue with normal operation, this is known as a WDT wake-up.

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 The WDT has a nominal time-out period of 18 ms, (with no postscaler). The time-out period varies with temperature, VDD and process variations from part to part (see DC specs). If longer time-outs are desired, a postscaler with a division ratio of up to 1:128 can be assigned to the WDT, under software control, by writing to the OPTION_REG register. The CLRWDT and SLEEP instructions clear the WDT and the postscaler prevent it from timing out and generating a device RESET.
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WDT Period

Capture/Compare/PWM(CCP) module
Each CCP module has 3 registers. -CCP control register(CCPxCON) -CCP High byte(CCPRxH) -CCP low byte(CCPRxL) Multiple CCP modules may exist on a single device Each CCP module contains a 16-bit register(CCPRxH & CCPRxL)) which can operate as a 16-bit capture register, as a 16-bit compare register or as a 10-bit PWM.

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CCP1 module
CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1 Module. The following table shows the timer resource for the CCP modes. CCP mode Capture Compare PWM Timer used Timer 1 Timer 2 Timer 2
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CCP1CON Register

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Capture Mode : Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L register pair in response to an event occurring on RC2/CCP1 pin. An event on RC2/CCP1 pin is defined as follows: -Every falling edge -Every rising edge. -Every 4th rising edge. -Every 16th rising edge.

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Capture mode operation

Required condition for capture mode: RC2/CCP1 pin should be configured as an input by setting TRISC (bit 2). Timer 1 should be operated from the internal clock (fosc/4), i.e., timer mode or in synchronized counter mode.

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Compare mode
In compare mode, the 16-bit CCPR1 register value is compared against TMR1 register pair (TMR1H and TMR1L) value. When a match occurs, the RC2/CCP1 pin is driven high or driven low or remains unchanged as decided by CCP1CON<3:0> bits.

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 Required conditions for compare mode -RC2/CCP1 pin must be configured as an output by clearing TRISC<2> bit. -Timer-1 should be operated in timer mode (i.e., internal clock source of fosc/4) or in synchronized counter mode. When generate Software Interrupt mode is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).

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ADC module
PIC 16C74A has an inbuilt ADC with the following features 8-bit conversion 8 analog input channels An analog multiplexer A sample and hold circuit for signal on the selected input channel Alternative clock sources for carrying out conversion Adjustable sampling rate Choice of an internal or external reference voltage Interrupt to microcontroller on end of conversion

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 Port A and Port E pins are used for analog inputs/reference voltage for ADC. In A/D conversion, the input analog voltage is digitized and an equivalent digital output is generated as shown in the figure.

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 Port-A pins (Alternate functions) RA0/AN0 - can be used as analog input-0 RA1/AN1 - can be used as analog input-1 RA2/AN2 - can be used as analog input-2 RA3/AN3/Vref - can be used as analog input-3 or analog reference voltage RA4/TOCKI - clock input to Timer-0 RA5/ /AN4 - can be used for analog input 4 Port-E pins (Alternate functions) RE0/ AN5 - can be used as analog input-5 RE1/ AN6 - can be used as analog input-6 RE2/ AN7 - can be used as analog input-7

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 PIC microcontroller has internal sample and hold circuit. The input signal should be stable across the capacitor before the conversion is initiated .

After waiting for the sampling time, a conversion can be initiated. The ADC Circuit will open the sampling switch and carry out the conversion of the input voltage as it was at the moment of opening of the switch. Upon completion of the conversion, the sampling switch is again closed and VHold once again tracks VSource.

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Using ADC module

Registers ADCON1, TRISA, and TRISE must be initialized to select the reference voltage and input channels. The first step selects the ADC clock from among the four choices (f osc/2, fosc/8, fosc/32, and RC). The constraint for selecting clock frequency is that the ADC clock period must be 1.6 micro seconds or greater. The A/D module has 3registers. These registers are:-A/D result register (ADRES) -A/D control register 0 (ADCON 0) -A/D control register 1 (ADCON 1)

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Schematic diagram of A/D convertor analog inputs and reference voltage

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Steps for A/D conversion

Configure A/D module
Configure analog inputs/voltage reference and digital I/O (ADCON1) Select A/D Channel (ADCON0) Select A/D Conversion Clock (ADCON0) Turn on A/D Module (ADCON0)

Configure A/D Interrupt (Optional)

Clear ADIF bit in PIR1 register Set ADIE bit in PIE1 register Set GIE bit

Wait for required acquisition time(conversion time) Start Conversion - set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either polling GO/DONE bit or by waiting for the A/D interrupt Read A/D result registers (ADRES). Clear ADIF if required.

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Example Program :A/D conversion with interrupt org 000H goto Mainline org 020H Mainline: bsf STATUS, RP0 ; Select Bank 1 clrf ADCON 1 ; Configure A/D inputs bsf PIE1, ADIE ; Enable A/D interrupt bcf STATUS, RP0 ; Select Bank 0 movlw 081H ; Select fosc/32, channel 0, A/D on movwf ADCON0 bcf PIR1, ADIF bsf INTCON, PEIE ; Enable peripheral and global interrupt bits bsf INTCON, GIE ; interrupt bits ; Ensure that the required sampling time of the selected input channel has been elapsed. ; Then conversion may be started. ; bsf ADCON0, GO ; Start A/D conversion. ; ADIF bit will be set and GO/ DONE ; bit is cleared upon completion of A/D conversion. ;Interrupt Service Routine Org 004H Movf ADRES, W ; Result of A/D conversion in W retfie ;return ISR

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Interrupts
PIC micro MCUs can have many sources of interrupt. These sources generally include one interrupt source for each peripheral module, though some modules may generate multiple interrupts. The Interrupt Control Register, INTCON, records individual flag bits for core interrupt requests. It also has various individual enable bits and the global interrupt enable bit. Depending on the number of peripheral interrupt sources, there may be multiple Peripheral Interrupt Enable registers (PIE1, PIE2). These registers contain the individual enable bits for the Peripheral interrupts. Depending on the number of peripheral interrupt sources, there may be multiple Peripheral Interrupt Flag registers (PIR1, PIR2). These registers contain the individual flag bits for the peripheral interrupts.

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Interrupt Logic in PIC 16C74A

PIC 16C74A microcontroller has one vectored interrupt location (i.e., 0004H) but has 12 interrupt sources. There is no interrupt priority. Only one interrupt is served at a time. However interrupts can be masked. The interrupt logic is shown below :

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 During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS register. This has to be implemented in software. When interrupt occurs GIE bit of INTCON register is cleared to avoid any further interrupts. A interrupt can wake up processor from SLEEP mode.

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PIC Reset actions

PIC reset action take place due to different mechanisms. -Power-on Reset (POR) - MCLR reset during normal operation -MCLR reset during SLEEP -Watch Dog Timer reset during normal operation -Brown-out Reset (BOR) - Parity Error Reset (PER)

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Power On Reset
A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD as shown in figure below. A minimum rise time for VDD is required The reset function will set the program counter to the starting address of the program.(E.g.PIC 16C71 reset vector is 000h where as for PIC 16C57 it is 7FFh) Power up timer operating on the internal RC oscillator generates 72 ms delay on power up for VDD to rise to required level.(can be shut down) The oscillator start up timer generates additional delay of 1024 cycles for oscillator to stabilize.

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Brown-out-Reset
On-chip Brown-out Reset circuitry places the device into reset when the device voltage falls below a trip point (BVDD-typically 4V). The BODEN configuration bit can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry.(Configuration bit is in program memory. It is factory setting). Power up timer operating on the internal RC oscillator generates 72 ms delay on power up for VDD to rise to required level.(cant be shut down) The oscillator start up timer generates additional delay of 1024 cycles for oscillator to stabilize.

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Brown-out Situations

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PCON register
This register contains flag bit(s), that together with the TO and PD bits of status register, allows the user to differentiate between the device resets.

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Status register

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Instruction set
Every instruction fits in a single 14-bit word. In addition, every instruction also executes in a single cycle, unless it changes the content of the Program Counter. These features are due to the fact that PIC micro controller has been designed on the principles of RISC (Reduced Instruction Set Computer) architecture(pipe lining) Guidelines from Microchip Technology For writing assembly language program Microchip Technology has suggested the following guidelines. Write instruction mnemonics in lower case. (e.g., movwf) Write the special register names, RAM variable names and bit names in upper case. (e.g., PCL, RP0, etc.) Write instructions and subroutine labels in mixed case. (e.g., Mainline, LoopTime)

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Instruction types
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction.(SFRs & RAM locations) The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction.

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 For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located.

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 The literal instructions require an operand having a known value (e.g., 0AH) or a label that represents a known value.
E.g. NUM equ 0AH ; Assigns 0AH to the label NUM ( a constant ) movlw NUM ; will move 0AH to the W register.

'k' represents an eight or eleven bit constant or literal value.

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