Contents

Contents..................................................................................................................... 2 How to interface customize IP to micro blaze using AXI protocol????.........................6 Compiling a Test Application Using SDK.....................................................................9 Creating a Custom AXI IP Using the Wizard..............................................................12 Customizing the New Peripheral...............................................................................16 Adding the Custom Peripheral to the System...........................................................18 Test Customize IP ....................................................................................................24 Setting up the Simulation Environment....................................................................25 Adding a Test Bench File..........................................................................................26

Advanced eXtensible Interface

AXI is part of ARM AMBA, a family of micro controller buses first introduced in 1996. The first version of AXI was first included in AMBA 3.0, released in 2003. AMBA 4.0, released in 2010, includes the second version of AXI, AXI4.

There are three types of AXI4 interfaces: AXI4for high-performance memory-mapped requirements. AXI4-Litefor simple, low-throughput memory-mapped communication (for example, to and from control and status registers). AXI4-Streamfor high-speed streaming data.

Xilinx introduced these interfaces in the ISE Design Suite, release 12.3. Below Fig.1 is a block diagram of the hardware platform of interconnection of microblaze and IP using AXI protocol.

Fig.1 hardware platform of interconnection of microblaze and IP using AXI protocol AXI4 Benefits AXI4 provides improvements and enhancements to the Xilinx product offering across the board, providing benefits to Productivity, Flexibility, and Availability.

Productivityby standardizing on the AXI interface, developers need to learn only a single protocol for IP. FlexibilityProviding the right protocol for the application: AXI4 is for memory mapped interfaces and allows burst of up to 256 data transfer cycles with just a single address phase.

 AXI4-Lite is a light-weight, single transaction memory mapped interface. It has a small logic footprint and is a simple interface to work with both in design and usage. AXI4-Stream removes the requirement for an address phase altogether and allows unlimited data burst size. AXI4-Stream interfaces and transfers do not have address phases and are therefore not considered to be memory-mapped.

Availabilityby moving to an industry-standard, you have access not only to the Xilinx IP catalog, but also to a worldwide community of ARM Partners. Many IP providers support the AXI protocol. A robust collection of third-party AXI tool vendors is available that provide a variety of verification, system development, and performance characterization tools. As you begin developing higher performance AXI-based systems, the availability of these tools is essential.

How AXI Works This section provides a brief overview of how the AXI interface works. The Xilinx AXI Interconnect IP contains AXI-compliant master and slave interfaces, and can be used to route transactions between one or more AXI masters and slaves. Both AXI4 and AXI4-Lite interfaces consist of five different channels: Read Address Channel Write Address Channel Read Data Channel Write Data Channel Write Response Channel Data can move in both directions between the masters and slave simultaneously, and data transfer sizes can vary. The limit in AXI4 is a burst transaction of up to 256 data transfers. AXI4-Lite allows only 1 data transfer per transaction. Fig 2 shows how an AXI4 Read transaction uses the Read address and Read data channels. Fig.3 shows how a Write transaction uses the Write address, Write data, and Write response channels.

Fig.2 Channel Architecture of Reads

Fig.3 Channel Architecture of Writes As shown in the preceding figures, AXI4 provides separate data and address connections for Reads and Writes, which allows simultaneous, bidirectional data transfer. AXI4 requires a single address and then bursts up to 256 words of data. The AXI4 protocol describes a variety of options that allow AXI4-compliant systems to achieve very high data throughput. Some of these features, in addition to bursting, are: data upsizing and downsizing, multiple outstanding addresses, and out-of-order transaction processing. At a hardware level, AXI4 allows a different

clock for each AXI master-slave pair. In addition, the AXI protocol allows the insertion of register slices (often called pipeline stages) to aid in timing closure. AXI4-Lite is similar to AXI4 with some exceptions, the most notable of which is that bursting is not supported. The AXI4-Stream protocol defines a single channel for transmission of streaming data. The AXI4-Stream channel is modeled after the Write Data channel of the AXI4. Unlike AXI4, AXI4-Stream interfaces can burst an unlimited amount of data. Unlike AXI4, AXI4-Stream transfers cannot be reordered.

How to interface customize IP to micro blaze using AXI protocol????

1. Start Xilinx ISE Project Navigator

Start > Programs > Xilinx ISE Design Suite 13.2 > ISE Design Tools > Project Navigator 2. Create a new project File > New Project

Set the Project Location and write project name. Click next.
3. Select Spartan6, XC6SLX9, CSG324, -3. For this tutorial, pick VHDL as the Preferred

Language. Click Next.

4. Click Finish.
5. Go to Project > New Source then select Embedded Processor. Type system for the File

name. Click Next. Click Finish.

6. A message will appear asking if you want to create a Base System using the BSB wizard, click Yes.

7. Select the AXI system (might already be selected) then click OK.

8. In the BSB window click Next to create a new design

9. In configuration window select Processor frequency 100MHz, Local memory size 16KB. Add peripheral as per your requirement. (click on Add Device to add new peripheral) Click Finish.

10. To start a software project in SDK, the hardware design information needs to be exported. Go to Project > Export Hardware Design to SDK Select Export Only.

11. Close XPS when finished. 12. Return to Project Navigator and Go to Project > Add Copy of Source to add the FPGA constraints to the project.

13. Select system.ucf in the system\data directory. Click OK. 14. Select system in the hierarchy window. 15. Double-click on Generate Top HDL Source in the Processes window.

Compiling a Test Application Using SDK

Xilinx SDK is an Eclipse based software development environment to create and debug software applications. It use for testing peripheral.

16. Start Xilinx SDK. Start > Programs >Xilinx ISE Design Suite 13.2 > EDK > Xilinx

Software Development Kit.

17. Create a Workspace named WorkSpace in the mb_adder directory. Click OK.

18. Close the Welcome window. 19. Go to File > New > Xilinx C Project to create a new C project. 20. Click on Specify 21. Click on Browse in the Target Hardware Specification section. Browse to the D:\mb_adder\mb_adder\system\SDK\SDK_Export\hw\system.xml. Click Finish. 22. Select the Peripheral Tests application from the project templates then click Next.

23. Change the Board Support Package project name to Standalone_BSP. 24. Click Finish.

25. The peripheral_tests_0 project contains C source files to test each peripheral. Expand the

project src folder to view the sources. The project is compiled automatically after being created. 26. Double click on the testperiph.c file to view the main application.

27. The system contains internal BRAM memory as well as external DDR memory. We can select where the code will be physically located through a linker script. Right-click on the peripheral_tests_0 project and select Generate Linker Script. 28. Use the drop-down list to select the internal BRAM memory, microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl, for all the code sections.

29. Click Generate then Yes. Then close SDK.

Creating a Custom AXI IP Using the Wizard

30. Start Project Navigator and open the mb_adder project.

31. Double-click on the system.xmp module to open the system in XPS.

32. Go to Hardware > Create or Import Peripheral Click on Next. 33. Make sure that Create templates for a new peripheral is selected then click Next.

34. Select To an XPS project. Click on Next.

35. Enter the name for the new peripheral, adder, and then click Next.

36. Select AXI4-Lite: Simpler, non-burst control register style interface. Click Next.

37. We will be using software registers to control the peripheral. Select User logic software register. Unselect all other choices. Click Next.

38. We will use one 32-bit wide register to communicate with the adder hardware. Though

only eight (4bit+4bit) bits will be used as input of adder.Select 1 for the number of registers. Click on Next.

39. The IP Interconnect (IPIC) uses a set of signals between the user logic and the AXI bus. We will use the default signals already selected. Click on Next.

40. Bus Functional Models can be generated to accelerate the IP verification.

41. Uncheck all, click next

42. Click on Finish to create the peripheral.

Customizing the New Peripheral

The new peripheral was created inside the system project directory, in the pcores directory. We will first add VHDL code for the adder functionality then modify the files needed to integrate the peripheral within XPS. Our adder peripheral will have a single output port for the sum output. Sum of the two 4 bit number will be coming through the software mapped register created in the previously.
43. Open the VHDL folder, File > Open, \pcores\ adder_v1_00_a \hdl\vhdl\.

The adder.vhd file is the top level VHDL entity for the new IP. It contains two files, AXI_LITE_IPIF and User Logic. The AXI_LITE_IPIF creates a proxy between the user logic and the AXI interface based on the settings we selected in the Create Templates for a New Peripheral Wizard. The User Logic file is where we will create our custom logic. As noted above, this IP will read two data from the AXI interface, and then add those numbers. That adder output will be given to external port. See in fig.4 is block diagram of total system.

Fig. 4 Block diagram of system

44. This new IP Core will only have one output, ADD_Out. Add the external port for the

adder output to the ports declaration: port ( -- ADD USER PORTS BELOW THIS LINE -----------------ADD_Out : out std_logic_vector (3 downto 0); -- ADD USER PORTS ABOVE THIS LINE -----------------45. Add the ports to the USER_LOGIC_I component instantiation: port map ( -- MAP USER PORTS BELOW THIS LINE -----------------ADD_Out => ADD_Out, -- MAP USER PORTS ABOVE THIS LINE -----------------46. Save and close the file.
47. File

> Open, \pcores\ adder_v1_00_a \hdl\vhdl\. Open user_logic.vhd. The user_logic.vhd file was created for users to place their custom code. The code to access the 32-bit AXI-interface register was created by the wizard.

48. Add the ports declaration port ( -- ADD USER PORTS BELOW THIS LINE ------------------

ADD_Out : out std_logic_vector (3 downto 0); -- ADD USER PORTS ABOVE THIS LINE -----------------49. Add user signals declaration --USER signal declarations added here, as needed for user logic signal add_1 : std_logic_vector (3 downto 0); signal add_2 : std_logic_vector (3 downto 0); 50. Add the user HDL code after the begin statement. The user_logic template already contains code to read and write the register. begin --USER logic implementation added here add_1 <= slv_reg0(3 downto 0); add_2 <= slv_reg0(7 downto 4); adder : process (Bus2IP_Clk) begin ADD_Out <= add_1 +add_2; end process adder; 51. Save and Close the file.
52. The new external port needs to be added to the definition file for the peripheral in order

to be used in XPS. Open the adder_v1_00_a \data directory and open the file adder_v2_1_0.mpd.
53. Add the ADD_Out port

## Ports PORT ADD_Out = "", DIR = O,VEC = [3:0] 54. Save and close the file. 55. Rescan the user IP directories. Project > Rescan User Repositories. 56. The new core will now be available.

Adding the Custom Peripheral to the System

We will add and connect the new custom IP to the existing system

57. In XPS, click on the IP Catalog tab in the Project Information Area. 58. Expand the Project Local Pcores/USER list to view the custom IP.
59. Select addr then drag and drop it to the System Assembly View window. Click OK.

60. Click OK to connect this IP to MicroBlaze.

61. Click on the port tab to view the port connection for the new IP, select make external so it

work as external port.

62. Click on the Addresses tab to view the address range for the new IP.

63. We need to update the design information for SDK. Go to Project > Export Hardware

Design to SDK Select Export Only.

64. For looking block diagram of microblaze and adder interfacing using AXI protocol in XPS go to Project > Generate Block Diagram Image

65. Close XPS.

66. In Project Navigator, select the system_top module in the Hierarchy window. Then

synthesize it.

67. Check start with explorer wizard, click ok. 68. Select system_top then click on Add then click Create Schematic.

Bellow fig is top module of system which generated after synthesize.

Device utilization summary: Selected Device : 6slx9csg324-3 Slice Logic Utilization: Number of Slice Registers: Number of Slice LUTs: Number used as Logic: Number used as Memory: Number used as RAM: Number used as SRL: Slice Logic Distribution: Number of LUT Flip Flop pairs used: Number with an unused Flip Flop: Number with an unused LUT: Number of fully used LUT-FF pairs: Number of unique control sets: IO Utilization: Number of IOs: Number of bonded IOBs: Specific Feature Utilization: Number of Block RAM/FIFO: Number using Block RAM only: Number of BUFG/BUFGCTRLs:

2316 out of 11440 20% 2537 out of 5720 44% 2343 out of 5720 40% 194 out of 1440 13% 64 130 3719 1403 out of 3719 1182 out of 3719 1134 out of 3719 133 9 7 out of 8 out of 8 5 out of

37% 31% 30%

200 32 16

3% 25% 31%

Number of DSP48A1s: Number of PLL_ADVs:

3 out of 1 out of

16 18% 2 50%

Timing Summary: Speed Grade: -3 Minimum period: 9.833ns (Maximum Frequency: 101.700MHz) Minimum input arrival time before clock: 7.268ns Maximum output required time after clock: 7.992ns Maximum combinational path delay: No path found

Test Customize IP
69. Start Xilinx SDK and select the Workspace from mb_adder. 70. SDK will detect that the hardware system has changed. Click Yes to update the hardware

platform and BSP. ( If SDK does not auto-detect the new hardware, right-click on the hardware platform project and select Change Hardware Platform Specification. Browse to the XML files and click OK.) 71. Go to File > New > Xilinx C Project.
72. Name the project Tutorial_Test and select Empty Application from the project templates.

Click Next.

73. Select Target an Existing Board Support Package then click Finish.

74. We need to add a source file for the new empty C project. Select the Tutorial_Test\src folder and go to File > New > Source File. Enter main.c for the file name. Click Finish. 75. Inside main.c, after the comments, add: #include "xparameters.h" #include "stdio.h" #include "xbasic_types.h" int main (void) { return 0; } 76. Save the main.c file. The application will be compiled when saved. The Project menu gives options to change the behavior for building the application. 77. Create a Linker Script for the new application. Right-click on the Tutorial_Test project and select Generate Linker Script.

Setting up the Simulation Environment

78. Start ISE Project Navigator and open the mb_adder project. 79. Go to Project > Add Source. Then go

D:\mb_adder\mb_adder\WorkSpace\Tutorial_Test\Debug\ directory and open Tutorial_Test.elf.

80. Set the associations to Simulation and click OK.

81. Check the box Use With box to associate the ELF file to the Micro Blaze processor for

simulation. Click OK.

Adding a Test Bench File

82. In Project Navigator, go to Project > New Source. 83. Select VHDL Test Bench and select Testbench for the file name. Click Next. 84. Select system_top and click Next. Click Finish. 85. Click on the Simulation View radio button. The type of simulation can be changed by using the drop-down list. We will do a Behavioral simulation. 86. The test bench should be open in the Editor.

87. Add external reset and RS232 signal in test bench which is generated by double click on add_t. -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. -- add code for reset wait for 100 ns; wait for CLK_P_period*10; -- insert stimulus here -- add code for RS232 for one time input if you want continuous input create separate --process block wait; end process; 88. Save the test bench file.
89. Click on Testbench add_t

90. Click on Behavior check syntax, then Double click on simulate behavior model.

91. So Isim will be open, select your test bench uut , select your port from object window

then drag and drop in waveform window. Then simulate it.