LIC Lab Mod

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL
Ex. No: 1 Date : STUDY OF BASIC LOGIC GATES AIM: To Study about the basic logic gates and also verify the truth table. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. The 7th pin of the IC is connected to the ground. The 14th pin of the IC is connected to the Vcc=5V. Switch on the power supply and verify the truth table. Components Required OR GATE AND GATE NOT GATE NAND GATE NOR GATE EXOR GATE Digital Trainer Kit Connecting Wires Range IC7432 IC 7408 IC7404 IC7400 IC7402 IC7486 (0-12) V Quantity 1 1 1 1 1 1 1 -
OR GATE: SYMBOL:
PIN DIAGRAM:
Department of Electrical and Electronics Engineering, ACET.
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TRUTH TABLE: INPUT A 0 0 1 1 AND GATE: SYMBOL: B 0 1 0 1 OUTPUT Y 0 1 1 1
PINDIAGRAM:
TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y 0 0 0 1
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NOT GATE: SYMBOL:
PINDIAGRAM:
TRUTH TABLE: INPUT A 0 1 NAND GATE: SYMBOL: OUTPUT Y 1 0
PINDIAGRAM:
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TRUTH TABLE: INPUT A 0 0 1 1 NOR GATE: SYMBOL: B 0 1 0 1 OUTPUT Y 1 1 1 0
PINDIAGRAM:
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EXOR GATE: SYMBOL:
PINDIAGRAM:
RESULT:
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Ex. No: 2 Date : STUDY OF BASIC FLIP FLOPS AIM To construct RS, D and JK Flip-flop and verify their truth table. APPARATUS REQUIRED S.NO 1 2 3 4 COMPONENTS NAND Gate NOR Gate 3i/p AND Gate Digital Trainer Kit SPECIFICATION QUANTITY IC 7411 1 IC 7402 1 IC 7411 1 (0-12)V 1
PROCEDURE 1. Design the circuit from the given specification. 2. Connections are given as per the Logic diagram. 3. Inputs are given as per the truth table. 4. Switch on the power supply and verify the truth table.
RS FLIP FLOP LOGIC SYMBOL
R S
Q Q
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LOGIC DIAGRAM
TRUTH TABLE R 0 0 1 1 D FLIP FLOP LOGIC SYMBOL S 0 1 0 1 Q NC 1 0 1/0 NC 1 1 0/1 STATE No Change Set Reset Indeterminate
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LOGIC DIAGRAM
TRUTH TABLE CP 0 1 1 JK FLIP FLOP LOGIC SYMBOL D X 0 1 Qn+1 Qn 0 1
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LOGIC DIAGRAM
3 4 5
2 3
CP
11 10 9 5 8
TRUTH TABLE
Qn 0 0 0 0 1 1 1 1
J 0 0 1 1 0 0 1 1
K 0 1 0 1 0 1 0 1
Qn+1 0 0 1 1 1 0 1 0
RESULT:
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Ex. No: 3 Date : DESIGN AND IMPLEMENTATION OF ADDERS AIM: To design, construct and test a half-adder and a full adder. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Components Required RPS Resistor LED IC IC IC Connecting wires Bread Board Range +5V 330 --7432 7408 7486 ----Quantity 1 2 2 1 1 1 -1
THEORY: Digital computer performs a variety of information processing tasks. Among them, the basic functions encountered are the various arithmetic operations. The most basic arithmetic operation, no doubt, is the addition of two binary digits. This simple addition consists of four possible elementary operations namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 10 These first three operations produce a sum whose length is one digit but the fourth operation consists of two digits. The lower significant bit is called the sum and the higher significant bit is called carry. A combinational circuit that performs the addition of two bits is called a halfadder. One that performs the addition of three bits (two significant bits and a pervious carry) is a full-adder. Half adder circuit needs 2 binary inputs and two binary outputs. The input variables designate the augends and addend bits; the output variable produces the sum and carry. In the truth table of half-adder, the carry output is 0 unless both inputs are 1. Full-adder circuit consists of 3 inputs. Two of the input variables denoted by x & y represent the two significant bits to be added. The third input z represents the carry from the previous lower significant position.
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The eight rows under the input variable in the truth table designate all possible combinations of 1s and 0s that these variables may have. When all input bits are 0s, the output is 0. The sum output is equal to 1 when only input is equal to 1 or when all 3 inputs are equal to 1. The carry output has a value of 1 if 2 or 3 input is equal to 1. SYMBOL DIAGRAM: A B HALF ADDER: HALF ADDER SUM CARRY
TRUTH TABLE:
INPUT A 0 0 1 1 KARNAUGH MAP: SUM=AB B 0 1 0 1 OUTPUT Sum Carry 0 0 1 0 1 0 0 1
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CARRY=AB
SYMBOL DIAGRAM:
A B FULL ADDER:
FULL ADDER
SUM CARRY
TRUTH TABLE: A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT Sum Carry 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0
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KARNAUGH MAP: CARRY=AB+BC+CA
SUM=ABC
PROCEDURE: Connection are given as per the circuit diagram The power supply is switched on and a voltage of 5V is maintained For half adder, the two inputs are connected to the corresponding digits as per the truth table and out verified. For full adder, the three inputs are connected to the corresponding digits as per the truth table and out verified. If the output is logic 1, the LED glows, if the output is logic 0, the LED does not glow.
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RESULT:
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Ex. No: 4 Date :

DESIGN AND IMPLEMENTATION OF SUBRACTORS
AIM: To design, construct and test a half-subtractor and a full subtractor. APPARATUS REQUIRED: Components Require RPS Resistor LED IC IC IC IC Connecting wires Bread Board
S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. THEORY:
Range +5V 330 --7432 7408 7486 7404 -----
Quantity 1 2 2 1 1 1 1 -1
This subtraction consists of four possible elementary operations namely, 00=0 0 1 = 1 with 1 borrow 10=1 11=0 In all operations, each subtrahend bit is subtracted from the minuend bit. In case of second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. Just as there are half and full-adders, there are half and full-Subtractors. HALF SUBTRACTOR: A half-subtractor is combinational circuit that subtracts two bits and produces their difference. It also has an output to specify a 1 has been borrowed. Designate the minuend bit by x and the subtrahend bit by y. To perform x-y, we have to check the relative magnitudes of x and y. if x > y, we have three possibilities: 0-0=01-0=1, and11=0. The result is called the difference bit. If x< y, we have 0-1, and it is necessary to borrow a 1 from the next higher stage. The 1 borrowed from the next higher stage adds 2 to the minuend bit, just as in the decimal system a borrow adds 10 to a minuend digit.
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With the minuend equal to 2, the difference becomes 2-1=1. The half-subtractor needs two outputs, one output generates the difference and will be designated by the by symbol D. The second output, designated B for borrow, generated the binary signal that informs the next state that a 1 has been borrowed. FULL SUBTRACTOR: A full-subtractor is a combinational circuit that performs a subtraction between two bits, taking into account borrows of the lower significant stage. This circuit has 3 inputs and 2 outputs. The three inputs denote the minuend, subtrahend and previous borrow, respectively. The two outputs represent the difference and output borrows respectively. The eight rows under the input variables given under the truth table designate all possible combinations of 1s and 0s that the binary variables may take. The 1s and 0s for the output variables are determined from the subtraction of x-y-z. The combinations having input borrow z = 0 reduce to the same four conditions of the half adder. For x = 0, y = 0 and z = 1, we have to borrow a 1 from the next stage, which makes B=1 and adds 2 to x. since 2-0-1=1, D=1. SYMBOL DIAGRAM:
HALF SUBTRACTOR:
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TRUTH TABLE: X 0 0 1 1 KARNAUGH MAP: DIFFERENCE=AB Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0
BORROW=AB
SYMBOL DIAGRAM:
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FULL SUBTRACTOR:
TRUTH TABLE: X 0 0 0 0 1 1 1 1 KARNAUGH MAP: DIFFERENCE =ABC Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1
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BORROW =AB+AC+BC
PROCEDURE: Connection are given as per the circuit diagram The power supply is switched on and a voltage of 5V is maintained For half subtractors, x and y inputs are given and the difference and borrow bit are verified as per truth table. For full subtractors x, y, z, inputs are given and the truth table verified. If the difference or borrow bit1, the LED glows, if it is 0, the LED does not glow.
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RESULT:
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Ex. No: 5 Date : DESIGN AND IMPLEMENTATION OF CODE CONVERTERS AIM: To design, construct and verify the truth table of binary to gray code, gray to binary and binary to excess-3 code converter. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Components Require RPS Resistor LED IC Connecting wires Bread Board Range +5V 330 --7486 ----Quantity 1 2 2 2 -1
THEORY: A code converter is a logic circuit that change data presented in one type of binary code to another type of binary code. The available of large verify The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit performs this transformation by means of logic gates. The bit combinations for the BCD and excess-3 codes are listed in Table. Since each code uses four bits to represent a decimal digit, there must be four input variables and four output variables. Let us designate the four input binary variables by the symbols A,B,C, and D, and the four output variables by w, x, y and z. The truth table relating the input and output variables is shown in Table. The bit combinations for the inputs and their corresponding outputs are obtained directly from Table. We note that four binary variables may have 16 bit combinations. The K-maps are drawn to obtain a simplified Boolean function for each output. Each of the four maps represents one of the four outputs of this circuit as a function of the four input variables. The 1s marked inside the
Department of Electrical and Electronics Engineering, ACET. Page 21
squares are obtained from the minterms that make the output equal to 1. The 1s are obtained from the truth table by going over output columns one at a time. The logic diagram may be obtained directly from the Boolean expressions derived by the maps. BCD TO EXCESS 3 CODE CONVERTERS: TRUTH TABLE: B3 0 0 0 0 0 0 0 0 1 1 KARNAUGH MAP: B2 0 0 0 0 1 1 1 1 0 0 B1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 E1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0
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LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTER: LOGIC DIAGRAM:
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TRUTH TABLE: DECIMAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 KARNAUGH MAP: BINARY CODE C B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 GRAY CODE G3 G2 G1 G0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0
D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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GRAY TO BINARY CODE CONVERTER: TRUTH TABLE: G3 G2 G1 G0 B3 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 1 1 0 0 1 0 KARNAUGH MAP:
B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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LOGIC DIAGRAM:
PROCEDURE: 1) Connections are given as per the circuit diagram 2) Power supply is switched on and a supply of +5V is maintained 3) Input binary code values are given and its appropriative gray code values are checked in the outputs G3, G2, G1 & G0 4) If an output bit is equal to 1, that output bits LED glows indicating logic 1 and it an output bit is equal to 0, that output bit LED does not glow indicating logic 0
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RESULT:
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Ex. No: 6 Date : DESIGN AND IMPLEMENTATION OF 16 BIT ODD/EVEN PARITY CHECKER, GENERATOR USING IC 74180 AIM: To design and implement the 16 bit odd/even parity checker and generator using IC 74180. APPARATUS REQUIRED: S.No 1. 2. 3. THEORY: The circuit for generating parity bits and checking the parity of a given word can be designed using gates. The technique of parity checking is the most popular method of detecting errors in stored code groups, especially for storage devices such as magnetic tapes, paper tapes and even core and drum systems. In IC 74180-odd/even parity bit for a given 9-bit number can be generated. If a 16-bit input number is applied at X15 to X0 and the logic 1 is given to even bit and the inverter is connected to odd input. So IC 74180 will generate even or odd parity bit in even or odd output. So that if the total number of 1s in the 16 input is odd (i.e. X 0 to X15 is even and even input=1 or X15 to X0 is odd and even input=0).Then a 1 is generated as even parity bit at even output. This result in even parity in 16 bits. If total number of 1s in the 16 input bit is even, then a 0 is generated as even parity bit at even output. This results in even parity in 16 bits. IC 74180 can be cascaded to increase the word length capability of odd/even parity checker. Two in a given 16 bit IC 74180 can be cascaded to check odd/even parity in a given 16 bit number (X15 to X0) by connecting even and odd output of IC74180 with even and odd input of IC 71480 1 respectively. Now if the total 1s in the 6-bit number is even, if the number of 1s is odd then a 1 is generated in even output and output respectively. Components IC 74180 IC 7404 Trainer Kit Range Quantity 2 1 1
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16 BIT ODD/EVEN PARITY CHECKER:
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TRUTH TABLE: INPUT A B 0 1 0 0 1 0 0 1 1 0 0 1 1 1 C 0 1 1 0 0 0 1 D 0 0 1 0 1 1 0 E 1 1 0 0 0 01 0 F 0 0 1 1 0 01 1 G 0 1 0 0 0 01 1 H 0 1 1 1 1 1 0 A 0 1 0 0 0 0 0 B 1 1 0 1 0 1 1 C 0 0 0 1 0 1 1 D 0 0 0 1 1 0 1 E 1 1 1 0 0 1 F 0 1 0 0 0 0 0 G 0 1 0 1 1 0 0 H 1 1 0 0 0 0 0 OUTPUT EVEN ODD 1 0 0 1 1 0 1 0 1 0 0 1 1 0
16 BIT ODD/EVEN PARITY GENERATOR USING IC 74180
TRUTH TABLE: A 0 0 1 0 1 0 1 B 1 0 0 1 0 1 1 C 0 1 1 0 0 0 1 D 0 0 1 0 1 1 0 E 1 1 0 0 0 01 0 F 0 0 1 1 0 01 1 G 0 1 0 0 0 01 1 INPUT H A 0 0 1 1 1 0 1 0 1 0 1 0 0 0 B 1 1 0 1 0 1 1 C 0 0 0 1 0 1 1 D 0 0 0 1 1 0 1 E 1 1 1 0 0 1 F 0 1 0 0 0 0 0 G 0 1 0 1 1 0 0 H 1 1 0 0 0 0 0 OUTPUT EVEN ODD 1 0 0 1 1 0 1 0 1 0 0 1 1 0
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PROCEDURE: 1. Connections are given as per the circuit diagram. The supply voltage is switched on and 5 V is maintained. 2. For parity checker corresponding inputs are given and verified as per truth table. 3. For parity generator corresponding 16 inputs are given and verified as per truth table.
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RESULT:
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Ex. No: 7 Date : DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS AIM: To verify the table of 2x4 decode and 4x2 encoder. APPARATUS REQUIRED: Components Require RPS Resistor LED ICS
S.No 1. 2. 3. 4.
Range +5V 330 --7432 7408 7404 7421
Quantity 1 4 4 1 1 1 2
THEORY: DECODER: Discrete quantities are represented in digital systems with binary with binary codes. A binary code of n bits capable of representing up to 2 n distinct elements of the coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. If the n-bit decoded information has unused or dont-care combination, the decoder output will have fewer than 2n outputs. As an example consider the 2 to 4 line decoder circuit. The 2 inputs are decoded into 4 outputs, each output representing one the minterms of the 2 input variables. The 2 inverters provide the complement of the inputs, and each one of the 4 AND gates generate one of the minterms. ENCODER: An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines, the output lines generate the binary code corresponding to the input value. An example of an encoder is the octal to binary encoder. It has eight inputs, one for each of the octal digits and the three outputs that generate the corresponding binary number. It is assumed that only one input has a value Of 1 at any given time; otherwise the circuit has no meaning. The circuit that is presented here is 4 x 2 encoder.
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4:2 ENCODER: TRUTH TABLE: INPUT D2 D3 0 0 1 0 0 1 0 0 OUTPUT X Y 0 0 0 1 1 0 1 1
D1 1 0 0 0 KARNAUGH MAP:
D4 0 0 0 1
CIRCUIT DIAGRAM: D1 D2 D3 D4
7432
X= D3+D4
7432
7404
Y= D1D3
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2:4 DECODER: TRUTH TABLE: INPUT X Y 0 0 0 1 1 0 1 1 LOGIC DIAGRAM: D1 1 0 1 0 OUTPUT D2 D3 0 0 1 0 0 1 0 0 D4 0 0 0 1
PROCEDURE: Check the components and ICS before given the circuit connection. Rig up the circuit as shown in fig. Switch on power supply. For logic 1connect the input to +5V and for logic 0, connect the input to ground. Verify the truth table, if LED is glowing the output is 1 and if it is not output is zero. Switch off the power supply.
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RESULT:
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Ex. No: 8 Date : CONSTRUCTION AND VERIFICATION OF 4-BIT RIPPLE COUNTER AIM: To construct and test the 4-bit ripple counter. APPARATUS REQUIRED: S.No 1. 2. 3. THEORY: A binary ripple or asynchronous counter consists of a series connection of complementing flip-flops with the output of each flip-flop connected to a clock input of the next higher order flip-flop. The flip-flop holding the least significant bit receives the incoming clock pulse. A complementary flip-flop can be obtained from a JK flip-flop with the J and K inputs tied together. The flip-flops will be complemented. In the JK flip-flop the clock signal is connected to the clock input of only the first stage flip-flop. The clock input of the second stage flip-flop is triggered by the Q A output of the first stage. Because of the inherent propagation delay time through the flip-flop a transmission of the input clock pulse and a transition of input clock pulse and transition of the QA output of first stage can never occur exactly the same time. Therefore the flipflops are never simultaneously triggered which results in asynchronous counter operation. In the four-bit ripple down counter using JK flip-flops the clock signal is connected to the clock input of only first flip-flop. This connection is same as the ripple up counter. However the clock input of the remaining flip-flops is triggered by QA not of the previous stage is triggered instead of QA output of the previous stage. 4-BIT RIPPLE COUNTER Components IC 7476 IC 7404 Trainer Kit Range Quantity 2 1 1
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TRUTH TABLE: INPUT PRESET CLOCK 0 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 PROCEDURE: 1. Connections are given as per the circuit diagram. The supply voltage is switched on and 5 V is maintained 2. Reset pins are activated and the state of flip-flops is brought to reset state. 3. Clock pulse is applied and the sequences of counter output are verified. OUTPUT QC QB 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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RESULT:
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Ex. No: 9 Date : IMPLEMENTATION OF SERIAL IN SERIAL OUT AND SERIAL IN PARALLEL OUT SHIFT REGISTERS USING IC 7476 AIM: To implement and test serial in serial out and serial in parallel out shift registers using IC 7476 APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Components Required RPS Resistor LED IC IC IC Range +5V 330 --7400 7476 7404 Quantity 1 4 4 1 1 1
THEORY: . A register is a clocked sequential circuit consisting of group of flip-flops and gates connected to the from a feedback path. Since each flip-flop is a binary cell cable of storing one bit of information. A group of flip-flops constitute a register. If it is an n-bit register it has a group of n-flip-flops and is capable of storing binary information of nbits. In addition to flip-flops a register may have gates that perform certain data processing tasks. A register capable of shifting its binary information either to the right or left is called a shift register. It consists of flip-flops in cascade with the output of one flip-flop connected as the input of the next flip-flop. All flip-flops receive a common clock pulse that causes the shift from one stage to the next stage. According to the register configuration each clock pulse shifts the contents of the register by one bit to the left or right. It can accept both serial and parallel data. It is possible to operate the shift register in four different modes. 1. serial in serial out 2. serial in parallel out 3. parallel in parallel out 4. Parallel in serial out. If the shift register can accept data serially i.e. one bit at a time on a single line and produce the stored information on its output in serial form then it is said to be in serial in serial out mode of operation. Once the data are stored each bit appears on its respective output line and all bits are available simultaneously. This type is said to be serial in parallel out shift register.
SERIAL IN SERIAL OUT
SERIAL IN PARALLEL OUT
TRUTH TABLE (SISO):
RESET H L L L L L L
INPUT 1 0 1 0 1 0
CLOCK 0 1 2 3 4 5 6
OUTPUT 0 0 0 0 1 0 1
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TRUTH TABLE (SIPO): OUTPUT Q2 Q3 0 0 0 0 1 0 0 1 1 0 0 1 1 0
RESET H L L L L L L
INPUT 1 0 1 0 1 0
CLOCK 0 1 2 3 4 5 6
Q1 0 1 0 1 0 1 0
PROCEDURE: Connection are given as per the circuit diagram Load serial data into the shift register. Apply the clock pulse from the debouncing circuit. For every clock pulse given the output is shifted one bit from left to right. The truth table is verified.
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RESULT:
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Ex. No: 10 Date : IMPLEMENTATION AND TESTING OF MULTIPLEXER AND DEMULTIPLEXER AIM: To design, construct and test a multiplexer and a demultiplexer using logic gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. THEORY: MULTIPLEXER: A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single out line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines whose bit combination determine which input is selected. In a 4-to-1 line multiplexer, each of the four input lines I0 to I3 is applied to one input of an AND gate. Selection lines S1 and S0 are decoded to select a particular AND gate. To demonstrate the circuit operation, consider the case when S1S0=10. the And gate associated with input I2 has two of its inputs equal to 1 and the third input connected to I2. The other three AND gates have at least one input equal to 0, which makes their output equal to 0. The OR gate is now equal to the value of I 2, thus providing a path from the selected input to the output. A multiplexer is also called a data-selector, since it selects one of many inputs and steers the binary information to the output line. Components Require RPS Resistor LED IC IC IC Connecting wires Bread Board Range (0-30)V 330 --74011 7404 7432 ----Quantity 1 2 2 1 1 1 -1
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DE-MULTIPLEXER: A demultiplexer is a combinational circuit that receives information on a signal line and transmits this information on one of 2n possible output lines. The selection of a specific output line is controlled by the bit values of the n selection lines. If the selection lines AB=10, output D2 will be the same as the input value E, While all other outputs are maintained at 1. Because decoder and demultiplexer operations are obtained from the same circuit, the decoder with an enable input is referred as a decoder/ demultiplexer If S0=0, S1= 0, then the data input will be transmitted to D0. If S0 = 0, S1 = 1 then the data input will be transmitted to D1. If S0 = 1, S1 = 0, then the data input will be transmitted to D2. If S0 =0, S1 = 1, then the data input will be transmitted to D3. MULTIPLEXER (2:1): SYMBOL:
TRUTH TABLE: S 0 0 0 0 1 1 1 1 INPUT I1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 OUTPUT Y 0 1 0 1 0 0 1 1
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KARNUGH MAP: Y=SI0+SI1
CIRCUIT DIAGRAM: I1 S
7404 7408 7408 7432
Y=SI0+SI1
I0 MULTIPLEXER (4:1): SYMBOL:
TRUTH TABLE: I0 0 0 0 0 I1 0 1 0 0 INPUT I2 I3 0 0 0 0 1 0 0 1 S1 0 0 1 1 S0 0 1 0 1 OUTPUT X I0 I1 I2 I3

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LOGIC DIAGRAM:
DE-MULTIPLEXER (1:2): SYMBOL:
TRUTH TABLE:
D 0 0 1 1 KARNAUGH MAP:
S 0 1 0 1
Y0 0 0 1 0
Y1 0 0 0 1
LOGIC DIAGRAM:
D S
7404
7408
Y1=DS
7408
Y0= DS
DE-MULTIPLEXER (1:4): SYMBOL:

Y0 Y1 D 1:4 DEMUX Y2 Y3
S1
S0
TRUTH TABLE:
S1 0 0 1 1 LOGIC DIAGRAM:
INPUT S1 0 1 0 1
D 1 1 1 1
Y0 1 0 0 0
OUTPUT Y1 Y2 0 0 1 0 0 1 0 0
Y3 0 0 0 1
PROCEDURE: Connection are given as per the circuit diagram The power supply is switched on and a voltage of 5V is maintained For multiplexer, appropriate inputs are given to the selection lines and we can find out which data line is selected and hence the function table is verified. In demultiplexer, the outputs of each AND gate is connected with a LED and by using the selection lines we can choose the input we want to get as the output.
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RESULT:
Ex. No: 11
Date : ASTABLE AND MONOSTABLE MULTIVIBRATOR USING NE555 TIMER AIM: To construct a) Astable Multivibrator and b) Monostable Multivibrator using IC 555 timer DESIGN: Let Vc Choose RB=3.3 k F = 1.44/(RA+2RB)C (RA+RB) D= (RA+2RB) (RA+3.3 k) 50 = (RA +2*3.3k) RA = 6.6 k Let T = 5 ms 1.44 200 = (6.6 k+ (2*3.3k))C , C = 0.5F *100 *100 Vcc = 5v = Vcc = 50%
Duty cycle
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APPARATUS REQUIRED: S.NO 1. 2. 3. APPARATUS NAME RANGE Regulated variable power (0-30) Volts supply Signal generator CRO 1MHz 20MHz QUANTITY 2 1 1
COMPONENTS REQUIRED: ASTABLE MULTIVIBIRATOR S.NO 1. 2. 3. COMPONENT NAME Resistors Timer Capacitors RANGE 1K ,2K NE555 0.1F 0.1F COMPONENTS REQUIRED: MONOSTABLE MULTIVIBIRATOR S.NO 1. 2. 3. COMPONENT NAME Resistors Timer Capacitors RANGE 5k NE555 0.1F 0.1F THEORY: Introduction: The number of amplifiers is used for specific purposes in the various applications. Instead of using discrete circuits and components for these applications, monolithic ICs are available, now a day. Such ICs are well matched characteristics of components, reduced cost, smaller size, improved performance etc. QUANTITY 1 each 1 2 QUANTITY 1 each 1 2
IC 555: The Astable and Monostable circuit are commonly available in monolithic ICs, and IC timers. The timer 555 is one example which has gained wide acceptance in terms of cost and versatility. It was first introduced by signetic corporation as SE/NE 555. Some important applications of this device are Monostable and Astable Multivibrator, dc-dc converters,
digital logic probes, waveform generators, analog frequency meters and tachometers, temperature measurement and control, infrared transmitters, burglar and toxic gas, alarms, voltage regulators, etc. The IC 555 timer is an 8-pin IC that can be connected to external components for either Astable or Monostable operation. The 555 timer will work with any supply voltage between 4.5V and 10V.In the internal structure of the 555 timer there are one flip flop and two op-amps. The non-inverting input of upper op-amp is called as threshold voltage and inverting input is called as control voltage. Astable Multivibrator: Multivibrator are group of regenerative circuits. They are widely used in timing applications. Multivibrator are classified as (1) Bistable multivibrators (2) Monostable Multivibrators (3) Astable Multivibrators Astable circuits are used to generate square waves. It is also known as free running Multivibrator. It has two quasi stable states. Thus there is no oscillation between these two states and no external signals to produce the change in state. As there is no need of trigger input the second pin is connected to the sixth pin. When the threshold voltage exceeds Vcc, the upper op-amp has a high input and this sets the flip flop allowing the capacitor discharging through RB. Therefore the discharge time constant is Rbc. When the capacitor drops below +Vcc/3, the lower amplifier has higher input and this resets the flip flop.
(RA+RB) D= (RA+2RB) Monostable Multivibrator: The 555 timer configured for Monostable operation is shown in the figure. Monostable Multivibrator often called a one shot Multivibrator is a pulse generating circuit in which the duration of this pulse is determined by the RC network connected externally to the 555 timer. In a stable or standby state, the output of the circuit is approximately zero or a logic-low level. When external trigger pulse is applied output is forced to go high ( VCC). The time for which output remains high is determined by the external RC network connected to the timer. At the end of the timing interval, the output automatically reverts back to its logic-low stable state. The output stays low until trigger pulse is again applied. Then the cycle *100
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repeats. The Monostable circuit has only one stable state (output low) hence the name Monostable Operation: Initially when the circuit is in the stable state i.e., when the output is low, transistor Q1 is ON and the capacitor C is shorted out to ground. Upon the application of a negative trigger pulse to pin 2, transistor Q1 is turned OFF, which releases the short circuit across the external capacitor C and drives the output high. The capacitor C now starts charging up towards VCC through R. When the voltage across the capacitor equals 2/3 VCC, comparator 1s output switches from low to high, which in turn drives the output to its low state via the output of the flip-flop. At the same time the output of the flip-flop turns transistor Q1 ON and hence the capacitor C rapidly discharges through the transistor. The output of the Monostable remains low until a trigger pulse is again applied. Then the cycle repeats. The pulse width of the trigger input must be smaller than the expected pulse width of the output waveform. Also the trigger pulse must be a negative going input signal with amplitude larger than 1/3 VCC. The time during which the output remains high is given by
Where R = is in Ohms and C is in Farads. Once triggered, the circuits output will remain in the high state until the set time, t elapses. The output will not change its state even if an input trigger is applied again during this time interval t. The circuit can be reset during the timing cycle by applying negative pulse to the reset terminal. The output will remain in the low state until a trigger is again applied. PROCEDURE:
1. 2. 3. 4. 5. Get the required components and check the condition of them. Connect the circuit as per the circuit diagram. Switch on the power supply and look at the output with CRO. Measure the width and time period of the output waveform. Look at the voltage across the capacitor, an exponentially rising and falling wave between5V and 10V is noted.
6. After completing the experiments, reduce the supply to zero potential and disconnect the circuit diagram. TABULATION:
ASTABLE MULTIVIBRATOR
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Parameters
Output voltage Capacitor voltage
Amplitude(Volts)
Time period(ms)
MONOSTABLE MULTIVIBRATOR
Parameters
Output voltage Capacitor voltage
Amplitude(Volts)
Time period(ms)
CIRCUIT DIAGRAM:
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MONOSTABLE MULTIVIBRATOR USING NE555 TIMER +Vcc
4
R 1k
8 3 Vout
7 555 5
C
6 2 1
1nF
1nF
Trigger input
ASTABLE MULTIVIBRATOR USING NE555 TIMER
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MODEL GRAPH:
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Astable Multivibrator
Capacitor voltage O/p voltage
T (ms) T (ms)
1/3 Vcc
2/3 Vcc
Tlow
Thigh
Monostable Multivibrators
Output voltage
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RESULT:
Ex. No: 12 Date : DESIGN AND TESTING OF INTEGRATOR

AIM: a) To design and analyze the integrator. DESIGN: Integrator design: The output voltage is given by Vout = - 1/ (RfCf) Vin (t) + Vo (0) Time constant 1) To find Cf: The gain value is given by A The corner frequency is Choose, = (Rf / R1) / (1 + j RfCf) ------------ (1) fc = 1 / 2 RfCf ------------------------------ (2) = Rf Cf
fc = 100Hz and Rf = 10K
By substituting all in equation (2), calculate the value of Cf . 2) To find R1 : Let Gain (A) = 1 and substitute all remaining values in equation (1), then find the value of R1. APPARATUS REQUIRED: S.NO 1. 2. 3.
Rf = 10K
Cf = 10 F
APPARATUS NAME RANGE Regulated variable power (0-30) Volts R1 = supply 4 10K V2 1 Signal generator 1MHz OS1 6 CRO 20MHz OUT
3 + 7 OS2 V+ 5 LM741 U2 Vin = 1 Vpp
QUANTITY 2 1 V 1 out
COMPONENTS REQUIRED:
S.NO COMPONENTS NAME 1. Resistors 2. Op- amp 0 Rcomp =5K 3. Capacitor CIRCUIT DIAGRAM:
0
RANGE 10k,5 k LM741 10F
QUANTITY 2,1 1 1
Page 61
THEORY: In an integrator circuit, the output voltage is the integration of the input voltage. There are two types of integrators called passive integrator and active integrator. The active integrator using active components like op-amp. The output voltage is given by Vout = - 1/ (RfCf) Vin (t) + Vo (0) Time constant = - 1/ (RfCf)
The negative sign indicates that there is a phase shift of 180 degree between input and output. The main advantage of such an active integrator is the large time constant which gives perfect integration. Sometimes a compensation resistance is needed to connect to the non-inverting terminal to provide the bias compensation. The compensation resistance value is given by Rcomp = (Rf parallel with R1).
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PROCEDURE: 1. Get the required components and check the condition of them. 2. Connect the circuit as per the circuit diagram. 3. For the integrator circuit, the square wave is given as the input waveform and the triangular wave is taken as the output using CRO. 4. Measure the input and output voltage and enter it into tabular column. 5. After completing the experiments, reduce the supply to zero potential and disconnect the circuit diagram. MODEL GRAPH:
TABULATION:
INPUT AMPLITUDE (Volts) INPUT TIME PERIOD (ms) OUTPUT AMPLITUDE (Volts) OUTPUT TIME PERIOD (ms)
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RESULT:
Ex. No: 13 Date :

DESIGN AND TESTING OF DIFFERENTIATOR AIM: b) To design and analyze the differentiator. DESIGN: Differentiator design: The gain value is given by A The lower corner frequency is The upper corner frequency is Design procedure: 1. Choose fa as the highest frequency of the input signal. i.e. fa = 100Hz 2. Choose C1 to be less than 1 micro Farad and calculate the value of R1. Choose C = 1micro Farad and from equation (2) and Calculate R1. 3. Choose fb as 10 times fa which ensures that fa < fb. That is fb =10 fa. Now find Rf. 4. To find Cf , use RfC1 = R1C1 and Rcomp = R1 parallel with Rf . APPARATUS REQUIRED: S.NO 1. 2. 3. APPARATUS NAME RANGE Regulated variable power (0-30) Volts supply Signal generator 1MHz CRO 20MHz QUANTITY 2 1 1 = - j RfC1 / (1 + j R1C1)2 fa = 1 / 2 R1C1 fb ------------------ (1) (2) -----------------------
= 1 / 2 RfC1 ------------------------------- (3)
Always assume fa < fb < fc and Rf C1 < T. Where T - time constant.
COMPONENTS REQUIRED: S.NO 1. 2. 3. COMPONENTS NAME Resistors Op- amp Capacitor RANGE 1.5K,0.1 K,800 ,143 LM741 QUANTITY Each one 1 2
CIRCUIT DIAGRAM:
DIFFERENTIATOR
Rf=1.5K
Cf=0.1 F
R1= 860
C1 =0. 1
4 -
VOS1 OUT OS2 V+
1 6 5 LM741 U2
741
3 + 7
Output
1 Vpp
Rcomp = 143
TABULATION:
INPUT AMPLITUDE (volts) SIGNAL INPUT (ms) SIGNAL OUTPUT AMPLITUDE (volts) SIGNAL OUTPUT SIGNAL TIME PERIOD (ms)
TIME PERIOD
MODEL GRAPH:
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THEORY: In a differentiator circuit, the output voltage is the differentiation of the input voltage. There are two types of differentiator called passive differentiator and active differentiator. The active differentiator using active components like op-amp. The output voltage is given by Vout = - 1/ (RfCf) [dVin / dt], Time constant = - RfCf The negative sign indicates that there is a phase shift of 180 degree between input and output. The main advantage of such an active differentiator is the small time constant which gives perfect differentiation. Sometimes a compensation resistance is needed to connect to the non-inverting terminal to provide the bias compensation. The compensation resistance values are given by Rcomp = (Rf parallel with R1 ). PROCEDURE: 1. Get the required components and check the condition of them. 2. Connect the circuit as per the circuit diagram. 3. For the integrator circuit, the triangular wave is given as the input waveform and the output wave is taken as the output using CRO. 4. Measure the input and output voltage and enter it into tabular column. 5. After completing the experiments, reduce the supply to zero potential and disconnect the circuit diagram.
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RESULT:
Ex. No: 14 Date :

DESIGN AND TESTING OF INVERTING AMPLIFIER AIM: To design an Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1
THEORY: The input signal Vi is applied to the inverting input terminal through R1 and the non-inverting input terminal of the op-amp is grounded. The output voltage V o is fed back to the inverting input terminal through the Rf - R1 network, where Rf is the feedback resistor. The output voltage is given as, Vo = - ACL Vi Here the negative sign indicates that the output voltage is 1800 out of phase with the input signal. PRECAUTIONS: 1. Output voltage will be saturated if it exceeds 15V. PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the OpAmp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. PIN DIAGRAM:
CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:
DESIGN: We know for an inverting Amplifier ACL = RF / R1 Assume R1 (approx. 10 K) and find Rf Hence Vo(theoretical) = - ACL Vi
OBSERVATIONS:
S.No. Input Output
Amplitude ( No. of div x Volts per div ) Theoretical Practical -
Time period ( No. of div x Time per div )
MODEL GRAPH:
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RESULT:
Ex. No: 15
Date : DESIGN AND TESTING OF NON - INVERTING AMPLIFIER AIM: To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1
THEORY: The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is also called negative feedback system since the output is feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of the op-amp is zero ideally and the output voltage is given as, Vo = ACL Vi Here the output voltage is in phase with the input signal. PRECAUTIONS: 1. Output voltage will be saturated if it exceeds 15V. PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. PIN DIAGRAM:
CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:
DESIGN: We know for a Non-inverting Amplifier ACL = 1 + (RF / R1) Assume R1 ( approx. 10 K ) and find Rf Hence Vo = ACL Vi
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OBSERVATIONS: S.No. Input Output Amplitude ( No. of div x Volts per div ) Theoretical Practical Time period ( No. of div x Time per div )
MODEL GRAPH:
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RESULT:
Ex. No: 16
Date : DESIGN AND VERIFY OP-AMP APPLICATION AS ADDER AIM: To design a Operational Amplifier application as adder for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1
THEORY: The inverting configuration with two inputs V1, V2. The circuit can be verified by examining the expression for the voltage V0, which is obtained KCL at node V2. Ia + Ib = IB + I F Since Ri and A of the op-amp are ideally infinity, IB = 0A and V1 = V2 = 0V.Therefore, If in the above circuit Ra = Rb = Rf. The equation can be written as, Vo = -(Rf / R) (V1+V2) This means that the output voltage is equal to negative sum of all the inputs times the gain of the circuit - hence, is called as a summing amplifier. When the gain of the circuit is unity that is Ra = Rb = Rf, the output voltage is equal to negative sum of all input voltage. Negative gain in this equation indicates that there is a phase shift of 180 between the input and output. PRECAUTIONS: 1. Output voltage will be saturated if it exceeds 15V. PROCEDURE: 1) Connect the circuit as shown in figure. 2) Give the supply voltage to op-amp. 3) Apply the input signals Va, Vb, to the inverting input terminal of opamp.
4) Note the output for the corresponding voltages. 5) Take the reading for several input voltages Va, Vb, Vc. 6) Calculate the theoretical and practical output voltage. CIRCUIT DIAGRAM OFADDER:
OBSERVATIONS: Sl.No Va (volts) Vb (volts) Vo=Va+Vb (Theoretical value) Vo=Va+Vb (Practical value)
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RESULT:
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Ex. No: 17 Date : VERIFICATION OF SLEW RATE AIM: Verification of op-amp parameter slew rate for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1
PRECAUTIONS: 1. Output voltage will be saturated if it exceeds 15V. PROCEDURE: 1) 2) 3) 4) 5) 6) Connect the circuit as shown in figure. Give the supply voltage to op-amp. Apply the input signals to the inverting input terminal of op-amp. Note the output for the corresponding voltages. Take the reading for various i/p and o/p voltages Calculate the theoretical and practical output voltage.
CIRCUIT DIAGRAM OFADDER:
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RESULT:
Ex. No: 18 Date : STUDY OF DAC CIRCUITS R 2 R LADDER TYPE AIM: To study and construct a 4 bit R 2R ladder type D/A converter. APPARATUS REQUIRED: S. No 1. 2. COMPONENTS NAME OP AMP Resistors RANGE Lm741 100K, 100 10K, 20K (0 24)V (0-30)V QUANTITY 1 1, 1 4, 7 1 As required 1 1
3. 4. 5. 6.
Bread board Wires Fixed supply Voltmeter
THEORY: Wide range of resistance is required in binary weighted resistor type DAC. Thus can avoided by using R 2R ladder type DAC where only two values of resistors are required. It is well suited for integrated circuit realization. The typical value of R ranges from 2.5K to 10K. PROCEDURE: 1. Get the required components and check the condition of them. 2. Connect the circuit as per the circuit diagram. 3. With all inputs (d0 to d3) shorted to ground adjust the 20K plot until the output is 0V. This will nullify any offset voltage at the input of the op amp. 4. Measure the output voltage for all binary inputs ( 0000 to 1111) states and plot a graph of binary inputs Vs output voltage.
5. Measure the size of each step and hence calculate resolution. 6. Calculate linearity.
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PINDIAGRAM:
CIRCUIT DIAGRAM:
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MODEL GRAPH:
TABULATION: DIGITAL INPUT ANALOG OUTPUT
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RESULT:
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Ex. No: 19 Date : STUDY OF ANALOG TO DIGITAL CONVERTER Aim: To study and verify the analog to digital converter of flash type. APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. THEORY: The basic principle of operation is to use the comparator principle to determine whether or not to turn on a particular bit of the binary number output. It is typical for an ADC to use a digital-to-analog converter to determine one of the inputs to the comparator. COMPONENTS NAME OP AMP Resistors Bread board Wires Fixed supply LEDs Voltmeter RANGE Lm741 470K, 12K 1K, (0 24)V (0-30)V QUANTITY 4 1, 1 11 1 As required 1 4 1
FLASH A/D CONVERTER: A 3-bit flash ADC with resolution 1 volt. The resistor net and comparator provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.). Such ADCs are available in IC form up to 8bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output.
The circuit consists of 4 comparators whose inverting inputs are connected to a voltage divider. A comparator is basically an operational amplifier used without feedback. The outputs of the comparators in Figure 5 correspond to a digital word. When the input rises above VN1 , the first comparator will switch to a high output voltage causing the LED to light up, indicating a (0001). For larger input voltages the output of other comparators will switch high as well. For large input voltages (above Vn3) all comparators will be high corresponding to (1111) digital output. Thus the comparators encode the analog input as a digital word on a thermometer scale. The output is usually further encoded to produce a standard 2-bit binary word as shown in table II. All comparators work in parallel which makes this ADC very fast. For that reason it is called a Flash Converter. PROCEDURE: 1. Get the required components and check the condition of them. 2. Connect the circuit as per the circuit diagram. 3. With all inputs (d0 to d3) shorted to ground adjust the 20K plot until the output is 0V. This will nullify any offset voltage at the input of the op amp. 4. Measure the output voltage for all binary inputs ( 0000 to 1111) states and plot a graph of binary inputs Vs output voltage. 5. Measure the size of each step and hence calculate resolution. 6. Calculate linearity. PIN DIAGRAM:
MODEL GRAPH:
Page 88
CIRCUIT DIAGRAM:
Page 89
RESULT:
Page 90
Ex. No: 20 Date : FREQUENCY MULTIPLIER USING PLL AIM: To construct and test the frequency multiplier using PLL 565 APPARATUS REQUIRED: S.NO 1. 2. 3. APPARATUS NAME RANGE Regulated variable power (0-30) Volts supply Signal generator CRO 1MHz 20MHz QUANTITY 2 1 1
COMPONENTS REQUIRED: S.NO 1. COMPONENT NAME Resistors RANGE QUANTITY 20K ,2K , Each Two 4.7K ,10K 2. 3. PLL COUNTER Capacitors IC565 IC7490 0.01F, 0.001F, 4. THEORY: In the frequency multiplier using PLL565, a divided by N network is inserted between the VCO output and the phase comparator input. Since the output of the comparator is locked to the input frequency fin, the VCO is running at a multiple of the input frequency. Therefore in the locked state the VCO output frequency fo is given by, fo= Nfin TRANSISTOR 10F 2N2222 1 1 1
PROCEDURE: 1. Rig up the circuit of frequency multiplier 2. Connect the signal generator output to the input terminal of PLL
3. Connect the CRO probes to display the input and output signals 4. Set the input signal at 1Vpp square wave at 1khz 5. Vary the VCO frequency by adjusting the 20K potentiometer till the PLL is locked 6. Measure the output frequency, it should be 5 times that of the input frequency 7. Repeat the steps for different range of frequencies TABULATION: fin (Hz) fo (Hz) Designed Vin= Multiple Factor Obtained
PIN DIAGRAM:
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RESULT:
Ex. No: 21 Date :

VOLTAGE TO FREQUENCY CHARACTERISTICS OF NE/ SE 566 IC.
AIM: To study and test the voltage to frequency characteristics IC 566. APPARATUS REQUIRED: S.NO 1. 2. 3. APPARATUS NAME RANGE Regulated variable power (0-30) Volts supply Signal generator CRO 1MHz 20MHz QUANTITY 2 1 1
COMPONENTS REQUIRED: S.NO 1. 2. 3. 4. THEORY: The VCO is an oscillator whose output frequency is directly related to the voltage at its input. With no input the VCO supplies a signal at its natural (free running) frequency. When a signal is applied to the input, the VCO will generate an output whose frequency follows the amplitude of the input in accordance with the applied voltage. COMPONENT NAME Resistors VCO COUNTER Capacitors TRANSISTOR RANGE 20K ,2K , 4.7K ,10K IC566 QUANTITY Each Two 1
IC7490 0.01F, 0.001F, 1 10F 2N2222 1
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Although we use sinusoidal signals in our analysis, most commercially available VCO ICs generate square signals.
This is a general purpose VCO. It can be used to generate square and triangular waves, the frequency of which is a linear function of a controlling voltage. The frequency is also controlled by an external resistor (pin6) and capacitor (pin7), whose values control the free running frequency. Voltage to Frequency Conversion Factor: A parameter of importance for VCO is voltage to frequency conversion factor Kv and is defined as Kv = fo Vc Here Vc is the modulation voltage required to produce the frequency shift fo for a VCO. If we assume that the original frequency is fo and the new frequency is f1, then fo = f1 fo = 2(Vcc-vc+vc) - 2(Vcc vc) C T R TVcc C T R TVcc = 2vc C T R TVcc Or Vc = fo C T R TVcc
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2 Putting the value of C T R T, Vc = fo Vcc/8fo Or, Kv = fo = 8fo Vc Vcc
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RESULT:
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LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

TRUTH TABLE: INPUT A 0 0 1 1 AND GATE: SYMBOL: B 0 1 0 1 OUTPUT Y 0 1 1 1

TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y 0 0 0 1

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

NOT GATE: SYMBOL:

TRUTH TABLE: INPUT A 0 1 NAND GATE: SYMBOL: OUTPUT Y 1 0

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

TRUTH TABLE: INPUT A 0 0 1 1 NOR GATE: SYMBOL: B 0 1 0 1 OUTPUT Y 1 1 1 0

TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y 1 0 0 0

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

EXOR GATE: SYMBOL:

TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y 0 1 1 0

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

RS FLIP FLOP LOGIC SYMBOL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

TRUTH TABLE CP 0 1 1 JK FLIP FLOP LOGIC SYMBOL D X 0 1 Qn+1 Qn 0 1

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

TRUTH TABLE: A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT Sum Carry 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

KARNAUGH MAP: CARRY=AB+BC+CA

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Ex. No: 4 Date :

Range +5V 330 --7432 7408 7486 7404 -----

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

TRUTH TABLE: X 0 0 1 1 KARNAUGH MAP: DIFFERENCE=AB Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

TRUTH TABLE: X 0 0 0 0 1 1 1 1 KARNAUGH MAP: DIFFERENCE =ABC Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL

BINARY TO GRAY CODE CONVERTER: LOGIC DIAGRAM:

Department of Electrical and Electronics Engineering, ACET.

LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL