Datasheet

322429- 008
Revi si on Number : 2.7

Apr i l 2011
I nt el
82599 10 GbE Cont r ol l er

Dat asheet
PRODUCT FEATURES
Gener al
Serial Flash I nt erface
4- wire SPI EEPROM I nt erface
Configurable LED operat ion for soft ware or OEM cust omizat ion
of LED displays
Prot ect ed EEPROM space for privat e configurat ion
Device disable capabilit y
Package Size - 25 mm x 25 mm
Net w or k i ng
Complies wit h t he 10 Gb/ s and 1 Gb/ s Et hernet / 802. 3ap ( KX/
KX4/ KR) specificat ion
Complies wit h t he 10 Gb/ s Et hernet / 802. 3ae ( XAUI )
specificat ion
Complies wit h t he 1000BASE- BX specificat ion
Complies wit h t he I EEE 802. 3x 100BASE-TX specificat ion
Support for j umbo frames of up t o 15. 5 KB
Aut o negot iat ion Clause 73 for support ed mode
CX4 per 802. 3ak
Flow cont rol support : send/ receive pause frames and receive
FI FO t hresholds
St at ist ics for management and RMON
802. 1q VLAN support
TCP segment at ion offload: up t o 256 KB
I Pv6 support for I P/ TCP and I P/ UDP receive checksum offload
Fragment ed UDP checksum offload for packet reassembly
Message Signaled I nt errupt s ( MSI )
Message Signaled I nt errupt s ( MSI -X)
I nt errupt t hrot t ling cont rol t o limit maximum int errupt rat e
and improve CPU usage
Receive packet split header
Mult iple receive queues ( Flow Direct or) 16 x 8 and 32 x 4
128 t ransmit queues
Receive header replicat ion
Dynamic int errupt moderat ion
DCA support
TCP t imer int errupt s
NO snoop
Relaxed ordering
Support for 64 virt ual machines per port ( 64 VMs x 2 queues)
Support for Dat a Cent er Bridging ( DCB) ( 802. 1Qaz, 802. 1Qbb,
802. 1p)
Host I nt er f ace
PCI e Base Specificat ion 2. 0 ( 2. 5GT/ s) or ( 5GT/ s)
Bus widt h x1, x2, x4, x8
64- bit address support for syst ems using more t han 4 GB of
physical memory
MAC FUNCTI ONS
Descript or ring management hardware for t ransmit and
receive
ACPI regist er set and power down funct ionalit y support ing
D0 and D3 st at es
A mechanism for delaying/ reducing t ransmit int errupt s
Soft ware- cont rolled global reset bit ( reset s everyt hing
except t he configurat ion regist ers)
Eight Soft ware- Definable Pins ( SDP) per port
Four of t he SDP pins can be configured as general- purpose
int errupt s
Wake up
I pv6 wakeup filt ers
Configurable flexible filt er ( t hrough EEPROM)
LAN funct ion disable capabilit y
Programmable memory t ransmit buffers ( 160 KB/ port )
Default configurat ion by EEPROM for all LEDs for pre- driver
funct ionalit y
Support for SR- I OV
Manageabi l i t y
Eight VLAN L2 filt ers
16 flex L3 port filt ers
Four Flexible TCO filt ers
Four L3 address filt ers ( I Pv4)
Advanced pass t hrough- compat ible management packet
t ransmit / receive support
SMBus int erface t o an ext ernal manageabilit y cont roller
NC- SI int erface t o an ext ernal manageabilit y cont roller
Four L3 address filt ers ( I Pv6)
Four L2 address filt ers
I nt el
82599 10 GbE Cont r ol l er Copy r i ght

2
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THE FAI LURE OF THE I NTEL PRODUCT COULD CREATE A SI TUATI ON WHERE PERSONAL I NJURY OR DEATH MAY OCCUR.
I nt el may make changes t o specificat ions and product descript ions at any t ime, wit hout not ice. Designers must not rely on t he absence or
charact erist ics of any feat ures or inst ruct ions marked "reserved" or "undefined. " I nt el reserves t hese for fut ure definit ion and shall have no
responsibilit y what soever for conflict s or incompat ibilit ies arising from fut ure changes t o t hem. The informat ion here is subj ect t o change wit hout not ice.
Do not finalize a design wit h t his informat ion.
The product s described in t his document may cont ain design defect s or errors known as errat a which may cause t he product t o deviat e from published
specificat ions. Current charact erized errat a are available on request .
Cont act your local I nt el sales office or your dist ribut or t o obt ain t he lat est specificat ions and before placing your product order.
Copies of document s which have an order number and are referenced in t his document , or ot her I nt el lit erat ure, may be obt ained by calling 1- 800- 548-
4725, or go t o: ht t p: / / www. int el.com/ design/ lit erat ure.ht m.
I nt el and I nt el logo are t rademarks or regist ered t rademarks of I nt el Corporat ion or it s subsidiaries in t he Unit ed St at es and ot her count ries.
* Ot her names and brands may be claimed as t he propert y of ot hers.
Copyright 2011, I nt el Corporat ion. All Right s Reserved.
Rev i si on Hi st or y / Cont ent s I nt el

3
Rev i si ons
Rev Dat e Not es
0.5 May 2008 I nit ial release ( I nt el Confident ial) . This release cont ains advanced informat ion.
0.6 Oct 2008 Updat ed t o reflect development s, correct ions.
0. 75 Feb 2009 Maj or updat e ( all sect ions) - reflect s lat est device development s and correct ions.
0. 76 March 2009
Updat ed t he following sect ions: Programming I nt erface, Manageabilit y, NVM, I nit ializat ion, Power Management ,
and I nt erconnect s.
1. 0 March 2009 Maj or updat e ( all sect ions) - reflect s lat est device development s and correct ions.
1.5 May 2009 Maj or updat e ( all sect ions) - reflect s lat est device development s and correct ions.
1.9 June 2009 Minor updat e ( all sect ions) - reflect s lat est device development s and correct ions.
2.0 July 2009 I nit ial release ( I nt el Public) .
2. 01 July 2009 Added x8 lane not e t o Sect ion 1. 2. 1.
2.1 Oct ober 2009
Changed j umbo frame size from KB t o byt es ( all occurrences) .
Changed XTAL_25_MODE t o RSVDAC6_VCC.
Updat ed sect ion 2.1.4 ( changed t ype from T/ s t o O) .
Added F20 and H7 t o t he t able in sect ion 2. 1.12.
Changed OSC_FREQ_SEL t o RSVDAC6_VCC.
Correct ed PCI e versions t o PCI e V2. 0 ( 2. 5GT/ s or 5GT/ s) .
Updat ed t he t able in sect ion 3.2.7.2.1 ( added t ext t o t he vendor I D column) .
Updat ed t he j umbo frame calculat ions in sect ions 3. 7. 7. 3. 3, 3. 7. 7. 3. 4, and 3.7.7.3.5.
Added sect ion 4. 6. 13 Alt ernat e MAC Address Support .
Updat ed sect ion 5.2.2 Auxiliary Power Usage.
Added t ext t o sect ion 6. 3. 6 Alt ernat e Et hernet MAC Address - Word Address 0x37.
Updat ed Table 6. 1 ( added / 1 t o row 4) .
Updat ed sect ion 6.4.5.8.
Added L34TI MI R regist er name t o t he Queue Enable bit in sect ion 8. 2.3.7.19.
Correct ed t he D10GMP and LMS bit descript ions in sect ion 8.2.3.22. 19.
Correct ed t he LP AN page D low bit descript ion in sect ion 8.2.3.22. 23.
Updat ed t he PRDC bit descript ion is sect ion 8.2.3.23. 75.
Changed t he bit lengt h ( 31 t o 8 t o 31 t o 0) t o t he t able heading in sect ion 8. 2. 3. 25.12.
Updat ed t he Rest art _AN bit descript ion in sect ion 8. 2. 3. 23.22.
Correct ed t he bit 8 descript ion in sect ion 9.3.7.1.4.
Updat ed sect ion 10. 2. 2. 2.4 ( bit s RAGEN and TFOENODX; read/ writ e value) .
Added t ext Jumbo packet s above 2 KB . . . t o Filt ering except ions in sect ion 10.3.1.
Correct t he Buffer Lengt h ( byt e 1) descript ion in sect ion 10.5.3.8. 2.
Changed t he t it le of t able 11.6, 11. 7, and 11.8.
Changed Wat t s t o mW in t he Power row of t able 11.6.
Updat ed t he power values in t able 11.7 and 11.8.
Updat ed t he mechanical package drawing in sect ion 11. 5. 4.
Added power summary t able ( t able 11.6) .
Updat ed sect ion 1.2.1, 3.1.4.5.3, 5.2.5.3. 2 ( not e) , and 6. 4. 5.2.2 ( bit descript ions) .
Updat ed bit descript ions for MRQE, RRM, TDRM, and PRDC.
Updat ed t ables in sect ions 10.3.1, 10.5.1.13.1, and 10.5. 2. 1. 5.
Added Single Port Power t able ( t able 11. 8)
Added SFI opt ics references.
Changed t he bit name in sect ion 5.3.1 from APM Wake Up ( APM) t o APM Enable ( APME) .
I nt el
82599 10 GbE Cont r ol l er Revi si on Hi st or y / Cont ent s

4
2.2 January 2010
Updat ed BX4 spec reference ( changed 1000BASE- BX4 t o 10GBASE- BX4) .
Added j umbo frame KB value t o not e aft er Table 1.2.
Added new sect ion 1.6.2 Byt e Count .
Added BX4 and CX4 references.
Updat ed t he not e in sect ion 2.1.8.
Updat ed pin name ( SDP0_6) in sect ion 2.1.10.
Updat ed sect ion 3. 1. 4. 5. 3 ( Relaxed Ordering) ; last paragraph.
Added BX4 info t o sect ion 3.7.
Added new BX4 sect ion ( 3.7.1.5) .
Updat ed sect ion 3. 7. 4. 4 ( link speed) .
Updat ed sect ion 3. 7. 7. 3. 3 and 3.7.7.3.5 ( j umbo frame values) .
Added not e aft er t able 3. 27 ( I PG pacing feat ure) .
Added VFLR not e aft er t able 4.6.
Added BX4 reference t o sect ion 4. 6. 4. 2.
Added I PG pacing feat ure not e at t he end of sect ion 4.6.11. 4.
Added j umbo frame value t o sect ion 4. 6.11.4 and t able 4.9 ( KB value) .
Changed t he bit name in sect ion 5.3.1 from APM Wake Up ( APM) t o APM Enable ( APME) .
Updat ed t he not e in sect ion 5.2.5.3.2 ( DMA complet ions) .
Changed GI O Mast er Disable t o PCI e Mast er Disable ( t hroughout ent ire EAS) .
Changed GI O Mast er Enable St at us t o PCI e Mast er Enable St at us ( t hroughout ent ire EAS) .
Updat ed bullet list in sect ion 5.3.1 and added WKEN bit not e at t he end of sect ion 5.3.1.
Swapped fields Possible Len/ LLC/ SNAP Header and Possible VLAN Tag in sect ions 5.3.3.1.4. t hrough
5.3.3. 1. 7 and sect ions 5.3.3. 2. 1 and 5.3.3.2.2.
Updat ed sect ion 6. 3. 5. 4 ( changed GI O t o PCI e; bit 3 descript ion) .
Changed t he default set t ing for CDQMH in sect ion 6.3.6. 5 t o 0x1404.
Updat ed sect ion 6. 3. 5. 22 ( MSI X and CDO bit definit ions) .
Removed old 6. 3. 6. 7 sect ion t it le ( Spare 0/ 1 - Offset 0x05) .
Added 5- t uple not e t o sect ion 7. 1. 2. 5.
Removed sub- bullet under 4- bit RSS Type field in sect ion 7. 1. 2.8.
Removed TcpI Pv6Ex, I Pv6Ex and UdpI PV6E info from sect ion 7.1.2.8.1. Updat ed TCP segment bullet and I Pv4
packet sub- bullet in sect ion 7. 1.2.8.1.
Updat ed t able 7.10 ( Dest inat ion Address/ Port and Source Address/ Port ; first row) .
Changed RXCTL t o DCA_RXCTL[ n] under t able 7.15 ( Packet Buffer Address ( 64) paragraph) .
Changed descript ors per queue value from 64 t o 40 in sect ion 7. 2. 3. 3.
Updat ed figure 7. 39 ( changed BCN t o t ransmit rat e scheduler) .
Updat ed SecTag bullet descript ion in sect ion 7. 8. 4.
Updat ed t he APME bit descript ion in sect ion 8. 2. 3. 2.9.
Updat ed t he MRQE bit descript ion in sect ion 8.2.3.7.12.
Added a not e t o t he Queue Enable bit descript ion in sect ion 8.2.3.7.19.
Removed t he not e from sect ion 8.2.3.8.5.
Changed GI O t o PCI e in sect ion 8. 2.2.1.1 ( bit 2 descript ion) .
Updat ed t he RRM bit descript ion in sect ion 8. 2. 2. 11.1.
Updat ed SECTX_OFF_DI S and ECC_TXERR bit descript ions in sect ion 8.2.2.13. 2.
Updat ed SECRX_OFF_DI S and ECC_RXERR bit descript ions in sect ion 8.2.2. 13. 7.
Added a not e t o t he KX_support bit descript ion in sect ion 8. 2. 2. 23.22.
Updat ed t he PRDC bit descript ion in sect ion 8.2.2.24. 75.
Updat ed bit 4 descript ion ( WKEN) in sect ion 8. 2. 2. 25.1.
Added a VF Mailbox not e t o sect ion 8.3.5.1.5.
Changed RW t o RO in sect ion 9.3.10. 13 t it le.
Updat ed t he Filt ers t able in sect ion 10. 3.1.
Added not e t o sect ion 10.5.1.13. 1 ( TCO Mode reference) .
Updat ed t he TCO Mode t able in sect ion 10. 5.2.1.4.
Updat ed sect ion 11. 3. 1. 1 ( rise t ime relat ionships) .
Added Single Port Power t able ( Table 11.8)
Changed all SFI Opt ics references t o uncondit ional t ext ( now exposed t o ext ernal cust omers) .
Added single port power numbers ( t able 11. 8) .
Added BX4 t o sect ion 11.4.4.
Changed cryst al load capacit ance t o 27 pF.
2.3 April 2010
Updat ed sect ion 3. 7. 7. 1. 4 ( changed TXOFF t o TC_XON) .
Changed VMBMEM t o VFMBMEM.
Updat ed sect ion 5. 3. 2 ( last paragraph) .
Added a not e aft er t he t able in sect ion 6.4.2. 3.
Updat ed sect ion 8. 2. 3. 5. 13 - changed VT31 t o VT32.
Changed all occurrences of SPD t o SDP in sect ion 8.2.3.1.4.
Updat ed t he TC_XON field descript ion.
Updat ed Table 9.6 - Address Space ( low regist er for 64- bit memory BARs) descript ion.
Added recommended and minimum EEPROM sizes t o sect ion 12.6.2.

5
2.4 Sept ember 2010
The following was updat ed and or changed for t his release:
Sect ion 4.6.11. 3. 1 ( changed MRQC.VT_Ena t o MTQC.VT_Ena) .
Sect ion 4.6.11. 3. 3 ( changed via set t ing RTTDQSEL first for t he lowest indexed queue of a pool t o via
set t ing RTTDQSEL first for t he pool index ) .
Sect ion 4.6.11. 6. 1 ( updat ed first st ep under Refill Credit s ) .
Sect ion 4.6.12 ( updat ed Securit y Offload descript ion) .
Sect ion 6.3.2.3 ( APM Enable Port 1/ 0 bit descript ions) .
Sect ion 6.3.3 ( PBA Number Module Word Address 0x15- 0x16) .
Sect ion 6.3.8 ( Checksum Word Calculat ion ( Word 0x3F) ) .
Sect ion 6.4.5.5 ( PCI e Cont rol 1 Offset 0x04) .
Sect ion 6.4.5.8 ( PCI e Cont rol 3 Offset 0x07) .
Sect ion 7.1.2.3 ( L2 Et hert ype Filt ers, st ep 9) .
Sect ion 7.1.2.5 ( L3/ L4 5- t uple Filt ers, removed I f t he packet is mirrored or replicat ed . . ..
Sect ion 7.1.2.7 ( Flow Direct or Filt ers, removed I n case of mirroring or replicat ion. . ..
Sect ion 7.2.5.3 ( added a not e t o Tx SCTP CRC Offload) .
Sect ion 8.2.3.11. 4 ( TXDQ_I DX bit descript ion) .
Sect ion 8.2.3.11. 5 ( regist er RTTDT1C descript ion) .
Sect ion 8.2.3.10. 3 ( VT bit descript ion) .
Sect ion 8.2.3.8.2 ( VET bit descript ion) .
Sect ion 8.2.3.11. 9 ( DCB Transmit Descript or Plane T2 Config bit descript ions) .
Sect ion 8.2.3.13 ( updat ed Securit y Offload descript ion) .
Sect ion 8.2.3.13. 5 ( updat ed MI NSECI FG and SECTXDCB bit descript ions) .
Sect ion 8.2.3.21. 22 ( updat ed Rx Queue I ndex bit descript ion) .
I nt el

6
2.5 November 2010
The following was updat ed and or changed for t his release:
Sect ion 2. 1. 8 ( changed pullup t o pull- down in t he not e following t he t able) .
Sect ion 6. 4. 2 ( updat ed bit 15 bit descript ion) .
Sect ion 7. 1. 2. 2 ( updat ed RSS queues reference) .
Sect ion 7. 1. 11 ( updat ed I Pv6 filt er descript ion) .
Sect ion 7. 7. 2. 2 ( added a not e about using advanced t ransmit descript ors in DCB mode) .
Sect ion 8. 2. 3. 6. 1 ( added not at ion about t he EI CR regist er) .
Sect ion 8. 2. 3. 8. 4 ( updat ed t he RQPL bit descript ion) .
Sect ion 8. 2. 3. 25. 3 ( updat ed t he WUS regist er descript ion) .
Sect ion 9. 3. 10. 7 ( updat ed bit descript ion for bit s 9: 4) .
Sect ion 11. 4. 5. 1 ( changed load capacit ance value t o 20 pF) .
Added new Table 12- 1 ( Microst rip Trace Dimensions for SFI Using Different Dielect ric
Mat erials) .
Sect ion 12. 12. 1. 1 ( updat ed t he part numbers for recommended cryst als) .
Updat ed Figures 12- 20 and 12- 21 ( changed 10 KO t o 100 O) .
Sect ion 13. 11. 4 ( updat ed t he maximum st at ic normal load value) .
2.6 December 2010
Updat ed sect ion 3. 4. 7 EEPROM Recovery ( changed Dat a Byt e value from 0xD8 t o 0xB6) .
Added reference clock specificat ions not e t o sect ion 11. 4. 3.
Updat ed t able 11. 25 ( changed dut y cycle values and added p- noise for non- high serial speed
paramet er.
Added new figure 11. 16 ( refclk phase noise as a funct ion of frequency) .
2.7 April 2011
Updat ed Table 1. 5 ( Flow Direct or Filt ers) .
Revised sect ion 2. 1. 13 ( LAN1_DI S_N and LAN1_DI S_N name and funct ion descript ion) .
Revised sect ion 3. 1. 4. 6. 1 ( changed t wo credit s t o four credit s under Rules for FC
updat es ) .
Revised t able 4. 4 ( LAN Disable St rapping Pins row; removed X from PCI e PERST# and I n-
band PCI e Reset
columns) .
Added SECTXMI NI FG. SECTXDCB field reference t o sect ions 4. 6. 11. 3. 1 4. 6. 11. 3. 2.
Revised sect ion 6. 4. 5. 11 ( PCI e Dummy Device I D Offset 0x0A; changed default value t o
0x10A6) .
Revised sect ion 7. 1. 2. 7 ( Flow Direct or Filt ers) .
Revised t able 7. 5 ( Flow Direct or Filt ers) .
Revised sect ion 7. 1. 2 ( added cross reference t o last bullet ) .
Revised sect ion 7. 1. 2. 1 ( Queuing in a Non- virt ualized Environment ) .
Revised sect ion 7. 1. 2. 2 ( Queuing in a Virt ualized Environment ) .
Revised t able 7. 19 ( Receive Errors ( RDESC. ERRORS) Layout ) .
Revised sect ion 7. 1. 7. 1 ( Fet ch On Demand; removed Figure 12 reference) .
Revised sect ion 8. 2. 3. 21. 1 ( Flow Direct or Filt ers Cont rol Regist er; bit s 1: 0 descript ion) .
Added a FTFT regist er not e t o sect ion 8. 2. 3. 25. 12.
Revised t he t ables at t he end of sect ion 8. 2. 3. 24. 9 ( Flexible Host Filt er Table Regist ers
FHFT) .
Revised sect ion 8. 2. 3. 22. 8 ( MAC Core Cont rol 0 Regist er; changed MDCSPD default value t o
1b) .
Revised sect ion 8. 2. 3. 8. 6 ( Receive Descript or Cont rol RXDCTL[ n] ; correct ed bit
assignment s) .

7
Cont ent s
1.0 I nt r oduct i on ...... ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... ..... .... ........ 13
1.1 Scope . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. .. 13
1.2 Product Overview . .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 13
1. 2.1 82599 Silicon/ Soft ware Feat ures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 13
1. 2.2 Syst em Configurat ions. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 14
1.3 Ext ernal I nt erfaces . .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 16
1. 3.1 PCI - Express* ( PCI e* ) I nt erface . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 16
1. 3.2 Net work I nt erfaces . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 16
1. 3.3 EEPROM I nt erface . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 17
1. 3.4 Serial Flash I nt erface .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 17
1. 3.5 SMBus I nt erface . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 17
1. 3.6 NC- SI I nt erface .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 18
1. 3.7 MDI O I nt erfaces . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 18
1. 3.8 I 2C I nt erfaces .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..18
1. 3.9 Soft ware- Definable Pins ( SDP) I nt erface ( General- Purpose I / O) . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 19
1. 3.10 LED I nt erface . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 19
1.4 Feat ures Summary . .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 19
1.5 Overview of New Capabilit ies Beyond t he 82598 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 23
1. 5.1 Securit y. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 23
1. 5.2 Transmit Rat e Limit ing .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 23
1. 5.3 Fibre Channel over Et hernet ( FCoE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 24
1. 5.4 Performance .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 24
1. 5.5 Rx/ Tx Queues and Rx Filt ering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 25
1. 5.6 I nt errupt s .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 25
1. 5.7 Virt ualizat ion.. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 25
1. 5.8 VPD .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 26
1. 5.9 Double VLAN.. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 26
1. 5. 10 Time Sync I EEE 1588 Precision Time Prot ocol ( PTP) .. .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . .. . . . . . . . . .. . . . . 26
1.6 Convent ions. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 26
1. 6.1 Terminology and Acronyms . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 26
1. 6.2 Byt e Count . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 27
1. 6.3 Byt e Ordering. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 27
1.7 Regist er/ Bit Not at ions . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 27
1.8 References .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 27
1.9 Archit ect ure and Basic Operat ion .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 29
1. 9.1 Transmit ( Tx) Dat a Flow . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 29
1. 9.2 Receive ( Rx) Dat a Flow.. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 30
2.0 Pi n I nt er f ace ..... ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... ..... .... ........ 31
2.1 Pin Assignment .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 31
2. 1.1 Signal Type Definit ion.. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 31
2. 1.2 PCI e Symbols and Pin Names .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 31
2. 1.3 MAUI .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 33
2. 1.4 EEPROM .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 34
2. 1.5 Serial Flash .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 35
2. 1.6 SMBus. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 35
2. 1.7 I
2
C . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 35
2. 1.8 NC- SI .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 36
2. 1.9 MDI O .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 36
2. 1.10 Soft ware Defined Pins ( SDPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 37
2. 1.11 LEDs . .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 37
2. 1.12 RSVD and No Connect Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 38
2. 1.13 Miscellaneous . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 40
2. 1.14 JTAG. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 40
2. 1.15 Power Supplies . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 41
2. 1.16 Pull- Ups. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 41
2.2 Ball Out Top Level . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 44
3.0 I nt er connect s.... ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... ...... ... ........ 47
3.1 PCI - Express* ( PCI e* ) .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 47
3. 1.1 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 47
3. 1.2 General Funct ionalit y.. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 49
3. 1.3 Host I nt erface .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 49
3. 1.4 Transact ion Layer . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 52
3. 1.5 Link Layer .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 58
3. 1.6 Physical Layer .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 59
3. 1.7 Error Event s and Error Report ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 64
3. 1.8 Performance Monit oring . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 69
3.2 SMBus .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 70
3. 2.1 Channel Behavior .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 70
3. 2.2 SMBus Addressing .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 70
3. 2.3 SMBus Not ificat ion Met hods .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 71
I nt el

8
3.2. 4 Receive TCO Flow . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 73
3.2. 5 Transmit TCO Flow.. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 73
3.2. 6 Concurrent SMBus Transact ions . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 75
3.2. 7 SMBus ARP Funct ionalit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 75
3.2. 8 LAN Fail- Over Through SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 79
3.3 Net work Cont roller Sideband I nt erface ( NC- SI ) .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 79
3.3. 1 Elect rical Charact erist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 79
3.3. 2 NC- SI Transact ions . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 79
3.4 EEPROM .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 80
3.4. 1 General Overview . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 80
3.4. 2 EEPROM Device .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 80
3.4. 3 EEPROM Vit al Cont ent . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 80
3.4. 4 Soft ware Accesses .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 80
3.4. 5 Signat ure Field . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..81
3.4. 6 Prot ect ed EEPROM Space .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 81
3.4. 7 EEPROM Recovery . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 82
3.4. 8 EEPROM Deadlock Avoidance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 83
3.4. 9 VPD Support .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 83
3.5 Flash. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. .. .. 85
3.5. 1 Flash I nt erface Operat ion .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 85
3.5. 2 Flash Writ e Cont rol . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 85
3.5. 3 Flash Erase Cont rol . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 86
3.5. 4 Flash Access Cont ent ion. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 86
3.6 Configurable I / O Pins Soft ware- Definable Pins ( SDP) .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 86
3.7 Net work I nt erface ( MAUI I nt erface) . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 90
3.7. 1 10 GbE I nt erface .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 90
3.7. 2 GbE I nt erface . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 100
3.7. 3 SGMI I Support . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 103
3.7. 4 Aut o Negot iat ion For Backplane Et hernet and Link Set up Feat ures . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 104
3.7. 5 Transceiver Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 107
3.7. 6 Management Dat a I nput / Out put ( MDI O) I nt erface.. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 109
3.7. 7 Et hernet Flow Cont rol ( FC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 113
3.7. 8 I nt er Packet Gap ( I PG) Cont rol and Pacing .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 122
3.7. 9 MAC Speed Change at Different Power Modes .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 123
4.0 I ni t i al i zat i on ..... ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... .... ..... ...... 127
4.1 Power Up. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 127
4.1. 1 Power- Up Sequence .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 127
4.1. 2 Power- Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 128
4.2 Reset Operat ion . .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 129
4.2. 1 Reset Sources .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 129
4.2. 2 Reset in PCI - I OV Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 132
4.2. 3 Reset Effect s .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 133
4.3 Queue Disable.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 136
4.4 Funct ion Disable . .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 136
4.4. 1 General . .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 136
4.4. 2 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 136
4.4. 3 Cont rol Opt ions .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 138
4.4. 4 Event Flow for Enable/ Disable Funct ions . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 138
4.5 Device Disable.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 139
4.5. 1 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 139
4.5. 2 BI OS Disable of t he Device at Boot Time by Using t he St rapping Opt ion . .. .. .. .. .. .. .. .. .. .. .. .. .. 139
4.6 Soft ware I nit ializat ion and Diagnost ics.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 140
4.6. 1 I nt roduct ion . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 140
4.6. 2 Power- Up St at e .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 140
4.6. 3 I nit ializat ion Sequence. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 140
4.6. 4 100 Mb/ s, 1 GbE, and 10 GbE Link I nit ializat ion . .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 141
4.6. 5 I nit ializat ion of St at ist ics. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 142
4.6. 6 I nt errupt I nit ializat ion . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 142
4.6. 7 Receive I nit ializat ion . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 143
4.6. 8 Transmit I nit ializat ion .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 146
4.6. 9 FCoE I nit ializat ion Flow .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 147
4.6. 10 Virt ualizat ion I nit ializat ion Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 147
4.6. 11 DCB Configurat ion .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 150
4.6. 12 Securit y I nit ializat ion. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 160
4.6. 13 Alt ernat e MAC Address Support . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 161
5.0 Pow er Management and Del i ver y . ......... ......... .......... ......... ......... ......... ......... .......... ......... ...... 163
5.1 Power Target s and Power Delivery .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 163
5.2 Power Management . .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 163
5.2. 1 I nt roduct ion t o t he 82599 Power St at es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 163
5.2. 2 Auxiliary Power Usage . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 163
5.2. 3 Power Limit s by Cert ain Form Fact ors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 164
5.2. 4 I nt erconnect s Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 164
5.2. 5 Power St at es.. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 167
5.2. 6 Timing of Power- St at e Transit ions .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 170

9
5.3 Wake Up . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 174
5. 3.1 Advanced Power Management Wake Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 174
5. 3.2 ACPI Power Management Wake Up . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 174
5. 3.3 Wake- Up Packet s.. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 176
5. 3.4 Wake Up and Virt ualizat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 181
6.0 Non- Vol at i l e Memor y Map ... ......... ......... ......... .......... ......... ......... ......... ......... .......... ......... ...... 183
6.1 EEPROM General Map .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 183
6.2 EEPROM Soft ware. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. 184
6. 2.1 SW Compat ibilit y Module Word Address 0x10- 0x14. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 184
6. 2.2 PBA Number Module Word Address 0x15- 0x16 . .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 184
6. 2.3 iSCSI Boot Configurat ion Word Address 0x17 . .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 184
6. 2.4 VPD Module Point er Word Address 0x2F .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 185
6. 2.5 EEPROM PXE Module Word Address 0x30- 0x36 .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 185
6. 2.6 Alt ernat e Et hernet MAC Address Word Address 0x37. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 185
6. 2.7 Checksum Word Calculat ion ( Word 0x3F) .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 185
6. 2.8 SAN MAC Addresses Point er Word Address 0x28. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 187
6.3 EEPROM Hardware Sect ions . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 187
6. 3.1 EEPROM Hardware Sect ion Aut o- Load Sequence. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 187
6. 3.2 EEPROM I nit Module .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 188
6. 3.3 PCI e Analog Configurat ion Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 189
6. 3.4 Core 0/ 1 Analog Configurat ion Modules. . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 190
6. 3.5 PCI e General Configurat ion Module . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 190
6. 3.6 PCI e Configurat ion Space 0/ 1 Modules.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 196
6. 3.7 LAN Core 0/ 1 Modules . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 198
6. 3.8 MAC 0/ 1 Modules.. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 200
6. 3.9 CSR 0/ 1 Aut o Configurat ion Modules .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 205
6.4 Firmware Module .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 206
6. 4.1 Test Configurat ion Module. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 207
6. 4.2 Common Firmware Paramet ers ( Global MNG Offset 0x3) . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 207
6. 4.3 Pass Through LAN 0/ 1 Configurat ion Modules .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 208
6. 4.4 Sideband Configurat ion Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 213
6. 4.5 Flexible TCO Filt er Configurat ion Module . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 215
6. 4.6 NC- SI Microcode Download Module. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 216
6. 4.7 NC- SI Configurat ion Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 216
7.0 I nl i ne Funct i ons ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... ....... .. ...... 219
7.1 Receive Funct ionalit y .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 219
7. 1.1 Packet Filt ering. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 220
7. 1.2 Rx Queues Assignment .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 224
7. 1.3 MAC Layer Offloads . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 248
7. 1.4 Receive Dat a St orage in Syst em Memory .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 248
7. 1.5 Legacy Receive Descript or Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 249
7. 1.6 Advanced Receive Descript ors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 251
7. 1.7 Receive Descript or Fet ching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 259
7. 1.8 Receive Descript or Writ e- Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 260
7. 1.9 Receive Descript or Queue St ruct ure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 260
7. 1.10 Header Split t ing.. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 263
7. 1.11 Receive Checksum Offloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 265
7. 1.12 SCTP Receive Offload .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 268
7. 1.13 Receive UDP Fragment at ion Checksum . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 268
7.2 Transmit Funct ionalit y . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 271
7. 2.1 Packet Transmission.. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 271
7. 2.2 Transmit Cont ext s. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 280
7. 2.3 Transmit Descript ors . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 281
7. 2.4 TCP and UDP Segment at ion. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 295
7. 2.5 Transmit Checksum Offloading in Non- segment at ion Mode .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 302
7.3 I nt errupt s.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 307
7. 3.1 I nt errupt Regist ers.. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 307
7. 3.2 I nt errupt Moderat ion . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 310
7. 3.3 TCP Timer I nt errupt .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 313
7. 3.4 Mapping of I nt errupt Causes . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 313
7.4 802.1q VLAN Support .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 320
7. 4.1 802. 1q VLAN Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 320
7. 4.2 802. 1q Tagged Frames .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 320
7. 4.3 Transmit t ing and Receiving 802.1q Packet s . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 321
7. 4.4 802. 1q VLAN Packet Filt ering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 321
7. 4.5 Double VLAN and Single VLAN Support . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 322
7.5 Direct Cache Access ( DCA) . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 324
7. 5.1 PCI e TLP Format for DCA .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 325
7.6 LEDs. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 326
7.7 Dat a Cent er Bridging ( DCB) . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 327
7. 7.1 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 327
7. 7.2 Transmit - side Capabilit ies . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 329
7. 7.3 Receive- Side Capabilit ies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 343
7.8 LinkSec . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 348
I nt el

10
7.8. 1 Packet Format .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 348
7.8. 2 LinkSec Header ( SecTag) Format . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 349
7.8. 3 LinkSec Management KaY ( Key Agreement Ent it y) . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 350
7.8. 4 Receive Flow .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 351
7.8. 5 Transmit Dat a Pat h . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 353
7.8. 6 LinkSec and Manageabilit y .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 354
7.8. 7 Key and Tamper Prot ect ion . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 354
7.8. 8 LinkSec St at ist ics.. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 355
7.9 Time SYNC ( I EEE1588 and 802. 1AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 356
7.9. 1 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 356
7.9. 2 Flow and Hardware/ Soft ware Responsibilit ies. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 356
7.9. 3 Hardware Time Sync Element s. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 358
7.9. 4 Time Sync Relat ed Auxiliary Element s. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 360
7.9. 5 PTP Packet St ruct ure . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 361
7.10 Virt ualizat ion.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 364
7.10.1 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 364
7.10.2 PCI - SI G SR- I OV Support . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 367
7.10.3 Packet Swit ching. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 378
7.10.4 Virt ualizat ion of Hardware . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 386
7.11 Receive Side Coalescing ( RSC) . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 388
7.11.1 Packet Viabilit y for RSC Funct ionalit y .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 390
7.11.2 Flow I dent ificat ion and RSC Cont ext Mat ching.. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 392
7.11.3 Processing New RSC.. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 393
7.11.4 Processing Act ive RSC . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 393
7.11.5 Packet DMA and Descript or Writ e Back . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 395
7.11.6 RSC Complet ion and Aging .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 397
7.12 I Psec Support .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 399
7.12.1 Overview . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 399
7.12.2 Hardware Feat ures List .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 399
7.12.3 Soft ware/ Hardware Demarcat ion.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 401
7.12.4 I Psec Format s Exchanged Bet ween Hardware and Soft ware . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 402
7.12.5 TX SA Table . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 405
7.12.6 TX Hardware Flow . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 406
7.12.7 AES- 128 Operat ion in Tx . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 408
7.12.8 RX Descript ors.. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 409
7.12.9 Rx SA Tables.. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 409
7.12.10 RX Hardware Flow wit hout TCP/ UDP Checksum Offload . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 411
7.12.11 RX Hardware Flow wit h TCP/ UDP Checksum Offload.. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 412
7.12.12 AES- 128 Operat ion in Rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 412
7.13 Fibre Channel over Et hernet ( FCoE) . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 414
7.13.1 I nt roduct ion . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 414
7.13.2 FCoE Transmit Operat ion .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 415
7.13.3 FCoE Receive Operat ion . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 420
7.14 Reliabilit y .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. .. 435
7.14.1 Memory I nt egrit y Prot ect ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 435
7.14.2 PCI e Error Handling. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 435
8.0 Pr ogr ammi ng I nt er f ace ....... ......... ......... ......... .......... ......... ......... ......... ......... .......... ......... .... .. 437
8.1 Address Regions . .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 437
8.1. 1 Memory- Mapped Access. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 437
8.1. 2 I / O- Mapped Access . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 438
8.1. 3 Regist ers Terminology . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 439
8.2 Device Regist ers PF. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. 439
8.2. 1 MSI - X BAR Regist er Summary PF. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 439
8.2. 2 Regist ers Summary PF BAR 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 439
8.2. 3 Det ailed Regist er Descript ions PF . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 453
8.3 Device Regist ers VF. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. 596
8.3. 1 Regist ers Allocat ed Per Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 596
8.3. 2 Non- Queue Regist ers. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 596
8.3. 3 MSI X Regist er Summary VF BAR 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 597
8.3. 4 Regist ers Summary VF BAR 0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 598
8.3. 5 Det ailed Regist er Descript ions VF .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 599
9.0 PCI e Pr ogr ammi ng I nt er f ace ....... ......... ......... .......... ......... ......... ......... ......... .......... ......... ...... 60 7
9.1 PCI Compat ibilit y .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 607
9.2 Configurat ion Sharing Among PCI Funct ions .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 608
9.3 PCI e Regist er Map .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 609
9.3. 1 Regist er At t ribut es .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 609
9.3. 2 PCI e Configurat ion Space Summary . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 609
9.3. 3 Mandat ory PCI Configurat ion Regist ers Except BARs . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 610
9.3. 4 Subsyst em I D Regist er ( 0x2E; RO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 613
9.3. 5 Cap_Pt r Regist er ( 0x34; RO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 613
9.3. 6 Mandat ory PCI Configurat ion Regist ers BARs.. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 613
9.3. 7 PCI e Capabilit ies. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 614
9.3. 8 MSI - X Capabilit y . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 618
9.3. 9 VPD Regist ers. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 622

11
9. 3.10 PCI e Configurat ion Regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 623
9.4 PCI e Ext ended Configurat ion Space. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 631
9. 4.1 Advanced Error Report ing Capabilit y ( AER) .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 632
9. 4.2 Serial Number .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 635
9. 4.3 Alt ernat e Rout ing I D I nt erpret at ion ( ARI ) Capabilit y St ruct ure . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 637
9. 4.4 I OV Capabilit y St ruct ure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 638
9.5 Virt ual Funct ions Configurat ion Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 644
9. 5.1 Mandat ory Configurat ion Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 646
9. 5.2 PCI Capabilit ies .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 647
10.0 Manageabi l i t y .... ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... ..... .... ...... 651
10.1 Plat form Configurat ions . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 651
10. 1. 1 On- Board BMC Configurat ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 651
10. 1. 2 t he 82599 NI C.. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 652
10.2 Pass Through ( PT) Funct ionalit y .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 652
10. 2. 1 DMTF NC- SI Mode. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 652
10. 2. 2 SMBus Pass Through ( PT) Funct ionalit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 654
10.3 Manageabilit y Receive Filt ering . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 657
10. 3. 1 Overview and General St ruct ure .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 657
10. 3. 2 L2 Et herType Filt ers .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 659
10. 3. 3 VLAN Filt ers - Single and Double VLAN Cases .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 660
10. 3. 4 L3 and L4 Filt ers . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 660
10. 3. 5 Manageabilit y Decision Filt ers .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 662
10. 3. 6 Possible Configurat ions .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 663
10.4 LinkSec and Manageabilit y . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 665
10. 4. 1 Handover of LinkSec Responsibilit y Bet ween BMC and Host . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 666
10.5 Manageabilit y Programming I nt erfaces . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 668
10. 5. 1 NC- SI Programming .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 668
10. 5. 2 SMBus Programming . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 713
10. 5. 3 Manageabilit y Host I nt erface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 748
10. 5. 4 Soft ware and Firmware Synchronizat ion.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 751
11.0 El ect r i cal / Mechani cal Speci f i cat i on ..... ......... .......... ......... ......... ......... ......... .......... ......... ...... 7 55
11.1 I nt roduct ion. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 755
11.2 Operat ing Condit ions. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 755
11. 2. 1 Absolut e Maximum Rat ings . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 755
11. 2. 2 Recommended Operat ing Condit ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 756
11.3 Power Delivery . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 756
11. 3. 1 Power Supply Specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 756
11. 3. 2 I n- Rush Current . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 758
11.4 DC/ AC Specificat ion .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 758
11. 4. 1 DC Specificat ions .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 758
11. 4. 2 Digit al I / F AC Specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 762
11. 4. 3 PCI e I nt erface AC/ DC Specificat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 773
11. 4. 4 Net work ( MAUI ) I nt erface AC/ DC Specificat ion. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 773
11. 4. 5 SerDes Cryst al/ Reference Clock Specificat ion. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 774
11.5 Package .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 778
11. 5. 1 Mechanical . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 778
11. 5. 2 Thermal. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 778
11. 5. 3 Elect rical . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 778
11. 5. 4 Mechanical Package .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 779
11.6 Devices Support ed.. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 779
11. 6. 1 Flash. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 779
11. 6. 2 EEPROM .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 780
12.0 Desi gn Consi der at i ons and Gui del i nes... ......... .......... ......... ......... ......... ......... .......... ......... ...... 781
12.1 Connect ing t he PCI e I nt erface .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 781
12. 1. 1 Link Widt h Configurat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 781
12. 1. 2 Polarit y I nversion and Lane Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 781
12. 1. 3 PCI e Reference Clock .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 782
12. 1. 4 PCI e Analog Bias Resist or . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 782
12. 1. 5 Miscellaneous PCI e Signals.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 782
12. 1. 6 PCI e Layout Recommendat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 782
12.2 Connect ing t he MAUI I nt erfaces.. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 782
12. 2. 1 MAUI Channels Lane Connect ions. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 782
12. 2. 2 MAUI Bias Resist or .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 783
12. 2. 3 XAUI , KX/ KR, BX4, CX4, BX and SFI + Layout Recommendat ions .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 783
12. 2. 4 Board St ack- Up Example .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 783
12. 2. 5 Trace Geomet ries . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 784
12. 2. 6 Ot her High- Speed Signal Rout ing Pract ices.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 786
12. 2. 7 Reference Planes .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 790
12. 2. 8 Dielect ric Weave Compensat ion . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 791
12. 2. 9 I mpedance Discont inuit ies . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 792
12. 2. 10 Reducing Circuit I nduct ance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 792
12. 2. 11 Signal I solat ion. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 793
12. 2. 12 Power and Ground Planes . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 793
12. 2. 13 KR and SFI + Recommended Simulat ions. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 798
I nt el

12
12.2.14 Addit ional Different ial Trace Layout Guidelines for SFI + Boards .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 799
12. 3 Connect ing t he Serial EEPROM . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 801
12.3.1 Support ed EEPROM Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 802
12. 4 Connect ing t he Flash . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 802
12.4.1 Support ed Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 802
12. 5 SMBus and NC- SI . .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 803
12. 6 NC- SI . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 804
12.6.1 NC- SI Design Requirement s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 804
12.6.2 NC- SI Layout Requirement s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 805
12. 7 Reset s. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. .. 810
12. 8 Connect ing t he MDI O I nt erfaces . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 811
12. 9 Connect ing t he Soft ware- Definable Pins ( SDPs) . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 811
12. 10 Connect ing t he Light Emit t ing Diodes ( LEDs) . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 812
12. 11 Connect ing Miscellaneous Signals.. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 812
12.11.1 LAN Disable . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 812
12.11.2 BI OS Handling of Device Disable .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 813
12. 12 Oscillat or Design Considerat ions . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 813
12.12.1 Oscillat or Types .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 814
12.12.2 Oscillat or Solut ion . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 814
12.12.3 Oscillat or Layout Recommendat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 814
12.12.4 Reference Clock Measurement Recommendat ions. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 815
12. 13 Power Supplies. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 815
12.13.1 Power Supply Sequencing . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 815
12.13.2 Power Supply Filt ering . .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 815
12.13.3 Support for Power Management and Wake Up . .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 816
12. 14 Connect ing t he JTAG Port . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. 816
13.0 Ther mal Desi gn Recommendat i ons ....... ......... .......... ......... ......... ......... ......... .......... ......... ...... 817
13. 1 Thermal Considerat ions .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. 817
13. 2 I mport ance of Thermal Management . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 818
13. 3 Packaging Terminology . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. 818
13. 4 Thermal Specificat ions .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. 818
13. 5 Case Temperat ure .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 819
13. 6 Thermal At t ribut es .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 820
13.6.1 Designing for Thermal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 820
13.6.2 Model Syst em Definit ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 820
13.6.3 Package Thermal Charact erist ics . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 820
13. 7 Thermal Enhancement s .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 822
13. 8 Clearances .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. .. 822
13. 9 Default Enhanced Thermal Solut ion . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 824
13. 10 Ext ruded Heat sinks .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 824
13. 11 At t aching t he Ext ruded Heat sink .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. 825
13.11.1 Clips .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... .. 825
13.11.2 Thermal I nt erface ( PCM45 Series) . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 826
13.11.3 Avoid Damaging Die- Side Capacit ors wit h Heat Sink At t ached .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 826
13.11.4 Maximum St at ic Normal Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 827
13. 12 Reliabilit y . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 827
13.12.1 Thermal I nt erface Management for Heat - Sink Solut ions . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 828
13. 13 Measurement s for Thermal Specificat ions . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 828
13.13.1 Case Temperat ure Measurement s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 828
13.13.2 At t aching t he Thermocouple ( No Heat sink) .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 829
13.13.3 At t aching t he Thermocouple ( Heat sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 829
13. 14 Heat sink and At t ach Suppliers . .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 830
13. 15 PCB Guidelines . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 831
14.0 Di agnost i cs ....... ......... ......... ......... ......... ......... .......... ......... ......... ......... ......... .......... .... ..... ...... 833
14. 1 Link Loopback Operat ions .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 833
15.0 Gl ossar y and Acr ony ms ....... ......... ......... ......... .......... ......... ......... ......... ......... .......... ......... ... ... 835
15. 1 Regist er At t ribut es .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .... .. .. .. .. .. 847
I nt r oduct i on I nt el

13
1. 0 I nt r oduct i on
1.1 Scope
This document describes t he ext ernal archit ect ure ( including device operat ion, pin descript ions, regist er
definit ions, et c. ) for t he 82599, a dual 10 Gigabit Et hernet ( GbE) Net work I nt erface Cont roller.
This document is int ended as a reference for logical design group, archit ect ure validat ion, firmware
development , soft ware device driver developers, board designers, t est engineers, or anyone else who
may need specific t echnical or programming informat ion about t he 82599.
1.2 Pr oduct Over vi ew
The 82599 is a derivat ive of previous generat ions of I nt el 1 GbE and 10 GbE Net work I nt erface Card
( NI C) designs. Many feat ures of it s predecessors remain int act ; however, some have been removed or
modified as well as new feat ures int roduced.
Two versions are available:
82599EB PCI Express* ( PCI e* ) 2. 0, dual port 10 Gigabit Et hernet cont roller
82599ES Serial 10 GbE backplane int erface for blade implement at ions ( includes t he 82599EB
SKU funct ionalit y plus serial) .
1.2.1 82599 Si l i con/ Sof t w ar e Feat ur es
The base soft ware device driver support s t he following int erfaces:
XAUI ( BX4)
SFI
KX/ KX4
KR
Linux soft ware feat ures include:
LLI Low Lat ency I nt errupt s
DCA Direct Cache Access
RSC Receive Side Coalescing
All sleep st at es ( S0 t hrough S5) ; however, for sleep st at es S3 t hrough S5, t here are power and
airflow condit ions t hat need t o be met . Refer t o Sect ion 5. 0 and Sect ion 11. 0 for more det ails.
Header Split This feat ure consist s of split t ing a packet header t o a different memory space and
help t he host t o fet ch headers only for processing.
Flow Direct or ( SW ATR only) A large number of flow affinit y filt ers t hat direct receive packet s by
t heir flows t o queues for classificat ion, load balancing, and mat ching bet ween flows and CPU cores.
I nt el
82599 10 GbE Cont r ol l er I nt r oduct i on

14
Windows soft ware feat ures include:
LLI
DCA
Wake on LAN ( WoL) support :
WoL from S3 and S4 are not current ly support ed for t he 82599. Also, t here are no plans t o
support it in t he fut ure.
WoL from S5 is support ed for connect ions capable of KR t o KX t ransit ions only. I mplement at ion
of t his feat ure has special requirement s, cont act your I nt el represent at ive for more det ails.
Header Split This feat ure consist s of split t ing a packet header t o a different memory space and
help t he host t o fet ch headers only for processing.
Not e: Some PCI e x8 slot s are act ually configured as x4 slot s. These slot s have insufficient
bandwidt h for full 10 GbE line rat e wit h dual port 10 GbE devices. I f a solut ion suffers
bandwidt h issues when bot h 10 GbE port s are act ive, it is recommended t o verify t hat t he
PCI e slot is indeed a t rue PCI e x8.
1.2.2 Sy st em Conf i gur at i ons
The 82599 is t arget ed for syst em configurat ions such as rack mount ed or pedest al servers, where it can
be used as an add- on NI C or LAN on Mot herboard ( LOM) . Anot her syst em configurat ion is for blade
servers, where t he 82599 can be used in a LOM or mezzanine card.
Fi gur e 1.1. Typi cal Rack / Pedest al Syst em Conf i gur at i on
Ethernet Controller
Network
MAUI PHY
PCIe* V 2.0 (2.5GT/s or 5GT/s) x 8
EEPROM/
FLASH
SMBUS/
NC-SI
BMC /
ME
MAUI PHY

15
Fi gur e 1. 2. Typi cal Bl ade Syst em Conf i gur at i on
Backplane
Ethernet Controller
EEPROM/FLASH
SMBUS
NC-SI
BMC / ME
10GbE Switch
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1.3 Ex t er nal I nt er f aces
1.3.1 PCI - Ex pr ess* ( PCI e* ) I nt er f ace
The 82599 support s PCI e V2. 0 ( 2. 5GT/ s or 5GT/ s) . See Sect ion 2. 1. 2 for full pin descript ion and
Sect ion 11.4. 3 for int erface t iming charact erist ics.
1.3.2 Net w or k I nt er f aces
The 82599 int erfaces t he net work t hrough t he Mult i- Speed At t achment Unit I nt erface also referred t o
as t he MAUI int erface.
Two independent MAUI int erfaces are used t o connect t wo t he 82599 port s t o ext ernal devices. Each
MAUI int erface can be configured t o int erface using t he following high speed links:
a. XAUI for connect ion t o anot her XAUI compliant PHY device or opt ical module.
b. SGMI I for connect ion t o anot her SGMI I compliant PHY using 1000BASE- BX or 1000BASE- KX
elect rical signaling.
c. 1000BASE- KX for connect ion over a backplane t o anot her 1000BASE- KX compliant device.
d. 10GBASE- KX4 for connect ion over a backplane t o anot her 10GBASE- KX4 device.
e. 1000BASE- BX for connect ion over a backplane t o anot her 1000BASE- BX compliant device.
Fi gur e 1.3. 82599 Ex t er nal I nt er f aces Di agr am
82599
100M / 1G / 10G
MAC 0
100M / 1G / 10G
MAC 1
Host Interface
MDIO_0
DFT I/F
GPIO_0
LEDs_0
EEPROM I/F
Serial Flash I/F
SMBUS I/F
NCSI I/F
MAUI_0 MAUI_1
MDIO_1
GPIO_1
LEDs_1

17
f. 10GBASE- CX4 for connect ion over a CX4 compliant cable t o anot her 10GBASE- CX4 compliant
device.
g. SFI for connect ion t o anot her SFI compliant PHY or opt ical module.
h. 10GBASE- KR for connect ion over a backplane t o anot her 10GBASE- KR compliant device.
i. 10GBASE- BX4 for connect ion over a backplane t o anot her 10GBASE- BX4 device.
The 82599 also support s:
I EEE 802. 3ae ( 10 Gb/ s) implement at ions. I t performs all of t he funct ions required for t ransmission
and recept ion handling called out in t he st andards for a XAUI Media int erface.
I EEE 802. 3ak, I EEE 802. 3ap Backplane Et hernet ( KX, KX4, or KR) , and PI CMG3. 1 ( BX only)
implement at ions including an Aut o- Negot iat ion layer and PCS layer synchronizat ion.
SFP+ MSA ( SFI ) implement at ions.
These int erfaces can be configured t o operat e in 100 Mb/ s mode ( SGMI I ) , 1 Gb/ s mode ( SGMI I , BX and
KX) and 10 Gb/ s mode ( XAUI , CX4, KX4, KR and SFI ) . I n 100 Mb/ s mode, 1 Gb/ s mode and in KR and
SFI 10 Gb/ s modes, only one of t he four MAUI lanes ( lane 0) is used and t he remaining lanes ( lanes 1
t o 3) are powered down. For more informat ion on how t o configure t he 82599 for 100 Mb/ s,
1 Gb/ s or 10 Gb/ s operat ing modes, refer t o Sect ion 3.7.
Refer t o Sect ion 2. 1. 3 for full- pin descript ions and t o t he respect ive specificat ions ( I EEE802. 3, opt ical
module MSAs. . . ) . For t he t iming charact erist ics of t hose int erfaces see t he relevant ext ernal
specificat ions as list ed in Sect ion 11. 4. 4 for int erface t iming charact erist ics.
1.3.3 EEPROM I nt er f ace
The 82599 uses an EEPROM device for st oring product configurat ion informat ion. Several words of t he
EEPROM are accessed aut omat ically by t he 82599 aft er reset in order t o provide pre- boot configurat ion
dat a t hat must be available t o it before it is accessed by host soft ware. The remainder of t he st ored
informat ion is accessed by various soft ware modules used t o report product configurat ion, serial
number, et c.
The 82599 uses a SPI ( 4- wire) serial EEPROM devices. Refer t o Sect ion 2. 1. 4 for t he I / O pin
descript ions; Sect ion 11. 4. 2. 4 for t iming charact erist ics of t his int erface and Sect ion 11. 6. 2 for a list of
support ed EEPROM devices.
1. 3. 4 Ser i al Fl ash I nt er f ace
The 82599 provides an ext ernal SPI serial int erface t o a Flash ( or boot ROM) device. The 82599
support s serial Flash devices wit h up t o 64 Mb ( 8 MB) of memory. The size of t he Flash used by t he
82599 can be configured by t he EEPROM. See Sect ion 2. 1. 5 for full pin descript ion and Sect ion 11.4. 2. 3
for int erface t iming charact erist ics.
Not e: Though t he 82599 support s devices wit h up t o 8 MB of memory, bigger devices can also be
used. Accesses t o memory beyond t he Flash device size result s in access wrapping as only
t he lower address bit s are used by t he Flash cont rol unit .
1.3.5 SMBus I nt er f ace
SMBus is an opt ional int erface for pass- t hrough and/ or configurat ion t raffic bet ween an ext ernal MC
and t he 82599.
The 82599' s SMBus int erface support s st andard SMBus, up t o a frequency of 400 KHz. Refer t o
Sect ion 2. 1. 6 for full- pin descript ions and Sect ion 11. 4. 2. 2 for t iming charact erist ics of t his int erface.
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18
1.3.6 NC- SI I nt er f ace
NC- SI is an opt ional int erface for pass- t hrough t raffic t o and from a MC. The 82599 meet s t he NC- SI
version 1. 0. 0a specificat ion.
Refer t o Sect ion 3. 3 for an addit ional descript ion of t he NC- SI int erface, Sect ion 2. 1. 8 for t he pin
descript ions, Sect ion 10. 5. 1 for NC- SI programming and Sect ion 11. 4. 1. 4 for t he t iming charact erist ics.
1.3.7 MDI O I nt er f aces
The 82599 implement s t wo serial management int erfaces known as t he Management Dat a I nput /
Out put ( MDI O) I nt erface t hat cont rols and manages PHY devices ( mast er side) . This int erface provides
t he Media Access Cont roller ( MAC) and soft ware wit h t he abilit y t o monit or and cont rol t he st at e of t he
PHY. The 82599 support s t he MDI O frame format s specified in bot h I EEE802. 3 clause 22 and I EEE802. 3
clause 45 using t he elect rical specificat ion defined in I EEE802. 3 clause 22 ( LVTTL signaling) . The MDI O
int erface can be cont rolled by soft ware via a MDI single command and address regist er MSCA ( see
Sect ion 8. 2. 3. 22. 11 for more det ails) .
Each MDI O int erface should be connect ed t o t he relevant PHY as shown in t he following example ( each
MDI O int erface is driven by t he appropriat e MAC funct ion) .
Refer t o Sect ion 3. 7. 6 for complet e descript ion of t he MDI O int erface, Sect ion 2. 1. 9 for t he pin
descript ions, t he MSCA regist er in Sect ion 8. 2. 3. 22.11, and Sect ion 11. 4.2. 7 for t he t iming
charact erist ics.
1.3.8 I
2
C I nt er f aces
The 82599 implement s t wo serial management int erfaces known as I
2
C Management I nt erfaces for t he
cont rol and management of ext ernal opt ical modules ( XFP and SFP+ ) . This int erface provides t he MAC
and soft ware wit h t he abilit y t o monit or and cont rol t he st at e of t he opt ical module. The use, direct ion,
and values of t he I
2
C pins are cont rolled and accessed using fields in t he I 2C Cont rol ( I 2CCTL) regist er.
Each I
2
C int erface should be connect ed t o t he relevant PHY as shown in t he following example ( each
I
2
C int erface is driven by t he appropriat e MAC funct ion) .
Refer t o Sect ion 2. 1. 7 for t he pin descript ions, I 2CCTL regist er informat ion in Sect ion 8. 2. 3.1.4 for I
2
C
programming, and Sect ion 11. 4. 2. 2 for t iming charact erist ics.
Fi gur e 1.4. MDI O Connect i on Ex ampl e
Ethernet Controller
XAUI PHY
XAUI PHY
MAUI0
MAUI1
MDIO_1
MDIO_0

19
1.3.9 Sof t w ar e- Def i nabl e Pi ns ( SDP) I nt er f ace ( Gener al - Pur pose I / O)
The 82599 has eight SDP pins per port t hat can be used for miscellaneous hardware or soft ware-
cont rollable purposes. These pins can each be individually configured t o act as eit her input or out put
pins. Via t he SDP pins, t he 82599 can support I EEE1588 auxiliary device connect ions, cont rol of t he low
speed opt ical module int erface, and ot her funct ionalit y. For more det ails on t he SDPs see Sect ion 3. 6
and t he ESDP regist er informat ion in Sect ion 8. 2. 3.1.3.
1.3.10 LED I nt er f ace
The 82599 implement s four out put drivers int ended for driving ext ernal LED circuit s per port . Each of
t he four LED out put s can be individually configured t o select t he part icular event , st at e, or act ivit y,
which is indicat ed on t hat out put . I n addit ion, each LED can be individually configured for out put
polarit y as well as for blinking versus non- blinking ( st eady- st at e) indicat ions.
The configurat ion for LED out put s is specified via t he LEDCTL regist er ( see Sect ion 8. 2. 3.1.5) . I n
addit ion, t he hardware- default configurat ion for all LED out put s can be specified via an EEPROM field
( see Sect ion 6. 3. 7. 3) , t hereby support ing LED displays configured t o a part icular OEM preference.
See Sect ion 2. 1. 11 for a full pin descript ion.
1.4 Feat ur es Summar y
Table 1.1 t o Table 1. 7 list t he 82599' s feat ures in comparison t o previous dual- port 1 Gb/ s and 10 Gb/ s
Et hernet cont rollers.
Fi gur e 1. 5. I
2
C Connect i on Ex ampl e
Tabl e 1. 1. Gener al Feat ur es
Feat ur e 82599 82598 Reser v ed
Serial Flash I nt erface Y Y
4- wire SPI EEPROM I nt erface Y Y
Configurable LED Operat ion for Soft ware or OEM
Cust omizat ion of LED Displays
Y Y
Prot ect ed EEPROM Space for Privat e Configurat ion Y Y
Ethernet Controller
Optical
Module
Optical
Module
MAUI0
MAUI1
I
2
C_1
I
2
C_0
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Device Disable Capabilit y Y Y
Package Size 25 x 25 mm 31 x 31 mm
Wat chdog Timer Y N
Time Sync ( I EEE 1588) Y N
Tabl e 1.2. Net w or k Feat ur es
Compliant wit h t he 10 Gb/ s and 1 Gb/ s Et hernet / 802. 3ap
( KX/ KX4) Specificat ion
Y Y
Compliant wit h t he 10 Gb/ s 802. 3ap ( KR) specificat ion Y N
Support of 10GBASE- KR FEC Y N
Compliant wit h t he 10 Gb/ s Et hernet / 802. 3ae ( XAUI )
Specificat ion
Y Y
Compliant wit h SFI int erface Y N
Support for EDC N N
Compliant wit h t he 1000BASE- BX Specificat ion Y Y
Half- duplex at 10/ 100 Mb/ s Operat ion and Full- Duplex
Operat ion at all Support ed Speeds
Y ( 100 Mb FDX) NA
10/ 100/ 1000 Copper PHY I nt egrat ed On- chip N N
Support Jumbo Frames of up t o 15. 5 KB ( 15872 byt es) Y
1
1. The 82599 support s full- size 15. 5 KB ( 15872- byt e) j umbo packet s while in a basic mode of operat ion. When DCB mode is enabled,
or securit y engines enabled or virt ualizat ion is enabled, t he 82599 support s 9. 5 KB ( 9728- byt e) j umbo packet s.
Y
Aut o- Negot iat ion Clause 73 for Support ed Modes Y Y
Flow Cont rol Support : Send/ Receive Pause Frames and
Receive FI FO Thresholds
Y Y
St at ist ics for Management and RMON Y Y
802. 1q VLAN Support Y Y
SerDes I nt erface for Ext ernal PHY Connect ion or Syst em
I nt erconnect
Y Y
SGMI I I nt erface Y ( 100 M/ 1G only) N
SerDes Support of non Aut o- Negot iat ion Part ner Y Y
Double VLAN Y N
Tabl e 1.3. Host I nt er f ace Feat ur es
PCI e* Host I nt erface
PCI e V2. 0 ( 2. 5GT/ s
or 5GT/ s)
PCI e v2. 0 ( 2. 5GT/ s)
Number of Lanes x1, x2, x4, x8 x1, x2, x4, x8
64- bit Address Support for Syst ems Using More Than 4 GB of
Physical Memory
Y Y
Out st anding Request s for Tx Dat a Buffers 16 16
Tabl e 1.1. Gener al Feat ur es
Feat ur e 82599 82598 Reser ved

21
Out st anding Request s for Tx Descript ors 8 8
Out st anding Request s for Rx Descript ors 8 4
Credit s for P- H/ P- D/ NP- H/ NP- D ( shared for t he 2 port s) 16/ 16/ 4/ 4 8/ 16/ 4/ 4
Max Payload Size Support ed 512 Byt es 256 Byt es
Max Request Size Support ed 2 KB 256 Byt es
Link Layer Ret ry Buffer Size ( shared for t he 2 port s) 3. 4 KB 2 KB
Vit al Product Dat a ( VPD) Y N
End t o End CRC ( ECRC) Y N
Tabl e 1. 4. LAN Funct i ons Feat ur es
Programmable Host Memory Receive Buffers Y Y
Descript or Ring Management Hardware for Transmit and
Receive
Y Y
ACPI Regist er Set and Power Down Funct ionalit y Support ing
D0 & D3 St at es
Y Y
I nt egrat ed LinkSec securit y engines: AES- GCM 128- bit ;
Encrypt ion + Aut hent icat ion; One SC x 2 SA per port . Replay
Prot ect ion wit h Zero Window
Y N
I nt egrat ed I Psec securit y engines: AES- GCM 128bit ; AH or
ESP encapsulat ion; I Pv4 and I Pv6 ( no opt ion or ext ended
headers)
1024 SA / port N
Soft ware- Cont rolled Global Reset Bit ( Reset s Everyt hing
Except t he Configurat ion Regist ers)
Y Y
Soft ware- Definable Pins ( SDP) ; ( per port ) 8 8
Four SDP Pins can be Configured as General Purpose
I nt errupt s
Y Y
Wake- on- LAN ( WoL) Y Y
I Pv6 Wake- up Filt ers Y Y
Configurable ( t hrough EEPROM) Wake- up Flexible Filt ers Y Y
Default Configurat ion by EEPROM for all LEDs for Pre- Driver
Funct ionalit y
Y Y
LAN Funct ion Disable Capabilit y Y Y
Programmable Memory Transmit Buffers 160 KB / port 320 KB / port
Programmable Memory Receive Buffers 512 KB / port 512 KB / port
Tabl e 1. 5. LAN Per f or mance Feat ur es
TCP/ UDP Segment at ion Offload 256 KB in all modes
256 KB in legacy
mode, 32 KB in DCB
TSO I nt erleaving for Reduced Lat ency Y N
TCP Receive Side Coalescing ( RSC) 32 flows / port N
Tabl e 1. 3. Host I nt er f ace Feat ur es
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22
Dat a Cent er Bridging ( DCB) , I EEE Compliance t o:
Priorit y Groups ( up t o 8) and Bandwidt h Allocat ion ( ETS)
I EEE802. 1Qaz
Priorit y- based Flow Cont rol ( PFC) I EEE802. 1Qbb
Y
Y
Y
Y
Transmit Rat e Scheduler Y N
I Pv6 Support for I P/ TCP and I P/ UDP Receive Checksum
Offload
Y Y
Fragment ed UDP Checksum Offload for Packet Reassembly Y Y
FCoE Tx / Rx CRC Offload Y N
FCoE Transmit Segment at ion 256 KB N
FCoE Coalescing and Direct Dat a Placement
512 out st anding
Read Writ e
request s / port
N
Message Signaled I nt errupt s ( MSI ) Y Y
Message Signaled I nt errupt s ( MSI -X) Y Y
I nt errupt Throt t ling Cont rol t o Limit Maximum I nt errupt Rat e
and I mprove CPU Use
Y Y
Rx Packet Split Header Y Y
Mult iple Rx Queues ( RSS) Y ( mult iple modes)
8x8
16x4
Flow Direct or Filt ers: up t o 32 K - 2 Flows by Hash Filt ers or
up t o 8 K - 2 Perfect Mat ch Filt ers
Y N
Number of Rx Queues ( per port ) 128 64
Number of Tx Queues ( per port ) 128 32
Low Lat ency I nt errupt s
DCA Support
TCP Timer I nt errupt s
Relax Ordering
Yes t o all Yes t o all
Rat e Cont rol of Low Lat ency I nt errupt s Y N
Tabl e 1.6. Vi r t ual i zat i on Feat ur es
Support for Virt ual Machine Device Queues ( VMDq) 64 16
L2 Et hernet MAC Address Filt ers ( unicast and mult icast ) 128 16
L2 VLAN filt ers 64 -
PCI - SI G SR I OV Y N
Mult icast and Broadcast Packet Replicat ion Y N
Packet Mirroring Y N
Packet Loopback Y N
Traffic Shaping Y N
Tabl e 1.5. LAN Per f or mance Feat ur es
Feat ur e 82599 82598 Reser ved

23
1.5 Over vi ew of New Capabi l i t i es Bey ond t he 82598
1.5.1 Secur i t y
The 82599 support s t he I EEE P802. 1AE LinkSec specificat ion. I t incorporat es an inline packet crypt o
unit t o support bot h privacy and int egrit y checks on a packet by packet basis. The t ransmit dat a pat h
includes bot h encrypt ion and signing engines. On t he receive dat a pat h, t he 82599 includes bot h
decrypt ion and int egrit y checkers. The crypt o engines use t he AES GCM algorit hm, which is designed t o
support t he 802. 1AE prot ocol. Not e t hat bot h host t raffic and Manageabilit y Cont roller ( MC)
management t raffic might be subj ect t o aut hent icat ion and/ or encrypt ion.
The 82599 support s I Psec offload for a given number of flows. I t is t he operat ing syst ems responsibilit y
t o submit ( t o hardware) t he most loaded flows in order t o t ake maximum benefit s of t he I Psec offload
in t erms of CPU ut ilizat ion savings. Main feat ures are:
Offload I Psec for up t o 1024 Securit y Associat ions ( SA) for each of Tx and Rx
AH and ESP prot ocols for aut hent icat ion and encrypt ion
AES- 128- GMAC and AES- 128- GCM crypt o engines
Transport mode encapsulat ion
I Pv4 and I Pv6 versions ( no opt ions or ext ension headers)
1.5.2 Tr ansmi t Rat e Li mi t i ng
The 82599 support s Transmit Rat e Scheduler ( TRS) in addit ion t o t he Dat a Cent er Bridging ( DCB)
funct ionalit y provided in t he 82598. TRS is enabled for each t ransmit queue. The following modes of
TRS are used:
Frame Overhead I PG is ext ended by a fixed value for all t ransmit queues.
Payload Rat e I PG, st ret ched relat ive t o frame size, provides pre- det ermined dat a ( byt es) rat es
for each t ransmit queue.
Tabl e 1. 7. Manageabi l i t y Feat ur es
Advanced Pass Through- Compat ible Management Packet
Transmit / Receive Support
Y Y
SMBus I nt erface t o an Ext ernal MC Y Y
NC- SI I nt erface t o an Ext ernal MC Y Y
New Management Prot ocol St andards Support ( NC- SI ) Y Y
L2 Address Filt ers 4 4
VLAN L2 Filt ers 8 8
Flex L3 Port Filt ers 16 16
Flexible TCO Filt ers 4 4
L3 Address Filt ers ( I Pv4) 4 4
L3 Address Filt ers ( I Pv6) 4 4
I nt el

24
1.5.3 Fi br e Channel ov er Et her net ( FCoE)
Fibre Channel ( FC) is t he predominant prot ocol used in St orage Area Net works ( SAN) . Fibre Channel
over Et hernet ( FCoE) enables a connect ion bet ween an Et hernet st orage init iat or and legacy FC st orage
t arget s or a complet e Et hernet connect ion bet ween a st orage init iat or and a device.
Exist ing FC Host Bus Adapt ers ( HBAs) used t o connect bet ween FC init iat or and FC t arget s provide full
offload of t he FC prot ocol t o t he init iat or t hat enables maximizing st orage performance. The 82599
offloads t he main dat a pat h of I / O Read and Writ e commands t o t he st orage t arget .
1.5.4 Per f or mance
The 82599 improves on previous 10 GbE product s in t he following performance vect ors:
Throughput The 82599 aims t o provide wire speed dual- port 10 Gb/ s t hroughput . This is
accomplished using t he PCI e physical layer ( PCI e V2. 0 ( 5GT/ s) , by t uning t he int ernal pipeline t o 10
Gb/ s operat ion, and by enhancing t he PCI e concurrency capabilit ies.
Lat ency The 82599 reduces end- t o- end lat ency for high priorit y t raffic in presence of ot her
t raffic. Specifically, t he 82599 reduces t he delay caused by preceding TCP Segment at ion Offload
( TSO) packet s. Unlike previous product s, a TSO packet might be int erleaved wit h ot her packet s
going t o t he wire. I nt erleaving is done at t he Et hernet packet boundary, t herefore reducing t he
maximum delay due t o a TSO from a TSO- wort h of dat a t o an MTU- wort h of dat a.
CPU ut ilizat ion The 82599 support s reduct ion in CPU ut ilizat ion, mainly by support ing Receive
Side Coalescing ( RSC)
Flow affinit y filt ers
1. 5. 4. 1 Recei v e Si de Coal esci ng ( RSC)
RSC coalesces incoming TCP/ I P packet s int o larger receive segment s. I t is t he inverse operat ion t o TSO
on t he t ransmit side. I t has t he same mot ivat ion, reducing CPU ut ilizat ion by execut ing t he TCP/ I P st ack
only once for a set of received Et hernet packet s. The 82599 can handle up t o 32 flows per port at any
given t ime. See Sect ion 7. 11 for more det ails on RSC.
1.5.4. 2 PCI e V2.0 ( 5GT/ s)
Several changes are defined in t he size of PCI e t ransact ions t o improve t he performance in
virt ualizat ion environment s. Larger request sizes decrease t he number of independent t ransact ions on
PCI e and t herefore decreases t rashing of t he I OTLB cache. Changes include:
I ncrease in t he number of out st anding request s ( dat a, descript ors) t o a t ot al of 32 request s
I ncrease in t he number of credit s for post ed t ransact ion ( such as for t ail updat es) t o 16
I ncrease in t he maximum payload size support ed from 256 byt es t o 512 byt es
I ncrease in t he support ed maximum read request size from 256 byt es t o 2 KB. Not e t hat t he
amount of out st anding request dat a does not change. That is, if t he 82599 support s N out st anding
request s of 256 byt es, t hen it would support N/ 2 request s of 512 byt es, et c.
Ret ry buffer size The link layer ret ry buffer size increases t o 3. 4 KB t o meet t he higher speed of
PCI e V2. 0 ( 5GT/ s) .

25
1. 5. 5 Rx / Tx Queues and Rx Fi l t er i ng
The 82599 Tx and Rx queues have increased in size t o 128 Tx queues and 128 Rx queues. Addit ional
filt ering capabilit ies are provided based on:
L2 Et hert ype
5- t uples
SYN ident ificat ion
Flow Direct or a large number of flow affinit y filt ers t hat direct receive packet s by t heir flows t o
queues for classificat ion, load balancing, and mat ching bet ween flows and CPU cores.
See Sect ion 7. 0 for a complet e descript ion.
1. 5. 6 I nt er r upt s
Several changes in t he int errupt scheme are available in t he 82599:
Cont rol over t he rat e of Low Lat ency I nt errupt s ( LLI )
Ext ensions t o t he filt ers t hat invoke LLI s
Addit ional MSI -X vect ors for t he five- t uple filt ers and for I OV virt ualizat ion
See Sect ion 7. 3 for more det ails.
1.5.7 Vi r t ual i zat i on
See Sect ion 7. 10 for more det ails.
1.5.7.1 PCI - I OV
The 82599 support s t he PCI - SI G single- root I / O Virt ualizat ion init iat ive ( SR- I OV) , including t he
following funct ionalit y:
Replicat ion of PCI configurat ion space
Allocat ion of BAR space per virt ual funct ion
Allocat ion of request er I D per virt ual funct ion
Virt ualizat ion of int errupt s
The 82599 provides t he infrast ruct ure for direct assignment archit ect ures t hrough a mailbox
mechanism. Virt ual Funct ions ( VFs) might communicat e wit h t he Physical Funct ion ( PF) t hrough t he
mailbox and t he PF can allocat e shared resources t hrough t he mailbox channel.
1. 5. 7. 2 Pack et Fi l t er i ng and Repl i cat i on
The 82599 adds ext ensive coverage for packet filt ering for virt ualizat ion by support ing t he following
filt ering modes:
Filt ering by unicast Et hernet MAC address
Filt ering by VLAN t ag
Filt ering of mult icast Et hernet MAC address
Filt ering of broadcast packet s
I nt el

26
For each of t he above cat egories, t he 82599 can replicat e packet s t o mult iple Virt ual Machines ( VMs) .
Various mirroring modes are support ed, including mirroring a VM, a Virt ual LAN ( VLAN) , or all t raffic
int o a specific VM.
1. 5.7. 3 Pack et Sw i t chi ng
The 82599 forwards t ransmit packet s from a t ransmit queue t o an Rx soft ware queue t o support VM- VM
communicat ion. Transmit packet s are filt ered t o an Rx queue based on t he same crit eria as packet s
received from t he wire.
1. 5.7. 4 Tr af f i c Shapi ng
Transmit bandwidt h is allocat ed among t he virt ual int erfaces t o avoid unfair use of bandwidt h by a
single VM. Allocat ion is done separat ely per DCB t raffic class so t hat bandwidt h assignment t o each
t raffic class is part it ioned among t he different VMs.
1.5.8 VPD
The 82599 support s VPD capabilit y defined in t he PCI Specificat ion, version 3. 0. See Sect ion 3. 4. 9 for
more det ails.
1. 5. 9 Doubl e VLAN
The 82599 support s a mode where all received and sent packet s have at least one VLAN t ag in addit ion
t o t he regular t agging t hat can opt ionally be added. This mode is used for syst ems where t he swit ches
add an addit ional t ag cont aining swit ching informat ion.
When a port is configured t o double VLAN, t he 82599 assumes t hat all packet s received or sent t o t his
port have at least one VLAN. The only except ion t o t his rule is flow cont rol packet s, which don' t have a
VLAN t ag. See Sect ion 7. 4. 5 for more det ails.
1. 5. 10 Ti me Sy nc I EEE 1588 Pr eci si on Ti me Pr ot ocol ( PTP)
The I EEE 1588 I nt ernat ional St andard let s net worked Et hernet equipment synchronize int ernal clocks
according t o a net work mast er clock. The prot ocol is implement ed most ly in soft ware, wit h t he 82599
providing accurat e t ime measurement s of special Tx and Rx packet s close t o t he Et hernet link. These
packet s measure t he lat ency bet ween t he mast er clock and an endpoint clock in bot h link direct ions.
The endpoint can t hen acquire an accurat e est imat e of t he mast er t ime by compensat ing for link
lat ency. See Sect ion 7. 9 for more det ails.
The 82599 provides t he following support for t he I EEE 1588 prot ocol:
Det ect ing specific PTP Rx packet s and capt uring t he t ime of arrival of such packet s in dedicat ed
CSRs
Det ect ing specific PTP Tx packet s and capt uring t he t ime of t ransmission of such packet s in
dedicat ed CSRs
A soft ware- visible reference clock for t he above t ime capt ures
1.6 Convent i ons
1.6.1 Ter mi nol ogy and Acr ony ms
See Sect ion 15. 0 for a list of t erminology and acronyms used t hroughout t his document .

27
1.6.2 By t e Count
When referencing j umbo packet size, 1 KB equals 1024 byt es.
For example:
9. 5 KB equals 9. 5 x 1024 = 9728 byt es
15.5 KB equals 15. 5 x 1024 = 15872 byt es
1.6.3 By t e Or der i ng
This sect ion defines t he organizat ion of regist ers and memory t ransfers, as it relat es t o informat ion
carried over t he net work:
Any regist er defined in big endian not at ion can be t ransferred as is t o/ from Tx and Rx buffers in t he
host memory. Big endian not at ion is also referred t o as being in net work order or ordering.
Any regist er defined in lit t le endian not at ion must be swapped before it is t ransferred t o/ from Tx
and Rx buffers in t he host memory. Regist ers in lit t le endian order are referred t o being in host
order or ordering.
Tx and Rx buffers are defined as being in net work ordering; t hey are t ransferred as is over t he net work.
Not e: Regist ers not t ransferred on t he wire are defined in lit t le endian not at ion. Regist ers
t ransferred on t he wire are defined in big endian not at ion, unless specified different ly.
1.7 Regi st er / Bi t Not at i ons
This document refers t o device regist er names wit h all capit al let t ers. To refer t o a specific bit in a
regist er t he convent ion REGI STER. BI T is used. For example CTRL. GI O Mast er Disable refers t o t he GI O
Mast er Disable bit in t he Device Cont rol ( CTRL) regist er.
This document also refers t o bit names as init ial capit al let t ers in an it alic font . For example, GI O Mast er
Disable.
1.8 Ref er ences
The 82599 implement s feat ures from t he following specificat ions:
I EEE Specificat ions
I EEE st andard 802. 3- 2005 ( Et hernet ) . I ncorporat es various I EEE St andards previously published
separat ely. I nst it ut e of Elect rical and Elect ronic Engineers ( I EEE) .
10GBASE-X An I EEE 802. 3 physical coding sublayer for 10 Gb/ s operat ion over XAUI and four
lane PMDs as per I EEE 802.3 Clause 48.
1000BASE- CX 1000BASE- CX over specially shielded 150 O balanced copper j umper cable
assemblies as specified in I EEE 802. 3 Clause 39.
10GBASE- LX4 I EEE 802. 3 Physical Layer specificat ion for 10 Gb/ s using 10GBASE-X encoding
over four WWDM lanes over mult imode fiber as specified in I EEE 802. 3 Clause 54.
10GBASE- CX4 I EEE 802.3 Physical Layer specificat ion for 10 Gb/ s using 10GBASE-X encoding
over four lanes of 100 O shielded balanced copper cabling as specified in I EEE 802. 3 Clause 54.
1000BASE- KX I EEE 802. 3ap Physical Layer specificat ion for 1 Gb/ s using 1000BASE-X encoding
over an elect rical backplane as specified in I EEE 802. 3 Clause 70.
10GBASE- KX4 I EEE 802. 3ap Physical Layer specificat ion for 10 Gb/ s using 10GBASE-X encoding
I nt el

28
10GBASE- KR I EEE 802. 3ap Physical Layer specificat ion for 10 Gb/ s using 10GBASE- R encoding
1000BASE- BX 1000BASE- BX is t he PI CMG 3. 1 elect rical specificat ion for t ransmission of 1 Gb/ s
Et hernet or 1 Gb/ s Fibre Channel encoded dat a over t he backplane.
10GBASE- BX4 10GBASE- BX4 is t he PI CMG 3.1 elect rical specificat ion for t ransmission of 10 Gb/
s Et hernet or 10 Gb/ s Fibre Channel encoded dat a over t he backplane.
I EEE st andard 802. 3ap, draft D3. 2.
I EEE st andard 1149. 1, 2001 Edit ion ( JTAG) . I nst it ut e of Elect rical and Elect ronics Engineers ( I EEE) .
I EEE st andard 802. 1Q for VLAN.
I EEE 1588 I nt ernat ional St andard, Precision clock synchronizat ion pr ot ocol for net worked
measurement and cont rol syst ems, 2004- 09.
I EEE P802. 1AE/ D5. 1, Media Access Cont rol ( MAC) Securit y, January 19, 2006.
PCI - SI G Specificat ions
PCI Express 2. 0 Base specificat ion, 12/ 20/ 2006.
PCI Express 2. 0 Card Elect romechanical Specificat ion, Revision 0. 9, January 19, 2007.
PCI Bus Power Management I nt erface Specificat ion, Rev. 1. 2, March 2004.
PI CMG3. 1 Et hernet / Fibre Channel Over PI CMG 3.0 Draft Specificat ion January 14, 2003 Version
D1.0.
Single Root I / O Virt ualizat ion and Sharing, Revision 0. 7, 1/ 11/ 2007.
I ETF Specificat ions
I Pv4 specificat ion ( RFC 791)
I Pv6 specificat ion ( RFC 2460)
TCP specificat ion ( RFC 793)
UDP specificat ion ( RFC 768)
ARP specificat ion ( RFC 826)
RFC4106 The Use of Galois/ Count er Mode ( GCM) in I Psec Encapsulat ing Securit y Payload ( ESP) .
RFC4302 I P Aut hent icat ion Header ( AH)
RFC4303 I P Encapsulat ing Securit y Payload ( ESP)
RFC4543 The Use of Galois Message Aut hent icat ion Code ( GMAC) in I Psec ESP and AH.
I ETF I nt ernet Draft , Marker PDU Aligned Framing for TCP Specificat ion.
I ETF I nt ernet Draft , Direct Dat a Placement over Reliable Transport s.
Ot her
Serial- GMI I Specificat ion, Cisco Syst ems document ENG- 46158, Revision 1.7.
Advanced Configurat ion and Power I nt erface Specificat ion, Rev 2. 0b, Oct ober 2002
Net work Cont roller Sideband I nt erface ( NC- SI ) Specificat ion, Version cPubs- 0. 1, 2/ 18/ 2007.
Syst em Management Bus ( SMBus) Specificat ion, SBS I mplement ers Forum, Ver. 2. 0, August 2000.
EUI - 64 specificat ion, ht t p: / / st andards. ieee. org/ regaut h/ oui/ t ut orials/ EUI 64.ht ml.
Backward Congest ion Not ificat ion Funct ional Specificat ion, 11/ 28/ 2006.
Definit ion for new PAUSE funct ion, Rev. 1.2, 12/ 26/ 2006.
GCM spec McGrew, D. and J. Viega, The Galois/ Count er Mode of Operat ion ( GCM) , Submission
t o NI ST. ht t p: / / csrc. nist . gov/ Crypt oToolkit / modes/ proposedmodes/ gcm/ gcm- spec. pdf, January
2004.

29
FRAMI NG AND SI GNALI NG- 2 ( FC- FS- 2) Rev 1.00
Fibre Channel over Et hernet Draft Present ed at t he T11 on May 2007
Per Priorit y Flow Cont rol ( by Cisco* Syst ems) Definit ion for new PAUSE funct ion, Rev 1. 2, EDCS-
472530
I n addit ion, t he following document provides applicat ion informat ion:
82563EB/ 82564EB Gigabit Et hernet Physical Layer Device Design Guide, I nt el Corporat ion.
1.9 Ar chi t ect ur e and Basi c Oper at i on
1. 9.1 Tr ansmi t ( Tx ) Dat a Fl ow
Tx dat a flow provides a high- level descript ion of all dat a/ cont rol t ransformat ions st eps needed for
sending Et hernet packet s over t he wire.
Tabl e 1. 8. Tx Dat a Fl ow
St ep Descr i pt i on
1
The host creat es a descript or ring and configures one of t he 82599s t ransmit queues wit h t he address locat ion,
lengt h, head, and t ail point ers of t he ring ( one of 128 available Tx queues) .
2
The host is request ed by t he TCP/ I P st ack t o t ransmit a packet , it get s t he packet dat a wit hin one or more dat a
buffers.
3
The host init ializes t he descript or( s) t hat point t o t he dat a buffer( s) and have addit ional cont rol paramet ers t hat
describes t he needed hardware funct ionalit y. The host places t hat descript or in t he correct locat ion at t he
appropriat e Tx ring.
4 The host updat es t he appropriat e Queue Tail Point er ( TDT)
5
The 82599s DMA senses a change of a specific TDT and as a result sends a PCI e request t o fet ch t he descript or( s)
from host memory.
6
The descript or( s) cont ent is received in a PCI e read complet ion and is writ t en t o t he appropriat e locat ion in t he
descript or queue.
7
The DMA fet ches t he next descript or and processes it s cont ent . As a result , t he DMA sends PCI e request s t o fet ch
t he packet dat a from syst em memory.
8
The packet dat a is being received from PCI e complet ions and passes t hrough t he t ransmit DMA t hat performs all
programmed dat a manipulat ions ( various CPU offloading t asks as checksum offload, TSO offload, et c. ) on t he
packet dat a on t he fly.
9
While t he packet is passing t hrough t he DMA, it is st ored int o t he t ransmit FI FO.
Aft er t he ent ire packet is st ored in t he t ransmit FI FO, it is t hen forwarded t o t ransmit swit ch module.
10
The t ransmit swit ch arbit rat es bet ween host and management packet s and event ually forwards t he packet t o t he
MAC.
11 The MAC appends t he L2 CRC t o t he packet and sends t he packet over t he wire using a pre- configured int erface.
12 When all t he PCI e complet ions for a given packet are complet e, t he DMA updat es t he appropriat e descript or( s) .
13
The descript ors are writ t en back t o host memory using PCI e post ed writ es. The head point er is updat ed in host
memory as well.
14
An int errupt is generat ed t o not ify t he host driver t hat t he specific packet has been read t o t he 82599 and t he
driver can t hen release t he buffer( s) .
I nt el

30
1.9.2 Recei ve ( Rx ) Dat a Fl ow
Rx dat a flow provides a high- level descript ion of all dat a/ cont rol t ransformat ion st eps needed for
receiving Et hernet packet s.
Tabl e 1.9. Rx Dat a Fl ow
St ep Descr i pt i on
1
The host creat es a descript or ring and configures one of t he 82599s receive queues wit h t he address locat ion,
lengt h, head, and t ail point ers of t he ring ( one of 128 available Rx queues)
2
The host init ializes descript or( s) t hat point t o empt y dat a buffer( s) . The host places t hese descript or( s) in t he
correct locat ion at t he appropriat e Rx ring.
3 The host updat es t he appropriat e Queue Tail Point er ( RDT) .
6 A packet ent ers t he Rx MAC.
7 The MAC forwards t he packet t o t he Rx filt er.
8 I f t he packet mat ches t he pre- programmed crit eria of t he Rx filt ering, it is forwarded t o an Rx FI FO.
9
The receive DMA fet ches t he next descript or from t he appropriat e host memory ring t o be used for t he next
received packet .
10
Aft er t he ent ire packet is placed int o an Rx FI FO, t he receive DMA post s t he packet dat a t o t he locat ion indicat ed by
t he descript or t hrough t he PCI e int erface.
I f t he packet size is great er t han t he buffer size, more descript ors are fet ched and t heir buffers are used for t he
received packet .
11
When t he packet is placed int o host memory, t he receive DMA updat es all t he descript or( s) t hat were used by t he
packet dat a.
12
The receive DMA writ es back t he descript or cont ent along wit h st at us bit s t hat indicat e t he packet informat ion
including what offloads were done on t hat packet .
13 The 82599 init iat es an int errupt t o t he host t o indicat e t hat a new received packet is ready in host memory.
14
The host reads t he packet dat a and sends it t o t he TCP/ I P st ack for furt her processing. The host releases t he
associat ed buffer( s) and descript or( s) once t hey are no longer in use.
Pi n I nt er f ace I nt el

31
2. 0 Pi n I nt er f ace
2.1 Pi n Assi gnment
2.1.1 Si gnal Ty pe Def i ni t i on
2.1.2 PCI e Sy mbol s and Pi n Names
See AC/ DC specificat ions in Sect ion 11. 4. 3.
Si gnal Def i ni t i on DC Speci f i cat i on
I n I nput is a st andard input - only signal. Sect ion 11. 4. 1. 2
Out ( O) Tot em Pole Out put ( TPO) is a st andard act ive driver. Sect ion 11. 4. 1. 2
T/ s Tri- st at e is a bidirect ional, t ri- st at e input / out put pin. Sect ion 11. 4. 1. 2
O/ d Open drain enables mult iple devices t o share as a wire- OR. Sect ion 11. 4. 1. 3
A- in Analog input signals. Sect ion 11. 4. 3 and Sect ion 11. 4. 4
A- out Analog out put signals. Sect ion 11. 4. 3 and Sect ion 11. 4. 4
B I nput BI AS. -
CML- in CML input signal. Sect ion 11. 4. 5
NCSI - in NC- SI input signal. Sect ion 11. 4. 1. 4
NCSI - out NC- SI out put signal. Sect ion 11. 4. 1. 4
Pu I nt ernal pullup. -
Pd I nt ernal pull- down. -
Reser ved Pi n Name Bal l # Ty pe Name and Funct i on
PE_CLK_p
PE_CLK_n
AB23
AB24
A- in
PCI e Different ial Reference Clock I n. A 100 MHz different ial
clock input . This clock is used as t he reference clock for t he PCI e
Tx/ Rx circuit ry and by t he PCI e core PLL t o generat e clocks for
t he PCI e core logic.
PET_0_p
PET_0_n
Y23
Y24
A- out
PCI e Serial Dat a Out put . A serial different ial out put pair running
at 5 Gb/ s or 2. 5 Gb/ s. This out put carries bot h dat a and an
embedded 5 GHz or 2. 5 GHz clock t hat is recovered along wit h
dat a at t he receiving end.
PET_1_p
PET_1_n
V23
V24
A- out
PET_2_p
PET_2_n
T23
T24
A- out
I nt el
82599 10 GbE Cont r ol l er Pi n I nt er f ace

32
PET_3_p
PET_3_n
P23
P24
A- out
PET_4_p
PET_4_n
J23
J24
A- out
PET_5_p
PET_5_n
G23
G24
A- out
PET_6_p
PET_6_n
E23
E24
A- out
PET_7_p
PET_7_n
C23
C24
A- out
PER_0_p
PER_0_n
AC20
AC21
A- in
PCI e Serial Dat a I nput . A serial different ial input pair running at
5 Gb/ s or 2. 5 Gb/ s. An embedded clock present in t his input is
recovered along wit h t he dat a.
PER_1_p
PER_1_n
AA20
AA21
A- in
PER_2_p
PER_2_n
U20
U21
A- in
PER_3_p
PER_3_n
R20
R21
A- in
PER_4_p
PER_4_n
K20
K21
A- in
PER_5_p
PER_5_n
H20
H21
A- in
PER_6_p
PER_6_n
D20
D21
A- in
PER_7_p
PER_7_n
B20
B21
A- in
Reser v ed Pi n Name Bal l # Ty pe Name and Funct i on

33
2.1.3 MAUI
See AC/ DC specificat ions in Sect ion 11. 4. 4 and Sect ion 11. 4. 5.
PE_WAKE_N AA18 O/ d
Wake. Pulled t o 0b t o indicat e t hat a Power Management Event
( PME) is pending and t he PCI e link should be rest ored. Defined
in t he PCI e specificat ions.
PE_RST_N AD18 I n
Power and Clock Good I ndicat ion. I ndicat es t hat power and PCI e
reference clock are wit hin specified values. Defined in t he PCI e
specificat ions; also called: PCI e Reset and PERST.
PE_RBI AS
PE_RSENSE
M24
N24
B
PCI e BI AS.
A 24. 9 O 0. 5%, 50 ppm resist or should be connect ed from
PE_RBI AS t o t he chip' s 1. 2V Analog PCI e supply rail
( VCC1P2_PE) . Connect ion should be as close as possible t o t he
chip. Resist or is used for int ernal impedance compensat ion and
BI AS current generat ion circuit ry.
PE_RSENSE is used as sensing node and should be short ed on
board t o PE_RBI AS as close as possible t o t he ext ernal resist or' s
pad.
XA_RBI AS_p
XA_RBI AS_n
L2
L1
B
MAUI BI AS.
A 1 KO 0. 5%, 50 ppm resist or should be connect ed bet ween
XA_RBI AS_p and XA_RBI AS_n and locat ed close t o t he chip.
Resist or generat es int ernal BI AS current s used for impedance
compensat ion. XA_RBI AS_n is int ernally connect ed t o ground.
REFCLKI N_p
REFCLKI N_n
P2
P1
CML- in
Ext ernal Reference Clock I nput / Cryst al Oscillat or I nput . I f an
ext ernal clock is applied, it must be 25 MHz 0. 01%.
RX0_L3_p
RX0_L3_n
B4
A4
A- in
XAUI Serial Dat a I nput for Port 0. A serial different ial input pair
running at up t o 3. 125 Gb/ s. An embedded clock present in t his
input is recovered along wit h t he dat a.
RX0_L2_p
RX0_L2_n
D4
D5
A- in
RX0_L1_p
RX0_L1_n
F4
F5
A- in
RX0_L0_p
RX0_L0_n
H4
H5
A- in
This lane is also used in BX, BX4, CX4, KX, KR, and SFI modes.
TX0_L3_p
TX0_L3_n
C1
C2
A- out
XAUI Serial Dat a Out put for Port 0. A serial different ial out put pair
running at up t o 3. 125 Gb/ s. This out put carries bot h dat a and an
embedded clock t hat is recovered along wit h dat a at t he receiving
end.
TX0_L2_p
TX0_L2_n
E1
E2
A- out
end.
I nt el

34
2.1.4 EEPROM
See AC specificat ions in Sect ion 11.4.2.4.
TX0_L1_p
TX0_L1_n
G1
G2
A- out
end.
TX0_L0_p
TX0_L0_n
J1
J2
A- out
end.
RX1_L3_p
RX1_L3_n
U4
U5
A- in
RX1_L2_p
RX1_L2_n
W4
W5
A- in
RX1_L1_p
RX1_L1_n
AA4
AA5
A- in
RX1_L0_p
RX1_L0_n
AC4
AD4
A- in
TX1_L3_p
TX1_L3_n
T1
T2
A- out
end.
TX1_L2_p
TX1_L2_n
V1
V2
A- out
end.
TX1_L1_p
TX1_L1_n
Y1
Y2
A- out
end.
TX1_L0_p
TX1_L0_n
AB1
AB2
A- out
end.
EE_DI B18 O Dat a out put t o EEPROM.
EE_DO A18
I n
Pu
Dat a input from EEPROM.
EE_SK B19 O EEPROM serial clock operat es at maximum of 2 MHz.
EE_CS_N C19 O EEPROM chip select out put .

35
2. 1. 5 Ser i al Fl ash
See AC specificat ions in Sect ion 11. 4. 2. 3.
2.1.6 SMBus
See t he AC specificat ions in Sect ion 11. 4. 2.2.
Not e: I f t he SMBus is disconnect ed, an ext ernal pullup should be used for t he SMBCLK, SMBD pins.
2.1.7 I
2
C
See t he I
2
C specificat ion and Sect ion 11. 4. 2.2 for AC specificat ions.
Not e: I f t he I
2
C is disconnect ed, an ext ernal pullup should be used for t he clock and dat a pins.
FLSH_SI B6 T/ s Serial dat a out put t o t he Flash.
FLSH_SO A7
I n
Pu
Serial dat a input from t he Flash.
FLSH_SCK A8 T/ s Flash serial clock operat es at 12. 5 MHz.
FLSH_CE_N B7 T/ s Flash chip select out put .
SMBCLK AC19 o/ d
SMBus Clock. One clock pulse is generat ed for each dat a bit
t ransferred.
SMBD AB19 o/ d
SMBus Dat a. St able during t he high period of t he clock ( unless it is a
st art or st op condit ion) .
SMBALRT_N AA19 o/ d SMBus Alert . Act s as an int errupt pin of a slave device on t he SMBus.
SCL0 AB12 o/ d I
2
C Clock. One clock pulse is generat ed for each dat a bit t ransferred.
SDA0 AA12 o/ d
I
2
C Dat a. St able during t he high period of t he clock ( unless it is a st art or
st op condit ion) .
SCL1 AD17 o/ d I
2
C Clock. One clock pulse is generat ed for each dat a bit t ransferred.
SDA1 AC18 o/ d
I
2
C Dat a. St able during t he high period of t he clock ( unless it is a st art or
st op condit ion) .
I nt el

36
2.1.8 NC- SI
Not es: I f NC- SI is disconnect ed, an ext ernal pull- down should be used for t he NCSI _CLK_I N,
NCSI _TXD[ 1: 0] , and NCSI _TX_EN pins.
2.1.9 MDI O
NCSI _CLK_I N AC11 NCSI - I n
NC- SI Reference Clock I nput . Synchronous clock reference for receive,
t ransmit , and cont rol int erface. I t is a 50 MHz clock 50 ppm.
NCSI _CRS_DV AB11 NCSI - Out Carrier Sense/ Receive Dat a Valid ( CRS/ DV) .
NCSI _RXD_0
NCSI _RXD_1
AA11
AC10
NCSI - Out Receive Dat a. Dat a signals t o t he BMC.
NCSI _TX_EN AB10 NCSI - I n Transmit Enable.
NCSI _TXD_0
NCSI _TXD_1
AA10
AD11
NCSI - I n Transmit Dat a. Dat a signals from t he BMC.
MDI O0 AD12 T/ s
Management Dat a. Bi- direct ional signal for serial dat a t ransfers bet ween
t he 82599 and t he PHY management regist ers for port 0. Not e: Requires
an ext ernal pullup device.
MDC0 AC12 O
Management Clock. Clock out put for accessing t he PHY management
regist ers for port 0. MDC clock frequency is Proport ional t o link speed. At
10 Gb/ s Link speed MDC frequency can be set t o 2. 4 MHz ( default ) or
24 MHz.
MDI O1 AC17 T/ s
Management Dat a. Bi- direct ional signal for serial dat a t ransfers bet ween
t he 82599 and t he PHY management regist ers for port 1. Not e: Requires
an ext ernal pullup device.
MDC1 AB18 O
Management Clock. Clock out put for accessing t he PHY management
regist ers for port 1. MDC clock frequency is Proport ional t o link speed. At
10 Gb/ s Link speed MDC frequency can be set t o 2. 4 MHz ( default ) or
24 MHz.

37
2.1.10 Sof t w ar e Def i ned Pi ns ( SDPs)
See Sect ion 3. 6 for more det ails on configurable SDPs.
2.1.11 LEDs
SDP0_0
SDP0_1
SDP0_2
SDP0_3
SDP0_4
SDP0_5
SDP0_6
SDP0_7
AD8
AC8
AB8
AA8
AD7
AC7
AB7
AA7
T/ s
Pu
General Purpose SDPs. 3. 3V I / Os for funct ion 0.
Can be used t o support I EEE1588 Auxiliary
devices, Low speed opt ical module int erface
SDP0_4 is dedicat ed input pin for Securit y
enablement . Securit y offload on bot h port s is
enabled if t he Securit y Enablement flags in t he
SKU Fuses regist er are set t o 1b and SDP0_4
input pin is driven high.
See Sect ion 3. 6 for possible usages of t he pins.
SDP1_0
SDP1_1
SDP1_2
SDP1_3
SDP1_4
SDP1_5
SDP1_6
SDP1_7
AC16
AB16
AB17
AA17
AA16
AC15
AB15
AA15
T/ s
Pu
General purpose SDPs. 3. 3V I / Os for funct ion 1.
Can be used t o support I EEE1588 auxiliary
devices, low speed opt ical module int erface
See Sect ion 3. 6 for possible usages of t he pins.
LED0_0 AD14 O Port 0 LED0. Programmable LED t hat indicat es Link- Up ( default ) .
LED0_1 AC14 O Port 0 LED1. Programmable LED t hat indicat es 10 Gb/ s Link ( default ) .
LED0_2 AB14 O
Port 0 LED2. Programmable LED t hat indicat es a Link/ Act ivit y indicat ion
( default ) .
LED0_3 AA14 O Port 0 LED3. Programmable LED t hat indicat es a 1 Gb/ s Link ( default ) .
LED1_0 AD13 O Port 1 LED0. Programmable LED t hat indicat es Link- Up ( default ) .
LED1_1 AC13 O Port 1 LED1. Programmable LED t hat indicat es 10 Gb/ s Link ( default ) .
LED1_2 AB13 O
Port 1 LED2. Programmable LED t hat indicat es a Link/ Act ivit y indicat ion
( default ) .
LED1_3 AA13 O Port 1 LED3. Programmable LED t hat indicat es a 1 Gb/ s Link ( default ) .
I nt el

38
2. 1. 12 RSVD and No Connect Pi ns
Connect ing RSVD pins based on naming convent ion:
NC pin is not connect ed in t he package
RSVD_NC reserved pin. Should be left unconnect ed.
RSVD_VSS reserved pin. Should be connect ed t o GND.
Reser ved Pi n Name Bal l # Name and Funct i on
RSVDA11_NC
RSVDA12_NC
RSVDA17_NC
RSVDA20_NC
RSVDA21_NC
RSVDB10_NC
RSVDB11_NC
RSVDB12_NC
RSVDB17_NC
A11
A12
A17
A20
A21
B10
B11
B12
B17
RSVD* pins.
RSVDB8_NC
RSVDB9_NC
RSVDC10_NC
RSVDC11_NC
RSVDC12_NC
RSVDC13_NC
RSVDC14_NC
RSVDC15_NC
RSVDC16_NC
B8
B9
C10
C11
C12
C13
C14
C15
C16
RSVD* pins.
RSVDC17_NC
RSVDC18_NC
RSVDC7_NC
RSVDC8_NC
RSVDC9_NC
RSVDD10_NC
RSVDD11_NC
RSVDD12_NC
RSVDD13_NC
C17
C18
C7
C8
C9
D10
D11
D12
D13
RSVD* pins.
RSVDD14_NC
RSVDD15_NC
RSVDD16_NC
RSVDD17_NC
RSVDD18_NC
RSVDD7_NC
RSVDD8_NC
RSVDD9_NC
RSVDE11_NC
D14
D15
D16
D17
D18
D7
D8
D9
E11
RSVD* pins.
RSVDE13_NC
RSVDE15_NC
RSVDE9_NC
RSVDJ6_NC
RSVDJ7_NC
RSVDL23_NC
RSVDL24_NC
E13
E15
E9
J6
J7
L23
L24
RSVD* pins.

39
RSVDM1_NC
RSVDM2_NC
RSVDM20_NC
RSVDM21_NC
RSVDN1_NC
RSVDN2_NC
RSVDN20_NC
RSVDN21_NC
RSVDN4_NC
M1
M2
M20
M21
N1
N2
N20
N21
N4
RSVD* pins.
RSVDN5_NC
RSVDT6_NC
RSVDT7_NC
RSVDW20_NC
RSVDW21_NC
N5
T6
T7
W20
W21
RSVD* pins.
RSVDY11_NC
RSVDY13_NC
RSVDY15_NC
RSVDY17_NC
RSVDY18_NC
Y11
Y13
Y15
Y17
Y18
RSVD* pins.
NCY16
NCY14
NCY12
NCY10
NCY8
NCU7
NCE18
NCE16
NCE14
NCE12
NCE10
NCE8
NCP4
NCL4
NCF20
NCH7
Y16
Y14
Y12
Y10
Y8
U7
E18
E16
E14
E12
E10
E8
P4
L4
F20
H7
NC pins.
RSVDY9_VSS
RSVDV16_VSS
RSVDW16_VSS
RSVDF21_VSS
RSVDE17_VSS
Y9
V16
W16
F21
E17
RSVD* pins.
Reser v ed Pi n Name Bal l # Name and Funct i on
I nt el

40
2.1.13 Mi scel l aneous
2.1.14 JTAG
Reser v ed Pi n Name Bal l # Type Name and Funct i on
LAN_PWR_GOOD A14
I n
Pu
LAN Power Good. A 3. 3V input signal. A t ransit ion from low t o
high init ializes t he 82599 int o operat ion. I f not used
( POR_BYPASS = 0b) , an int ernal Power- on- Reset ( POR) circuit
t riggers t he 82599 power- up.
POR_BYPASS D19
I n
Pu
Bypass indicat ion as t o whet her or not t o use t he int ernal POR or
t he LAN_PWR_GOOD pin. When set t o 1b, t he 82599 disables
t he int ernal POR circuit and uses t he LAN_PWR_GOOD pin as a
POR indicat ion.
RSVDAC6_VCC AC6 I n This pin must be connect ed t o logic one.
OSC_SEL AA9
T/ s
Pu
Defines t he input clock connect ed t o t he REFCLKI N_p/
REFCLKI N_n pins:
0b = XTAL Clock ( valid only for 25 MHz)
1b = OSC Clock
This pin is a st rapping opt ion lat ched at LAN_PWR_GOOD.
AUX_PWR AB9 T/ s
Auxiliary Power Available. When set , indicat es t hat auxiliary
power is available and t he 82599 should support D3
COLD
power
st at e if enabled t o do so. This pin is lat ched at t he rising edge of
LAN_PWR_GOOD.
MAI N_PWR_OK AC9 I n
Main Power OK. I ndicat es t hat plat form main power is up. Must
be connect ed ext ernally.
LAN1_DI S_N AD20
T/ s
Pu
This pin is a st rapping pin lat ched at t he rising edge of
LAN_PWR_GOOD. I f t his pin is not connect ed or driven high
during init ializat ion, LAN 1 is enabled. I f t his pin is driven low
during init ializat ion, LAN 1 port is disabled.
LAN0_DI S_N AD21
T/ s
Pu
This pin is a st rapping opt ion pin lat ched at t he rising edge of
LAN_PWR_GOOD. I f t his pin is not connect ed or driven high
during init ializat ion, LAN 0 is enabled. I f t his pin is driven low
during init ializat ion, LAN 0 port is disabled.
When LAN 0 port is disabled MNG is not funct ional and it must
not be enabled in t he EEPROM Cont rol Word 1.
JTCK B16 I n JTAG Clock I nput .
JTDI A13
I n
Pu
JTAG Dat a I nput .
JTDO B15 O/ d JTAG Dat a Out put .
JTMS B13
I n
Pu
JTAG TMS I nput .
JRST_N B14 I n Pu JTAG Reset I nput . Act ive low reset for t he JTAG port .

41
2.1.15 Pow er Suppl i es
See AC specificat ions in Sect ion 11. 3. 1.
2.1.16 Pul l - Ups
Not e: I nt el
82599 10 GbE Cont roller Checklist s for pullup values. Refer t o t he reference
schemat ics for implement at ion det ails.
VCC1P2
1. 2V Power supply.
W14, W11, W9, V14, V11, V9, U16, U14, U11, U9, T16, T14, T11, R16, R14, R13, R12,
R11, P14, P11, N14, N11, M14, M11, L14, L11, K16, K14, K13, K12, K11, J16, J14,
J11, H16, H14, H11, H9, G16, G14, G11, G9, F16, F14, F11, F9, U18, T18, R18, P18,
P16, N18, N16, M18, M16, L18, L16, K18, J18, H18, K9, K7, J9, T9, R9, R7, M9, M7,
L9, L7, P9, P7, N9, N7
VCC3P3
3. 3V Power supply.
AD19, AD15, AD10, AD6, A19, A15, A10, A6, E7, Y7, L5, P5
VSS
0V Ground
AD16, AD9, W18, W17, W15, W13, W12, W10, W8, W7, V17, V15, V13, V12, V10, V8,
U15, U13, U12, U10, T15, T13, T12, T10, R15, R10, P15, P13, P12, P10, N15, N13,
N12, N10, M15, M13, M12, M10, L15, L13, L12, L10, K15, K10, J15, J13, J12, J10,
H15, H13, H12, H10, G17, G15, G13, G12, G10, G8, F18, F17, F15, F13, F12, F10, F8,
F7, A16, A9, K8, K6, J8, J5, J4, H8, H6, G7, G6, G5, G4, F6, E6, E5, E4, D6, C6, C5,
C4, B5, B3, A5, A3, AD5, AD3, AC5, AC3, AB6, AB5, AB4, AA6, Y6, Y5, Y4, W6, V7, V6,
V5, V4, U8, U6, T8, T5, T4, R8, R6, M8, M6, M5, M4, M3, L8, L6, L3, K5, K4, K3, K2,
K1, J3, H3, H2, H1, G3, F3, F2, F1, E3, D3, D2, D1, C3, B2, B1, A2, A1, AD2, AD1,
AC2, AC1, AB3, AA3, AA2, AA1, Y3, W3, W2, W1, V3, U3, U2, U1, T3, R5, R4, R3, R2,
R1, P8, P6, P3, N8, N6, N3, AD24, AD23, AD22, AC24, AC23, AC22, AB22, AB21,
AB20, AA24, AA23, AA22, Y22, Y21, Y20, Y19, W24, W23, W22, W19, V22, V21, V20,
V19, V18, U24, U23, U22, U19, U17, T22, T21, T20, T19, T17, R24, R23, R22, R19,
R17, P22, P21, P20, P19, P17, N23, N22, N19, N17, M23, M22, M19, M17, L22, L21,
L20, L19, L17, K24, K23, K22, K19, K17, J22, J21, J20, J19, J17, H24, H23, H22, H19,
H17, G22, G21, G20, G19, G18, F24, F23, F22, F19, E22, E21, E20, E19, D24, D23,
D22, C22, C21, C20, B24, B23, B22, A24, A23, A22
Reser v ed
Pi n
Name
Reser v ed
I nt er nal Pul l Up at
Pow er Up
Nomi nal Act i v e St at e
PUP Comment PUP Comment
EE_DI N N
EE_DO Y Y
EE_SK N N
EE_CS_N N N
FLSH_SI Y N
FLSH_SO Y Y
FLSH_SCK Y N
FLSH_CE_N Y N
SMBCLK N N
SMBD N N
SMBALRT_N N N
SCL0/ SCL1 N N
I nt el

42
SDA0/ SDA1 N N
NCSI _CLK_I N N N
NCSI _CRS_DV N N
NCSI _RXD_0 N N
NCSI _RXD_1 N N
NCSI _TX_EN N N
NCSI _TXD_0 N N
NCSI _TXD_1 N N
MDI O0 N N
MDC0 N N
MDI O1 N N
MDC1 N N
SDP0_0 / RX_LOS_0
SDP0_1
SDP0_2
SDP0_3
SDP0_4 / TX_DI S_0
SDP0_5 /
LI NK_SPEED_0
SDP0_6
SDP0_7
Y Y
SDP1_0 / RX_LOS_1
SDP1_1
SDP1_2
SDP1_3
SDP1_4 / TX_DI S_1
SDP1_5 /
LI NK_SPEED_1
SDP1_6
SDP1_7
Y Y
LED0_0
LED0_1
LED0_2
LED0_3
N N
LED1_0
LED1_1
LED1_2
LED1_3
N N
LAN_PWR_GOOD Y Y
AUX_PWR N N
LAN0_DI S_N Y Y
LAN1_DI S_N Y Y
MAI N_PWR_OK N N
JTCK N N
Reser ved
Pi n
Name
Reser ved
Pow er Up
Nomi nal Act i ve St at e

43
JTDI N N
JTDO N N
JTMS N N
JRST_N Y Y
PE_RST_N N N
PE_WAKE_N N N
OSC_SEL Y Y
POR_BYPASS Y N
Reser v ed
Pi n
Name
Reser v ed
Pow er Up
Nomi nal Act i v e St at e
I nt el

44
2. 2 Bal l Out Top Lev el
Top view, t hrough package.
Fi gur e 2.1. Pack age Layout - Lef t Vi ew
24 23 22 21 20 19 18 17 16 15 14 13
AD VSS VSS VSS LAN0_DIS_N LAN1_DIS_N VCC3P3 PE_RST_N SCL1 VSS VCC3P3 LED0_0 LED1_0
AC VSS VSS VSS PER_0_n PER_0_p SMBCLK SDA1 MDIO1
SDP1_0 /
RX_LOS_1
SDP1_5 /
LINK_SPEED_
1
LED0_1 LED1_1
AB PE_CLK_n PE_CLK_p VSS VSS VSS SMBD MDC1 SDP1_2 SDP1_1 SDP1_6 LED0_2 LED1_2
AA VSS VSS VSS PER_1_n PER_1_p SMBALRT_N PE_WAKE_N SDP1_3
SDP1_4 /
TX_DIS_1
SDP1_7 LED0_3 LED1_3
Y PET_0_n PET_0_p VSS VSS VSS VSS RSVDY18_NC RSVDY17_NC NCY16 RSVDY15_NC NCY14 RSVDY13_NC
W VSS VSS VSS RSVDW21_NC RSVDW20_NC VSS VSS VSS
RSVDW16_VS
S
VSS VCC1P2 VSS
V PET_1_n PET_1_p VSS VSS VSS VSS VSS VSS RSVDV16_VSS VSS VCC1P2 VSS
U VSS VSS VSS PER_2_n PER_2_p VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
T PET_2_n PET_2_p VSS VSS VSS VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
R VSS VSS VSS PER_3_n PER_3_p VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VCC1P2
P PET_3_n PET_3_p VSS VSS VSS VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
N PE_RSENSE VSS VSS RSVDN21_NC RSVDN20_NC VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
M PE_RBIAS VSS VSS RSVDM21_NC RSVDM20_NC VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
L RSVDL24_NC RSVDL23_NC VSS VSS VSS VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
K VSS VSS VSS PER_4_n PER_4_p VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VCC1P2
J PET_4_n PET_4_p VSS VSS VSS VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
H VSS VSS VSS PER_5_n PER_5_p VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS
G PET_5_n PET_5_p VSS VSS VSS VSS VSS VSS VCC1P2 VSS VCC1P2 VSS
F VSS VSS VSS RSVDF21_VSS NCF20 VSS VSS VSS VCC1P2 VSS VCC1P2 VSS
E PET_6_n PET_6_p VSS VSS VSS VSS NCE18 RSVDE17_VSS NCE16 RSVDE15_NC NCE14 RSVDE13_NC
D VSS VSS VSS PER_6_n PER_6_p POR_BYPASS RSVDD18_NC RSVDD17_NC RSVDD16_NC RSVDD15_NC RSVDD14_NC RSVDD13_NC
C PET_7_n PET_7_p VSS VSS VSS EE_CS_N RSVDC18_NC RSVDC17_NC RSVDC16_NC RSVDC15_NC RSVDC14_NC RSVDC13_NC
B VSS VSS VSS PER_7_n PER_7_p EE_SK EE_DI RSVDB17_NC JTCK JTDO JRST_N JTMS
A VSS VSS VSS RSVDA21_NC RSVDA20_NC VCC3P3 EE_DO RSVDA17_NC VSS VCC3P3
LAN_PWR_GO
OD
JTDI
24 23 22 21 20 19 18 17 16 15 14 13

45
Fi gur e 2. 2. Pack age Layout - Ri ght Vi ew
12 11 10 9 8 7 6 5 4 3 2 1
MDIO0 NCSI_TXD_1 VCC3P3 VSS
SDP0_0 /
RX_LOS_0
SDP0_4 /
TX_DIS_0
VCC3P3 VSS RX1_L0_n VSS VSS VSS AD
MDC0 NCSI_CLK_IN NCSI_RXD_1
MAIN_PWR_O
K
SDP0_1
SDP0_5 /
LINK_SPEED_
0
RSVDAC6_
VSS
VSS RX1_L0_p VSS VSS VSS AC
SCL0 NCSI_CRS_DV NCSI_TX_EN AUX_PWR SDP0_2 SDP0_6 VSS VSS VSS VSS TX1_L0_n TX1_L0_p AB
SDA0 NCSI_RXD_0 NCSI_TXD_0 OSC_SEL SDP0_3 SDP0_7 VSS RX1_L1_n RX1_L1_p VSS VSS VSS AA
NCY12 RSVDY11_NC NCY10 RSVDY9_VSS NCY8 VCC3P3 VSS VSS VSS VSS TX1_L1_n TX1_L1_p Y
VSS VCC1P2 VSS VCC1P2 VSS VSS VSS RX1_L2_n RX1_L2_p VSS VSS VSS W
VSS VCC1P2 VSS VCC1P2 VSS VSS VSS VSS VSS VSS TX1_L2_n TX1_L2_p V
VSS VCC1P2 VSS VCC1P2 VSS NCU7 VSS RX1_L3_n RX1_L3_p VSS VSS VSS U
VSS VCC1P2 VSS VCC1P2 VSS RSVDT7_NC RSVDT6_NC VSS VSS VSS TX1_L3_n TX1_L3_p T
VCC1P2 VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS VSS VSS VSS VSS VSS R
VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS VCC3P3 NCP4 VSS REFCLKIN_p REFCLKIN_n P
VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS RSVDN5_NC RSVDN4_NC VSS RSVDN2_NC RSVDN1_NC N
VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS VSS VSS VSS RSVDM2_NC RSVDM1_NC M
VSS VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS VCC3P3 NCL4 VSS XA_RBIAS_p XA_RBIAS_n L
VCC1P2 VCC1P2 VSS VCC1P2 VSS VCC1P2 VSS VSS VSS VSS VSS VSS K
VSS VCC1P2 VSS VCC1P2 VSS RSVDJ7_NC RSVDJ6_NC VSS VSS VSS TX0_L0_n TX0_L0_p J
VSS VCC1P2 VSS VCC1P2 VSS NCH7 VSS RX0_L0_n RX0_L0_p VSS VSS VSS H
VSS VCC1P2 VSS VCC1P2 VSS VSS VSS VSS VSS VSS TX0_L1_n TX0_L1_p G
VSS VCC1P2 VSS VCC1P2 VSS VSS VSS RX0_L1_n RX0_L1_p VSS VSS VSS F
NCE12 RSVDE11_NC NCE10 RSVDE9_NC NCE8 VCC3P3 VSS VSS VSS VSS TX0_L2_n TX0_L2_p E
RSVDD12_NC RSVDD11_NC RSVDD10_NC RSVDD9_NC RSVDD8_NC RSVDD7_NC VSS RX0_L2_n RX0_L2_p VSS VSS VSS D
RSVDC12_NC RSVDC11_NC RSVDC10_NC RSVDC9_NC RSVDC8_NC RSVDC7_NC VSS VSS VSS VSS TX0_L3_n TX0_L3_p C
RSVDB12_NC RSVDB11_NC RSVDB10_NC RSVDB9_NC RSVDB8_NC FLSH_CE_N FLSH_SI VSS RX0_L3_p VSS VSS VSS B
RSVDA12_NC RSVDA11_NC VCC3P3 VSS FLSH_SCK FLSH_SO VCC3P3 VSS RX0_L3_n VSS VSS VSS A
12 11 10 9 8 7 6 5 4 3 2 1
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46
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I nt er connect s I nt el

47
3. 0 I nt er connect s
3.1 PCI - Ex pr ess* ( PCI e* )
3.1.1 Ov er v i ew
PCI e is an I / O archit ect ure t hat enables cost compet it ive solut ions as well as provide indust ry leading
price/ performance and feat ure richness. I t is an indust ry- driven specificat ion.
PCI e defines a basic set of requirement s t hat addresses t he maj orit y of t he t arget ed applicat ion classes.
Higher- end applicat ions requirement s ( Ent erprise class servers and high- end communicat ion
plat forms) are addressed by a set of advanced ext ensions t hat compliment t he baseline requirement s.
To guarant ee headroom for fut ure applicat ions, PCI e provides a soft ware- managed mechanism for
int roducing new, enhanced capabilit ies.
Figure 3.1 shows t he PCI e archit ect ure.
The PCI e physical layer consist s of a different ial t ransmit pair and a different ial receive pair. Full- duplex
dat a on t hese t wo point - t o- point connect ions is self- clocked such t hat no dedicat ed clock signals are
required. The bandwidt h of t his int erface increases in direct proport ion wit h frequency increases.
Fi gur e 3. 1. PCI e St ack St r uct ur e
2.5+ 2.5+ Gb Gb/s /s
Configurable widths 1 .. 32 Configurable widths 1 .. 32
Preserve Driver Model
Config/OS
S/W
Protocol
Link
Physical
Common Base Protocol Common Base Protocol
Advanced Advanced Xtensions Xtensions
Physical
(electrical
Mechanical)
Point to point, serial, differential, Point to point, serial, differential,
hot hot- -plug, inter plug, inter- -op op formfactors formfactors
PCI Compliant Block
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82599 10 GbE Cont r ol l er I nt er connect s

48
The packet is t he fundament al unit of informat ion exchange and t he prot ocol includes a message space
t o replace a variet y of sideband signals found on previous int erconnect s. This movement of hardwired
signals from t he physical layer t o messages wit hin t he t ransact ion layer enables easy and linear
physical layer widt h expansion for increased bandwidt h.
The common base prot ocol uses split t ransact ions along wit h several mechanisms t o eliminat e wait
st at es and t o opt imize t he re- ordering of t ransact ions t o furt her improve syst em performance.
3. 1. 1. 1 Ar chi t ect ur e, Tr ansact i on and Li nk Lay er Pr oper t i es
Split t ransact ion, packet - based prot ocol
Common flat address space for load/ st ore access ( for example, PCI addressing model)
32- bit memory address space t o enable a compact packet header ( must be used t o access
addresses below 4 GB)
64- bit memory address space using an ext ended packet header
Transact ion layer mechanisms:
PCI -X st yle relaxed ordering
Credit - based flow cont rol
Packet sizes/ format s:
Maximum packet size: 512 byt es
Maximum read request size: 2 KB
Reset / init ializat ion:
Frequency/ widt h/ profile negot iat ion performed by hardware
Dat a int egrit y support
Using CRC- 32 for Transact ion layer Packet s ( TLP)
Link Layer Ret ry ( LLR) for recovery following error det ect ion
Using CRC- 16 for Link Layer ( LL) messages
No ret ry following error det ect ion
8b/ 10b encoding wit h running disparit y
Soft ware configurat ion mechanism:
Uses PCI configurat ion and bus enumerat ion model
PCI e- specific configurat ion regist ers mapped via PCI ext ended capabilit y mechanism
Baseline messaging:
I n- band messaging of formerly sideband legacy signals ( int errupt s, et c. )
Syst em- level power management support ed via messages
Power management :
Full support for PCI m
Wake capabilit y from D3cold st at e
Compliant wit h ACPI , PCI m soft ware model
Act ive st at e power management

49
Support for PCI e V2. 0 ( 2. 5GT/ s or 5GT/ s)
Support for complet ion t ime out cont rol
Support for addit ional regist ers in t he PCI e capabilit y st ruct ure
3. 1. 1. 2 Phy si cal I nt er f ace Pr oper t i es
Point - t o- point int erconnect
Full- duplex; no arbit rat ion
Signaling t echnology:
Low Volt age Different ial ( LVD)
Embedded clock signaling using 8b/ 10b encoding scheme
Serial frequency of operat ion: PCI e V2. 0 ( 2. 5GT/ s or 5GT/ s) .
I nt erface widt h of 1, 2, 4, or 8 PCI e lanes.
DFT and DFM support for high- volume manufact uring
3.1.1.3 Adv anced Ex t ensi ons
PCI e defines a set of opt ional feat ures t o enhance plat form capabilit ies for specific usage modes. The
82599 support s t he following opt ional feat ures:
Advanced Error Report ing ( AER) Messaging support t o communicat e mult iple t ypes/ severit y of
errors
Device Serial Number Allows exposure of a unique serial number for each device
Alt ernat ive RI D I nt erpret at ion ( ARI ) allows support of more t han eight funct ions per device
Single Root I / O Virt ualizat ion ( SR- I OV) allows exposure of virt ual funct ions cont rolling a subset
of t he resources t o Virt ual Machines ( VMs)
3. 1. 2 Gener al Funct i onal i t y
3.1.2.1 Nat i v e/ Legacy
All 82599 PCI funct ions are nat ive PCI e funct ions.
3.1.2.2 Lock ed Tr ansact i ons
The 82599 does not support locked request s as a t arget or a mast er.
3. 1.3 Host I nt er f ace
PCI e device numbers ident ify logical devices wit hin t he physical device ( t he 82599 is a physical device) .
The 82599 implement s a single logical device wit h t wo separat e PCI Funct ions: LAN 0 and LAN 1. The
device number is capt ured from each t ype 0 configurat ion writ e t ransact ion.
Each of t he PCI e funct ions int erfaces wit h t he PCI e unit t hrough one or more client s. A client I D
ident ifies t he client and is included in t he Tag field of t he PCI e packet header. Complet ions always carry
t he t ag value included in t he request t o enable rout ing of t he complet ion t o t he appropriat e client .
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50
3. 1. 3. 1 TAG I D Al l ocat i on
Tag I Ds are allocat ed different ly for read and writ e as det ailed in t he following sect ions.
3.1.3. 1.1 TAG I D Al l ocat i on f or Read Tr ansact i ons
Table 3. 1 list s t he Tag I D allocat ion for read accesses. The Tag I D is used by hardware in order t o be
able t o forward t he read dat a t o t he required int ernal client .
3.1.3. 1.2 TAG I D Al l ocat i on f or Wr i t e Tr ansact i ons
Request t ag allocat ion depends on t hese syst em paramet ers:
DCA support ed or not support ed in t he syst em ( DCA_CTRL. DCA_DI S)
DCA enabled or disabled ( DCA_TXCTRL.TX Descript or DCA EN, DCA_RXCTRL. RX Descript or DCA
EN, DCA_RXCTRL.RX Header DCA EN, DCA_RXCTRL. Rx Payload DCA EN)
Syst em t ype: Legacy DCA versus DCA 1. 0 ( DCA_CTRL. DCA_MODE)
CPU I D ( DCA_RXCTRL.CPUI D or DCA_TXCTRL.CPUI D)
Case 1 DCA Disabled in t he Syst em:
The following t able list s t he writ e request s t ags:
Tabl e 3.1. TAG I D Al l ocat i on Tabl e f or Read Tr ansact i ons
TAG I D Descr i pt i on TAG I D Descr i pt i on
0x0 Dat a Request 0x0 0x10 Tx Descript or 0
0x8 Dat a Request 0x8 0x18 Rx Descript or 0
0x9 Dat a Request 0x9 0x19 Rx Descript or 1
0xA Dat a Request 0xA 0x1A Rx Descript or 2
0xB Dat a Request 0xB 0x1B Rx Descript or 3
0xC Dat a Request 0xC 0x1C Rx Descript or 4
0xD Dat a Request 0xD 0x1D Rx Descript or 5
0xE Dat a Request 0xE 0x1E Rx Descript or 6
0xF Dat a Request 0xF 0x1F Rx Descript or 7
Tag I D Descr i pt i on
2 Writ e- back descript or Tx / writ e- back head.
4 Writ e- back descript or Rx.
6 Writ e dat a.

51
Case 2 DCA Enabled in t he Syst em, but Disabled for t he Request :
Legacy DCA plat forms I f DCA is disabled for t he request , t he t ags allocat ion is ident ical t o t he
case where DCA is disabled in t he syst em ( refer t o t he previous t able) .
DCA 1.0 plat forms All writ e request s have t he t ag of 0x00.
Case 3 DCA Enabled in t he Syst em, DCA Enabled for t he Request :
Legacy DCA Plat forms: t he request t ag is const ruct ed as follows:
Bit [ 0] DCA Enable = 1b
Bit s[ 3: 1] The CPU I D field t aken from t he CPUI D[ 2: 0] bit s of t he DCA_RXCTRL or
DCA_TXCTRL regist ers
Bit s[ 7: 4] Reserved
DCA 1. 0 Plat forms: t he request t ag ( all eight bit s) is t aken from t he CPU I D field of t he
DCA_RXCTRL or DCA_TXCTRL regist ers
3.1.3.2 Compl et i on Ti meout Mechani sm
I n any split t ransact ion prot ocol, t here is a risk associat ed wit h t he failure of a request er t o receive an
expect ed complet ion. To enable request ers t o at t empt recovery from t his sit uat ion in a st andard
manner, t he complet ion t imeout mechanism is defined.
The complet ion t imeout mechanism is act ivat ed for each request t hat requires one or more complet ions
when t he request is t ransmit t ed. The 82599 provides a programmable range for t he complet ion
t imeout , as well as t he abilit y t o disable t he complet ion t imeout alt oget her. The complet ion t imeout is
programmed t hrough an ext ension of t he PCI e capabilit y st ruct ure.
The 82599s react ion t o a complet ion t imeout is list ed in Table 3.8.
The 82599 cont rols t he following aspect s of complet ion t imeout :
Disabling or enabling complet ion t imeout
Disabling or enabling resending a request on complet ion t imeout
A programmable range of t imeout values
Programming t he behavior of complet ion t imeout is list ed in Table 3. 2. Not e t hat syst em soft ware
can configure a complet ion t imeout independent ly per each LAN funct ion.
Complet ion Timeout Enable Programmed t hrough t he PCI configurat ion space. The default is:
Complet ion Timeout Enabled.
Resend Request Enable The Complet ion Timeout Resend EEPROM bit ( loaded t o t he
Complet ion_Timeout _Resend bit in t he PCI e Cont rol Regist er ( GCR) enables resending t he request
( applies only when complet ion t imeout is enabled) . The default is t o resend a request t hat t imed out .
Tabl e 3. 2. Compl et i on Ti meout Pr ogr ammi ng
Capabi l i t y Pr ogr ammi ng Capabi l i t y
Complet ion Timeout Enabling Cont rolled t hrough PCI configurat ion. Visible t hrough a read- only CSR bit .
Resend Request Enable Loaded from t he EEPROM int o a read- only CSR bit .
Complet ion Timeout Period Cont rolled t hrough PCI configurat ion.
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52
3.1.3. 2.1 Compl et i on Ti meout Per i od
Programmed t hrough t he PCI configurat ion. Visible t hrough bit s 3: 0 in t he Device Capabilit ies 2
Regist er ( 0xC4; RO) regist er ( see Sect ion 9. 3. 10.10) . The 82599 support s all four ranges defined by
PCI e V2. 0 ( 2. 5GT/ s or 5GT/ s) :
50 s t o 10 ms
10 ms t o 250 ms
250 ms t o 4 s
4 s t o 64 s
Syst em soft ware programs a range ( one of nine possible ranges t hat sub- divide t he four previous
ranges) int o t he PCI configurat ion regist er. The support ed sub- ranges are:
50 s t o 50 ms ( default ) .
50 s t o 100 s
1 ms t o 10 ms
16 ms t o 55 ms
65 ms t o 210 ms
260 ms t o 900 ms
1 s t o 3.5 s
4 s t o 13 s
17 s t o 64s
A memory read request for which t here are mult iple complet ions are considered complet ed only when
all complet ions have been received by t he request er. I f some, but not all, request ed dat a is ret urned
before t he complet ion t imeout t imer expires, t he request or is permit t ed t o keep or t o discard t he dat a
t hat was ret urned prior t o t imer expirat ion.
3.1.4 Tr ansact i on Lay er
The upper layer of t he PCI e archit ect ure is t he t ransact ion layer. The t ransact ion layer connect s t o
82599' s core using an implement at ion- specific prot ocol. Through t his core- t o- t ransact ion- layer
prot ocol, t he applicat ion- specific part s of t he 82599 int eract wit h t he PCI e subsyst em and t ransmit s
and receives request s t o or from t he remot e PCI e agent , respect ively.
3.1.4. 1 Tr ansact i on Ty pes Accept ed by t he 82599
Tabl e 3.3. Tr ansact i on Types Accept ed by t he Tr ansact i on Layer
Tr ansact i on Ty pe FC Ty pe
Tx Lay er
React i on
Har dw ar e Shoul d Keep Dat a
Fr om Or i gi nal Pack et
For Cl i ent
Configurat ion Read Request NPH CPLH + CPLD Request er I D, TAG, at t ribut e Configurat ion space
Configurat ion Writ e Request NPH + NPD CPLH Request er I D, TAG, at t ribut e Configurat ion space
Memory Read Request NPH CPLH + CPLD Request er I D, TAG, at t ribut e CSR space
Memory Writ e Request
PH +
PD
- - CSR space
I O Read Request NPH CPLH + CPLD Request er I D, TAG, at t ribut e CSR space

53
Flow Cont rol Types Legend:
CPLD Complet ion Dat a Payload
CPLH Complet ion Headers
NPD Non- Post ed Request Dat a Payload
NPH Non- Post ed Request Headers
PD Post ed Request Dat a Payload
PH Post ed Request Headers
3. 1. 4. 2 Tr ansact i on Ty pes I ni t i at ed by t he 82599
Not e: MAX_PAYLOAD_SI ZE is loaded from t he EEPROM ( up t o 512 byt es) . Effect ive
MAX_PAYLOAD_SI ZE is defined for each PCI funct ion according t o t he configurat ion space
regist er for t hat funct ion.
3.1.4.2.1 Dat a Al i gnment
Not e: Request s must never specify an address/ lengt h combinat ion t hat causes a memory space
access t o cross a 4 KB boundary.
The 82599 breaks request s int o 4 KB- aligned request s ( if needed) . This does not pose any requirement
on soft ware. However, if soft ware allocat es a buffer across a 4 KB boundary, hardware issues mult iple
request s for t he buffer. Soft ware should consider aligning buffers t o a 4 KB boundary in cases where it
improves performance.
I O Writ e Request NPH + NPD CPLH Request er I D, TAG, at t ribut e CSR space
Read Complet ions CPLH + CPLD - - DMA
Message PH - -
Message unit / I NT/ PM/
error unit
Tabl e 3. 4. Tr ansact i on Types I ni t i at ed by t he Tr ansact i on Lay er
Tr ansact i on t y pe Pay l oad Si ze FC Ty pe Fr om Cl i ent
Configurat ion Read Request Complet ion Dword CPLH + CPLD Configurat ion space
Configurat ion Writ e Request Complet ion - CPLH Configurat ion space
I O Read Request Complet ion Dword CPLH + CPLD CSR
I O Writ e Request Complet ion - CPLH CSR
Read Request Complet ion Dword/ Qword CPLH + CPLD CSR
Memory Read Request - NPH DMA
Memory Writ e Request < = MAX_PAYLOAD_SI ZE PH + PD DMA
Message - PH
Message unit / I NT/ PM/ error
unit
Tabl e 3. 3. Tr ansact i on Types Accept ed by t he Tr ansact i on Lay er
Tr ansact i on Ty pe FC Ty pe
Tx Lay er
React i on
Har dw ar e Shoul d Keep Dat a
Fr om Or i gi nal Pack et
For Cl i ent
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54
The general rules for packet alignment are as follows. Not e t hat t hese apply t o all t he 82599 request s
( read/ writ e and snoop) :
The lengt h of a single request does not exceed t he PCI e limit of MAX_PAYLOAD_SI ZE for writ e and
MAX_READ_REQ for read.
The lengt h of a single request does not exceed t he 82599 int ernal limit at ions.
A single request does not span across different memory pages as not ed by t he 4 KB boundary
alignment previously ment ioned.
I f a request can be sent as a single PCI e packet and st ill meet t he general rules for packet alignment ,
t hen it is not broken at t he cache line boundary but rat her sent as a single packet ( mot ivat ion is t hat
t he chipset can break t he request along cache line boundaries, but t he 82599 should st ill benefit from
bet t er PCI e use) . However, if any of t he t hree general rules require t hat t he request is broken int o t wo
or more packet s, t hen t he request is broken at t he cache line boundary.
3.1.4. 2.2 Mul t i pl e Tx Dat a Read Request s ( MULR)
The 82599 support s 16 mult iple pipelined request s for t ransmit dat a. I n general, request s can belong t o
t he same packet or t o consecut ive packet s. However, t he following rest rict ions apply:
All request s for a packet must be issued before a request is issued for a consecut ive packet .
Read request s can be issued from any of t he support ed queues, as long as t he previous rest rict ion
is met . Pipelined request s can belong t o t he same queue or t o separat e queues. However, as
previously not ed, all request s for a cert ain packet are issued ( from t he same queue) before a
request is issued for a different packet ( pot ent ially from a different queue) .
The PCI e specificat ion does not insure t hat complet ions for separat e request s ret urn in- order. Read
complet ions for concurrent request s are not required t o ret urn in t he order issued. The 82599
handles complet ions t hat arrive in any order. Once all complet ions arrive for a given request , it can
issue t he next pending read dat a request .
The 82599 incorporat es a reorder buffer t o support re- ordering of complet ions for all issued
request s. Each request / complet ion can be up t o 512 byt es long. The maximum size of a read
request is defined as t he minimum { 2 KB byt es, Max_Read_Request _Size} .
I n addit ion t o t he t ransmit dat a request s, t he 82599 can issue eight pipelined read request s for Tx
descript ors and eight pipelined read request s for Rx descript ors. The request s for Tx dat a, Tx
descript ors, and Rx descript ors are independent ly issued.
3. 1.4. 3 Messages
3.1.4. 3.1 Recei ved Messages
Message packet s are special packet s t hat carry a message code. The upst ream device t ransmit s special
messages t o t he 82599 by using t his mechanism. The t ransact ion layer decodes t he message code and
responds t o t he message accordingly.
Tabl e 3.5. Suppor t ed Message i n t he 82599 ( as a Recei ver )
Message
Code [ 7: 0]
Rout i ng r 2r 1r 0 Message 82599 Lat er Response
0x14 100b PM_Act ive_St at e_NAK I nt ernal Signal Set
0x19 011b PME_Turn_Off I nt ernal Signal Set
0x50 100b Slot power limit support ( has one Dword dat a) Silent ly Drop
0x7E 010b, 011b, 100b Vendor_defined t ype 0 No dat a Unsupport ed Request
0x7E 010b, 011b, 100b Vendor_defined t ype 0 dat a Unsupport ed Request

55
3.1.4.3.2 Tr ansmi t t ed Messages
The t ransact ion layer is also responsible for t ransmit t ing specific messages t o report int ernal/ ext ernal
event s ( such as int errupt s and PMEs) .
3.1.4.4 Or der i ng Rul es
The 82599 meet s t he PCI e ordering rules by following t he PCI simple device model:
1. Deadlock Avoidance The 82599 meet s t he PCI e ordering rules t hat prevent deadlocks:
a. Post ed writ es overt ake st alled read request s. This applies t o bot h t arget and mast er direct ions.
For example, if mast er read request s are st alled due t o lack of credit s, mast er post ed writ es are
allowed t o proceed. On t he t arget side, it is accept able t o t imeout on st alled read request s in
order t o allow lat er post ed writ es t o proceed.
b. Target post ed writ es overt ake st alled t arget configurat ion writ es.
c. Complet ions overt ake st alled read request s. This applies t o bot h t arget and mast er direct ions.
For example, if mast er read request s are st alled due t o lack of credit s, complet ions generat ed
by t he 82599 are allowed t o proceed.
2. Descript or/ Dat a Ordering The 82599 insures t hat a Rx descript or is writ t en back on PCI e only
aft er t he dat a t hat t he descript or relat es t o is writ t en t o t he PCI e link.
0x7F 010b, 011b, 100b Vendor_defined t ype 1 no dat a Silent ly Drop
0x7F 010b, 011b, 100b Vendor_defined t ype 1 dat a Silent ly Drop
0x00 011b Unlock Silent ly Drop
Tabl e 3. 6. Suppor t ed Message i n t he 82599 ( as a Tr ansmi t t er )
Message
code [ 7: 0]
Rout i ng
r 2r 1r 0
Message
0x20 100b Assert I NT A
0x21 100b Assert I NT B
0x22 100b Assert I NT C
0x23 100b Assert I NT D
0x24 100b DE- Assert I NT A
0x25 100b DE- Assert I NT B
0x26 100b DE- Assert I NT C
0x27 100b DE- Assert I NT D
0x30 000b ERR_COR
0x31 000b ERR_NONFATAL
0x33 000b ERR_FATAL
0x18 000b PM_PME
0x1B 101b PME_TO_Ack
Tabl e 3. 5. Suppor t ed Message i n t he 82599 ( as a Recei v er )
Message
Code [ 7: 0]
Rout i ng r 2r 1r 0 Message 82599 Lat er Response
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56
3. MSI and MSI -X Ordering Rules Syst em soft ware can change t he MSI or MSI -X t ables during run-
t ime. Soft ware expect s t hat int errupt messages issued aft er t he t able has been updat ed are using
t he updat ed cont ent s of t he t ables.
a. Since soft ware doesn t know when t he t ables are act ually updat ed in t he 82599, a common
scheme is t o issue a read request t o t he MSI or MSI -X t able ( a PCI configurat ion read for MSI
and a memory read for MSI -X) . Soft ware expect s t hat any message issued following t he
complet ion of t he read request , is using t he updat ed cont ent s of t he t ables.
b. Once an MSI or MSI -X message is issued using t he updat ed cont ent s of t he int errupt t ables, any
consecut ive MSI or MSI -X message does not use t he cont ent s of t he t ables prior t o t he change.
4. The 82599 meet s t he rules relat ing t o independence bet ween t arget and mast er accesses:
a. The accept ance of a t arget post ed request does not depend upon t he t ransmission of any TLP.
b. The accept ance of a t arget Non- post ed Request does not depend upon t he t ransmission of a non-
post ed request .
c. Accept ing a complet ion does not depend upon t he t ransmission of any TLP.
3.1.4. 4.1 Out of Or der Compl et i on Handl i ng
I n a split t ransact ion prot ocol, when using mult iple read request s in a mult i- processor environment ,
t here is a risk t hat complet ions for separat e request s arrive from t he host memory out of order and
int erleaved. I n t his case, t he 82599 sort s t he complet ions and t ransfers t hem t o t he net work in t he
correct order.
Not e: Complet ions for separat e read request s are not guarant eed t o ret urn in order. Complet ions for
t he same read request are guarant eed t o ret urn in address order.
3. 1.4. 5 Tr ansact i on Def i ni t i on and At t r i but es
3.1.4. 5.1 Max Payl oad Si ze
The 82599' s policy for det ermining Max Payload Size ( MPS) is as follows:
1. Mast er request s init iat ed by t he 82599 ( including complet ions) limit Max Payload Size t o t he value
defined for t he funct ion issuing t he request .
2. Target writ e accesses t o t he 82599 are accept ed only wit h a size of one Dword or t wo Dwords.
Writ e accesses in t he range of t hree Dwords ( MPS) are flagged as unreliable. Writ e accesses above
MPS are flagged as malformed.
3.1.4. 5.2 Tr af f i c Cl ass ( TC) and Vi r t ual Channel s ( VC)
The 82599 only support s TC = 0 and VC = 0 ( default ) .
3.1.4. 5.3 Rel ax ed Or der i ng
The 82599 t akes advant age of t he relaxed ordering rules in PCI e. By set t ing t he relaxed ordering bit in
t he packet header, t he 82599 enables t he syst em t o opt imize performance in t he following cases:
1. Relaxed ordering for descript or and dat a reads When t he 82599 mast ers a read t ransact ion, it s
split complet ion has no ordering relat ionship wit h t he writ es from t he CPUs ( same direct ion) . I t
should be allowed t o bypass t he writ es from t he CPUs.
2. Relaxed ordering for receiving dat a writ es When t he 82599 mast ers receive dat a writ es, it also
enables t hem t o bypass each ot her in t he pat h t o syst em memory because soft ware does not
process t his dat a unt il t heir associat ed descript or writ es are done.
3. The 82599 cannot relax ordering for descript or writ es or an MSI writ e.

57
Relaxed ordering is enabled globally in Niant ic by clearing t he CTRL_EXT. RO_DI S bit and furt her
enabled per queue in t he DCA_RXCTRL[ n] regist ers.
3.1.4.6 Fl ow Cont r ol
3.1.4.6.1 Fl ow Cont r ol Rul es
The 82599 only implement s t he default Virt ual Channel ( VC0) . A single set of credit s is maint ained for
VC0.
Rules for FC updat es:
The 82599 maint ains t wo credit s for NPD at any given t ime. I t increment s t he credit by one aft er
t he credit is consumed, and sends an Updat eFC packet as soon as possible. Updat eFC packet s are
scheduled immediat ely aft er a resource is available.
The 82599 provides 16 credit s for PH ( such as for concurrent t arget writ es) and four credit s for NPH
( such as for four concurrent t arget reads) . Updat eFC packet s are scheduled immediat ely aft er a
resource is available.
The 82599 follows t he PCI e recommendat ions for frequency of Updat eFC FCPs.
3.1.4.6.2 Upst r eam Fl ow Cont r ol Tr ack i ng
The 82599 issues a mast er t ransact ion only when t he required flow cont rol credit s are available. Credit s
are t racked for post ed, non- post ed, and complet ions ( t he lat er t o operat e against a swit ch) .
3.1.4.6.3 Fl ow Cont r ol Updat e Fr equency
I n all cases, Updat e Flow Cont rol Packet s ( FCPs) are scheduled immediat ely aft er a resource is
available.
When t he link is in t he L0 or L0s link st at e, Updat e FCPs for each enabled t ype of non- infinit e flow
cont rol credit must be scheduled for t ransmission at least once every 30 s ( - 0% / + 50%) , except when
t he Ext ended Sync bit of t he Cont rol Link regist er is set , in which case t he limit is 120 s ( - 0% / + 50%) .
Tabl e 3. 7. Fl ow Cont r ol Cr edi t s Al l ocat i on
Cr edi t Ty pe Oper at i ons Number of Cr edi t s ( dual por t )
Post ed Request Header ( PH)
Target writ e
Message ( one unit )
16 credit unit s t o support t ail writ e at wire
speed.
Post ed Request Dat a ( PD)
Target Writ e ( Lengt h/ 16 byt es = one)
Message ( one unit )
max{ MAX_PAYLOAD_SI ZE/ 16, 32} .
Non- Post ed Request Header ( NPH)
Target read ( one unit )
Configurat ion read ( one unit )
Configurat ion writ e ( one unit )
Four unit s ( t o enable concurrent t arget
accesses t o bot h LAN port s) .
Non- Post ed Request Dat a ( NPD) Configurat ion writ e ( one unit ) Four unit s.
Complet ion Header ( CPLH) Read complet ion ( n/ a) I nfinit e ( accept ed immediat ely) .
Complet ion Dat a ( CPLD) Read complet ion ( n/ a) I nfinit e ( accept ed immediat ely) .
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3.1.4. 6.4 Fl ow Cont r ol Ti meout Mechani sm
The 82599 implement s t he opt ional flow cont rol updat e t imeout mechanism.
The mechanism is act ive when t he link is in L0 or L0s link st at e. I t uses a t imer wit h a limit of 200 s ( -
0% / + 50%) , where t he t imer is reset by t he receipt of any I nit or Updat e FCP. Alt ernat ely, t he t imer
can be reset by t he receipt of any DLLP.
Upon t imer expirat ion, t he mechanism inst ruct s t he PHY t o ret rain t he link ( via t he LTSSM recovery
st at e) .
3.1.5 Li nk Lay er
3. 1.5. 1 ACK/ NAK Scheme
The 82599 support s t wo alt ernat ive schemes for ACK/ NAK rat e:
ACK/ NAK is scheduled for t ransmission following any TLP.
ACK/ NAK is scheduled for t ransmission according t o t imeout s specified in t he PCI e specificat ion.
The PCI e Error Recovery bit ( loaded from t he EEPROM) det ermines which of t he t wo schemes is used.
3. 1.5. 2 Suppor t ed DLLPs
The following DLLPs are support ed by t he 82599 as a receiver:
ACK
NAK
PM_Request _Ack
I nit FC1- P
I nit FC1- NP
I nit FC1- Cpl
I nit FC2- P
I nit FC2- NP
I nit FC2- Cpl
Updat eFC- P
Updat eFC- NP
Updat eFC- Cpl

59
The following DLLPs are support ed by t he 82599 as a t ransmit t er:
ACK
NAK
PM_Ent er_L1
PM_Ent er_L23
I nit FC1- P
I nit FC1- NP
I nit FC1- Cpl
I nit FC2- P
I nit FC2- NP
I nit FC2- Cpl
Updat eFC- P
Updat eFC- NP
Not e: Updat eFC- Cpl is not sent because of t he infinit e FC- Cpl allocat ion.
3. 1. 5. 3 Tr ansmi t EDB Nul l i f y i ng ( End Bad)
I f ret rain is necessary, t here is a need t o guarant ee t hat no abrupt t erminat ion of t he Tx packet
happens. For t his reason, early t erminat ion of t he t ransmit t ed packet is possible. This is done by
appending t he EDB t o t he packet .
3.1.6 Phy si cal Lay er
3.1.6.1 Li nk Speed
The 82599 support s PCI e V2. 0 ( 2. 5GT/ s or 5GT/ s) . The following configurat ion cont rols link speed:
PCI e Support ed Link Speeds bit I ndicat es t he link speeds support ed by t he 82599. Loaded from
t he PCI e Link Speed field in t he EEPROM.
PCI e Current Link Speed bit I ndicat es t he negot iat ed Link speed.
PCI e Target Link Speed bit used t o set t he t arget compliance mode speed when soft ware is using
t he Ent er Compliance bit t o force a link int o compliance mode. The default value is t he highest link
speed support ed defined by t he previous Support ed Link Speeds.
The 82599 does not init iat e a hardware aut onomous speed change.
The 82599 support s ent ering compliance mode at t he speed indicat ed in t he Target Link Speed field in
t he PCI e Link Cont rol 2 regist er. Compliance mode funct ionalit y is cont rolled via t he PCI e Link Cont rol 2
regist er.
EEPROM Wor d Of f set
( St ar t i ng at Odd
Wor d)
Al l ow PCI e
V2. 0( Def aul t )
For ce PCI e
V2. 0 Set t i ng
Descr i pt i on
2* N+ 1 0x094 MORI A6 regist er offset ( lower word) .
2* N+ 2 0x0000 0x0100
Disabling PCI e V2. 0 is cont rolled by set t ing bit [ 8] in t his regist er.
When t he bit is set t he 82599 does not advert ise PCI e V2. 0 link-
speed support .
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3. 1.6. 2 Li nk Wi dt h
The 82599 support s a maximum link widt h of x8, x4, x2, or x1 as det ermined by t he PCI e Analog
Configurat ion Module in t he EEPROM and can be set as follows. Not e t hat t hese set t ings might not
be needed during normal operat ion:
The maximum link widt h is loaded int o t he Max Link Widt h field of t he PCI e Capabilit y regist er
( LCAP[ 11: 6] ) . Hardware default is t he x8 link.
During link configurat ion, t he plat form and t he 82599 negot iat e on a common link widt h. The link widt h
must be one of t he support ed PCI e link widt hs ( x1, 2x, x4, x8) , such t hat :
I f Maximum Link Widt h = x8, t hen t he 82599 negot iat es t o eit her x8, x4, x2 or x1
1
I f Maximum Link Widt h = x4, t hen t he 82599 negot iat es t o eit her x4 or x1
I f Maximum Link Widt h = x1, t hen t he 82599 only negot iat es t o x1
The 82599 does not init iat e a hardware aut onomous link widt h change.
Not e: Some PCI e x8 slot s are act ually configured as x4 slot s. These slot s have insufficient
bandwidt h for full 10 GbE line rat e wit h dual port 10 GbE devices. I f a solut ion suffers
bandwidt h issues when bot h 10 GbE port s are act ive, it is recommended t o verify t hat t he
PCI e slot is indeed a t rue PCI e x8.
3. 1.6. 3 Pol ar i t y I nv er si on
I f polarit y inversion is det ect ed, t he receiver must invert t he received dat a.
During t he t raining sequence, t he receiver looks at symbols 6- 15 of TS1 and TS2 as t he indicat ors of
lane polarit y inversion ( D+ and D- are swapped) . I f lane polarit y inversion occurs, t he TS1 symbols 6-
15 received are D21. 5 as opposed t o t he expect ed D10. 2. Similarly, if lane polarit y inversion occurs,
symbols 6- 15 of t he TS2 ordered set are D26. 5 as opposed t o t he expect ed 5 D5. 2. This provides t he
clear indicat ion of lane polarit y inversion.
3. 1.6. 4 L0s Ex i t Lat ency
The number of FTS sequences ( N_FTS) sent during L0s exit is loaded from t he EEPROM int o an 8- bit
read- only regist er.
Wor d)
Enabl e x 8
Set t i ng
( Def aul t )
Li mi t t o x 4
Set t i ng
Li mi t t o x 2
Set t i ng
Li mi t t o x 1
Set t i ng
Descr i pt i on
2* N+ 1 0x094 MORI A6 regist er offset ( lower word) .
2* N+ 2 0x0000 0x00F0 0x00FC 0x00FE
Lanes can be disabled by set t ing bit s[ 7: 0] in
t his offset . Having bit [ X] set causes laneX t o
be disabled, result ing in narrower link widt hs
( bit s per lane) .
1. See rest rict ion in Sect ion 3.1. 6. 6.

61
3.1.6.5 Lane- t o- Lane De- Sk ew
A mult i- lane link can have many sources of lane- t o- lane skew. Alt hough symbols are t ransmit t ed
simult aneously on all lanes, t hey cannot be expect ed t o arrive at t he receiver wit hout lane- t o- lane
skew. The lane- t o- lane skew can include component s, which are less t han one bit t ime, bit t ime unit s
( 400/ 200 ps for 2. 5/ 5 Gb) , or full symbol t ime unit s ( 4/ 2 ns) . This t ype of skew is caused by t he
ret iming repeat ers' insert / delet e operat ions. Receivers use TS1 or TS2 or Skip Ordered Set s ( SOS) t o
perform link deskew funct ions.
The 82599 support s deskew of up t o 12 symbols t ime [ 48 ns for PCI e v2. 0 ( 2. 5GT/ s) and 24 ns for
PCI e V2. 0 ( 5GT/ s) ] .
3.1.6.6 Lane Rev er sal
Aut o lane reversal is support ed by t he 82599 at it s hardware default set t ing. The following lane reversal
modes are support ed:
Lane configurat ions x8, x4, x2, and x1
Lane reversal in x8 and in x4
Degraded mode ( downshift ) from x8 t o x4 t o x2 t o x1 and from x4 t o x1, wit h one rest rict ion if
lane reversal is execut ed in x8, t hen downshift is only t o x1 and not t o x4.
Figure 3.2 t hrough Figure 3. 5 shows t he lane downshift in bot h regular and reversal connect ions as well
as lane connect ivit y from a syst em level perspect ive.
Fi gur e 3.2. Lane Dow nshi f t i n an x 8 Conf i gur at i on
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Fi gur e 3.3. Lane Dow nshi f t i n a Rever sal x 8 Conf i gur at i on
Fi gur e 3.4. Lane Dow nshi f t i n a x 4 Conf i gur at i on
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Ethernet Controller Ethernet Controller

63
Aut o lane reversal can be disabled or forced t o reversal mode by set t ing t he int ernal regist ers:
PHYLTSSMDBG00 and LTSSMDBG0. These regist ers are loaded from t he PCI e Analog Configurat ion
Module in t he EEPROM and could be set as follows. Not e t hat t hese set t ing are not likely being needed
in normal operat ion:
3.1.6.7 Reset
The PCI e PHY supplies t he core reset t o t he 82599. The reset can be caused by t he following event s:
Upst ream move t o hot reset I nband Mechanism ( LTSSM) .
Recovery failure ( LTSSM ret urns t o det ect )
Upst ream component moves t o disable.
3.1.6.8 Scr ambl er Di sabl e
The scrambler/ de- scrambler funct ionalit y in t he 82599 can be eliminat ed by t wo mechanisms:
Upst ream according t o t he PCI e specificat ion
EEPROM bit Scram_dis.
Fi gur e 3. 5. Lane Dow nshi f t i n an x 4 Rever sal Conf i gur at i on
Wor d)
Lane Rev er sal
Di sabl e Set t i ng
For ce Lane
Rever sal
Set t i ng
Descr i pt i on
2* N+ 1 0x310 0x310 PHYLTSSMDBG00 regist er OFFSET ( lower word)
2* N+ 2 0x0003 0x0013 Lower word DATA of t he PHYLTSSMDBG00 regist er
2* N+ 5 0x314 0x314 LTSSMDBG0 regist er OFFSET ( lower word)
2* N+ 6 0x3920 0x3920 Lower word DATA of t he LTSSMDBG0 regist er
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3.1.7 Er r or Ev ent s and Er r or Repor t i ng
3. 1.7. 1 Gener al Descr i pt i on
PCI e defines t wo error report ing paradigms: t he baseline capabilit y and t he Advanced Error Report ing
( AER) capabilit y. The baseline error report ing capabilit ies are required of all PCI e devices and define t he
minimum error report ing requirement s. The AER capabilit y is defined for more robust error report ing
and is implement ed wit h a specific PCI e capabilit y st ruct ure. Bot h mechanisms are support ed by t he
82599.
The SERR# Enable and t he Parit y Error bit s from t he Legacy Command regist er also t ake part in t he
error report ing and logging mechanism.
I n a mult i- funct ion device, PCI e errors t hat are not relat ed t o any specific funct ion wit hin t he device are
logged in t he corresponding st at us and logging regist ers of all funct ions in t hat device. These include
t he following cases of Unsupport ed Request ( UR) :
A memory or I / O access t hat does not mat ch any BAR for any funct ion
Messages
Configurat ion accesses t o a non- exist ent funct ion
Figure 3. 6 shows, in det ail, t he flow of error report ing in t he 82599.

65
3. 1. 7. 2 Er r or Ev ent s
Table 3.8 list s t he error event s ident ified by t he 82599 and t he response in t erms of logging, report ing,
and act ions t aken. Refer t o t he PCI e specificat ion for t he effect on t he PCI St at us regist er.
Fi gur e 3. 6. Er r or Repor t i ng Mechani sm

Device Status ::
Correctable Error Detected
Device Status ::
Non-Fatal Error Detected
Device Status ::
Fatal Error Detected
Device Status ::
Unsupported Request Detected
Status ::
Signaled Target Abort
Status ::
Received Target Abort
Status ::
Received Master Abort
Status ::
Detected Parity Error
Root Error Status
Correctable Error Status
Correctable Error Mask
Uncorrectable Error Status
Uncorrectable Error Mask
Uncorrectable Error Severity
S
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g

-
N
o
t

G
a
t
e
d

Error Sources
(Associated with Port)
Device Control ::
Correctable Error Reporting Enable
Device Control ::
Unsupported Request Reporting Enable
Device Control ::
Non-Fatal Error Reporting Enable
Device Control ::
Fatal Error Reporting Enable
Report Error Command ::
Correctable Error Reporting Enable
Non-Fatal Error Reporting Enable
Fatal Error Reporting Enable
Interrupt
Command::
Parity Error Response
Bridge Control::
SERR Enable
Error Message
Processing
Rcv
Msg
Secondary Side Error Sources
System
Error
Root Control::
System Error on Correctable Error Enable
Root Control::
System Error on Non-Fatal Error Enable
Root Control::
System Error on Fatal Error Enable
Status::
Master Data Parity Error
Status::
Signaled System Error
Secondary Status::
Detected Parity Error
Secondary Status::
Signaled Master Abort
Secondary Status::
Secondary Status::
Bridge Control::
Parity Error Response Enable
Secondary Status::
Master Data Parity
Error
Secondary Status::
Received System Error
Either Implementation
Acceptable the unqualified
version is more like PCI P2P
bridge spec
Command::
SERR# Enable
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66
Tabl e 3.8. Response and Repor t i ng of PCI e Er r or Event s
Er r or Name Er r or Ev ent s Def aul t Sev er i t y Act i on
Physical Layer Errors
Receiver Error
8b/ 10b Decode Errors
Packet Framing Error
Correct able
Send ERR_CORR
TLP t o I nit iat e NAK, Drop Dat a
DLLP t o Drop
Dat a Link Errors
Bad TLP
Bad CRC
Not Legal EDB
Wrong Sequence Number
Correct able
Send ERR_CORR
TLP t o I nit iat e NAK, Drop Dat a
Bad DLLP Bad CRC
Correct able
Send ERR_CORR
DLLP to Drop
Replay Timer
Timeout
REPLAY_TI MER expirat ion
Correct able
Send ERR_CORR
Follow LL Rules
REPLAY NUM
Rollover
REPLAY NUM Rollover
Correct able
Send ERR_CORR
Follow LL Rules
Dat a Link Layer
Prot ocol Error
Violat ions of Flow Cont rol
I nit ializat ion Prot ocol
Uncorrect able
Send ERR_FATAL
TLP Errors
Poisoned TLP
Received
TLP Wit h Error Forwarding
Uncorrect able
ERR_NONFATAL
Log Header
I f complet ion TLP:
Error is non- fat al ( default case)
Send error message if advisory
Ret ry t he request once and send
advisory error message on each failure
I f fails, send uncorrect able error
message
Error is defined as fat al
Send uncorrect able error message
Unsupport ed
Request ( UR)
Wrong Config Access
MRdLk
Config Request Type1
Unsupport ed Vendor Defined
Type 0 Message
Not Valid MSG Code
Not Support ed TLP Type
Wrong Funct ion Number
Received TLP Out side Address
Range
Uncorrect able
ERR_NONFATAL
Log header
Send Complet ion Wit h UR
Complet ion Timeout
Complet ion Timeout Timer
Expired
Uncorrect able
ERR_NONFATAL
Error is non- fat al ( default case)
Send error message if advisory
Ret ry t he request once and send
advisory error message on each failure
I f fails, send uncorrect able error
message
Error is defined as fat al
Send uncorrect able error message
Complet er Abort
Received Target Access Wit h
Dat a Size > 64 bit s
Uncorrect able.
ERR_NONFATAL
Log header
Send complet ion wit h CA
Unexpect ed
Complet ion
Received Complet ion Wit hout
a Request For I t ( Tag, I D, et c. )
Uncorrect able
ERR_NONFATAL
Log Header
Discard TLP
Receiver Overflow
Received TLP Beyond
Allocat ed Credit s
Uncorrect able
ERR_FATAL
Receiver Behavior is Undefined

67
3. 1. 7. 3 Er r or For w ar di ng ( TLP Poi soni ng)
I f a TLP is received wit h an error- forwarding t railer, t he packet is dropped and is not delivered t o it s
dest inat ion. The 82599 t hen react s as described in Table 3.8.
The 82599 does not init iat e any addit ional mast er request s for t hat PCI funct ion unt il it det ect s an
int ernal soft ware reset for t he associat ed LAN port . Soft ware is able t o access device regist ers aft er
such a fault .
Syst em logic is expect ed t o t rigger a syst em- level int errupt t o inform t he operat ing syst em of t he
problem. Operat ing syst ems can t hen st op t he process associat ed wit h t he t ransact ion, reallocat e
memory t o a different area inst ead of t he fault y area, et c.
3.1.7.4 End- t o- End CRC ( ECRC)
The 82599 support s ECRC as defined in t he PCI e specificat ion. The following funct ionalit y is provided:
I nsert ing ECRC in all t ransmit t ed TLPs:
The 82599 indicat es support for insert ing ECRC in t he ECRC Generat ion Capable bit of t he PCI e
configurat ion regist ers. This bit is loaded from t he ECRC Generat ion EEPROM bit .
I nsert ing ECRC is enabled by t he ECRC Generat ion Enable bit of t he PCI e configurat ion
regist ers.
ECRC is checked on all incoming TLPs. A packet received wit h an ECRC error is dropped. Not e t hat
for complet ions, a complet ion t imeout occurs lat er ( if enabled) , which result s in re- issuing t he
request .
The 82599 indicat es support for ECRC checking in t he ECRC Check Capable bit of t he PCI e
configurat ion regist ers. This bit is loaded from t he ECRC Check EEPROM bit .
Checking of ECRC is enabled by t he ECRC Check Enable bit of t he PCI e configurat ion regist ers.
ECRC errors are report ed
Syst em soft ware can configure ECRC independent ly per each LAN funct ion
Flow Cont rol
Prot ocol Error
Minimum I nit ial Flow Cont rol
Advert isement s
Flow Cont rol Updat e for
I nfinit e Credit Advert isement
Uncorrect able.
ERR_FATAL
Receiver Behavior is Undefined
Malformed TLP ( MP)
Dat a Payload Exceed
Max_Payload_Size
Received TLP Dat a Size Does
Not Mat ch Lengt h Field
TD field value does not
correspond wit h t he observed
size
PM Messages That Don t Use
TC0.
Usage of Unsupport ed VC
Uncorrect able
ERR_FATAL
Log Header
Drop t he Packet , Free FC Credit s
Complet ion wit h
Unsuccessful
Complet ion St at us
No Act ion ( already done
by originat or of
complet ion)
Free FC Credit s
Tabl e 3. 8. Response and Repor t i ng of PCI e Er r or Ev ent s
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3.1.7. 5 Par t i al Read and Wr i t e Request s
Par t i al memor y accesses
The 82599 has limit ed support of read and writ e request s wit h only part of t he byt e enable bit s set :
Part ial writ es wit h at least one byt e enabled are silent ly dropped.
Zero- lengt h writ es have no int ernal impact ( not hing writ t en, no effect such as clear- by- writ e) . The
t ransact ion is t reat ed as a successful operat ion ( no error event ) .
Part ial reads wit h at least one byt e enabled are handled as a full read. Any side effect of t he full
read ( such as clear by read) is also applicable t o part ial reads.
Zero- lengt h reads generat e a complet ion, but t he regist er is not accessed and undefined dat a is
ret urned.
Not e: The 82599 does not generat e an error indicat ion in response t o any of t he previous event s.
Par t i al I / O accesses
Part ial access on address
A writ e access is discarded
A read access ret urns 0xFFFF
Part ial access on dat a, where t he address access was correct
A writ e access is discarded
A read access performs t he read
3. 1. 7. 6 Er r or Pol l ut i on
Error pollut ion can occur if error condit ions for a given t ransact ion are not isolat ed t o t he error' s first
occurrence. I f t he PHY det ect s and report s a receiver error, t o avoid having t his error propagat e and
cause subsequent errors at t he upper layers, t he same packet is not signaled at t he dat a link or
t ransact ion layers. Similarly, when t he dat a link layer det ect s an error, subsequent errors t hat occur for
t he same packet are not signaled at t he t ransact ion layer.
3. 1.7. 7 Compl et i on Wi t h Unsuccessf ul Compl et i on St at us
A complet ion wit h unsuccessful complet ion st at us is dropped and not delivered t o it s dest inat ion. The
request t hat corresponds t o t he unsuccessful complet ion is ret ried by sending a new request for
undeliverable dat a.
3. 1. 7. 8 Er r or Repor t i ng Changes
The PCI e Rev. 1.1 specificat ion defines t wo changes t o advanced error report ing. A ( new) Role Based
Error Report ing bit in t he Device Capabilit ies regist er is set t o 1b t o indicat e t hat t hese changes are
support ed by t he 82599.
1. Set t ing t he SERR# Enable bit in t he PCI Command regist er also enables UR report ing ( in t he same
manner t hat t he SERR# Enable bit enables report ing of correct able and uncorrect able errors) . I n
ot her words, t he SERR# Enable bit overrides t he Unsupport ed Request Error Report ing Enable bit in
t he PCI e Device Cont rol regist er.

69
2. Changes in t he response t o some uncorrect able non- fat al errors det ect ed in non- post ed request s t o
t he 82599. These are called Advisory Non- Fat al Error cases. For each of t he errors list ed, t he
following behavior is defined:
The Advisory Non- Fat al Error St at us bit is set in t he Correct able Error St at us regist er t o indicat e
t he occurrence of t he advisory error and t he Advisory Non- Fat al Error Mask corresponding bit in
t he Correct able Error Mask regist er is checked t o det ermine whet her t o proceed furt her wit h
logging and signaling.
I f t he Advisory Non- Fat al Error Mask bit is clear, logging proceeds by set t ing t he corresponding
bit in t he Uncorrect able Error St at us regist er, based upon t he specific uncorrect able error t hat ' s
being report ed as an advisory error. I f t he corresponding Uncorrect able Error bit in t he
Uncorrect able Error Mask regist er is clear, t he First Error Point er and Header Log regist ers are
updat ed t o log t he error, assuming t hey are not st ill occupied by a previous unserviced error.
An ERR_COR Message is sent if t he Correct able Error Report ing Enable bit is set in t he Device
Cont rol regist er. An ERROR_NONFATAL message is not sent for t his error.
The following uncorrect able non- fat al errors are considered as advisory non- fat al errors:
A complet ion wit h an Unsupport ed Request or Complet er Abort ( UR/ CA) st at us t hat signals an
uncorrect able error for a non- post ed request . I f t he severit y of t he UR/ CA error is non- fat al, t he
complet er must handle t his case as an advisory non- fat al error.
When t he request er of a non- post ed request t imes out while wait ing for t he associat ed complet ion,
t he request er is permit t ed t o at t empt t o recover from t he error by issuing a separat e subsequent
request or t o signal t he error wit hout at t empt ing recovery. The request er is permit t ed t o at t empt
recovery zero, one, or mult iple ( finit e) t imes, but must signal t he error ( if enabled) wit h an
uncorrect able error message if no furt her recovery at t empt is made. I f t he severit y of t he
complet ion t imeout is non- fat al, and t he request er elect s t o at t empt recovery by issuing a new
request , t he request er must first handle t he current error case as an advisory non- fat al error.
Recept ion of a poisoned TLP. See Sect ion 3. 1. 7. 3.
When a receiver receives an unexpect ed complet ion and t he severit y of t he unexpect ed complet ion
error is non- fat al, t he receiver must handle t his case as an advisory non- fat al error.
3.1.8 Per f or mance Moni t or i ng
The 82599 incorporat es PCI e performance monit oring count ers t o provide common capabilit ies t o
evaluat e performance. The 82599 implement s four 32- bit count ers t o correlat e bet ween concurrent
measurement s of event s as well as t he sample delay and int erval t imers. The four 32- bit count ers can
also operat e in a t wo 64- bit mode t o count long int ervals or payloads. Soft ware can reset , st op, or st art
t he count ers ( all at t he same t ime) .
Some count ers operat e wit h a t hreshold t he count er increment s only when t he monit ored event
crossed a configurable t hreshold ( such as t he number of available credit s is below a t hreshold)
Count ers operat e in one of t he following modes:
Count mode t he count er increment s when t he respect ive event occurred
Leaky bucket mode t he count er increment s only when t he rat e of event s exceeded a cert ain
value. See Sect ion 3.1. 8. 1 for more det ails.
The list of event s support ed by t he 82599 and t he count ers Cont rol bit s are described in
Sect ion 8. 2. 3. 4.
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3. 1.8. 1 Leak y Buck et Mode
Each of t he count ers can be configured independent ly t o operat e in a leaky bucket mode. When in leaky
bucket mode, t he following funct ionalit y is provided:
One of four 16- bit Leaky Bucket Count ers ( LBC) is enabled via t he LBC Enable [ 3: 0] bit s in t he PCI e
St at ist ic Cont rol regist er # 1.
The LBC is cont rolled by t he GI O_COUNT_START, GI O_COUNT_STOP, GI O_COUNT_RESET bit s in
t he PCI e St at ist ic Cont rol regist er # 1.
The LBC increment s every t ime t he respect ive event occurs.
The LBC is decrement ed every T s as defined in t he LBC Timer field in t he PCI e St at ist ic Cont rol
regist ers.
When an event occurs and t he value of t he LBC meet s or exceeds t he t hreshold defined in t he LBC
Threshold field in t he PCI e St at ist ic Cont rol regist ers, t he respect ive st at ist ics count er increment s,
and t he LBC count er is cleared t o zero.
3.2 SMBus
SMBus is a management int erface for pass t hrough and/ or configurat ion t raffic bet ween an ext ernal
Management Cont roller ( MC) and t he 82599.
3.2.1 Channel Behav i or
The SMBus specificat ion defines t he maximum frequency of t he SMBus as 100 KHz. However, t he
SMBus int erface can be act ivat ed up t o 400 KHz wit hout violat ing any hold and set up t ime.
SMBus connect ion speed bit s define t he SMBus mode. Also, SMBus frequency support can be defined
only from t he EEPROM.
3.2.2 SMBus Addr essi ng
The number of SMBus addresses t hat t he 82599 responds t o depends on t he LAN mode ( t eaming/ non-
t eaming) . I f t he LAN is in t eaming mode ( failover mode) , t he 82599 is present ed over t he SMBus as
one device and has one SMBus address. I f t he LAN is in non- t eaming mode, t he SMBus is present ed as
t wo SMBus devices on t he SMBus ( t wo SMBus addresses) . I n dual- address mode, all pass t hrough
funct ionalit y is duplicat ed on t he SMBus address, where each SMBus address is connect ed t o a different
LAN port .
Not e: Designers are not allowed t o configure bot h port s t o t he same address. When a LAN funct ion
is disabled, t he corresponding SMBus address is not present ed t o t he MC.
The SMBus address met hod is defined t hrough t he SMB Addressing Mode bit in t he EEPROM. The
SMBus addresses are set using t he SMBus 0 Slave Address and SMBus 1 Slave Address fields in t he
EEPROM.
Not e: I f single- address mode is select ed, only t he SMBus 0 Slave Address field is valid.
The SMBus addresses ( t hose t hat are enabled from t he EEPROM) can be re- assigned using t he SMBus
ARP prot ocol.
Besides t he SMBus address values, all t he previous paramet ers of t he SMBus ( SMBus channel select ion,
addressing mode, and address enable) can be set only t hrough t he EEPROM.
All SMBus addresses should be in Net work Byt e Order ( NBO) wit h t he most significant byt e first .

71
3. 2. 3 SMBus Not i f i cat i on Met hods
The 82599 support s t hree met hods of signaling t he ext ernal MC t hat it has informat ion t hat needs t o be
read by t he ext ernal MC:
SMBus alert Refer t o Sect ion 3.2. 3. 1.
Asynchronous not ify Refer t o Sect ion 3. 2. 3. 2.
Direct receive Refer t o sect ion Sect ion 3. 2. 3. 3.
The not ificat ion met hod t hat is used by t he 82599 can be configured from t he SMBus using t he Receive
Enable command. The default met hod is set from t he Not ificat ion Met hod field in t he LRXEN1 word from
t he EEPROM.
The following event s cause t he 82599 t o send a not ificat ion event t o t he ext ernal MC:
Receiving a LAN packet designat ed for t he MC.
Receiving a Request St at us command from t he MC t hat init iat es a st at us response.
The 82599 is configured t o not ify t he ext ernal MC upon st at us changes ( by set t ing t he EN_STA bit
in t he Receive Enable command) along wit h one of t he following event s:
TCO Command Abort ed
Link St at us changed
Power st at e change
LinkSec indicat ion
There can be cases where t he ext ernal MC is hung and cannot respond t o t he SMBus not ificat ion. The
82599 has a t imeout value defined in t he EEPROM ( refer t o Sect ion 6.4. 4. 3) t o avoid hanging while
wait ing for t he not ificat ion response. I f t he MC does not respond unt il t he t imeout expires, t he
not ificat ion is deassert ed.
3.2. 3.1 SMBus Al er t and Al er t Response Met hod
The SMBus Alert # signal is an addit ional SMBus signal, which act s as an asynchronous int errupt signal
t o an ext ernal SMBus mast er. The 82599 assert s t his signal each t ime it has a message t hat it needs
t he ext ernal MC t o read and if t he chosen not ificat ion met hod is t he SMBus alert met hod.
Not e: SMBus Alert # is an open- drain signal, which means t hat ot her devices beside t he 82599 can
be connect ed t o t he same alert pin and t he ext ernal MC requires a mechanism t o dist inguish
bet ween t he alert sources as follows:
The ext ernal MC responds t o t he alert by issuing an ARA cycle t o det ect t he alert source device. The
82599 responds t o t he ARA cycle ( if it was t he SMBus alert source) and deassert s t he alert when t he
ARA cycle complet es. Following t he ARA cycle, t he MC issues a Read command t o ret rieve t he t he
82599 message.
Not e: Some MCs do not implement t he ARA cycle t ransact ion. These MCs respond t o an alert by
issuing a Read command t o t he 82599 ( 0xC0/ 0xD0 or 0xDE) . The 82599 always responds t o
a Read command even if it is not t he source of t he not ificat ion. The default response is a
st at us t ransact ion. I f t he 82599 is t he source of t he SMBus alert , it replies t o t he read
t ransact ion.
The ARA cycle is an SMBus receive byt e t ransact ion t o SMBus Address 0x18.
Not e: The ARA t ransact ion does not support PEC.
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72
The alert response address t ransact ion format is as follows:
Fi gur e 3.7. SMBus ARA Cycl e For mat
3. 2.3. 2 Asy nchr onous Not i f y Met hod
When configured using t he asynchronous not ify met hod, t he 82599 act s as an SMBus mast er and
not ifies t he ext ernal MC by issuing a modified form of t he writ e word t ransact ion. The asynchronous
not ify t ransact ion SMBus address and dat a payload are configured using t he Receive Enable command
or by using t he EEPROM default s ( see Sect ion 6. 4. 3. 19) .
Not e: The asynchronous not ify is not prot ect ed by a PEC byt e.
Fi gur e 3.8. Asy nchr onous Not i f y Command For mat
3. 2.3. 3 Di r ect Recei v e Met hod
I f configured, t he 82599 has t he capabilit y t o send t he message it needs t o t ransfer t o t he ext ernal MC,
as a mast er over t he SMBus inst ead of alert ing t he MC and wait ing for it t o read t he message.
The message format is shown Figure 3. 9. Not e t hat t he command t hat should be used is t he same
command t hat should be used by t he MC in t he Block Read command and t he opcode t hat t he 82599
put s in t he dat a is t he same as it would have put in t he Block Read command of t he same funct ionalit y.
The rules for t he F an L flags are also t he same as in t he Block Read command.
Fi gur e 3.9. Di r ect Recei ve Tr ansact i on For mat
1 7 1 1 8 1 1
S Alert Response Address Rd A Slave Device Address A P
0001 100 0 0 1
1 7 1 1 7 1 1
S Tar get Address Wr A Sending Device Address A - - -
MC Slave Address 0 0
Manageabilit y Slave SMBus
Address
0 0
8 1 8 1 1
Dat a Byt e Low A Dat a Byt e High A P
I nt erface 0 Alert Value 0
1 7 1 1 1 1 6 1
S Target Address Wr A F L Command A - - -
MC Slave Address 0 0
First
Flag
Last
Flag
Receive TCO Command
01 0000b
0
8 1 8 1 1 8 1 1
Byt e Count A Dat a Byt e 1 A - - - A Dat a Byt e N A P
N 0 0 0 0

73
3. 2.4 Recei v e TCO Fl ow
The 82599 is used as a channel for receiving packet s from t he net work link and passing t hem t o t he
ext ernal MC. The MC can configure t he 82599 t o pass specific packet s t o t he MC ( see Sect ion 10. 2) .
Once a full packet is received from t he link and ident ified as a manageabilit y packet t hat should be
t ransferred t o t he MC, t he 82599 st art s t he receive TCO t ransact ion flow t o t he MC.
The maximum SMBus fragment lengt h is defined in t he EEPROM ( see Sect ion 6. 4. 4. 2) . The 82599 uses
t he SMBus not ificat ion met hod t o not ify t he MC t hat it has dat a t o deliver. The packet is divided int o
fragment s, where t he 82599 uses t he maximum fragment size allowed in each fragment . The last
fragment of t he packet t ransfer is always t he st at us of t he packet . As a result , t he packet is t ransferred
in at least t wo fragment s. The dat a of t he packet is t ransferred in t he receive TCO LAN packet
t ransact ion.
When SMBus alert is select ed as MC not ificat ion met hod, t he 82599 not ifies t he MC on each fragment of
a mult i- fragment packet .
When asynchronous not ify is select ed as t he MC not ificat ion met hod, t he 82599 not ifies t he MC only on
t he first fragment of a received packet . I t is t he MC' s responsibilit y t o read t he full packet including all
t he fragment s.
Any t imeout on t he SMBus not ificat ion result s in discarding of t he ent ire packet . Any NACK by t he MC
on one of t he 82599' s receive byt es also causes t he packet t o be silent ly discarded.
Since SMBus t hroughput is lower t han t he net work link t hroughput , t he 82599 uses an 8 KB int ernal
buffer per LAN port , which st ores incoming packet s prior t o being sent over t he SMBus int erface. The
82599 services back- t o- back management packet s as long as t he buffer does not overflow.
The maximum size of t he received packet is limit ed by t he 82599 hardware t o 1536 byt es. Packet s
larger t hen 1536 byt es are silent ly discarded. Any packet smaller t han 1536 byt es is processed by t he
82599.
Not e: When t he RCV_EN bit is cleared, all receive TCO funct ionalit y is disabled including packet s
direct ed t o t he MC as well as aut o ARP processing.
3.2.5 Tr ansmi t TCO Fl ow
The 82599 is used as a channel for t ransmit t ing packet s from t he ext ernal MC t o t he net work link. The
net work packet is t ransferred from t he ext ernal MC over t he SMBus, and t hen, when fully received by
t he 82599, is t ransmit t ed over t he net work link.
I n dual- address mode, each SMBus address is connect ed t o a different LAN port . When a packet
received in SMBus t ransact ions using t he SMBus 0 Slave Address, it is t ransmit t ed t o t he net work using
LAN port 0 and is t ransmit t ed t hrough LAN port 1 if received on SMBus 1 Slave Address. I n single-
address mode, t he t ransmit t ed port is chosen according t o t he failover algorit hm ( see
Sect ion 10. 2. 2.2) .
The 82599 support s packet s up t o an Et hernet packet lengt h of 1536 byt es. SMBus t ransact ions can be
up t o 240 byt es in lengt h, which means t hat packet s can be t ransferred over t he SMBus in more t han
one fragment . I n each command byt e t here are t he F and L bit s. When t he F bit is set , it means t hat
t his is t he first fragment of t he packet and L means t hat it is t he last fragment of t he packet ( when bot h
are set , it means t hat t he ent ire packet is in one fragment ) . The packet is sent over t he net work link
only aft er all it s fragment s have been received correct ly over t he SMBus.
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The 82599 calculat es t he L2 CRC on t he t ransmit t ed packet , and adds it s four byt es at t he end of t he
packet . Any ot her packet field ( such as XSUM) must be calculat ed and insert ed by t he ext ernal MC
cont roller ( t he 82599 does not change any field in t he t ransmit t ed packet , besides adding padding and
CRC byt es) . I f t he packet sent by t he MC is bigger t han 1536 byt es, t hen t he packet is silent ly discard
by t he 82599.
The minimum packet lengt h defined by t he 802. 3 specificat ion is 64 byt es. The 82599 pads packet s
t hat are less t han 64 byt es t o meet t he specificat ion requirement s ( no need for t he MC t o do it ) . There
is one except ion, t hat is if t he packet sent over t he SMBus is less t han 32 byt es, t he MC must pad it for
at least 32 byt es. The passing byt es value should be zero. Packet s which are smaller t hen 32 byt es
( including padding) are silent ly discarded by t he 82599.
I f t he net work link is down when t he 82599 has received t he last fragment of t he packet , it silent ly
discards t he packet .
Not e: Any link down event while t he packet is being t ransferred over t he SMBus does not st op t he
operat ion, since t he 82599 wait s for t he last fragment t o end t o see whet her t he net work link
is up again.
The t ransmit SMBus t ransact ion is described in Sect ion 10. 5. 2.1.
3. 2. 5. 1 Tr ansmi t Er r or s i n Sequence Handl i ng
Once a packet is t ransferred over t he SMBus from t he MC t o t he 82599 t he F and L flags should follow
specific rules. The F flag defines t hat t his is t he first fragment of t he packet , and t he L flag defines t hat
t he t ransact ion cont ains t he last fragment of t he packet .
Table 3. 9 list s t he different opt ion of t he flags in t ransmit packet t ransact ions.
Please not e t hat since every ot her Block Writ e command in t he TCO prot ocol has bot h t he F and L flags
off, t hey cause flushing any pending t ransmit fragment s t hat were previously received.
3. 2.5. 2 TCO Command Abor t ed Fl ow
Bit 6 in first byt e of t he st at us ret urned from t he 82599 t o t he ext ernal MC indicat es t hat t here was a
problem wit h previous SMBus t ransact ions or wit h t he complet ion of t he operat ion request ed in
previous t ransact ion.
The abort can be assert ed due t o any of t he following reasons:
Any error in t he SMBus prot ocol ( NACK, SMBus t ime out s) .
Any error in compat ibilit y due t o required prot ocols t o specific funct ionalit y ( RX Enable command
wit h byt e count not 1/ 14 as defined in t he command specificat ion) .
Tabl e 3.9. SMBus Tr ansmi t Sequenci ng
Pr ev i ous Cur r ent Act i on/ Not es
Last First Allowed accept bot h.
Last Not First Error for current t ransact ion. Current t ransact ion is discarded and an abort st at us is assert ed.
Not Last First
Error for previous t ransact ion. The previous t ransact ion ( unt il previous First ) is discarded. The current
packet is processed.
No abort st at us is assert ed.
Not Last Not First The 82599 can process t he current t ransact ion.

75
I f t he 82599 does not have space t o st ore t he t ransmit packet from t he MC ( in an int ernal buffer)
before sending it t o t he link. I n t his case, all t ransact ions are complet ed but t he packet is discarded
and t he MC is not ified t hrough t he Abort bit .
Error in F/ L bit sequence during mult i- fragment t ransact ions.
The Abort bit is assert ed aft er an int ernal reset t o t he 82599 manageabilit y unit .
Not e: The abort in t he st at us does not always imply t hat t he last t ransact ion of t he sequence was
incorrect . There is a t ime delay bet ween t he t ime t he st at us is read from t he 82599 and t he
t ime t he t ransact ion has occurred.
3. 2. 6 Concur r ent SMBus Tr ansact i ons
Concurrent SMBus writ e t ransact ions are not permit t ed. Once a t ransact ion is st art ed, it must be
complet ed before addit ional t ransact ion can be init iat ed.
3.2.7 SMBus ARP Funct i onal i t y
The 82599 support s t he SMBus ARP prot ocol as defined in t he SMBus 2. 0 specificat ion. Not e t hat t he
82599 is a persist ent slave address device each t ime it s SMBus address is valid aft er power- up and
loaded from t he EEPROM. The 82599 support s all SMBus ARP commands defined in t he SMBus
specificat ion, bot h general and direct ed.
Not e: SMBus ARP can be disabled t hrough EEPROM configurat ion ( See Sect ion 6. 4. 4.3) .
3. 2. 7. 1 SMBus ARP i n Dual - / Si ngl e- Mode
The 82599 can operat e in eit her single SMBus address mode or in dual SMBus address mode. These
modes reflect on it s SMBus-ARP behavior.
When working in single- address mode, t he 82599 present s it self on t he SMBus as one device, and
responds t o SMBus-ARP as only one device. I n t his case it s SMBus address is SMBus address 0 as
defined in EEPROM SMBus ARP addresses word ( see Sect ion 6. 4. 4. 4) . The device has only one Address
Resolved ( AR) and one Address Valid ( AV) flag each. The vendor I D t hat is t he Et hernet MAC address of
t he LAN' s port , is t aken from port 0 address.
I n dual- address mode, t he 82599 responds as t wo SMBus devices, meaning it has t wo set s of AR/ AV
flags ( one for each port ) . The 82599 should respond t wice t o t he SMBus-ARP mast er, one t ime for each
port . Bot h SMBus addresses are t aken from t he SMBus ARP addresses word of t he EEPROM. The Unique
Device I dent ifier ( UDI D) is different bet ween t he t wo port s in t he version I D field, which represent t he
Et hernet MAC address, which is different bet ween t he t wo port s. I t is recommended for t he 82599 t o
first answer as port 0, and only when t he address is assigned, t o answer as port 1 t o t he Get UDI D
command.
3.2.7.2 SMBus ARP Fl ow
SMBus- ARP flow is based on t he st at us of t wo AVs and ARs:
Address Valid This flag is set when t he 82599 has a valid SMBus address.
Address Resolved This flag is set when t he 82599 SMBus address is resolved: SMBus address
was assigned by t he SMBus- ARP process.
Not e: These flags are int ernal t he 82599 flags and not shown t o ext ernal SMBus devices.
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76
Since t he 82599 is a Persist ent SMBus Address ( PSA) device, t he AV flag is always set , while t he AR flag
is cleared aft er power- up unt il t he SMBus- ARP process complet es. Since AV is always set , it means t hat
t he 82599 always has a valid SMBus address. The ent ire SMBus ARP Flow is described in Figure 3. 10.
When t he SMBus mast er needs t o st art t he SMBus- ARP process, it reset s ( in t erms of ARP funct ionalit y)
all t he devices on t he SMBus, by issuing eit her Prepare t o ARP or Reset Device commands. When t he
82599 accept s one of t hese commands, it clears it s AR flag ( if set from previous SMBus- ARP process) ,
but not it s AV flag ( The current SMBus address remains valid unt il t he end of t he SMBus ARP process) .
A cleared AR flag means t hat t he 82599 answers t he following SMBus ARP t ransact ions t hat are issued
by t he mast er. The SMBus mast er t hen issues a Get UDI D command ( General or Direct ed) , t o ident ify
t he devices on t he SMBus. The 82599 responds t o t he Direct ed command all t he t ime, and t o t he
General command only if it s AR flag is not set . Aft er t he Get UDI D, t he mast er assigns t he 82599
SMBus address, by issuing Assign Address command. The 82599 checks whet her t he UDI D mat ches it s
own UDI D, and if t here is a mat ch it swit ches it s SMBus address t o t he address assigned by t he
command ( byt e 17) . Aft er accept ing t he Assign Address command, t he AR flag is set , and from t his
point ( as long as t he AR flag is set ) , t he 82599 does not respond t o t he Get UDI D General command,
while all ot her commands should be processed even if t he AR flag is set .

77
Fi gur e 3.10. SMBus ARP Fl ow
Set AV flag; Clear AR flag
Load SMB address from EPROM
Rx SMB
packet
No
SMB ARP
address match
Prepare to ARP
ACK the command
and clear AR flag
Reset device
ACK the command
and clear AR flag
Assign Address
command
UDID
match
NACK packet
ACK packet
Set slave Address and
store it in EEPROM
Set AR flag
AR flag
set
Return UDID
Process regular
command
NACK packet
Return UDID
Get UDID
CMD general
Get UDID
CMD directed
Power-Up reset
Yes
No
Yes
Yes
No
Yes
No
Yes
No
No
Yes
Illegal command handling
Yes
No
Yes
No
No
Yes
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3.2.7. 2.1 SMBus ARP UDI D Cont ent
The UDI D provides a mechanism t o isolat e each device for t he purpose of address assignment . Each
device has a unique ident ifier. The 128- bit number is comprised of t he following fields:
Where:
Devi ce Capabi l i t i es: Dynamic and Persist ent Address, PEC Support bit
Ver si on/ Revi si on: UDI D Version 1, Silicon Revision
Silicon Revision I D:
1 By t e 1 By t e 2 By t es 2 By t es 2 By t es 2 By t es 2 Byt es 4 Byt es
Device
Capabilit ies
Version/
Revision
Vendor I D Device I D I nt erf ace
Subsyst em
Vendor I D
Subsyst em
Device I D
Vendor
Specific I D
See as follows See as follows
0x8086
As reflect ed in
t he Device I D
field in t he
PCI config
space
As reflect ed in
t he Device I D
field in t he
PCI config
space
0x0004 0x0000 0x0000 See as follows
MSB LSB
I nt erface:
I dent ifies t he prot ocol layer int erfaces support ed over t he SMBus connect ion by t he device.
I n t his case, SMBus Version 2. 0
Const ant value: 0x0004.
Subsyst em Fields These fields are not support ed and ret urn zeros.
7 6 5 4 3 2 1 0
Address Type Reserved ( 0) Reserved ( 0) Reserved ( 0) Reserved ( 0) Reserved ( 0)
PEC
Support ed
0b 1b 0b 0b 0b 0b 0b 0b
MSB LSB
7 6 5 4 3 2 1 0
Reserved ( 0) Reserved ( 0) UDI D Version Silicon Revision I D
0b 0b 001b See as follows
MSB LSB
Si l i con Ver si on Revi si on I D
A0 000b
B0 001b

79
Vendor Specific I D:
Four LSB byt es of t he device Et hernet MAC address. The device Et hernet MAC address is t aken from t he
EEPROM LAN Core 0/ 1 Modules in t he EEPROM ( see Sect ion 6. 3. 7. 2) . Not e t hat in t he 82599 t here are
t wo Et hernet MAC Addresses ( one for each port ) .
3. 2. 8 LAN Fai l - Ov er Thr ough SMBus
I n failover mode, t he 82599 det ermines which port s are used for t ransmit / react ive ( according t o t he
configurat ion) . LAN failover is t ied t o t he SMBus addressing mode. When t he SMBus is dual- address
mode, t he 82599 does not act ivat e it s failover mechanism ( it ignores t he failover regist er) , and
operat es in t wo individual LAN port s. When t he SMBus is in single- address mode, in PT mode, t he
82599 operat es in failover mode as described in sect ion Sect ion 10. 2. 2. 2.
3.3 Net w or k Cont r ol l er Si deband I nt er f ace ( NC- SI )
I n t he 82599, t he NC- SI int erface is connect ed t o an ext ernal MC. Not e t hat t he 82599 NC- SI int erface
meet s t he NC- SI specificat ion as a PHY- side device.
3.3.1 El ect r i cal Char act er i st i cs
The 82599 complies wit h t he elect rical charact erist ics defined in t he NC- SI specificat ion.
The 82599 NC- SI behavior is configured by t he 82599 on power- up:
The out put driver st rengt h for t he NC- SI out put signals is configured by t he EEPROM RMM Out
Buffer St rengt h field ( default = 0x1F) .
The NC- SI t opology is loaded from t he EEPROM ( point - t o- point or mult i- drop wit h t he default being
point - t o- point ) .
The 82599 dynamically drives it s NC- SI out put signals as required by t he sideband prot ocol:
On power up, t he 82599 float s t he NC- SI out put s.
I f t he 82599 operat es in point - t o- point mode, t hen t he 82599 st art s driving t he NC- SI out put s at
some t ime following power up.
I f t he 82599 operat es in a mult i- drop mode, t he 82599 drives t he NC- SI out put s as configured by
t he MC.
3.3.2 NC- SI Tr ansact i ons
Compat ible wit h t he NC- SI specificat ion.
1 By t e 1 By t e 1 By t e 1 By t e
Et her net MAC Address, byt e 3 Et hernet MAC Address, byt e 2 Et hernet MAC Address, byt e 1 Et hernet MAC Address, byt e 0
MSB LSB
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3.4 EEPROM
3.4.1 Gener al Over vi ew
The 82599 uses an EEPROM device for st oring product configurat ion informat ion. The EEPROM is
divided int o t hree general regions:
Hardware accessed loaded by t he 82599 hardware aft er power- up, PCI reset deassert ion, D3 t o D0
t ransit ion, or soft ware reset . Different hardware sect ions in t he EEPROM are loaded at different event s.
See furt her det ails on power- up and reset sequences in Sect ion 4. 0.
Firmware Area I ncludes st ruct ures used by t he firmware for management configurat ion in it s
different modes.
Soft ware accessed used by soft ware only. The meaning of t hese regist ers as list ed here is a
convent ion for soft ware only and is ignored by t he 82599.
3.4.2 EEPROM Devi ce
The EEPROM int erface support s an SPI int erface and. I t expect s t he EEPROM t o be capable of 5 MHz
operat ion.
The 82599 is compat ible wit h many sizes of 4- wire serial EEPROM devices. A 4096- bit serial SPI
compat ible EEPROM can be used. All EEPROM' s are accessed in 16- bit dat a words only.
The 82599 aut omat ically det ermines t he address size t o be used wit h t he SPI EEPROM it is connect ed
t o, and set s t he EEPROM Size field of t he EEPROM/ FLASH Cont rol and Dat a regist er
( EEC.EE_ADDR_SI ZE) field appropriat ely. Soft ware can use t his size t o det ermine how t o access t he
EEPROM. The exact size of t he EEPROM is det ermined wit hin one of t he EEPROM words.
3.4.3 EEPROM Vi t al Cont ent
The EEPROM cont ains several main t ypes of vit al cont ent : pre- boot , pre- operat ing syst em and pre-
driver paramet ers, manageabilit y relat ed st ruct ures, hardware default paramet ers, and driver default
paramet ers. The 82599 must have t he EEPROM t o aut o- load t hese set t ings.
3.4.4 Sof t w ar e Accesses
The 82599 provides t wo different met hods for soft ware access t o t he EEPROM.
Use t he built - in cont roller t o read t he EEPROM
Access t he EEPROM direct ly using t he EEPROM' s 4- wire int erface
I n addit ion, t he Vit al Product Dat a ( VPD) area of t he EEPROM can be accessed via t he VPD capabilit y
st ruct ure of t he PCI e.
Soft ware can use t he EEPROM Read ( EERD) regist er t o cause t he 82599 t o read a word from t he
EEPROM t hat t he soft ware can t hen use. To do t his, soft ware writ es t he address t o read t o t he Read
Address ( EERD. ADDR) field and t hen simult aneously writ es a 1b t o t he St art Read bit ( EERD. START) .
The 82599 reads t he word from t he EEPROM, set s t he Read Done bit ( EERD. DONE) , and put s t he dat a
in t he Read Dat a field ( EERD.DATA) . Soft ware can t hen poll t he EEPROM Read regist er unt il it sees t he
Read Done bit set , t hen use t he dat a from t he Read Dat a field.
Not e: Any words read t his way are not writ t en t o t he 82599' s int ernal regist ers.

81
Soft ware can also direct ly access t he EEPROM' s 4- wire int erface t hrough t he EEPROM/ Flash Cont rol
( EEC) regist er. I t can use t his for reads, writ es, or ot her EEPROM operat ions.
To direct ly access t he EEPROM, soft ware should follow t hese st eps:
1. Writ e a 1b t o t he EEPROM Request bit ( EEC. EE_REQ) .
2. Read t he EEPROM Grant bit ( EEC. EE_GNT) unt il it becomes 1b. I t remains 0b as long as hardware is
accessing t he EEPROM.
3. Writ e or read t he EEPROM using t he direct access t o t he 4- wire int erface as defined in t he EEPROM/
Flash Cont rol and Dat a ( EEC) regist er. The exact prot ocol used depends on t he EEPROM placed on
t he board and can be found in t he appropriat e EEPROM dat asheet .
4. Writ e a 0b t o t he EEPROM Request bit ( EEC. EE_REQ) .
Not e: Each t ime t he EEPROM is not valid ( blank EEPROM or wrong signat ure) , soft ware should use
t he direct access t o t he EEPROM t hrough t he EEC regist er.
3.4.5 Si gnat ur e Fi el d
The only way t he 82599 has t o t ell if an EEPROM is present is by t rying t o read t he EEPROM. The 82599
first reads t he EEPROM Cont rol word at word address 0x000000 and at address 0x000800. I t t hen
checks t he signat ure value at bit s 7 and 6 in bot h addresses. I f bit 7 is 0b and bit 6 is 1b in one of t he
t wo addresses, it considers t he EEPROM t o be present and valid. I t t hen reads t he addit ional EEPROM
words and programs it s int ernal regist ers based on t he values read. Ot herwise, it ignores t he values it
reads from t hat locat ion and does not read any ot her words.
3. 4. 6 Pr ot ect ed EEPROM Space
The 82599 provides a mechanism for a hidden area in t he EEPROM of t he host . The hidden area cannot
be read or writ e accessed via t he EEPROM regist ers in t he CSR space. I t can be accessed only by t he
manageabilit y subsyst em.
Aft er t he EEPROM was configured t o be prot ect ed, changing bit s t hat are prot ect ed require specific
manageabilit y inst ruct ions wit h an aut hent icat ion mechanism. This mechanism is defined in t he
firmware document at ion.
3.4.6.1 I ni t i al EEPROM Pr ogr ammi ng
I n most applicat ions, init ial EEPROM programming is done direct ly on t he EEPROM pins. Nevert heless, it
is desired t o enable exist ing soft ware ut ilit ies ( accessing t he EEPROM via t he host int erface) t o init ially
program t he ent ire EEPROM wit hout breaking t he prot ect ion mechanism. Following a power up
sequence, t he 82599 reads t he hardware init ializat ion words in t he EEPROM. I f t he signat ure in bot h
word addresses 0x000000 and 0x000800 is not equal t o 01b t he EEPROM is assumed as non-
programmed. There are t wo effect s of a non- valid signat ure:
1. The 82599 does not read any furt her EEPROM dat a and set s t he relevant regist ers t o default .
2. The 82599 enables host writ e ( and read) access t o any locat ion in t he EEPROM via t he EEPROM CSR
regist ers.
3.4.6.2 EEPROM Pr ot ect ed Ar eas
The 82599 defines t wo prot ect ed areas in t he EEPROM. The first area is words 0x00- 0x0F. These words
hold t he basic configurat ion and t he point ers t o all ot her configurat ion sect ions. The second area is a
programmable size area locat ed at t he end of t he EEPROM and assigned wit h prot ect ing t he appropriat e
sect ions t hat should be blocked for changes.
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3. 4. 6. 3 Act i v at i ng t he Pr ot ect i on Mechani sm
Following a device init ializat ion, t he 82599 reads t he I nit cont rol 1 word from t he EEPROM sect ors 0 and
1. The 82599 t urns on t he prot ect ion mechanism if t his word cont ains a valid signat ure ( equals t o 01b)
and bit 4 ( EEPROM prot ect ion) is set t o 1b. Once t he prot ect ion mechanism is t urned on, words 0x00-
0x0F area become writ e- prot ect ed and t he hidden area t hat is defined by word 0x0 becomes read/ writ e
prot ect ed t o host access.
Not e: Alt hough possible by configurat ion, it is prohibit ed t hat t he soft ware sect ions in t he EEPROM
is included as part of t he EEPROM prot ect ed area.
3. 4. 6. 4 Non Per mi t t ed Access t o Pr ot ect ed Ar eas i n t he EEPROM
This sect ion refers t o EEPROM accesses by t he host via t he EEC ( bit banging) or EERD ( parallel read
access) regist ers. Following a writ e access t o t he prot ect ed areas in t he EEPROM ( word 0x0 and t he
hidden area defined by word 0x0) , hardware responds properly on t he PCI e bus but does not init iat e
any access t o t he EEPROM. Following a read access t o t he hidden area in t he EEPROM ( as defined by
word 0x0) , hardware does not access t he EEPROM and ret urns meaningless dat a t o t he host .
Not es: Using t he bit banging access, t he SPI EEPROM can be accessed in a burst mode by providing
opcode, address, and t hen read or writ e dat a for mult iple byt es. Hardware inhibit s any
at t empt t o access t he prot ect ed EEPROM locat ions even in burst accesses.
Soft ware should not access t he EEPROM in a burst writ e mode st art ing in a non- prot ect ed
area and cont inue t o a prot ect ed one, or vice versa. I n such a case, it is not guarant eed t hat
t he writ e access t o t he non- prot ect ed area t akes place.
3.4.7 EEPROM Recover y
The EEPROM cont ains fields t hat if programmed incorrect ly might affect t he funct ionalit y of t he 82599.
The impact might range from an incorrect set t ing of some funct ion ( like LED programming) , via
disabling of ent ire feat ures ( such as no manageabilit y) and link disconnect ion, t o inabilit y t o access t he
device via t he regular PCI e int erface.
The 82599 implement s a mechanism t hat enables recovery from a fault y EEPROM no mat t er what t he
impact is, using an SMBus message t hat inst ruct s t he firmware t o invalidat e t he EEPROM.
This mechanism uses an SMBus message t hat t he firmware is able t o receive in all modes, no mat t er
what is t he cont ent of t he EEPROM. Aft er receiving t his message, firmware clears word 0x0 including
t he signat ure. Aft erwards, t he BI OS/ operat ing syst em init iat es a reset t o force an EEPROM aut o- load
process t hat fails and enables access t o t he device.
Firmware is programmed t o receive such a command only from PCI e reset unt il one of t he funct ions
changes it s st at us from D0u t o D0a. Once one of t he funct ions moves t o D0a it can be safely assumed
t hat t he device is accessible t o t he host and t here is no furt her need for t his funct ion. This reduces t he
possibilit y of malicious soft ware using t his command as a back door and limit s t he t ime t he firmware
must be act ive in non- manageabilit y mode.
The command is sent on a fixed SMBus address of 0xC8. The format of t he SMBus Block Writ e
command is as follows:
Funct i on Command Dat a Byt e
Release EEPROM 0xC7 0xB6

83
Not es: This solut ion requires a cont rollable SMBus connect ion t o t he 82599.
I n case more t han one t he 82599 is in a st at e t o accept t his solut ion, all of t he t he 82599
devices connect ed t o t he same SMBus accept t he command. The devices in D0u st at e release
t he EEPROM.
Aft er receiving a release EEPROM command, firmware should keep it s current st at e. I t is t he
responsibilit y of t he programmer updat ing t he EEPROM t o send a firmware reset if required aft er t he
full EEPROM updat e process is done.
An addit ional command is int roduced t o enable t he EEPROM writ e direct ly from t he SMBus int erface t o
enable t he EEPROM modificat ion ( writ ing from t he SMBus t o any MAC CSR regist er) . The same rules as
for t he Release EEPROM command t hat det ermine when firmware accept s t his command apply t o t his
command as well.
The command is sent on a fixed SMBus address of 0xC8. The format of t he SMBus Block Writ e
command is as follows:
The most significant bit in Configurat ion address 2 indicat es which port is t he t arget of t he access ( 0 or
1) . The 82599 always enables t he manageabilit y block aft er power up. The manageabilit y clock is
st opped only if t he manageabilit y funct ion is disabled in t he EEPROM and one of t he funct ions had
t ransit ioned t o D0a; ot herwise, t he manageabilit y block get s t he clock and is able t o wait for t he new
command.
This command enables writ ing t o any MAC CSR regist er as part of t he EEPROM recovery process. This
command can be used t o writ e t o t he EEPROM and updat e different sect ions in it .
3.4.8 EEPROM Deadl ock Av oi dance
The EEPROM is a shared resource bet ween t he following client s:
1. Hardware aut o read.
2. LAN port 0 and LAN port 1 soft ware accesses.
3. Manageabilit y- firmware accesses.
When accessing t he EEPROM, soft ware and manageabilit y- firmware should use t he EEPROM parallel
access. On t his int erface, hardware schedules t he act ual accesses t o t he EEPROM, avoiding st arvat ion
of any client . The bit banging int erface does not guarant ee fairness bet ween t he client s, t herefore it
should be avoided in nominal operat ion as much as possible. When writ e accesses t o t he EEPROM are
required t he soft ware or manageabilit y should access t he EEPROM one word at a t ime releasing t he
int erface aft er each word.
3. 4. 9 VPD Suppor t
The EEPROM image can cont ain an area for VPD. This area is managed by t he OEM vendor and does not
influence t he behavior of t he hardware. Word 0x2F of t he EEPROM image cont ains a point er t o t he VPD
area in t he EEPROM. A value of 0xFFFF means VPD is not support ed and t he VPD capabilit y does not
appear in t he configurat ion space.
The maximum area size is 256 byt es but can be smaller. The VPD block is built of a list of resources. A
resource can be eit her large or small. The st ruct ure of t hese resources are list ed in t he following t ables.
Funct i on Command
Byt e
Count
Dat a 1 Dat a 2 Dat a 3 Dat a 4 Dat a 7
EEPROM Writ e 0xC8 7
Config
Address 2
Config
Address 1
Config
Address 0
Config
Dat a MSB
Config Dat a
LSB
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The 82599 parses t he VPD st ruct ure during t he aut o- load process following PCI e reset in order t o
det ect t he read only and read/ writ e area boundaries. The 82599 assumes t he following VPD fields wit h
t he limit at ions list ed in Table 3.12.
VPD st ruct ure limit at ions:
The st ruct ure must st art wit h a t ag equal t o 0x82. I f t he 82599 does not det ect a value of 0x82 in
t he first byt e of t he VPD area or t he st ruct ure does not follow t he informat ion list ed inTable 3.12, it
assumes t he area is not programmed and t he ent ire 256 byt es area is read only.
The RO area and R/ W area are bot h opt ional and can appear in any order. A single area is
support ed per t ag t ype. See PCI 3. 0 specificat ion Appendix I for det ails of t he different t ags.
I f a VPD- W t ag is found, t he area defined by it s size is writ able via t he VPD st ruct ure.
Bot h read and writ e sect ions on t he VPD area must be Dword aligned ( for example, each t ag must
st art on Dword boundaries, and each dat a field must end on Dword boundary) . Writ e accesses t o
Dwords t hat are only part ially in t he R/ W area are ignored. VPD soft ware is responsible t o make t he
right alignment t o enable a writ e t o t he ent ire area.
The st ruct ure must end wit h a t ag equal t o 0x78. The t ag must be word aligned.
The VPD area is accessible for read and writ e via t he regular EEPROM mechanisms pending t he
EEPROM prot ect ion capabilit ies enabled. The VPD area can be accessed t hrough t he PCI e
configurat ion space VPD capabilit y st ruct ure list ed in Table 3. 12. Writ e accesses t o a read only area
or any accesses out side of t he VPD area via t his st ruct ure are ignored.
Tabl e 3.10. Smal l Resour ce St r uct ur e
Of f set 0 1 n
Cont ent
Tag = 0xxx, xyyyb ( Type = Small( 0) , I t em Name = xxxx, lengt h = yy
byt es)
Dat a
Tabl e 3.11. Lar ge Resour ce St r uct ur e
Of f set 0 1 - 2 3 n
Cont ent Tag = 1xxx, xxxxb ( Type = Large( 1) , I t em Name = xxxxxxxx) Lengt h Dat a
Tabl e 3.12. VPD St r uct ur e
Tag
Lengt h
( Byt es)
Dat a Resour ce Descr i pt i on
0x82
Lengt h of
ident ifier st ring
I dent ifier I dent ifier st r ing.
0x90
Lengt h of RO
area
RO dat a VPD- R list cont aining one or more VPD keywords.
0x91
Lengt h of RW
area
RW dat a VPD-W list cont aining one or more VPD keywords. This part is opt ional.
0x78 N/ A N/ A End t ag.

85
3.5 Fl ash
The 82599 provides an int erface t o an ext ernal serial Flash/ ROM memory device. This Flash/ ROM
device can be mapped int o memory space for each LAN device t hrough t he use of Base Address
Regist ers ( BARs) . EEPROM bit s associat ed wit h each LAN device select ively disable/ enable whet her t he
Flash can be mapped for each LAN device by cont rolling t he BAR regist er advert isement and writ e
abilit y.
3. 5. 1 Fl ash I nt er f ace Oper at i on
The 82599 provides t wo different met hods for soft ware access t o t he Flash.
Using t he legacy Flash t ransact ions t he Flash is read from, or writ t en t o, each t ime t he host CPU
performs a read or a writ e operat ion t o a memory locat ion t hat is wit hin t he Flash address mapping or
upon boot via accesses in t he space indicat ed by t he Expansion ROM Base Address regist er. All accesses
t o t he Flash require t he appropriat e command sequence for t he device used. Refer t o t he specific Flash
dat a sheet for more det ails on reading from or writ ing t o Flash. Accesses t o t he Flash are based on a
direct decode of CPU accesses t o a memory window defined in eit her:
Memory CSR + Flash Base Address regist er ( PCI e Cont rol regist er at offset 0x10) .
The Expansion ROM Base Address regist er ( PCI e Cont rol regist er at offset 0x30) .
The 82599 cont rols accesses t o t he Flash when it decodes a valid access.
Not e: Flash read accesses must always be assembled by t he 82599 each t ime t he access is great er
t han a byt e- wide access.
The 82599 byt e reads or writ es t o t he Flash t ake about 2 s t ime. The device cont inues t o
issue ret ry accesses during t his t ime.
The 82599 support s only byt e writ es t o t he Flash.
Anot her way for soft ware t o access t he Flash is direct ly using t he Flash' s 4- wire int erface t hrough t he
Flash Access ( FLA) regist er. I t can use t his for reads, writ es, or ot her Flash operat ions ( accessing t he
Flash st at us regist er, erase, et c) .
To direct ly access t he Flash, soft ware should follow t hese st eps:
1. Writ e a 1b t o t he Flash Request bit ( FLA. FL_REQ) .
2. Read t he Flash Grant bit ( FLA. FL_GNT) unt il it becomes 1b. I t remains 0b as long as t here are ot her
accesses t o t he Flash.
3. Writ e or read t he Flash using t he direct access t o t he 4- wire int erface as defined in t he FLA regist er.
The exact prot ocol used depends on t he Flash placed on t he board and can be found in t he
appropriat e Flash dat asheet .
4. Writ e a 0b t o t he Flash Request bit ( FLA. FL_REQ) .
3.5.2 Fl ash Wr i t e Cont r ol
The Flash is writ e cont rolled by t he bit s in t he EEPROM/ FLASH Cont rol and Dat a ( EEC. FWE) regist er.
Not e t hat at t empt s t o writ e t o t he Flash device when writ es are disable ( FWE= 01b) should not be
at t empt ed. Behavior aft er such an operat ion is undefined, and might result in component and/ or
syst em hangs.
Aft er sending one byt e t o writ e t o t he Flash, soft ware can check if it can send t he next byt e t o writ e
( check if t he writ e process in t he Flash had finished) by reading t he FLA regist er. I f bit ( FLA. FL_BUSY) in
t his regist er is set , t he current writ e did not finish. I f bit ( FLA. FL_BUSY) is cleared, t hen soft ware can
cont inue and writ e t he next byt e t o t he Flash.
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86
3.5.3 Fl ash Er ase Cont r ol
When soft ware needs t o erase t he Flash it should set t he FLA. FL_ER bit in t he FLA regist er t o 1b ( Flash
erase and set bit s EEC. FWE in t he EEPROM/ Flash Cont rol regist er t o 0b) .
Hardware get s t his command and sends t he Erase command t o t he Flash. The erase process t hen
finishes by it self. Soft ware should wait for t he end of t he erase process before any furt her access t o t he
Flash. This can be checked by using t he Flash Writ e cont rol mechanism previously described ( see
Sect ion 3. 5. 2) .
The opcode used for t he erase operat ion is defined in t he FLOP regist er.
Not e: Sect or erase by soft ware is not support ed. To delet e a sect or, t he serial ( bit bang) int erface
should be used.
3. 5. 4 Fl ash Access Cont ent i on
The 82599 implement s int ernal arbit rat ion bet ween Flash accesses init iat ed t hrough t he LAN 0 device
and t hose init iat ed t hrough t he LAN 1 device. I f accesses from bot h LAN devices are init iat ed during t he
same approximat e size window, The first one is served first and only t hen t he next one. Not e t hat t he
82599 does not synchronize bet ween t he t wo ent it ies accessing t he Flash t hough cont ent ions caused
from one ent it y reading and t he ot her modifying t he same locat ions is possible.
To avoid t his cont ent ion, accesses from bot h LAN devices should be synchronized using ext ernal
soft ware synchronizat ion of t he memory or I / O t ransact ions responsible for t he access. I t is possible t o
ensure cont ent ion- avoidance simply by t he nat ure of t he soft ware sequence.
3.6 Conf i gur abl e I / O Pi ns Sof t w ar e- Def i nabl e Pi ns ( SDP)
The 82599 has eight Soft ware- Defined Pins ( SDP pins) per port t hat can be used for miscellaneous
hardware or soft ware- cont rollable purposes ( see Figure 3. 11) . These pins and t heir funct ion are bound
t o a specific LAN device. The use, direct ion, and values of SDP pins are cont rolled and accessed by t he
Ext ended SDP Cont rol ( ESDP) regist er. To avoid signal cont ent ion, following power up, all eight pins are
defined as input pins.
Some SDP pins have specific funct ionalit y:
The default direct ion of t he lower SDP pins ( SDP0- SDP3) is loaded from t he SDP Cont rol word in t he
EEPROM.
The lower SDP pins ( SDP0- SDP3) can also be configured for use as ext ernal int errupt sources
( GPI ) . To act as GPI pins, t he desired pins must be configured as input s and enabled by t he GPI E
regist er. When enabled, an int errupt is assert ed following a rising- edge det ect ion of t he input pin
( rising- edge det ect ion occurs by comparing values sampled at t he int ernal clock rat e, as opposed t o
an edge- det ect ion circuit ) . When det ect ed, a corresponding GPI int errupt is indicat ed in t he EI CR
regist er.
Cert ain SDP pins can be allocat ed t o hardware funct ions. For example SDP2, SDP3, SDP6 and SDP7 can
be defined t o support I EEE1588 auxiliary devices. I n addit ion, t he funct ionalit y of t he I / O pins are
programmed by t he TimeSync Auxiliary Cont rol ( TSAUXC) regist er.

87
Table 3.13 defines an example of possible usage of SDP I / O pins, MDI O pins, and I
2
C pins as a funct ion
of an opt ical module or t he PHY being int erfaced. I f mapping of t hese SDP pins t o a specific hardware
funct ion is not required t hen t he pins can be used as general purpose soft ware defined I / Os. For any of
t he funct ion specific usages, t he SDP I / O pins should be set t o nat ive mode by soft ware by set t ing t he
SDPxxx_NATI VE bit s in t he ESDP regist er. Nat ive mode in t hose SDP I / O pins designed for PHY and
opt ical module specific usages, defines t he pin funct ionalit y while in an inact ive st at e ( reset or power
down) while behavior in an act ive st at e is cont rolled by soft ware. The hardware funct ionalit y of t hese
SDP I / O pins differ mainly by t he act ive behavior cont rolled by soft ware.
Tabl e 3. 13. Ex ampl e f or SDP, MDI O and I
2
C Por t s Usage
SFP+ Reser v ed Copper PHY X2/ XPAK
1
1. To Support XENPAK, X2 or XPAK modules, 3. 3V t o 1. 2V level shift ers are required bet ween t he 82599 and an opt ical
module.
SDP0 GPI O: RX_LOS GPI O: I NTR_L GPI O: LASI
SDP1 GPI O: RX_LOS_N
SDP2 GPI O: MOD_ABS_N
SDP3
GPI O: TX_DI SABLE
NATI VE: TS_SDP3 NATI VE: TS_SDP3
SDP4 Port 0 I N: SEC_ENA I N: SEC_ENA I N: SEC_ENA
SDP4 Port 1 GPI O GPI O GPI O
SDP5 NATI VE: RS0/ RS1 drive NATI VE: RESET NATI VE: TX ON/ OFF
2
2. When TX ON/ OFF is low in XENPAK, X2 and XPAK modules t ransmission is disabled. The SDP5_Funct ion bit in t he ESDP
regist er should be set t o 0b enabling t he pin t o be at a HiZ st at e while t he 82599 is in an inact ive st at e ( as defined in t he
regist er) . Board designers should populat e wit h an ext ernal pull- down resist or forcing a low level during an inact ive st at e.
SDP6 GPI O: RS0/ RS1 sense NATI VE: TS_SDP6 GPI O: RESET_N
SDP7 GPI O: TX_FAULT NATI VE: TS_SDP7 NATI VE: TS_SDP7
MDI O MDI O MDI O
I
2
C I
2
C
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88
Table 3. 14 list s t he signals defined in Table 3. 13 and behavior during reset and power down st at e ( D3)
wit hout management .
Fi gur e 3.11. SDP Connect i ons
Tabl e 3.14. SDP Assi gned Si gnal s Descr i pt i on
Si gnal Descr i pt i on
Sof t w ar e I / O
Pr ogr ammi ng
Def aul t Val ues at
( Reset , D3 no WoL and no MNG)
RX_LOS,
RX_LOS_N
RX_LOS high and RX_LOS_N low indicat e
insufficient opt ical power for reliable signal
recept ion.
GPI O: I nput I nput , no change.
LASI , I NTR_L
I NTR_L or Link Alarm St at us I nt errupt ( LASI )
when low, indicat es possible module operat ional
fault or a st at us crit ical t o t he host syst em.
GPI O: I nput
( I nt errupt )
I nput , no change.
RS0/ RS1 drive Short - circuit prot ect ed. Nat ive: Out put
Out put , aut onomous high or t ri- st at e
wit h pullup.
RS0/ RS1 sense Direct ly connect ed input . GPI O: I nput I nput , no change.
Stuffing Opt
(Empty)
Stuffing Opt
(Empty)
Connect to 82599
SDP
RS1
RX_LOS
RS0
TX_DISABLE
TX_FAULT
SDP0_7
SDP0_3
SDP0_2
SDP0_0
SDP0_1
SDP0_5
SDP0_6
SFP Cage
3.3V
GND
TX FAULT0
RX LOS0
RS0/RS1 SENSE0
MOD ABS0
TX DISABLE0
TX FAULT0
RX LOS0
MOD ABS0
RS0/RS1 DRIVE0
TX
DISABLE0
SDP0_4
3.3V
GND
RS0/RS1 DRIVE0
RX LOS0 N
MOD ABS0 N
SEC_ENA
10K
10K
10K
1.5K
1.5K
100
10K
Port 0 configuration shown. Port 1 is configured the same, except
that SDP1_4 is not used for SEC_ENA and may be used as a GPIO.
100
Notes:
SEC_ENA is used on
Port0 only (SDP0_4).
Port1 may configure
as GPIO (SDP1_4)
Pull-up & Pull-down resistors
MOD_ABS

89
P_DOWN/ RST
When held high by t he host , places t he module in
st andby ( low power) mode.
The negat ive edge of P_DOWN/ RST signal init iat es
a complet e module reset .
GPI O: Out put
I nput , no change. I n order t o minimize
PHY power, soft ware should drive t he
SDP t o high or set t o input while
populat ing a pullup.
RESET_N
When low, XENPAK, X2 or XPAK opt ical module is
r eset .
GPI O: Out put
Out put , no change. I n order t o
minimize PHY power soft ware should
drive t he SDP t o low or set t o input
while populat ing a pull- down.
RESET When high, t he copper PHY is reset . Nat ive: Out put
wit h pullup.
TX_DI SABLE
When TX_DI SABLE is assert ed high, opt ical
module t ransmit t er is t urned off.
GPI O: Out put
Out put , no change. I n order t o
minimize PHY power soft ware should
drive t he SDP t o high or set t o input
while populat ing a pullup.
TX_DI S
When TX_DI S is assert ed high, opt ical module
t ransmit t er is t urned off.
Nat ive: Out put
wit h pullup.
TX ON/ OFF
1b = Transmit t er on.
0b = Transmit t er off.
Nat ive: Out put
Out put , aut onomous low or t ri- st at e
wit h pull- down.
MOD_DET_N I nvert ed mode det ect .
GPI O: I nput
( I nt errupt )
I nput , no change.
TS_SDPX
Time sync support pins, can be used as event in or
event out .
Nat ive: According
t o programmed
funct ionalit y
Tri- st at e during reset . No change in
D3. Ext ernal pullup / pull- down as
required by t he syst em designer.
TX_FAULT
When high, indicat es t hat t he module t ransmit t er
has det ect ed a fault condit ion relat ed t o laser
operat ion or safet y.
GPI O: I nput
( I nt errupt )
I nput , no change.
MOD_NR
When high, indicat es t hat t he module has det ect ed
a condit ion t hat renders t ransmit t er and or
receiver dat a invalid.
GPI O: I nput
( I nt errupt )
I nput , no change.
MOD_ABS
GPI O: I nput
( I nt errupt )
I nput , no change.
FAN_St at us Opt ional healt h indicat ion of t he fan.
GPI O: I nput
( I nt errupt )
I nput , no change.
Tabl e 3. 14. SDP Assi gned Si gnal s Descr i pt i on
Si gnal Descr i pt i on
Sof t w ar e I / O
Pr ogr ammi ng
Def aul t Val ues at
( Reset , D3 no WoL and no MNG)
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90
3.7 Net w or k I nt er f ace ( MAUI I nt er f ace)
The 82599 support s 10 GbE operat ion, 1 GbE operat ion and 100 Mb/ s Et hernet operat ion on t he MAUI
int erface. The 82599 can support different or t he same link speeds ( 10 Gb/ s, 1 Gb/ s and 100 Mb/ s) and
prot ocols on each of t he t wo MAUI port s. The 82599 also support s aut omat ic crossover and polarit y
correct ion on each of t he MAUI port s t o eliminat e t he need for crossover cables bet ween similar
devices. The 82599 also support s aut o- negot iat ion when configured for backplane Et hernet t o
aut omat ically select bet ween KX, KX4 and KR.
When in 10 GbE operat ing mode, t he MAUI int erface can be configured as any of t he following:
A four lane XAUI int erface.
A four lane 10GBASE- BX4 int erface.
A four lane 10GBASE- KX4 int erface.
A four lane 10GBASE- CX4 int erface.
A single lane 10GBASE- KR int erface.
A single lane SFI int erface.
When in 1 GbE operat ing mode, t he MAUI int erface can be configured as any of t he following:
A single lane 1000BASE- KX int erface.
A single lane 1000BASE- BX int erface.
A single SGMI I ( 1 Gb/ s or 100 Mb/ s) lane over a KX or BX compliant elect rical int erface.
The device implement s all feat ures required for t ransmission and recept ion defined for t he XAUI , BX4,
CX4, KX4, KX, KR, SFI and BX Media int erface. The MAUI int erface support s t he I EEE 802. 3ae
( 10 GbE XAUI ) , I EEE 802. 3ap ( KX, KX4 and KR) , I EEE802. 3ak ( 10GBASE- CX4) , PI CMG3. 1
( 1000BASE- BX and 10GBASE- BX4) , and SFI st andards.
I n 10 GbE BX4, KX4, CX4 or XAUI operat ing modes, dat a passes on all four MAUI lanes complying wit h
t he BX4, KX4, CX4 or XAUI prot ocol. I n 10GBASE- KR, SFI , SGMI I , 1000BASE- KX, 1000BASE- BX, or
10GBASE- BX4 operat ion, dat a passes on MAUI lane 0 complying wit h t he 10 GbE KR, SFI prot ocols, t he
1 GbE KX or BX prot ocols or t he 100 Mb/ s and 1 GbE SGMI I prot ocol over a KX or BX elect rical
int erface.
3.7.1 10 GbE I nt er f ace
The 82599 provides complet e funct ionalit y t o support up t o t wo 10 Gb/ s port s. The device performs all
funct ions required for t ransmission and recept ion defined in t he various st andards.
A lower- layer PHY int erface is included t o at t ach eit her t o an ext ernal PMA or Physical Medium
Dependent ( PMD) component s.
The 82599 enables 10 GbE operat ion compliant t o t he XAUI , CX4, KX4, KR, SFI specificat ions by
programming t he appropriat e bit s in t he AUTOC regist er.
3.7.1. 1 XAUI Oper at i ng Mode
The Ten Gigabit At t achment Unit I nt erface ( XAUI ) support s dat a rat es of 10 Gb/ s over four different ial
pat hs in each direct ion for a t ot al of eight pairs, wit h each pat h operat ing at 3. 125 Gb/ s. The int erface
is used t o connect t he 82599 t o an ext ernal 10 GbE PHY device wit h a XAUI int erface. XAUI operat ing
mode can be forced by soft ware by set t ing t he relevant bit s in t he AUTOC regist er and disabling aut o-
negot iat ion ( see Sect ion 3. 7. 4. 2) .

91
3. 7.1. 1.1 XAUI Ov er v i ew
XAUI is a full- duplex int erface t hat uses four self- clocked serial different ial links in each direct ion t o
achieve 10 Gb/ s dat a t hroughput . Each serial link operat es at 3. 125 GBaud t o accommodat e bot h dat a
and t he overhead associat ed wit h 8B/ 10B coding. The self- clocked nat ure eliminat es skew concerns
bet ween clock and dat a, and enables a funct ional reach of up t o 50 cm. Conversion bet ween t he XGMI I
and XAUI int erfaces occurs at t he XGXS ( XAUI Ext ender Sublayer) . Funct ional and elect rical
specificat ions of XAUI int erface can be found in I EEE802. 3 clause 47.
Fi gur e 3. 12. XGMI I t o XAUI at t he XGXS
Tx_CLK
TxD (7:0)
TxD (15:8)
TxD (23:16)
TxD (31:24)
Rx_CLK
RxD (7:0)
RxD (15:8)
RxD (23:16)
RxD (31:24)
XGMII XAUI XGXS
Lane 0
Lane 2
Lane 3
Lane 1
Lane 0
Lane 2
Lane 3
Lane 1
Source Lane
Destination Lane
D1_0_P
D1_0_N
D1_1_P
D1_1_N
D1_2_P
D1_2_N
D1_3_P
D1_3_N
D0_0_P
D0_0_N
D0_1_P
D0_1_N
D0_2_P
D0_2_N
D0_3_P
D0_3_N
I nt el

92
The XAUI int erface has t he following charact erist ics:
a. Simple signal mapping t o t he XGMI I .
b. I ndependent t ransmit and receive dat a pat hs.
c. Four lanes conveying t he XGMI I 32- bit dat a and cont rol.
d. Different ial signaling wit h low volt age swing.
e. Self- t imed int erface enables j it t er cont rol t o t he PCS.
f. Using 8B/ 10B coding.
Figure 3. 13 Shows t he archit ect ural posit ioning of XAUI .
3.7.1. 1.2 XAUI Oper at i on
XAUI support s t he 10 Gb/ s dat a rat e of t he XGMI I . The 10 Gb/ s MAC dat a st ream is convert ed int o four
lanes at t he XGMI I int erface. The byt e st ream of each lane is 8B/ 10B encoded by t he XGXS for
t ransmission across t he XAUI at a nominal rat e of 3. 125 GBaud. The XGXS and XAUI at bot h sides of
t he connect ion ( MAC or PHY) can operat e on independent clocks.
The following is a list of t he maj or concept s of XGXS and XAUI :
1. The XGMI I is organized int o four lanes wit h each lane conveying a dat a oct et or cont rol charact er on
each edge of t he associat ed clock. The source XGXS convert s byt es on an XGMI I lane int o a self
clocked, serial, 8B/ 10B encoded dat a st ream. Each of t he four XGMI I lanes is t ransmit t ed across
one of t he four XAUI lanes.
2. The source XGXS convert s XGMI I I dle cont rol charact ers ( int er- frame) int o an 8B/ 10B code
sequence.
3. The dest inat ion XGXS recovers clock and dat a from each XAUI lane and de- skews t he four XAUI
lanes int o t he single- clock XGMI I .
4. The dest inat ion XGXS adds t o or delet es from t he int er- frame gap as needed for clock rat e disparit y
compensat ion prior t o convert ing t he int er- frame code sequence back int o XGMI I idle cont rol
charact ers.
5. The XGXS uses t he same code and coding rules as t he 10GBASE-X PCS and PMA specified in I EEE
802. 3 Clause 48.
Fi gur e 3.13. Ar chi t ect ur al Posi t i oni ng of XAUI

M E D I U M
X A U I
M D I
P M D
P M A
1 0 G B A S E - X P C S ( 8 B / 1 0 B )
X G M I I
R e c o n c i l i a t i o n
M A C

M A C C o n t r o l ( O p t i o n a l )
L L C L o g i c a l L i n k C o n t r o l o r o t h e r M A C C l i e n t
H i g h e r L a y e r s
L A N C S M A / C D L A Y E R S

93
3.7.1.1.3 XAUI El ect r i cal Char act er i st i cs
The XAUI lane is a low swing AC coupled different ial int erface using NRZ signaling. AC coupling allows
for int er- operabilit y bet ween component s operat ing at different supply volt ages. Low swing different ial
signaling provides noise immunit y and reduced Elect romagnet ic I nt erference ( EMI ) . Different ial signal
swings specificat ions depend on several fact ors, such as t ransmit t er pre- equalizat ion and t ransmission
line losses.
The XAUI signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a XAUI lane and is
comprised of t wo complement ary signals making a balanced different ial pair. There are four different ial
pat hs in each direct ion for a t ot al of eight pairs, or 16 connect ions. The signal pat hs are int ended t o
operat e up t o approximat ely 50 cm over cont rolled impedance t races on st andard FR4 Print ed Circuit
Boards ( PCBs) .
3.7. 1.2 10GBASE- KX4 Oper at i ng Mode
The KX4 int erface support s dat a rat es of 10 Gb/ s over copper t races in improved FR4 PCBs. Dat a is
t ransferred over four different ial pat hs in each direct ion for a t ot al of eight pairs, wit h each pat h
operat ing at 3. 125Gbaud t o support overhead of 8B/ 10B coding. The int erface is used t o connect t he
82599 t o a KX4 swit ch port over t he backplane or t o an ext ernal 10 GbE PHY device wit h a KX4
int erface.
The MAUI int erface is configured as a KX4 int erface while aut o- negot iat ion t o a KX4 link part ner is
det ect ed. KX4 operat ion can also be forced by EEPROM or soft ware by set t ing t he relevant bit s in t he
AUTOC regist er and disabling aut o- negot iat ion ( see Sect ion 3. 7. 4.2) .
3. 7.1. 2.1 KX4 Over vi ew
10GBASE- KX4 definit ion is based on XAUI wit h 10GBASE- CX4 ext ensions and specifies 10 Gb/ s
operat ion over four different ial pat hs in each direct ion for a t ot al of eight pairs, or 16 connect ions. This
syst em uses t he 10GBASE-X PCS and PMA as defined in I EEE802. 3 Clause 48 wit h amendment s for
aut o- negot iat ion as specified in I EEE802. 3ap. The 10GBASE- KX4 PMD is defined in I EEE802. 3ap Clause
71.
KX4 is a full- duplex int erface t hat uses four self- clocked serial different ial links in each direct ion t o
achieve 10 Gb/ s dat a t hroughput . Each serial link operat es at 3. 125 Gbaud t o accommodat e bot h dat a
bet ween clock and dat a, and enables a funct ional reach of up t o one met er.
I nt el

94
Figure 3. 14 shows t he archit ect ural posit ioning of 10GBASE- KX4.
3.7.1. 2.2 KX4 El ect r i cal Char act er i st i cs
The KX4 lane is a low swing AC coupled different ial int erface using NRZ signaling. AC coupling allows for
int er- operabilit y bet ween component s operat ing at different supply volt ages. Low swing different ial
signaling provides noise immunit y and reduced EMI . Different ial signal swings specificat ions depend on
several fact ors, such as t ransmit t er pre- equalizat ion and t ransmission line losses.
The KX4 signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a KX4 lane and is
operat e up t o approximat ely one met er over cont rolled impedance t races on improved FR4 PCBs.
3. 7.1. 3 10GBASE- KR Oper at i ng Mode
The KR int erface support s dat a rat es of 10 Gb/ s over copper t races in improved FR4 PCBs. Dat a is
t ransferred over a single different ial pat h in each direct ion for a t ot al of t wo pairs, wit h each pat h
operat ing at 10. 3125 Gbaud 100 ppm t o support overhead of 64B/ 66B coding. The int erface is used
t o connect t he 82599 t o a KR swit ch port over t he backplane.
The MAUI int erface is configured as a KR int erface while aut o- negot iat ion t o a KR link part ner is
det ect ed. KR operat ion can also be forced by EEPROM or soft ware by set t ing t he relevant bit s in t he
AUTOC regist er and disabling aut o- negot iat ion ( see Sect ion 3. 7. 4. 2) . When in 10GBASE- KR operat ing
mode, MAUI lane 0 is used for receive and t ransmit act ivit y while lanes 1 t o 3 of t he MAUI int erface are
powered down.
Fi gur e 3.14. Ar chi t ect ur al Posi t i oni ng of 10GBASE- KX4
LAN CSMA/CD LAYERS
Higher Layers
LLC Logical Link Control or other MAC Client
MAC Control (optional)
MAC
Reconciliation
XGMII
MDI
8B/10B PCS
MEDIUM
PMA
PMD
AN
10GBASE KX4

95
3. 7.1. 3.1 KR Over vi ew
10GBASE- KR definit ion enables 10 Gb/ s operat ion over a single different ial pat h in each direct ion for a
t ot al of t wo pairs, or four connect ions. This syst em uses t he 10GBASE- KR PCS as defined in I EEE802. 3
Clause 49 wit h amendment s for aut o- negot iat ion specified in I EEE802. 3ap and 10 Gigabit PMA as
defined in I EEE802. 3 clause 51. The 10GBASE- KR PMD is defined in I EEE802. 3ap Clause 72. The
10GBASE- KR PHY includes 10GBASE- KR Forward Error Correct ion ( FEC) , as defined in I EEE802. 3ap
Clause 74. FEC support is opt ional and is negot iat ed bet ween Link part ners during aut o- negot iat ion as
defined in I EEE802. 3ap clause 73. Act ivat ing FEC improves link qualit y ( 2dB coding gain) by enabling
correct ion of up t o 11 bit - burst errors.
KR is a full- duplex int erface t hat uses a single self- clocked serial different ial link in each direct ion t o
achieve 10 Gb/ s dat a t hroughput . The serial link t ransfers scrambled dat a at 10. 3125 Gbaud t o
accommodat e bot h dat a and t he overhead associat ed wit h 64B/ 66B coding. The self- clocked nat ure
eliminat es skew concerns bet ween clock and dat a, and enables a funct ional reach of up t o one met er.
Following init ializat ion and aut o- negot iat ion 10GBASE- KR defines a st art - up prot ocol, where link
part ners exchange cont inuous fixed lengt h t raining frames using different ial Manchest er Encoding
( DME) at a signaling rat e equal t o one quart er of t he 10GBASE- KR signaling rat e. This prot ocol
facilit at es t iming recovery and receive equalizat ion while also providing a mechanism t hrough which t he
receiver can t une t he t ransmit equalizer t o opt imize performance over t he backplane int erconnect .
Successful complet ion of t he st art - up prot ocol enables t ransmission of dat a bet ween t he link part ners.
Figure 3.15 shows t he archit ect ural posit ioning of 10GBASE- KR.
Fi gur e 3.15. Ar chi t ect ur al Posi t i oni ng of 10GBASE- KR
LAN CSMA/CD LAYERS
Higher Layers
MAC
Reconciliation
XGMII
MDI
64B/66B PCS
MEDIUM
PMA
PMD
AN
10GBASE Kr
FEC (optional)
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3.7.1. 3.2 KR El ect r i cal Char act er i st i cs
The KR lane is a low swing AC coupled different ial int erface using NRZ signaling. AC coupling allows for
int er- operabilit y bet ween component s operat ing from at different supply volt ages. Low swing
different ial signaling provides noise immunit y and improved reduced EMI . Different ial signal swings
defined specificat ions depend on several fact ors, such as t ransmit t er pre- equalizat ion and t ransmission
line losses.
The KR signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a KR lane and is
comprised of t wo complement ary signals making a balanced different ial pair. There is a single
different ial pat h in each direct ion for a t ot al of t wo pairs, or four connect ions.
The 10GBASE- KR link requires a nominal 100 O different ial source and load t erminat ions wit h AC
coupling on t he receive side. The signal pat hs are int ended t o operat e up t o approximat ely one met er,
including t wo connect ors, over cont rolled impedance t races on improved FR4 PCBs.
3.7.1. 3.3 KR Rever se Pol ar i t y
The 82599 support s reverse polarit y of t he KR t ransmit and receive lanes. I t is enabled by t he following
EEPROM set t ing in t he Core 0/ 1 Analog Configurat ion Modules:
Reverse Tx polarit y set t ing:
Reverse Rx polarit y set t ing
3. 7.1. 4 10GBASE- CX4 Oper at i ng Mode
The CX4 int erface support s dat a rat es of 10 Gb/ s over t winaxial cable. Dat a is t ransferred over four
different ial pat hs in each direct ion for a t ot al of eight pairs, wit h each pat h operat ing at 3.125Gbaud t o
support overhead of 8B/ 10B coding. The int erface is used t o connect t he 82599 t o a CX4 swit ch. CX4
operat ion can be forced by EEPROM or soft ware by set t ing t he relevant bit s in t he AUTOC regist er and
disabling aut o- negot iat ion ( see Sect ion 3. 7. 4.2) .
3.7.1. 4.1 CX4 Ov er v i ew
10GBASE- CX4 definit ion specifies 10 Gb/ s operat ion over four different ial pat hs in each direct ion for a
t ot al of eight pairs, or 16 connect ions. This syst em uses t he 10GBASE-X PCS and PMA as defined in
I EEE802. 3 Clause 48. The 10GBASE- CX4 PMD is defined in I EEE802.3 Clause 54.
Wor d)
Reser v ed
KR / SFI Rever se
Pol ar i t y
Descr i pt i on
2* N+ 1 0x0101 Set page 1.
2* N+ 2 0x1E12 Writ e regist er 0x1E t he dat a 0x12 t o invert Tx polarit y.
Wor d)
Reser v ed
KR / SFI Rever se
Pol ar i t y
Descr i pt i on
2* N+ 1 0x0101 Set page 1.
2* N+ 2 0x1FC0 Writ e regist er 0x1F t he dat a 0xC0 t o invert Rx polarit y.

97
CX4 is a full- duplex int erface t hat uses four self- clocked serial different ial links in each direct ion t o
achieve 10 Gb/ s dat a t hroughput . Each serial link operat es at 3. 125 Gbaud t o accommodat e bot h dat a
bet ween clock and dat a.
Figure 3.16 shows t he archit ect ural posit ioning of 10GBASE- CX4.
3.7.1.4.2 CX4 El ect r i cal Char act er i st i cs
The CX4 lane is a low swing AC coupled different ial int erface using NRZ signaling. AC coupling allows for
different ial signaling provides noise immunit y and improved reduced EMI . Different ial signal swings
line losses.
The CX4 signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a CX4 lane and is
operat e on t winaxial cable assemblies up t o 15 m in lengt h.
Fi gur e 3.16. Ar chi t ect ur al Posi t i oni ng of 10GBASE- CX4
LAN CSMA/CD LAYERS
Higher Layers
MAC
Reconciliation
XGMII
MDI
10GBASE-X PCS (8B/10B)
MEDIUM
PMA
PMD
10GBASE-CX4
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3. 7.1. 5 10GBASE- BX4 Oper at i ng Mode
10 GbE is support ed wit hin PI CMG 3. 1 by adopt ing a subset of t he I EEE 802. 3 XAUI specificat ions.
Where XAUI is a chip- t o- chip int erface bet ween t est point s TP- 1 and TP- 4, t he PI CMG 3. 1 specifies what
goes int o t he backplane at TP-T and what comes out of t he backplane at TP- R. When implement ing a
10 Gb/ s PI CMG 3.1 channel, board designers must implement t his channel wit h compliant TP-T and TP-
R t est point s.
Not e: The channel- t o- channel skew is handled by t he XAUI prot ocol.
3.7.1. 5.1 10GBASE- BX4 El ect r i cal Char act er i st i cs
Transmit t ed Elect rical Specificat ions at TP- 1:
PI CMG 3. 1 specifies t he compliance point TP-T. Syst em designers are required t o implement addit ional
margin at TP- 1 t o ensure compliance at TP-T.
The impedance at t erminat ion must be 100 O 10%.
Transmit t ed Elect rical Specificat ions at TP-T:
The PI CMG 3. 1 drive levels int o t he backplane must conform t o t he following specificat ions as list ed in
Table 3. 15.
Tabl e 3.15. Tr ansmi t Speci f i cat i ons at TP- T
Not e: All measurement s are made t hrough a mat ed pair connect or.
To maint ain int er- operabilit y bet ween older and newer t echnologies and t o avoid damage t o t he
component s, t he maximum drive amplit ude of any PI CMG 3. 1 driver must not exceed 1600 mV P- P.
The out put impedance requirement applies t o all valid out put levels. The reference impedance for
different ial ret urn loss measurement s is 100 O.
Receiver Elect rical Specificat ions at TP- R:
Table 3. 16 list s t he receiver specificat ions at TP- R.
Par amet er Val ue Uni t s
Baud rat e 3. 125 GBd
Clock t olerance 100 ppm
Different ial amplit ude maximum 1600 mV p- p
Absolut e out put volt age limit s - 0. 4 min, 1. 6 max V
Different ial out put ret urn loss See foot not e
1
1. s11 = 10 dB for 312. 5 MHz < Freq ( f) < 625 MHz, and 10 + 10log( f/ 625) dB for 625 MHz < = Freq ( f) = < 3. 125
GHz; where f is frequency in MHz.
dB
Out put j it t er
Near- end maximums ( TP-T)
Tot al j it t er 0. 075 peak from t he mean UI
Det erminist ic j it t er 0. 085 peak from t he mean UI

99
Tabl e 3. 16. Recei ver Speci f i cat i ons at TP- R
Receiver input impedance must result in a different ial ret urn loss bet t er t han 10 dB and a common
mode ret urn loss bet t er t han 6 dB from 100 MHz t o 2. 5 GHz. This includes cont ribut ions from all
component s relat ed t o t he receiver including coupling component s. The ret urn loss reference
impedance is 100 O for different ial ret urn loss and 25 O for common mode.
Receiver Elect rical Specificat ions at TP- 4:
PI CMG 3. 1 specifies t he compliance point TP- R. Syst em designers are required t o ensure t he addit ional
losses t o TP- 4 are account ed for.
The AC coupling capacit ors at t he receiver must be no more t han 470 pF + 1% and mat ched wit hin 2%
wit h each ot her.
A 10GBASE- BX4 int erface bet ween t wo GbE port s is shown in Figure 3. 17.
Par amet er Val ue Uni t s
Baud rat e 3. 125 GBd
Clock t olerance 100 ppm
Different ial ret urn loss 10 dB
Common mode ret urn loss 6 dB
Jit t er amplit ude t olerance ( p- p) 0. 65 UI
Different ial skew 75 ps
Fi gur e 3. 17. 10GBASE- BX4 El ect r i cal Envi r onment
Dr iver
Bo ar d
Mated ZD
conn ec tor
Ba ckpl ane
Bo ar d
TP -1 TP -T TP -R TP -4
TP -4 TP -R TP -T TP -1
PICMG 3. 1
IE E E 802. 3 XAUI

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3. 7.1. 6 SFI Oper at i ng Mode
The MAUI int erface is configured as SFI by EEPROM or soft ware by set t ing t he relevant bit s in t he
AUTOC regist er and disabling aut o- negot iat ion ( see Sect ion 3. 7. 4. 2) . When in SFI operat ing mode, only
t he operat ion of t he 82599 Analog Front End ( AFE) is modified, while t he rest of t he 82599 logic and
circuit ry operat es similar t o 10GBASE- KR. When in SFI operat ing mode, MAUI lane 0 is used for receive
and t ransmit act ivit y while lanes 1 t o 3 of t he MAUI int erface are powered down.
3.7.1. 6.1 SFI Ov er vi ew
SFI definit ion enables 10 Gb/ s operat ion over a single different ial pat h in each direct ion for a t ot al of
t wo pairs, or four connect ions. When in SFI operat ing mode t he 82599 uses t he 10GBASE- R PCS and
10 Gigabit PMA as defined in I EEE802. 3 Clause 49 and 51, respect ively.
SFI is a full- duplex int erface t hat uses a single self- clocked serial different ial link in each direct ion t o
achieve 10 Gb/ s dat a t hroughput . The serial link t ransfers scrambled dat a at 10. 3125 Gbaud t o
eliminat es skew concerns bet ween clock and dat a.
3.7.1. 6.2 SFI El ect r i cal Char act er i st i cs
The SFI lane is a low swing AC coupled different ial int erface using NRZ signaling. AC coupling allows for
different ial signaling provides noise immunit y and improved reduced EM) . Different ial signal swings
line losses.
The SFI signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a SFI lane and is
comprised of t wo complement ary signals making a balanced different ial pair. There is a single
different ial pat h in each direct ion for a t ot al of t wo pairs, or four connect ions. The signal pat hs are
int ended t o operat e on FR4 PCBs.
SFI int erface t ypically operat es over 200 mm of improved FR4 mat erial or up t o about 150 mm of
st andard FR4 wit h one connect or. The elect rical int erface is based on high speed low volt age AC coupled
logic wit h a nominal different ial impedance of 100 O. The SFI link requires nominal 100 O different ial
source and load t erminat ions on bot h t he host board and t he module. The SFI t erminat ions provide
bot h different ial and common mode t erminat ion t o effect ively absorb different ial and common mode
noise and reflect ions. All SFI t ransmit t ers and receivers are AC coupled. SFP+ modules incorporat e
blocking capacit ors on all SFI lines.
3.7.2 GbE I nt er f ace
The 82599 provides complet e support for up t o t wo 1 Gb/ s port implement at ions. The device performs
all funct ions required for t ransmission and recept ion defined by t he different st andards.
A lower- layer PHY int erface is included t o at t ach eit her t o ext ernal PMA or Physical Medium Dependent
( PMD) component s.
When operat ing in 1 GbE operat ion mode, t he 82599 uses Lane 0 of t he XAUI int erface for 1 GbE
operat ion while t he ot her t hree XAUI lanes are powered down.
The 82599 enables 1 GbE operat ion compliant wit h t he KX, BX or SGMI I specificat ions by programming
t he appropriat e bit s in t he AUTOC regist er.

101
3.7. 2.1 1000BASE- KX Oper at i ng Mode
The MAUI int erface, when operat ing as a KX I nt erface, support s dat a rat es of 1 Gb/ s over copper t races
on improved FR4 PCBs. Dat a is t ransferred over a single different ial pat h in each direct ion for a t ot al of
t wo pairs ( Lane 0 of MAUI int erface and Lanes 1 t o 3 powered down) , wit h each pat h operat ing at 1. 25
Gbaud t o support overhead of 8B/ 10B coding. The int erface is used t o connect t he 82599 t o a KX
compliant swit ch port over t he backplane or t o KX compliant 1 GbE PHY device. I n t he event of aut o-
negot iat ion defined in I EEE802. 3ap clause 73 ending wit h 1 Gb/ s as t he HCD, t he MAUI int erface is
configured as a KX int erface. KX operat ing mode can also be forced by soft ware by set t ing t he relevant
bit s in t he AUTOC regist er and disabling aut o- negot iat ion ( see Sect ion 3. 7. 4. 2) .
3. 7.2. 1.1 KX Over v i ew
1000BASE- KX ext ends t he family of 1000BASE-X Physical Layer signaling syst ems. KX specifies
operat ion at 1 Gb/ s over t wo different ial, cont rolled impedance pairs of t races ( one pair for t ransmit ,
one pair for receive) . This syst em uses t he 1000BASE-X PCS and PMA as defined in I EEE802.3 Clause
36 t oget her wit h t he amendment s placed in I EEE802. 3ap. The 1000BASE- KX PMD is defined in
I EEE802. 3ap Clause 70.
KX is a full- duplex int erface t hat uses a single serial different ial link in each direct ion t o achieve 1 Gb/ s
dat a t hroughput . Each serial link operat es at 1. 25 GBaud t o accommodat e bot h dat a and t he overhead
associat ed wit h 8B/ 10B coding. The self- clocked nat ure eliminat es skew concerns bet ween clock and
dat a, and enables a funct ional reach of up t o one met er.
Figure 3.18 shows t he archit ect ure posit ioning of 1000BASE- KX.
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3.7.2. 1.2 KX El ect r i cal Char act er i st i cs
The KX lane is a low swing AC coupled different ial int erface using NRZ signaling. AC coupling allows for
different ial signaling provides noise immunit y and improved reduced elect romagnet ic int erference
( EMI ) . Different ial signal swings defined specificat ions depend on several fact ors, such as t ransmit t er
pre- equalizat ion and t ransmission line losses.
The KX signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a KX lane and is
comprised of t wo complement ary signals making a balanced different ial pair. There is one different ial
pat h in each direct ion for a t ot al of t wo pairs, or four connect ions. The signal pat hs are int ended t o
operat e up t o approximat ely one met er over cont rolled impedance t races on improved FR4 PCBs.
3. 7.2. 2 1000BASE- BX Oper at i ng Mode
1000BASE- BX is t he PI CMG 3. 1 elect rical specificat ion for t ransmission of 1 Gb/ s Et hernet encoded dat a
over a 100 O different ial backplane. The 1000BASE- BX st andard defines a full- duplex int erface t hat
uses a single serial different ial link in each direct ion ( one pair for receive and one for t ransmit ) t o
achieve 1 Gb/ s dat a t hroughput . Each serial link operat es at 1. 25 GBaud t o accommodat e bot h dat a
bet ween clock and dat a. BX operat ing mode can be forced by soft ware by set t ing t he relevant bit s in
t he AUTOC regist er and disabling aut o- negot iat ion ( see Sect ion 3. 7. 4. 2) .
Fi gur e 3.18. Ar chi t ect ur al Posi t i oni ng of 1000BASE- KX
LAN CSMA/CD LAYERS
Higher Layers
MAC
Reconciliation
GMII
MDI
8B/10B PCS
MEDIUM
PMA
PMD
AN
1000BASE- KX

103
3. 7.2. 2.1 BX El ect r i cal Char act er i st i cs
The BX lane is a low swing AC coupled different ial int erface. AC coupling allows for int er- operabilit y
bet ween component s operat ing from at different supply volt ages. Low swing different ial signaling
provides noise immunit y and improved reduced EMI . Different ial signal swings defined specificat ions
depend on several fact ors, such as t ransmit t er pre- equalizat ion and t ransmission line losses.
The BX signal pat hs are point - t o- point connect ions. Each pat h corresponds t o a BX lane and is
comprised of t wo complement ary signals making a balanced different ial pair. There is one different ial
pat h in each direct ion for a t ot al of t wo pairs, or four connect ions.
3. 7. 3 SGMI I Suppor t
The 82599 support s 1 Gb/ s and 100 Mb/ s operat ion using t he SGMI I prot ocol over t he KX and BX
elect rical int erface ( AC coupling, no source synchronous TX clock, et c. ) .
3.7.3.1 SGMI I Ov er v i ew
SGMI I int erface support ed by t he 82599 enables operat ion at 1 Gb/ s over t wo different ial, cont rolled
impedance pairs of t races ( one pair for t ransmit , one pair for receive) . When operat ing in SGMI I , t he
MAUI int erface uses t he 1000BASE-X PCS and PMA as defined in I EEE802. 3 Clause 36 and t he
1000BASE- KX PMD as defined in I EEE802. 3ap Clause 70 or t he 1000BASE- BX as defined in t he PCI MG
3. 1 st andard. I n SGMI I operat ing mode, t he MAUI int erface can support dat a rat es of 1 Gb/ s and
100 Mb/ s.
SGMI I , support ed by t he 82599, is a full- duplex int erface t hat uses a single serial different ial link in
each direct ion t o achieve 1 Gb/ s dat a t hroughput . Each serial link operat es at 1. 25 GBaud t o
eliminat es skew concerns bet ween clock and dat a.
SGMI I cont rol informat ion, as list ed in Table 3.17 is t ransferred from t he PHY t o t he MAC t o signal
change of link speed ( 100 Mb/ s or 1 Gb/ s) . This is achieved by using t he aut o- negot iat ion funct ionalit y
defined in Clause 37 of t he I EEE Specificat ion 802. 3z. I nst ead of t he abilit y advert isement , t he PHY
sends t he cont rol informat ion via it s t x_config_reg[ 15: 0] as list ed in Table 3. 17 each t ime t he link
speed informat ion changes. Upon receiving cont rol informat ion, t he MAC acknowledges t he updat e of
t he cont rol informat ion by assert ing bit 14 of it s t x_config_reg[ 15: 0] as list ed in Table 3. 17. Compared
t o t he definit ion in I EEE802. 3 clause 37, t he link_t imer inside t he aut o- negot iat ion has been changed
from 10 ms t o 1.6 ms t o ensure a prompt updat e of t he link st at us.
Tabl e 3. 17. SGMI I Li nk Cont r ol I nf or mat i on
Bi t
Number
TX_CONFI G_REG[ 15: 0] Sent Fr om PHY t o MAC TX_CONFI G_REG[ 15: 0] Sent Fr om MAC t o PHY
15 Link: 1b = link up, 0b = link down 0b: Reserved for fut ure use.
14
Reserved for aut o- negot iat ion acknowledge as
specified in 802. 3z
1b.
13 0b: Reserved for fut ure use 0b: Reserved for fut ure use.
12 Duplex mode: 1b = full duplex, 0b = half duplex 0b: Reserved for fut ure use.
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When operat ing in 100 Mb/ s t he SGMI I int erface elongat es t he frame by replicat ing each frame byt e 10
t imes for 100 Mb/ s. This frame elongat ion t akes place above t he 802. 3z PCS layer, t hus t he st art frame
delimit er only appears once per frame. Not e t hat t he 802. 3z PCS layer might remove t he first byt e of
t he elongat ed frame. An example of a 100 Mb/ s elongat ed frame can be seen in Figure 3.19.
3. 7. 4 Aut o Negot i at i on For Back pl ane Et her net and Li nk Set up
Feat ur es
Aut o- negot iat ion provides a linked device wit h t he capabilit y t o det ect t he abilit ies ( modes of operat ion)
support ed by t he device at t he ot her end of t he link, det ermine common abilit ies, and configure for
j oint operat ion.
Aut o- negot iat ion for backplane Et hernet is based on I EEE802. 3 clause 28 definit ion of aut o- negot iat ion
for t wist ed- pair link segment s. Aut o- negot iat ion for backplane Et hernet uses an ext ended base page
and next page format and modifies t he t imers t o allow rapid convergence. Furt hermore, aut o-
negot iat ion does not use Fast Link Pulses ( FLPs) for link code word signaling and inst ead uses
Different ial Manchest er Encoding ( DME) signaling, which is more suit able for elect rical backplanes.
Since DME provides a DC balanced signal.
Aut o- negot iat ion for backplane Et hernet is defined in I EEE802. 3ap Clause 73 and includes support for
parallel det ect ion of 1000BASE- KX and 10GBASE- KX4 links in addit ion t o t ransmission and recept ion of
ext ended base page and next page aut o- negot iat ion frames. The 82599 support s recept ion of ext ended
base page and next page aut o- negot iat ion frames but does not t ransmit next page aut o- negot iat ion
frames only NULL frames.
3. 7. 4. 1 Li nk Conf i gur at i on
The 82599 net work int erface meet s indust ry specificat ions for:
10 GbE:
XAUI ( I EEE 802. 3ae)
SFI ( SFF- 8431 Specificat ions for Enhanced 8. 5 and 10 Gigabit Small Form Fact or Pluggable
Module SFP+ )
10 GbE 10GBASE- CX4 ( I EEE 802. 3ak)
11: 10
Speed: Bit 11, 10:
11b = Reserved.
10b = 1000 Mb/ s: 1000BASE-TX.
01b = 100 Mb/ s: 100BASE-TX.
00b = 10 Mb/ s: 10BASE-T ( not support ed) .
00b: Reserved for fut ure use.
9: 1 0x0 = Reserved for fut ure use. 0x0: Reserved for fut ure use.
0 1b. 1b.
Fi gur e 3.19. Dat a Sampl i ng i n 100 Mb/ s Mode
Tabl e 3.17. SGMI I Li nk Cont r ol I nf or mat i on
Bi t
Number
TX_CONFI G_REG[ 15: 0] Sent Fr om PHY t o MAC TX_CONFI G_REG[ 15: 0] Sent Fr om MAC t o PHY
D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1
Data in 100 Mbps
Domain
RXD [7:0] After
Rate Adaptation
Data 0
Data 2 Data 1
D2 D2 D2 D2 D2 D2

105
1 GbE backplane:
Et hernet 1000BASE- KX ( I EEE 802. 3ap)
Et hernet 1000BASE- BX ( PI CMG3. 1)
SFI ( SFF- 8431 Specificat ions for Enhanced 8. 5 and 10 Gigabit Small Form Fact or Pluggable
Module SFP+ )
10 GbE backplane:
Et hernet 10GBASE- KX4 ( I EEE 802. 3ap)
Et hernet 10GBASE- KR ( I EEE 802. 3ap)
The MAUI AFE is configured at st art up t o support t he appropriat e prot ocol as a funct ion of t he
negot iat ion process and pre- defined cont rol bit s t hat are eit her loaded from t he EEPROM or configured
by soft ware.
3.7.4.2 MAC Li nk Set up and Aut o Negot i at i on
The MAC block in t he 82599 support s bot h 10 GbE and 1 GbE link modes and t he appropriat e
funct ionalit y specified in t he st andards for t hese link modes.
Each of t hese link modes can use different PMD sublayer and base band medium t ypes.
I n 10 GbE operat ing mode, t he 82599 support s 10GBase- KX4, 10GBase- CX4, 10GBase- KR, SFI or XAUI
( 10 GbE At t achment Unit I nt erface) . While in 1 GbE operat ing mode, t he 82599 support s 1000Base- KX,
1000Base- BX or SGMI I ( SGMI I also support s bot h 100 Mb/ s and 1 Gb/ s dat a rat es) prot ocols. The
different prot ocols support ed in 10 GbE operat ing mode and 1 GbE operat ing mode affect only t he
configurat ion of t he MAUI AFE and MAUI PHY logic blocks ( PCS, FEC, et c. ) while t he MAC support s rat es
of eit her 1 Gb/ s or 10 Gb/ s, wit hout need t o know t he elect rical medium act ually being int erfaced.
Link speed and link charact erist ics can be det ermined t hrough st at ic configurat ion, parallel det ect and
aut o- negot iat ion or forced operat ion for diagnost ic purposes. The aut o- negot iat ion processes defined in
I EEE802. 3ap clause 73 enables select ion bet ween KR ( 10G) , KX4 ( 10G) and KX ( 1G) compliant link
part ners and defining link charact erist ics and link speed. While t he aut o- negot iat ion process defined in
I EEE802. 3 clause 37 enables det ect ion of t he BX ( 1 GbE) link charact erist ics but not t he link speed.
Link set t ing is done by configuring t he speed configurat ion in t he AUTOC. LMS field, defining t he
appropriat e physical int erface by programming AUTOC. 1G_PMA_PMD,
AUTOC.10G_PMA_PMD_PARALLEL and AUTOC2.10G_PMA_PMD_Serial and rest art ing aut o- negot iat ion
by set t ing AUTOC. Rest art _AN t o 1b.
3.7.4.3 Har dw ar e Det ect i on of Legacy Li nk Par t ner ( Par al l el Det ect i on)
The 82599 support s t he I EEE802. 3ap clause 73 parallel det ect ion process t o enable a connect ion t o
legacy link part ners t hat do not support aut o- negot iat ion. Parallel det ect ion enables det ect ing t he link
part ner operat ing mode ( KX4 or KX as defined in I EEE802. 3ap clause 73) by act ivat ing KX4 and KX
alt ernat ely and at t empt ing t o achieve link synchronizat ion by t he relat ed PCS block.
Parallel det ect ion is enabled as part of clause 73 backplane aut o- negot iat ion process by appropriat ely
configuring t he link speed and aut o- negot iat ion mode in t he AUTOC. LMS regist er field, clearing
AUTOC2. PDD t o 0b and rest art ing aut o- negot iat ion by set t ing t he AUTOC. Rest art AN bit t o 1b.
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106
3. 7.4. 4 MAUI Li nk Set up Fl ow
The 82599 MAUI int erface is configured at st art up ( before t he driver is loaded) in t he following
manner:
1. I f t he link is st at ically configured by programming t he appropriat e AUTOC ( LMS, 1G_PMA_PMD,
10G_PMA_PMD_PARALLEL) regist er fields and AUTOC2. 10G_PMA_PMD_Serial field, t he 82599
at t empt s t o synchronize on incoming dat a and if successful updat es t he relevant Link st at us
regist ers ( LI NKS, ANLP1 and ANLP2) and set s up t he link. I f link synchronizat ion is not successful,
t he 82599 does not report linkup in t he LI NKS regist er and cont inuously at t empt s t o set up t he link
according t o t he st at ic configurat ion.
2. I f t he Link is not st at ically configured and parallel det ect ion is enabled ( aut o- negot iat ion enabled in
AUTOC. LMS and t he AUTOC2. PDD parallel det ect disable is 0b) t he 82599 st art s I EEE802. 3ap
clause 73 negot iat ion prot ocol by at t empt ing t o parallel det ect t he prot ocol on t he MAUI int erface
by enabling KX and KX4 receive circuit ry and t rying t o synchronize on incoming dat a. I f
synchronizat ion succeeds in eit her KX or KX4 modes, t he 82599 updat es t he relevant link st at us
regist ers ( LI NKS, ANLP1 and ANLP2) and commences wit h set t ing up t he link.
3. I f parallel det ect fails, t he 82599 at t empt s t o aut o- negot iat e according t o I EEE802. 3ap clause 73
using t he dat a writ t en t o t he AUTOC, AUTOC2 and AUTOC3 regist ers. I f aut o- negot iat ion succeeds,
t he 82599 updat es t he link st at us regist ers ( LI NKS, ANLP1 and ANLP2) . I f aut o- negot iat ion fails,
t he 82599 does not report link up in t he LI NKS regist er and ret ries acquiring t he link by parallel
det ect ion and aut o- negot iat ion cont inuously ( t he receiver goes t hrough a cont inuous cycle of
1 GbE parallel det ect , 10 GbE parallel det ect and clause 73 aut o- negot iat ion) .
4. I f parallel det ect or st at ic configurat ion succeeds and t he link rat e is 1 Gb/ s, AUTOC. LMS enables
I EEE802. 3 clause 37 aut o- negot iat ion. The 82599 aut o- negot iat es t o define link charact erist ics
according t o I EEE802. 3 clause 37 using informat ion placed in regist ers PCS1GANA and PCS1GANNP.
On complet ion of clause 37 aut o- negot iat ion, t he 82599 updat es t he st at us in t he LI NKS,
PCS1GLSTA, PCS1GANLPNP and PCS1GANLP regist ers.
5. I f parallel det ect or st at ic configurat ion succeeds and t he link rat e is 1 Gb/ s, SGMI I is enabled in t he
AUTOC. LMS field ( LMS = 101b) . I f t he 82599 det ect s t he SGMI I negot iat ion cont rol informat ion
sent by t he PHY, t he 82599 aut o- negot iat es t o define link charact erist ics ( 1 Gb/ s or 100 Mb/ s and
full duplex capabilit y) according t o t he SGMI I specificat ion. On complet ing SGMI I aut o- negot iat ion,
t he 82599 updat es t he st at us in t he LI NKS, PCS1GLSTA and PCS1GANLP regist ers.
When AUTOC. LMS is set t o 1b of t he aut o- negot iat ion modes and t he Link Up bit is set t o 1b in t he
LI NKS regist er, t he final link speed can be read from t he LI NK_SPEED field of LI NKS.
I f LI NK_SPEED is 10 Gb/ s, t he MLI NK_MODE field is used t o different iat e bet ween KX4 ( 10 GbE
parallel) and KR ( 10 GbE serial) .
Not e: AUTOC.AN_RESTART must be set on every AUTOC.LMS change.
3. 7.4. 5 Nex t Page Suppor t
Next Page ( NP) support in t he 82599 is compliant wit h I EEE802. 3ap.
The 82599 act s as receiver of NP each t ime t he link part ner needs t o t ransmit NP dat a t hrough t he KX/
KX4 aut o- negot iat ion process.
The 82599 does not support t ransmission of configurable NP. I t t ransmit s a null NP each t ime t he aut o-
negot iat ion arbit rat ion st at e machine is required t o go t hrough t he NP handshake. There is a possibilit y
t o configure t he Acknowledge2 field in t he NP t hrough t he AUTOC. ANACK2 bit .

107
3.7.4.6 For ci ng Li nk Up
Forcing link up can be accomplished by soft ware by set t ing t he AUTOC. FLU bit t o 1b, which forces t he
MAC t o t he appropriat e MAC link speed as defined by t he AUTOC. LMS field and t he appropriat e prot ocol
as defined by t he AUTOC. 10G_PMA_PMD_PARALLEL, AUTOC2. 10G_PMA_PMD_Serial and
AUTOC. 1G_PMA_PMD bit s. The Force- Link- Up mode enables loopback operat ion ( when HLREG0. LPBK is
set t o 1b) by set t ing t he link_up indicat ion regardless of t he XGXS/ PCS_1G/ KR_locked st at us. Link
indicat ion in regist er LI NKS should be ignored when in t his mode.
3.7.4.7 Cr ossov er
The 82599 support s crossover on each of t he t wo MAUI port s t o eliminat e t he need for crossover cables
bet ween similar devices. This has hist orically been accomplished using special crossover cables ( pat ch
cables) , magnet ic pinout s or PCB wiring. The 82599 support s crossover configurat ion in bot h 10 GbE
and1 GbE operat ing modes via t he SERDESC regist er.
Having est ablished t hat t here is a problem wit h t he link connect ion, t he driver det ect s and correct s
crossovers and arbit rary polarit y swaps for several configurat ions of pair swaps. Crossover can also be
set by EEPROM following power up.
The following receiver pairs:
A MI _QL0 ( MI P_QL0 and MI N_QL0)
B MI _QL1 ( MI P_QL1 and MI N_QL1)
C MI _QL2 ( MI P_QL2 and MI N_QL2)
D MI _QL3 ( MI P_QL3 and MI N_QL3)
can be connect ed t o t he corresponding link part ner s t ransmit pairs in any of t he following ways wit h
arbit rary polarit y ( posit ive and negat ive wires exchanged) :
No crossover
A/ B crossover only
C/ D crossover only
A/ B crossover and C/ D crossover
Crossover operat ion is cont rolled by programming t he relevant bit s in t he SerDes I nt erface Cont rol
( SERDESC) regist er. The SERDESC regist er support s correct ion of all combinat ions of crossover
scenarios, in addit ion t o t he scenarios previously described.
3. 7. 5 Tr anscei v er Modul e Suppor t
The 82599 MAUI int erface wit h addit ional usage of low speed int erface pins ( SDP, I
2
C and MDI O I / Os)
support s a connect ion t o t ransceiver modules compliant wit h t he following Mult i Source Agreement s
( MSAs) :
XENPAK A cooperat ion agreement for 10 Gigabit Et hernet Transceiver package Rev 3. 0
X2 A cooperat ion agreement for a small Versat ile 10 Gigabit Et hernet Transceiver package Rev
2. 0b
XPAK A cooperat ion agreement for a small form fact or pluggable 10 Gigabit Et hernet Transceiver
package Rev 2. 2
SFP+ SFF- 8431 Specificat ions for Enhanced 8. 5 and 10 Gigabit Small Form Fact or Pluggable
Module SFP+ rev 1.0
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108
Figure 3. 20 shows t he various t ransceiver module archit ect ure.
Table 3. 18 list s t he required int erface ( per port ) for support ing t he various modules. The 82599
support s t he high speed int erface using t he MAUI port and t he low speed int erface using t he SDP pins.
The 82599 enables int erfacing opt ical modules using t he MAUI pins, MDI O pins, I
2
C pins and SDP pins.
When int erfacing wit h XENPAK, XPAK and X2 modules, level t ranslat ors from LVTTL t o 1. 2V need t o be
added on t he MDI O pins and t he relevant SDP pins.
Fi gur e 3.20. XENPAK, XPAK and X2 Tr anscei ver Ar chi t ect ur e
Tabl e 3.18. Opt i cal Modul e I nt er f ace Suppor t
Modul e
Ty pe
Hi gh Speed
MAUI Pr ot ocol
Low Speed I nt er f ace ( per por t )
XENPAK XAUI
MDC
1
( 1. 2V OUT) , MDI O
1
( 1. 2V I / O) ,
TX ON/ OFF
2
( 1. 2V OUT) , RESET
2
( 1. 2V OUT)
LASI ( 1. 2V I N I nt errupt )
1. Single management int erface can be used for t wo port s.
2. Out put low during reset and power down.
X2 XAUI
MDC
1
1
( 1. 2V I / O) ,
TX ON/ OFF
2
2
( 1. 2V OUT)
XPAK XAUI
MDC
1
1
( 1. 2V I / O) ,
TX ON/ OFF
2
2
( 1. 2V OUT)
SFP+ SFI
SCL
1
( I 2C OD) , SDL
1
( I 2C OD)
TX Disable
3
( LVTTL OUT) , RS0/ 1 ( LVTTL OUT)
TX Fault ( LVTTL I N) , RX_LOS ( LVTTL I N)
SerDes
CDR
3.125G
Des
8B/10B
decode
3.125G
Ser
8B/10B
encode
3.125G
Des
8B/10B
decode
3.125G
Ser
8B/10B
encode
64B/
66B
encode
64B/
66B
decode
4x
3.125
Gbit/s
XAUI
XGXS PCS PMA PMD
XAUI-10G Serial SerDes PMA PHY
Includes 10-Gbit/s SerDes/CDR
4x3.125Gbit/s Electrical XAUI
interface
TIA
TOSA
ROSA
LDD
uP
PD
Laser
10G Serial TIA and LDD PMD PHY
Transimpedance Amplifier (TIA)
next to Photo Diode (PD) in
Receiver Optical Sub-Assembly
(ROSA)
Laser Device Driver (LDD)
driving the laser in the
Transmitter Optical Sub-
Assembly (TOSA)
10
Gbit/s
Serial
MDIO
Control/Status

109
3.7.6 Management Dat a I nput / Out put ( MDI O) I nt er f ace
The 82599 support s a MDI O int erface ( per port ) t o cont rol PHY funct ionalit y t hrough t he int erface. PHY
configurat ion regist ers are mapped int o t he MDI O space and can be accessed by t he MAC or any ot her
MDI O- mast er device.
The 82599 support s t he MDI O int erface for a cont rol plane connect ion bet ween t he MAC ( mast er side)
and PHY devices. The MDI O int erface enables bot h MAC and soft ware access t o t he PHY for monit or and
cont rol of PHY funct ionalit y. The 82599 is compliant wit h t he I EEE802. 3 clause 45 in bot h 10 GbE and
1 GbE operat ion. The 82599 also support s I EEE 802. 3 clause 22 frame format s and regist er address
space for accessing legacy PHY regist ers. The MDI O int erface uses LVTTL signaling as defined in Clause
22 of t he I EEE802. 3 st andard. To access PHYs t hat support clause 45 1. 2V elect rical int erface, level
t ranslat ors need t o be added on board.
Figure 3.21 shows t he basic connect ivit y bet ween t he PHY and MAC.
The MDI O int erface is a simple 2- wire serial int erface bet ween MAC and PHY and is used t o access
Cont rol and St at us regist ers inside t he PHY. The int erface is implement ed using t wo LVTTL I / Os:
1. MDC MDI O- int erface clock signal driven by an ext ernal MAC ( STA) device.
2. MDI O Read/ writ e dat a bet ween an ext ernal MAC and PHY.
3. 7. 6. 1 MDI O Ti mi ng Rel at i onshi p t o MDC
The MDC clock t oggles during a read/ writ e operat ion at a frequency of 24 MHz, 2.4 MHz or 240 KHz
depending on t he link speed and regist er bit HLREG0. MDCSPD as list ed in Table 3.19.
Fi gur e 3.21. Basi c PHY MAC Connect i vi t y
Tabl e 3. 19. MDC Fr equency as Funct i on of Li nk Speed and MDC Speed Bi t
Li nk Speed MDCSPD= 1b MDCSPD= 0b
10 Gb/ s 24 MHz 2. 4 MHz
1 Gb/ s 2. 4 MHz 240 KHz
100 Mb/ s 240 MHz 240 KHz
Communications
Controller
PHY/
Optical
Module
PHY/
Optical
Module
MDIO/I
2
C
Cable/Fiber
Status/Control
MAUI
MDIO/I
2
C
Status/Control
MAUI
Cable/Fiber
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110
MDI O is a bidirect ional signal t hat can be sourced by t he St at ion Management Ent it y ( STA) or t he PHY.
When t he STA sources t he MDI O signal, t he STA must provide a minimum of 10 ns of set up t ime and a
minimum of 10 ns of hold t ime referenced t o t he rising edge of MDC, as shown in Figure 3.22
( measured at t he MI I connect or) .
When t he MDI O signal is sourced by t he PHY, it is sampled by t he MAC ( STA) synchronously wit h
respect t o t he rising edge of MDC. The clock t o out put delay from t he PHY, as measured at t he MI I
connect or, must be a minimum of 0 ns, and a maximum of 300 ns, as shown in Figure 3. 23.
3.7.6. 2 I EEE802.3 Cl ause 22 and Cl ause 45 Di f f er ences
I EEE802. 3 clause 45 provides t he abilit y t o access addit ional device regist ers while st ill ret aining logical
compat ibilit y wit h int erface defined in Clause 22. Clause 22 specifies t he MDI O frame format and uses
an ST code of 01 t o access regist ers. I n clause 45, addit ional regist ers are added t o t he address space
by defining MDI O frames t hat use a ST code of 00.
Clause 45 ( MDI O int erface) maj or concept s:
a. Preserve management frame st ruct ure defined in I EEE 802. 3 Clause 22.
b. Define mechanism t o address more regist ers t han specified in I EEE802. 3 Clause 22.
c. Define ST and OP codes t o ident ify and cont rol t he ext ended access funct ions.
Fi gur e 3.22. MDI O Ti mi ng Sour ced by t he MAC
Fi gur e 3.23. MDI O Ti mi ng Sour ced by t he PHY

111
3. 7. 6. 3 MDI O Management Fr ame St r uct ur e
The MDI O int erface frame st ruct ure defined in I EEE802. 3 clause 22 and Clause 45 are compat ible so
t hat t he t wo syst ems support ing different format s can coexist on t he same MDI O bus. The 82599
support s bot h frame st ruct ures t o enable int erfacing PHYs t hat support eit her prot ocol.
The basic frame format as defined in I EEE802. 3 clause 22 can opt ionally be used for accessing legacy
PHY regist ers is list ed in Table 3.20.
Tabl e 3. 20. Cl ause 22 Basi c MDI O Fr ame For mat
The MDI O int erface defined in clause 45 uses indirect addressing t o creat e an ext ended address space
enabling access t o a large number of regist ers wit hin each MDI O Managed Device ( MMD) . The MDI O
management frame format is list ed in Table 3. 21.
To support clause 45 indirect addressing each MMD ( PHY MDI O managed device) implement s a 16-
bit address regist er t hat st ores t he address of t he regist er t o be accessed by dat a t ransact ion frames.
The address regist er must be overwrit t en by address frames. At power up or device reset , t he cont ent s
of t he address regist er are undefined. Writ e, read, and post - read- increment - address frames must
access t he regist er whose address is st ored in t he address regist er. Writ e and read frames must not
modify t he cont ent s of t he address regist er. Upon receiving a post - read- increment - address frame and
having complet ed t he read operat ion, t he MMD increment s t he Address regist er by one ( up t o a value of
0xFFFF) . Each MMD support ed implement s a separat e address regist er, so t hat t he MMD' s address
regist ers operat e independent ly of one anot her.
I dle Condit ion ( I DLE) The I DLE condit ion on MDI O is a high- impedance st at e. All t hree st at e drivers
must be disabled and t he PHY' s pullup resist or pulls t he MDI O line t o a logic one.
Preamble ( PRE) At t he beginning of each t ransact ion, t he st at ion management ent it y must send a
sequence of 32 cont iguous consecut ive one bit s on MDI O wit h 32 corresponding cycles on MDC t o
provide t he PHY wit h a pat t ern t hat it can use t o est ablish synchronizat ion. A PHY must observe a
sequence of 32 cont iguous consecut ive one bit s on MDI O wit h 32 corresponding cycles on MDC before it
responds t o any t ransact ion.
Management Fr ame Fi el ds
Fr ame Pr e ST OP PRTAD REGAD TA Dat a I dl e
Read 1. . . 1 01 10 PPPPP RRRRR Z0 DDDDDDDDDDDDDDDD Z
Writ e 1. . . 1 01 01 PPPPP RRRRR 10 DDDDDDDDDDDDDDDD Z
Tabl e 3. 21. Cl ause 45 I ndi r ect Addr essi ng MDI O Fr ame For mat
Management Fr ame Fi el ds
Fr ame Pr e ST OP PRTAD DEVAD TA Addr ess / Dat a I dl e
Address 1. . . 1 00 00 PPPPP EEEEE 10 AAAAAAAAAAAAAAAA Z
Writ e 1. . . 1 00 01 PPPPP EEEEE 10 DDDDDDDDDDDDDDDD Z
Read 1. . . 1 00 11 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z
Post - Read
I ncrement
Address
1. . . 1 00 10 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z
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St art of Frame ( ST) The ST is indicat ed by:
< 00> pat t ern for clause 45 compat ible frames for indirect access cycles.
< 01> pat t ern for clause 22 compat ible frames for direct access cycles.
These pat t erns ensure a t ransit ion from t he default value of one on t he MDI O signal, and ident ifies t he
st art of frame.
Operat ion Code ( OP) The OP field indicat es t he t ype of t ransact ion being performed by t he frame.
For Clause 45 compat ible frames:
A < 00> pat t ern indicat es t hat t he frame payload cont ains t he address of t he regist er t o access.
A < 01> pat t ern indicat es t hat t he frame payload cont ains dat a t o be writ t en t o t he regist er whose
address was provided in t he previous address frame.
A < 11> pat t ern indicat es t hat t he frame is an indirect read operat ion.
A < 10> pat t ern indicat es t hat t he frame is an indirect post - read- increment - address operat ion.
For Clause 22 compat ible frames:
A < 10> pat t ern indicat es a direct read t ransact ion from a regist er.
A < 01> pat t ern indicat es a direct writ e t ransact ion t o a regist er.
Port Address ( PRTAD) The PRTAD is five bit s, allowing 32 unique PHY port addresses. The first PRTAD
bit t o be t ransmit t ed and received is t he MSB of t he address. A st at ion management ent it y must have
prior knowledge of t he appropriat e port address for each port t o which it is at t ached, whet her
connect ed t o a single port or t o mult iple port s.
Device Address ( DEVAD) The DEVAD is five bit s, allowing 32 unique MMDs per port . The first DEVAD
bit t ransmit t ed and received is t he MSB of t he address. This field is relevant only in clause 45
compat ible frames ( ST= < 00> ) .
Regist er Address ( REGAD) The REGAD is five bit s, allowing 32 individual regist ers t o be addressed
wit hin each PHY. The first REGAD bit t ransmit t ed and received is t he MSB of t he address. This field is
relevant only in clause 22 compat ible frames ( ST= < 01> ) .
Turnaround ( TA) The TA t ime is a 2- bit t ime spacing bet ween t he DEVAD field and t he Dat a field of a
management frame. This is t o avoid cont ent ion during a read t ransact ion. For a read or post - read-
increment - address t ransact ion, bot h t he STA and t he PHY must remain in a high- impedance st at e for
t he first bit t ime of t he TA. The PHY must drive a zero bit during t he second bit t ime of t he TA of a read
or post read- increment - address t ransact ion. During a writ e or address t ransact ion, t he STA must drive a
one bit for t he first bit t ime of t he TA and a zero bit for t he second bit t ime of t he TA. Figure 3. 24 shows
t he behavior of t he MDI O signal during t he TA field of a read t ransact ion.
Fi gur e 3.24. Behavi or of MDI O Dur i ng TA Fi el d of a Read Tr ansact i on
MDC
MDIO
<R> <Z> <0>

113
Clause 45 compat ible frames have 16- bit address/ dat a fields. For an aut o- negat ion address cycle, it
cont ains t he address of t he regist er t o be accessed on t he next cycle. For t he dat a cycle of a writ e
frame, t he field cont ains t he dat a t o be writ t en t o t he regist er. For a read or post - read- increment -
address frame, t he field cont ains t he cont ent s of t he regist er. The first bit t ransmit t ed and received
must be bit 15.
Clause 22 compat ible frames have 16- bit dat a fields. The first dat a bit t ransmit t ed and received
must be bit 15 of t he regist er being addressed.
3. 7. 6. 4 MDI O Di r ect Access
The MDI is accessed t hrough regist ers MSCA and MSRWD. A single management frame is sent by
set t ing bit MSCA. MDI CMD t o 1b aft er programming t he appropriat e fields in t he MSCA and MSRWD
regist ers. The MSCA. MDI CMD bit is aut o cleared aft er t he read or writ e t ransact ion complet es. To
execut e clause 22 format writ e operat ions, t he following st eps should be done:
1. Dat a t o be writ t en is programmed in field MSRWD. MDI WRDATA.
2. Regist er MSCA is init ialized wit h t he appropriat e cont rol informat ion ( st art , code, et c.) wit h bit
MSCA. MDI CMD set t o 1b.
3. Wait for bit MSCA. MDI CMD t o reset t o 0b when indicat ing t hat t he t ransact ion on t he MDI O
int erface is complet e.
The st eps for clause 22 format read operat ions are ident ical t o t he writ e operat ion except t hat t he dat a
in field MSRWD. MDI WRDATA is ignored and t he dat a read from t he ext ernal device is st ored in regist er
field MSRWD. MDI RDDATA bit s. Clause 45 format read/ writ e operat ions must be performed in t wo st eps.
The address port ion of t he pair of frames is sent by set t ing regist er field MSCA. MDI ADD t o t he desired
address, field MSCA. STCODE t o 00b ( st art code t hat ident ifies clause 45 format ) , and regist er field
MSCA. OPCODE t o 00b ( clause 45 address regist er writ e operat ion) . A second dat a frame must be sent
aft er t he address frame complet es. This second frame execut es t he writ e or read operat ion t o t he
address specified in t he PHY address regist er.
3.7.7 Et her net Fl ow Cont r ol ( FC)
The 82599 support s flow cont rol as defined in 802. 3x, as well as t he specific operat ion of asymmet rical
flow cont rol defined by 802. 3z. The 82599 also support s Priorit y Flow Cont rol ( PFC) , somet imes
referred t o as Class Based Flow Cont rol or ( CBFC) , as part of t he DCB archit ect ure.
Not e: The 82599 can eit her be configured t o receive regular flow cont rol packet s or Priorit y Flow
Cont rol ( PFC) packet s. The 82599 does not support t he recept ion of bot h t ypes of packet s
simult aneously.
Flow cont rol is implement ed t o reduce receive buffer overflows, which result in t he dropping of received
packet s. Flow cont rol also allows for local cont rolling of net work congest ion levels. This can be
accomplished by sending an indicat ion t o a t ransmit t ing st at ion of a nearly full receive buffer condit ion
at a receiving st at ion.
The implement at ion of asymmet ric flow cont rol allows for one link part ner t o send flow cont rol packet s
while being allowed t o ignore t heir recept ion ( for example, not required t o respond t o PAUSE frames) .
The following regist ers are defined for t he implement at ion of flow cont rol. I n DCB mode, some of t he
regist ers are duplicat ed per Traffic Class ( TC) , up t o eight duplicat e copies of t he regist ers. I f DCB is
disabled, index [ 0] of each regist er is used.
MAC Flow Cont rol ( MFLCN) regist er Enables flow cont rol and passing of cont rol packet s t o t he
host .
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Flow Cont rol Configurat ion ( FCCFG) Det ermines mode for Tx flow cont rol ( no FC vs. link based
versus priorit y based) . Not e t hat if Tx flow cont rol is enabled t hen Tx CRC by hardware should be
enabled as well ( HLREG0. TXCRCEN = 1b) .
Flow Cont rol Address Low, High ( RAL[ 0] , RAH[ 0] ) 6- byt e flow cont rol mult icast address.
Priorit y Flow Cont rol Type Opcode ( PFCTOP) Cont ains t he t ype and opcode values for priorit y FC.
Flow Cont rol Receive Threshold High ( FCRTH[ 7: 0] ) A set of 13 bit high wat ermarks indicat ing
receive buffer fullness. A single wat ermark is used in link FC mode and up t o eight wat ermarks are
used in priorit y FC mode.
Flow Cont rol Receive Threshold Low ( FCRTL[ 7: 0] ) A set of 13 bit low wat ermarks indicat ing
receive buffer empt iness. A single wat ermark is used in link FC mode and up t o eight wat ermarks
are used in priorit y FC mode.
Flow Cont rol Transmit Timer Value ( FCTTV[ 3: 0] ) a set of 16 bit t imer values t o include in
t ransmit t ed PAUSE frame. A single t imer is used in link FC mode and up t o eight t imers are used in
priorit y FC mode.
Flow Cont rol Refresh Threshold Value ( FCRTV) 16- bit PAUSE refresh t hreshold value ( in legacy
FC FCRTV[ 0] must be smaller t han FCTTV[ 0] )
3. 7.7. 1 MAC Cont r ol Fr ames and Recept i on of Fl ow Cont r ol Pack et s
3.7.7. 1.1 MAC Cont r ol Fr ame Ot her t han FC
I EEE reserved t he Et hert ype value of 0x8808 for MAC cont rol frames as list ed in Table 3. 22.
3.7.7. 1.2 St r uct ur e of 802.3X FC Pack et s
802. 3X FC packet s are defined by t he following t hree fields ( see Table 3.23) :
1. A mat ch on t he six- byt e mult icast address for MAC cont rol frames or a mat ch t o t he st at ion address
of t he device ( Receive Address Regist er 0) . The 802. 3x st andard defines t he MAC cont rol frame
mult icast address as 01- 80- C2- 00- 00- 01.
2. A mat ch on t he Type field. The Type field in t he FC packet is compared against an I EEE reserved
value of 0x8808.
3. A mat ch of t he MAC Cont rol Opcode field has a value of 0x0001.
Frame based flow cont rol different iat es XOFF from XON based on t he value of t he PAUSE Timer field.
Non- zero values const it ut e XOFF frames while a value of zero const it ut es an XON frame. Values in t he
Timer field are in unit s of pause quant a ( slot t ime) . A pause quant a last s 64 byt e t imes, which is
convert ed in t o an absolut e t ime durat ion according t o t he line speed.
Tabl e 3.22. MAC Cont r ol Fr ame For mat
DA
The Dest inat ion Address field can be an individual or mult icast ( including broadcast ) address.
Permit t ed values for t he Dest inat ion Address field can be specified separat ely for a specific
cont rol opcode such as FC packet s.
SA Port Et hernet MAC address ( 6 byt es) .
Type 0x8808 ( 2 byt es) .
Opcode The MAC cont rol opcode indicat es t he MAC cont rol funct ion.
Paramet ers
The MAC Cont rol Paramet ers field must cont ain MAC cont rol opcode- specific paramet ers. This
field can cont ain none, one, or more paramet ers up t o a maximum of minFrameSize = 20
byt es.
Reserved field = 0x00
The Reserved field is used when t he MAC cont rol paramet ers do not fill t he fixed lengt h MAC
cont rol frame.
CRC 4 byt es.

115
Not e: XON frame signals t he cancellat ion of t he pause from t hat was init iat ed by an XOFF frame
pause for zero pause quant a) .
3. 7.7. 1.3 PFC
DCB int roduces support for mult iple t raffic classes assigning different priorit ies and bandwidt h per TC.
Link level Flow Cont rol ( PAUSE) st ops all t he t raffic classes. PFC or CBFC allows more granular flow
cont rol on t he Et hernet link in an DCB environment as opposed t o t he PAUSE mechanism defined in
802.3X.
PFC is implement ed t o prevent t he possibilit y of receive packet buffers overflow. Receive packet buffers
overflow result s in t he dropping of received packet s for a specific TC. Board designers can implement
PFC by sending a t imer indicat ion t o t he t ransmit t ing st at ion t raffic class ( XOFF) of a nearly full receive
buffer condit ion at t he 82599. At t his point t he t ransmit t er would st op t ransmit t ing packet s for t hat TC
unt il t he XOFF t imer expires or a XON message is received for t he st opped TC.
Similarly, once t he 82599 receives a priorit y- based XOFF it st ops t ransmit t ing packet s for t hat specific
TC unt il t he XOFF t imer expires or XON packet for t hat TC is received.
Tabl e 3. 23. 802.3X Pack et For mat
DA 01_80_C2_00_00_01 ( 6 byt es) .
SA Por t Et hernet MAC address ( 6 byt es) .
Opcode 0x0001 ( 2 byt es) .
Time XXXX ( 2 byt es) .
Pad 42 byt es.
CRC 4 byt es.
Fi gur e 3. 25. 802. 3X Li nk Fl ow Cont r ol ( PAUSE)
802.3
MAC Rx
802.3
MAC TX
Data to
MAC
1
1
8
i
n
.
XOFF blocks traffic on
the whole link
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Link flow cont rol ( 802. 3X) causes all t raffic t o be st opped on t he link. DCB uses t he same mechanism of
flow cont rol but provides t he abilit y t o do PFC on TCs as shown in Figure 3.26.
Fi gur e 3.26. Pr i or i t y Fl ow Cont r ol
Tabl e 3.24. Pack et For mat f or Pr i or i t y Fl ow Cont r ol
DA 01_80_C2_00_00_01 ( 6 byt es) .
SA Port Et hernet MAC Address ( 6 byt es) .
Opcode 0x0101 ( 2 byt es) .
Priorit y Enable Vect or 0x00XX ( 2 byt es) .
Timer 0 XXXX ( 2 byt es) .
Timer 3 XXXX ( 2 byt es)
Pad 26 byt es.
CRC 4 byt es.
802.3
MAC TX
802.3
MAC Rx
Class based XOFF blocks traffic on a
specific traffic class and not the whole link
Data to
MAC

117
The Priorit y Flow Cont rol Type Opcode ( PFCTOP) regist er cont ains t he t ype and opcode values for PFC.
These values are compared against t he respect ive fields in t he received packet .
Each of t he eight t imers refers t o a specific User Priorit y ( UP) . For example, Timer 0 refers t o UP 0, et c.
The 82599 binds a UP ( and t herefore t he t imer) t o one of it s TCs according t o t he UP- t o-TC binding
t ables. Refer t o t he RTTUP2TC regist er for t he binding of received PFC frames t o Tx TCs, and t o t he
RTRUP2TC regist er for t he binding of t ransmit t ed PFC frames t o Rx TCs.
Tx manageabilit y t raffic is bound t o one t he TCs via t he MNGTXMAP regist er, and should t hus be paused
according t o RTTUP2TC mapping whenever receiving PFC frames.
When a PFC frame is format t ed by t he 82599, t he same values are replicat ed int o every Timer field and
priorit y enable vect or bit of all t he UPs bound t o t he concerned TC. These values as configured in t he
RTRUP2TC regist er.
The following rule is applicable for t he case of mult iple UPs t hat share t he same TC ( as configured in t he
RTTUP2TC regist er) . When PFC frames are received wit h different t imer values for t he previous UPs, t he
t raffic on t he associat ed TC must be paused by t he highest XOFF t imer s value.
3.7.7.1.4 Oper at i on and Rul es
The 82599 operat es in eit her link FC or in PFC mode. Enabling bot h modes concurrent ly is not allowed:
Link FC is enabled by t he RFCE bit in t he MFLCN regist er.
PFC is enabled by t he RPFCE bit in t he MFLCN regist er.
Not e: Link flow cont rol capabilit y must be negot iat ed bet ween link part ners via t he aut o- negot iat ion
process. PFC capabilit y is negot iat ed via some higher level prot ocol and t he resolut ion is
usually provided t o t he driver by t he DCB management agent . I t is t he driver s responsibilit y
t o reconfigure t he link flow cont rol set t ings ( including RFCE and PRFCE) aft er t he aut o-
negot iat ion process was resolved.
Not e: Receiving a link FC frame while in PFC mode might be ignored or might pause TCs in an
unpredict able manner. Receiving a PFC frame while in link FC mode is ignored.
Once t he receiver has validat ed t he recept ion of an XOFF, or PAUSE frame, t he device performs t he
following:
I ncrement s t he appropriat e st at ist ics regist er( s)
I nit ialize t he pause t imer based on t he packet ' s PAUSE Timer field ( overwrit ing any current t imer s
value)
I n case of PFC, t his is done per TC. I f several UPs are associat ed wit h a TC, t hen t he device set s
t he t imer t o t he maximum value among all enabled t imer fields associat ed wit h t he TC.
Tabl e 3. 25. For mat of Pr i or i t y Enabl e Vect or
ms oct et ls oct et
Priorit y Enable vect or definit ion 0 e[ 7] . . . e[ n] . . . e[ 0]
e[n] =1 => time (n) valid
e[n] =0 => time (n) invalid
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Disable packet t ransmission or schedule t he disabling of t ransmission aft er t he current packet
complet es.
I n case of PFC, t his is done per paused TC
Tx manageabilit y t raffic is bound t o a specific TC as defined in t he MNGTXMAP regist er, and is
t hus paused when it s TC is paused
Resumpt ion of t ransmission can occur under t he following condit ions:
Expirat ion of t he PAUSE t imer
I n case of PFC, t his is done per TC
Recept ion of an XON frame ( a frame wit h it s PAUSE t imer set t o 0b)
I n case of PFC, t his is done per TC
Bot h condit ions set t he relevant TC_XON st at us bit s in t he Transmit Flow Cont rol St at us ( TFCS) regist er
and t ransmission can resume. Hardware records t he number of received XON frames.
3.7.7. 1.5 Ti mi ng Consi der at i ons
When operat ed at 10 Gb/ s line speed, t he 82599 must not begin t o t ransmit a ( new) frame more t han
60 pause quant a aft er receiving a valid Link XOFF frame, as measured at t he wires ( a pause quant um is
512 bit t imes) . When connect ed t o an ext ernal 10GBASE- KR PHY wit h FEC or t o an ext ernal 10GBASE-
T PHY, t he response t ime requirement decreases t o 74 pause quant a, because of ext ra delays
consumed by t hese ext ernal PHYs.
When operat ing at 1 Gb/ s line speed, t he 82599 must not begin t o t ransmit a ( new) frame more t han 2
pause quant a aft er receiving a valid Link XOFF frame, as measured at t he wires.
The 802. 1Qbb draft 1. 0, proposes t hat t he t olerat ed response t ime for Priorit y XOFF frames are t he
same as Link XOFF frames wit h ext ra budget of 19072 bit t imes if MACSec is used, or of 2 pause quant a
ot herwise. This ext ra budget is aimed t o compensat e t he fact t hat decision t o st op new t ransmissions
from a specific TC must be t aken earlier in t he t ransmit dat a pat h t han for t he Link Flow Cont rol case.
3. 7.7. 2 PAUSE and MAC Cont r ol Fr ames For w ar di ng
Two bit s in t he Receive Cont rol regist er cont rol t ransfer of PAUSE and MAC cont rol frames t o t he host .
These bit s are Discard PAUSE Frames ( DPF) and Pass MAC Cont rol Frames ( PMCF) . Not e also t hat any
packet must pass t he L2 filt ers as well.
The DPF bit cont rols t ransfer of PAUSE packet s t o t he host . The same policy applies t o bot h link FC
and priorit y FC packet s as list ed in Table 3.26. Not e t hat any packet must pass t he L2 filt ers as well.
The PMCF bit cont rols t ransfer of non- PAUSE packet s t o t he host . Not e t hat when link FC frames are
not enabled ( RFCE = 0b) t hen link FC frames are considered as MAC Cont rol ( MC) frames for t his
mat t er. Similarly, when PFC frames are not enabled ( RPFCE = 0b) t hen PFC frames are considered
as MC frames as well.

119
Not e: When virt ualizat ion is enabled, forwarded cont rol packet s are queued according t o t he regular
swit ching procedure defined in Sect ion 7. 10. 3. 4.
3.7.7.3 Tr ansmi t t i ng PAUSE Fr ames
The 82599 generat es PAUSE packet s t o insure t here is enough space in it s receive packet buffers t o
avoid packet drop. The 82599 monit ors t he fullness of it s receive FI FOs and compares it wit h t he
cont ent s of a programmable t hreshold. When t he t hreshold is reached, t he 82599 sends a PAUSE
frame. The 82599 support s bot h link flow cont rol and PFC but not bot h concurrent ly. When DCB is
enabled, it sends only PFC, and when DCB is disabled, it send only link flow cont rol.
Not e: Similar t o t he recept ion of flow cont rol packet s previously ment ioned, soft ware can enable
flow cont rol t ransmission by set t ing t he FCCFG.TFCE field only aft er it is negot iat ed bet ween
t he link part ners ( possibly by aut o- negot iat ion) .
3. 7.7. 3.1 Pr i or i t y Fl ow Cont r ol
Like Tx flow cont rol, Rx flow cont rol operat es in eit her a link 802. 3X compliant mode or in PFC mode,
but not in bot h at t he same t ime.
The same flow cont rol mechanism is used for PFC and for 802. 3X flow cont rol t o det ermine when t o
send XOFF and XON packet s. When PFC is used in t he receive pat h, Priorit y PAUSE packet s are sent
inst ead of 802. 3X PAUSE packet s. The format of priorit y PAUSE packet s is described in
Sect ion 3. 7. 7. 1. 3.
Specific considerat ions for generat ing PFC packet s:
When a PFC packet is sent , t he packet set s all t he UPs t hat are associat ed wit h t he relevant TC ( UP-
t o-TC associat ion in receive is defined in RTRUP2TC regist er) .
3.7.7.3.2 Oper at i on and Rul es
The TFCE field in t he Flow Cont rol Configurat ion ( FCCFG) regist er enables t ransmission of PAUSE
packet s as well as select s bet ween t he link flow cont rol mode and t he PFC mode.
The cont ent of t he Flow Cont rol Receive Threshold High ( FCRTH) regist er det ermines at what point t he
82599 t ransmit s t he first PAUSE frame. The 82599 monit ors t he fullness of t he receive FI FO and
compares it wit h t he cont ent s of FCRTH. When t he t hreshold is reached, t he 82599 sends a PAUSE
frame wit h it s pause t ime field equal t o FCTTV.
At t his t ime, t he 82599 st art s count ing an int ernal shadow count er ( reflect ing t he pause t imeout
count er at t he part ner end) . When t he count er reaches t he value indicat ed in FCRTV regist er, t hen, if
t he PAUSE condit ion is st ill valid ( meaning t hat t he buffer fullness is st ill above t he low wat ermark) , an
XOFF message is sent again.
Tabl e 3. 26. Tr ansf er of PAUSE Pack et t o Host ( DPF Bi t )
RFCE RPFCE DPF Li nk FC handl i ng Pr i or i t y FC handl i ng
0b 0b X Treat as MC ( according t o PMCF set t ing) . Treat as MC ( according t o PMCF set t ing) .
1b 0b 0b Accept . Treat as MC ( according t o PMCF set t ing) .
1b 0b 1b Rej ect . Treat as MC ( according t o PMCF set t ing) .
0b 1b 0b Treat as MC ( according t o PMCF set t ing) . Accept .
0b 1b 1b Treat as MC ( according t o PMCF set t ing) . Rej ect .
1b 1b X Unsupport ed set t ing. Unsupport ed set t ing.
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Once t he receive buffer fullness reaches t he low wat er mark, t he 82599 sends an XON message ( a
PAUSE frame wit h a t imer value of zero) . Soft ware enables t his capabilit y wit h t he XONE field of t he
FCRTL.
The 82599 sends a PAUSE frame if it has previously sent one and t he FI FO overflows. This is int ended
t o minimize t he amount of packet s dropped if t he first PAUSE frame did not reach it s t arget .
3.7.7. 3.3 Fl ow Cont r ol Hi gh Thr eshol d FCRTH
The 82599 sends a PAUSE frame when a Rx packet buffer is full above t he high t hreshold. The
t hreshold should be large enough t o overcome t he worst case lat ency from t he t ime t hat crossing t he
t hreshold is sensed unt il packet s are not received from t he link part ner. This lat ency is composed of t he
following element s:
Threshold Cross t o XOFF Transmission + Round- t rip Lat ency + XOFF Recept ion t o Link Part ner
Response, where:
Round- t rip Lat ency Calculat ion:
Pause Quant a ( PQ) = 512 bit t ime ( bt )
Round t rip for 10 GbE MAC + XAUI + 10 GbE PHY = 16+ 8+ 50 PQ ~ 4. 7 KB ( using anot her PHY
a lower lat ency can be t aken)
Round t rip capable ( 2x100 m) = 200 m x 50 bt / m = 10000 bt ~ 1.25 KB ( at ot her known
t opologies lower lat ency can be t aken)
Plus 2 KB for some guard- band and processing lat ency of t ransmission and recept ion pause
frames
The int ernal archit ect ure of t he Rx packet buffer is as follows:
1. Any packet st art s at 32 byt e aligned address.
2. Any packet has an int ernal st at us of 32 byt es. As a result , t he Rx packet buffer is used at worst
condit ions when t he Rx packet includes 65 byt es t hat are post ed t o t he host memory. Assuming
t hat t he CRC byt es are not post ed t o host memory t hen in t he worst case t he Rx packet buffer can
be filled at 1.44 higher rat e t han t he wire speed ( 69- byt e packet including CRC + 8- byt e preamble
+ 12- byt e back- t o- back I FS consumes 4 x 32 byt es = 128 byt es on t he Rx packet buffer) .
Translat ing t he lat encies t o possible consumed Rx packet buffer at worst case is:
Lat ency Par amet er Af f ect ed by . . . Val ue at 10 GbE w i t h Jumbo
Trigger t o XOFF t ransmission. Max packet size at all TCs. 9. 5 KB ( example) .
Link part ner XOFF t o t ransmission hold. Max packet size on t he specific TC. 9. 5 KB ( example) .
Round- t rip Lat ency.
The lat encies on t he wire and t he LAN devices at
bot h sides of t he wire.
8 KB ( see t he calculat ion t hat
follows) .
Lat ency Par amet er Val ue Consumed Rx Pack et Buf f er
Trigger t o XOFF t ransmission 9. 5 KB 1. 44 x 9. 5 KB ~ 14 KB
Link part ner XOFF t o t ransmission hold 9. 5 KB 9. 5 KB
Round- t rip lat ency 8 KB 1. 44 x 8 KB ~ 11. 5 KB

121
The FCRTH should be set t o t he size of t he Rx packet buffer minus ( 14 + 9.5 + 11. 5 = 35 KB) . As
previously indicat ed, t hese numbers are valid if j umbo frames are enabled in all t raffic classes. When it
is required t o avoid packet lost , soft ware must follow t his requirement and enable flow cont rol
funct ionalit y.
When Tx t o Rx swit ching is enabled, packet s can be received t o t he Rx packet buffer by local VM- t o-VM
t raffic. Once t he Rx packet buffer get s full and is above t he high t hreshold it might receive up t o one
addit ional packet from a local VM. Therefore, FCRTH should be set t o t he size of t he Rx packet buffer
minus ( t he size previously explained plus one addit ional max packet size) .
3. 7.7. 3.4 Fl ow Cont r ol Low Thr eshol d FCRTL
The low t hreshold value is aimed t o prot ect against wast ed available host bandwidt h. There is some
lat ency from t he t ime t hat t he low t hreshold is crossed unt il t he XON frame is sent and packet s are
received from t he link part ner. The low t hreshold can be set high enough so t hat t he Rx packet buffer
does not get empt y before new whole packet s are received from t he link part ner. When considering
dat a movement from t he Rx packet buffer t o host memory, t hen large packet s represent t he worst .
Assuming t he host bandwidt h is about as t wice t he bandwidt h on t he wire ( when only a single port is
act ive at a given t ime) . Therefore, on 10 GbE net work wit h j umbo packet s a t hreshold t hat guarant ee
t hat t he Rx packet buffer is not empt ied should be set larger t han: 2 x ( 2 x 9. 5 KB + 8 KB) ~ 54 KB.
Set t ing t he FCRTL t o lower values t han expressed by t he previous equat ion is permit t ed. I t might
simply result wit h pot ent ial sub- opt imal use of t he PCI e bus once bandwidt h is available.
3. 7.7. 3.5 Pack et Buf f er Si ze
When flow cont rol is enabled, t he t ot al size of a packet buffer must be large enough for t he low and
high t hresholds. I n order t o avoid const ant t ransmission of XOFF and XON frames it is recommended t o
add some space for hyst eresis t ype of behavior. The difference bet ween t he t wo t hresholds is
recommended t o be at least one frame size ( when 9. 5 KB ( 9728- byt e) j umbo frames are enabled) and
larger t han a few frames in ot her cases. I f t he available Rx packet is large enough, it is recommended
t o increase as much as possible t he hyst eresis budget . I f t he available Rx packet is not large enough it
might be required t o cut bot h t he low t hreshold as well as t he hyst eresis budget . The following t able
list s a few examples while it is recommended t o validat e t he values for a given use case.
When Tx- t o- Rx swit ching is enabled ( in virt ualizat ion mode) t he high t hreshold should t ake int o account
pot ent ial VM- t o-VM recept ion. As a result , t he Rx packet buffer' s sizes should be increased,
respect ively.
Lat ency Par amet er
Fl ow Cont r ol Hi gh
Thr eshol d
Fl ow Cont r ol Low
Thr eshol d
Tot al Pack et
Buf f er Si ze
9. 5 KB ( 9728- byt e) j umbo enabled wit h no DCB wit h flow
cont rol.
477 KB 54 KB 512 KB
9. 5 KB ( 9728- byt e) j umbo enabled x 8 TCs wit h flow cont rol. 29 KB 19. 5 KB 64 KB
9. 5 KB ( 9728- byt e) j umbo enabled x 8 TCs wit h flow cont rol
and flow direct or t able enabled wit h 128 KB.
13 KB 9 KB 48 KB
9. 5 KB ( 9728- byt e) j umbo enabled x 4 TCs wit h flow cont rol
and 1500- byt e ( no j umbo) x 4 TCs wit h flow cont rol and flow
direct or t able enabled wit h 128 KB.
21 KB
14 KB
11. 5 KB
9 KB
56 KB ( j umbo)
40 KB ( 1. 5 KB)
9. 5 KB ( 9728- byt e) j umbo enabled x 4 TCs WI THOUT flow
cont rol and
1500- byt e ( no j umbo) x 4 TCs WI TH flow cont rol and flow
direct or t able enabled wit h 128 KB.
N/ A
30 KB
N/ A
20 KB
40 KB ( j umbo)
56 KB ( 1. 5 KB)
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3. 7. 7. 4 Li nk FC i n DCB Mode
When operat ing in DCB mode, PFC is t he preferred met hod of get t ing t he best use of t he link for all TCs.
When connect ing t o swit ches t hat do not support ( or enable) PFC, t he 82599 t hrot t les t he t raffic using
link FC. Following is t he required device set t ing and funct ionalit y:
The 82599 should be set t o legacy link FC by set t ing MFLCN. RFCE.
Recept ion of XOFF pauses t ransmission in all TCs.
Crossing t he Rx buffer high t hreshold on any TC generat es XOFF t ransmission. Each TC can have it s
own t hreshold configured by t he FCRTH[ n] regist ers.
Crossing t he Rx buffer low t hreshold on any TC generat es XON t ransmission. This behavior is
undesired. Therefore, soft ware should not enable XON in t his mode by clearing FCRTL[ n] . XONE bit s
in all TC.
The Flow Cont rol Transmit Timer Value of all TCs must be set t o t he same value.
3.7.8 I nt er Pack et Gap ( I PG) Cont r ol and Paci ng
The 82599 support s t ransmission pacing by ext ending t he I PG ( t he gap bet ween consecut ive packet s) .
The pacing mode allows t he average dat a rat e t o be slowed in syst ems t hat cannot support t he full link
rat e ( 10 Gb/ s, 1Gb/ s or 100 Mb/ s) . As list ed in Table 3. 27, t he pacing modes work by st ret ching t he
I PG in proport ion t o t he dat a sent . I n t his case t he dat a sent is measured from t he end of preamble t o
t he last byt e of t he packet . No allowance is made for t he preamble or default I PG when using pacing
mode.
Ex ampl e 1:
Consider an example of a 64- byt e frame. To achieve a 1 Gb/ s dat a rat e when link rat e is 10 Gb/ s and
packet lengt h is 64 byt es ( 16 Dwords) , programmers need t o add an addit ional I PG of 144 Dwords
( nine t imes t he packet size t o reach 1 Gb/ s) . Which when added t o t he default I PG gives an I PG of 147
Dwords.
Ex ampl e 2:
Consider an example of a 65- byt e frame. To achieve a 1 Gb/ s dat a rat e when link rat e is 10 Gb/ s and
packet lengt h is 65 byt es ( 17 Dwords when rounded up) programmers need t o add an addit ional I PG of
153 Dwords ( nine t imes t he packet durat ion in Dwords) . Which when added t o t he default I PG gives an
I PG of 156 Dwords. Not e t hat in t hese case, where t he packet lengt h count ed in Dwords is not an
int eger, programmers need t o count any fract ion of a Dword as a whole Dword for comput ing t he
addit ional I PG.
Table 3. 27 list s t he pacing configurat ions support ed by t he 82599 at link rat es of 10 Gb/ s. When
operat ing at lower link speeds t he pacing speed is proport ional t o t he link speed.
Tabl e 3.27. Paci ng Speeds at 10 Gb/ s Li nk Speed
Paci ng Speeds ( Gb/ s) Del ay I nser t ed i nt o I PG Regi st er Val ue
10 ( LAN) None 0000b
9. 294196 ( WAN) 1 byt e for 13 t ransmit t ed 1111b
9. 0 1 Dword for 9 t ransmit t ed 1001b
8. 0 1 Dword for 4 t ransmit t ed 1000b
7. 0 3 Dwords for 7 t ransmit t ed 0111b

123
Pacing is configured in t he PACE field of t he Pause and Pace ( PAP) regist er.
Not e: The I PG pacing feat ure is a parallel feat ure t o t he Tx rat e scheduler where I PG pacing is
applied t o t he ent ire Tx dat a flow while t he Tx rat e scheduler is applied separat ely t o each Tx
queue. Therefore, if a single queue is used, eit her feat ure can be used t o limit t he Tx dat a
rat e; however, if mult iple queues are used, t he I PG pacing feat ure is a bet t er choice for a
homogeneous Tx dat a rat e limit at ion.
3. 7. 9 MAC Speed Change at Di f f er ent Pow er Modes
Normal speed negot iat ion drives t o est ablish a link at t he Highest Common Denominat or ( HCD) link
speed. The 82599 support s an addit ional mode of operat ion, where t he MAC est ablishes a link at t he
Lowest Common Denominat or ( LCD) link speed. The linkup process enables a link t o come up at any
possible speed in cases where power is more import ant t han performance. Different behavior is defined
for t he D0 st at e and non- D0 st at es as a funct ion of t he AUTOC. D10GMP, AUTOC. RATD and
MMNGC. MNG_VETO regist er bit s.
The 82599 can init iat e aut o- negot iat ion wit hout direct driver command in t he following cases:
When t he st at e of MAI N_PWR_OK pin changes.
When t he MNG_VETO bit value changes.
On a t ransit ion from D0a st at e t o a non- D0a st at e, or from a non- D0a st at e t o D0a st at e.
Figure 3.27 shows t he 82599 behavior when ent ering low power mode and Figure 3. 28 shows t he
82599 behavior when going t o power- up mode.
10 None Default
Tabl e 3. 27. Paci ng Speeds at 10 Gb/ s Li nk Speed
Paci ng Speeds ( Gb/ s) Del ay I nser t ed i nt o I PG Regi st er Val ue
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Fi gur e 3.27. MAC Speed Change When Ent er i ng Pow er Dow n Mode
Function switched to Dx(Dr/D3)
OR Function already in Dx and
MNG_VETO bit change OR
MAIN_PWR_OK de-assertion
AN enabled
RATD set
MNG VETO set MAIN_PWR_OK
set
D10GMP set
Restart Backplane AN -
advertise No capability of
Higher rates
Do
nothing
NO
YES
YES YES
NO
NO
Speed @LCD
NO
YES
NO
NO
YES
YES

125
Fi gur e 3. 28. MAC Speed Change on Ent er i ng Pow er - up Mode
Function switched to D0(D0a/D0u)
OR
Function in D0 and VETO bit cleared
AN enabled
Speed is 10G
VETO bit is set
Restart Backplane AN -
advertise all link rate
Do
nothing
NO
YES
Speed changed
due to low power?
NO
YES
NO
NO
YES
YES
Higher HCD is
enabled?
NO
YES
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I ni t i al i zat i on I nt el

127
4. 0 I ni t i al i zat i on
4.1 Pow er Up
4.1.1 Pow er - Up Sequence
Figure 4.1 shows t he 82599 power- up sequence from power ramp up unt il t he 82599 is ready t o accept
host commands.
Fi gur e 4. 1. 82599 Pow er - Up Sequence
Load EEPROM 1: Init Analog parameters, PLL,
Core Rx/Tx, PCIe Lanes & MNG / Wake up En
Load EEPROM 2: MAC, NC-SI,
Configure MNG and Wake up
Manageability & Wakeup Enabled (Dr state)
Load EEPROM 3:
Init PCIe and Configure MAC
MNG/
Wakeup
Ena?
Wait for Core PLL Stable
Yes
No
D0u state
Vcc power on (80%)
Wait for internal Power On Reset De-Assertion
(~35 ms after XTAL stabilizes)
Strapping pins are latched
PCIe Reset
De-Asserted
No
Yes
Wait for PCIe PLL stable
I nt el
82599 10 GbE Cont r ol l er I ni t i al i zat i on

128
4. 1. 2 Pow er - Up Ti mi ng Di agr am
Fi gur e 4.2. Pow er - Up Ti mi ng Di agr am
Tabl e 4.1. Not es f or Pow er - Up Ti mi ng Di agr am
Not e
1 Base 25 clock is st able t
xog
aft er power is st able.
2 I nt ernal Reset is released t
ppg
aft er Base 25 is st able ( also power supplies are good) .
3 NVM read st art s following t he rising edge of t he int ernal Power On Reset or ext ernal LAN Power Good.
4 EEPROM aut o- load 1: EEPROM I nit Sect ion; PCI e Analog; Core Analog.
5 EEPROM aut o- load 1 complet ion t o Core PLL( s) st able t
opll
.
6 EEPROM aut o- load 2: MAC module manageabilit y and wake up ( if manageabilit y / wake up enabled) .
7 APM wake up and/ or manageabilit y act ive, based on NVM cont ent s ( if enabled) .
8 The PCI e reference clock is valid t
PWRGD- CLK
before t he deassert ion of PCI e Reset ( PCI e specificat ion) .
9 PCI e Reset is deassert ed t
PVPGL
aft er power is st able

( PCI e specificat ion) .
10 De- assert ion of PCI e Reset invokes t he EEPROM aut o- load 3.
11 De- assert ion of PCI e Reset t o PCI e PLL st able t
PCI PLL
.
12
EEPROM aut o- load 3: PCI e General Configurat ion; PCI e Configurat ion Space; LAN Core Modules and MAC module if
manageabilit y is not enabled.
13 Link t raining st art s aft er t
pgt rn
from PCI e Reset deassert ion

14 A first PCI e configurat ion access might arrive aft er t
pgcfg

15 A first PCI configurat ion response can be sent aft er t
pgres

16
Set t ing t he Memory Access Enable or Bus Mast er Enable bit s in t he PCI Command regist er t ransit ions t he 82599 from D0u
t o D0 st at e.
D-State D0u
NVM Load
D0a
Core PLL(s) State
PCIe Link up L0
Manageability / Wake
4
Dr
10
3
Power
Power On Reset
(internal)
PCIe reference clock
PERST#
Base 25 MHz
1
t xog
16
t pgres t pgcfg
t PWRGD-CLK
t PVPGL
t ppg
Auto
Read 1
PLL reset PLL Stable
7
6
Auto
Read 2
Auto
Read 3
t ee t ee t ee
PCIe PLL State
11
t pcipll
14 15
8
9
PLL reset PLL Stable
5
t opll
13
12
2
t pgtrn

129
4. 1. 2. 1 Ti mi ng Requi r ement s
The 82599 requires t he following st art - up and power st at e t ransit ions.
Not e: I t is assumed t hat t he ext ernal 25 MHz clock source is st able aft er t he power is applied; t he
t iming for t hat is part of t xog.
4.1.2.2 Ti mi ng Guar ant ees
The 82599 guarant ees t he following st art - up and power st at e t ransit ion relat ed t iming paramet ers.
4.2 Reset Oper at i on
4.2.1 Reset Sour ces
The 82599 reset sources are described in t he sect ions t hat follow:
4.2.1.1 LAN_PWR_GOOD
The 82599 has an int ernal mechanism for sensing t he power pins. Once t he power is up and st able, t he
82599 creat es an int ernal reset , which act s as a mast er reset of t he ent ire chip. I t is level sensit ive, and
while it is 0b, all of t he regist ers are held in reset . LAN_PWR_GOOD is int erpret ed t o be an indicat ion
t hat device power supplies are all st able. LAN_PWR_GOOD changes st at e during syst em power up.
4.2.1.2 PE_RST_N ( PCI e Reset )
The deassert ion of PCI e reset indicat es t hat bot h t he power and t he PCI e clock sources are st able. This
pin assert s an int ernal reset also aft er a D3cold exit . Most unit s are reset on t he rising edge of PCI e
reset . The only except ion is t he PCI e unit , which is kept in reset while PCI e reset is assert ed ( level) .
Tabl e 4. 2. Pow er - Up Ti mi ng Requi r ement s
Par amet er Descr i pt i on Mi n Max . Not es
t
xog
Base 25 MHz clock st able from power st able. 10 ms
t
PWRGD- CLK
PCI e clock valid t o PCI e power good. 100 s - According t o PCI e specificat ion.
t
PVPGL
Power rails st able t o PCI e Reset inact ive. 100 ms - According t o PCI e specificat ion.
t
pgcfg
Ext ernal PCI e Reset signal t o first configurat ion cycle. 100 ms According t o PCI e specificat ion.
Tabl e 4. 3. Pow er - Up Ti mi ng Guar ant ees
t
xog
Xosc st able from power st able. 10 ms
t
ppg
I nt ernal power good delay from valid
power rail.
35 ms
Use int ernal count er for ext ernal devices
st abilizat ion.
t
ee
EEPROM read durat ion. 20 ms
Act ual t ime depends on t he EEPROM
cont ent .
t opll PCI e Reset t o st art of link t raining. 10 ms
t pcipll PCI e Reset t o first configurat ion cycle. 5 ms
t pgt rn PCI e Reset t o st art of link t raining. 20 ms According t o PCI e specificat ion.
t pgres PCI e Reset t o first configurat ion cycle. 100 ms According t o PCI e specificat ion.
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4. 2.1. 3 I n- band PCI e Reset
The 82599 generat es an int ernal reset in response t o a physical layer message from PCI e or when t he
PCI e link goes down ( ent ry t o polling or det ect st at e) . This reset is equivalent t o PCI reset in previous
( PCI ) GbE cont rollers.
4. 2.1. 4 D3hot t o D0 Tr ansi t i on
This is also known as ACPI reset . The 82599 generat es an int ernal reset on t he t ransit ion from D3hot
power st at e t o D0 ( caused aft er configurat ion writ es from D3 t o D0 power st at e) . Not e t hat t his reset is
per funct ion and reset s only t he funct ion t hat t ransit ioned from D3hot t o D0.
4. 2. 1. 5 Funct i on Lev el Reset ( FLR) Capabi l i t y
The FLR bit is required for t he Physical Funct ion ( PF) and per Virt ual Funct ion ( VF) . Set t ing of t his bit for
a VF reset s only t he part of t he logic dedicat ed t o t he specific VF and does not influence t he shared part
of t he port . Set t ing t he PF FLR bit reset s t he ent ire funct ion.
4.2.1. 5.1 FLR i n Non- I OV Mode
A FLR reset t o a funct ion is equivalent t o a D0 > D3 > D0 t ransit ion wit h t he except ion t hat t his reset
doesnt require driver int ervent ion in order t o st op t he mast er t ransact ions of t his funct ion. FLR affect s
t he device 1 parallel clock cycle from FLR assert ion by default set t ing, or any ot her value defined by t he
FLR Delay Disable and FLR Delay fields in t he PCI e I nit Configurat ion 2 Offset 0x02 word in t he
EEPROM.
4.2.1. 5.2 Physi cal Funct i on FLR ( PFLR)
An FLR reset t o t he PF funct ion in an I OV mode is equivalent t o a FLR in non- I OV mode. All VFs in t he
PCI e funct ion of t he PF are affect ed.
The affect ed VFs are not not ified of t he reset in advance. The RSTD bit in t he VFMailbox[ n] is set
following t he reset ( per VF) t o indicat e t o t he VFs t hat a PF FLR t ook place. Each VF is responsible t o
probe t his bit ( such as aft er a t imeout ) .
4.2.1. 5.3 Vi r t ual Funct i on FLR ( VFLR)
A VF operat ing in an I OV mode can issue a FLR. The VFLR reset s t he resources allocat ed t o t he VF ( such
as disabling t he queues and masking int errupt s) . I t also clears t he PCI e configurat ion for t he VF. There
is no impact on ot her VFs or on t he PF.
Tx and Rx flows for t he queues allocat ed t o t his VF are disabled. All pending read request s are dropped
and PCI e read complet ions t o t his funct ion can be complet ed as unsupport ed request s.
Not e: Clearing of t he I OV Enable bit in t he I OV st ruct ure is equivalent t o a VFLR t o all t he VFs in t he
same port .

131
4.2.1.6 Sof t w ar e Reset s
4.2.1.6.1 Sof t w ar e Reset
Soft ware reset is done by writ ing t o t he Device Reset bit of t he Device Cont rol regist er ( CTRL.RST) . The
82599 re- reads t he per- funct ion EEPROM fields aft er a soft ware reset . Bit s t hat are not normally read
from t he EEPROM are reset t o t heir default hardware values.
Not e: This reset is per funct ion and reset s only t he funct ion t hat received t he soft ware reset .
Fields cont rolled by t he LED, SDP and I nit 3 words of t he EEPROM are not reset and not re- read aft er a
soft ware reset .
PCI configurat ion space ( configurat ion and mapping) of t he device is unaffect ed. The MAC might or
might not be reset ( see Sect ion 4. 2. 3) .
Prior t o issuing soft ware reset , t he driver needs t o execut e t he mast er disable algorit hm as defined in
Sect ion 5. 2. 5. 3. 2.
I f DCB is enabled t hen following a soft ware reset t he following st eps must be execut ed t o prevent
pot ent ial races bet ween manageabilit y mapping t o TC before and aft er init ializat ion.
1. Clear t he flow cont rol enablement in t he MAC by clearing MFLCN. RFCE ( or clear t he ent ire regist er) .
2. Soft ware should wait ~ 10 s.
3. Soft ware polls TFCS. TC_XON( 0) = 0b ( in most cases it is expect ed t o be found at zero while max
poll t ime is always short er t han t he max expect ed PAUSE t ime before a soft ware reset is init iat ed) .
4. Soft ware maps t he manageabilit y t ransmit TC ( set t ing t he MNGTXMAP regist er) and t hen maps t he
user priorit y of manageabilit y t raffic t o t he manageabilit y TC ( set t ing t he RTRUP2TC and RTTUP2TC
regist ers) .
5. Soft ware wait s ~ 10 s.
6. Soft ware can re- enable t he flow cont rol as part of t he rest of t he init ializat ion flow.
4. 2.1. 6.2 Physi cal Funct i on ( PF) Sof t w ar e Reset
A soft ware reset by t he PF in I OV mode has t he same consequences as a soft ware reset in non- I OV
mode.
The procedure for a PF soft ware reset is as follows:
The PF driver disables mast er accesses by t he device t hrough t he mast er disable mechanism ( see
Sect ion 5. 2. 5. 3. 2) . Mast er disable affect s all VFs t raffic.
Execut e t he procedure described in Sect ion 4. 2. 2 t o synchronize bet ween t he PF and VFs.
VFs are expect ed t o t imeout and check on t he RSTD bit in order t o ident ify a PF soft ware reset event .
The RSTD bit s are cleared on read.
4.2.1.6.3 VF Sof t w ar e Reset
A soft ware reset applied by a VF is equivalent t o a FLR reset t o t his VF wit h t he except ion t hat t he PCI e
configurat ion bit s allocat ed t o t his funct ion are not reset . I t is act ivat ed by set t ing t he VTCTRL. RST bit .
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132
4.2.1. 6.4 For ce TCO
This reset is generat ed when manageabilit y logic is enabled. I t is only generat ed if enabled by t he Force
TCO Reset bit in t he Common Firmware Paramet ers word in t he EEPROM. I f enabled by t he EEPROM,
firmware t riggers a port reset by set t ing t he CTRL. RST bit . I n pass t hrough mode it is generat ed when
receiving a ForceTCO SMB command wit h bit 0 set .
4. 2.1. 7 Li nk Reset
Also referred t o as MAC reset .
I nit iat ed by writ ing t he Link Reset bit of t he Device Cont rol regist er ( CTRL. LRST) .
A link reset is equivalent t o a soft ware reset + reset of t he MAC. The 82599 re- reads t he per- funct ion
EEPROM fields aft er link reset . Bit s t hat are normally read from t he EEPROM are reset t o t heir default
hardware values. Not e t hat t his reset is per funct ion and reset s only t he funct ion t hat received t he link
reset .
The PF in I OV mode can also generat e a link reset .
Prior t o issuing link reset , t he driver needs t o execut e t he mast er disable algorit hm as defined in
Sect ion 5. 2. 5. 3.2.
4. 2. 2 Reset i n PCI - I OV Env i r onment
Several mechanisms are provided t o synchronize reset procedures bet ween t he PF and t he VFs.
4.2.2. 1 ( RSTI ) / ( RSTD)
This mechanism is provided specifically for a PF soft ware reset but can be used in ot her reset cases.
The procedure is as follows:
One of t he following reset cases t akes place:
LAN Power Good
PCI e Reset ( PERST and in- band)
D3hot - - > D0
FLR
Soft ware reset by t he PF
The 82599 set s t he RSTI bit s in all t he VFMailbox regist ers. Once t he reset complet es, each VF can
read it s VFMailbox regist er t o ident ify a reset in progress.
The VF might poll t he RSTI bit t o det ect if t he PF is in t he process of configuring t he device.
Once t he PF complet es configuring t he device, it set s t he CTRL_EXT. PFRSTD bit . As a result , t he
82599 clears t he RSTI bit s in all t he VFMailbox regist ers and set s t he Reset Done ( RSTD) bit s in all
t he VFMailbox regist ers.
The VF might read t he RSTD bit t o det ect t hat a reset has occurred. The RSTD bit is cleared on
read.

133
4. 2. 2. 2 VF Recei v e Enabl e PFVFRE / VF Tr ansmi t Enabl e PFVFTE
This mechanism insures t hat a VF cannot t ransmit or receive before t he Tx and Rx pat h has been
init ialized by t he PF.
The PFVFRE regist er cont ains a bit per VF. When t he bit is set t o 0b, Rx packet assignment for t he
VFs pool is disabled. When set t o 1b, Rx packet assignment for t he VFs pool is enabled.
The PFVFTE regist er cont ains a bit per VF. When t he bit is set t o 0b, dat a fet ching for t he VFs pool
is disabled. When set t o 1b, dat a fet ching for t he VFs pool is enabled. Descript or fet ching for t he VF
pool is maint ained, up t o t he limit of t he int ernal descript or queues regardless of PFVFTE
set t ings.
The PFVFTE and PFVFRE regist ers are init ialized t o zero ( VF Tx and Rx t raffic gat ed) following a PF
reset . The relevant bit s per VF are also init ialized by a VF soft ware reset or VFLR.
4.2.3 Reset Ef f ect s
Table 4.4 t hrough Table 4.6 list how reset s affect t he following regist ers and logic:
Tabl e 4. 4. Reset Ef f ect s Common Reset s
Reset Act i v at i on
LAN Pow er
Good
PCI e
PERST#
I n- band
PCI e Reset
FW Reset For ce TCO Not es
EEPROM Read See Sect ion 6. 3. 1
LTSSM ( back t o det ect / polling) X X X
PCI e Link Dat a Pat h X X X
PCI Configurat ion Regist ers RO X X X 9
PCI Configurat ion Regist ers RW X X X 9
PCI e Local Regist ers X X X 8
Dat a Pat h X X X X 2
On- die Memories X X X X 7
MAC, PCS, Aut o- Negot iat ion, LinkSec, I Psec X X 6 X 6 X
Wake Up ( PM) Cont ext X 1 3
Wake Up/ Manageabilit y Cont rol/ St at us
Regs
X 4, 5
Manageabilit y Unit X X
LAN Disable St rapping Pins X
All Ot her St rapping Pins X
Tabl e 4. 5. Reset Ef f ect s Per Funct i on Reset s
Reset Act i v at i on D3 or Dr
FLR or
PFLR
SW Reset
Li nk Reset
or Ex i t
f r om LAN
Di sabl e
Not es
EEPROM Read See Sect ion 6. 3. 1
LTSSM ( back t o det ect / polling)
PCI e Link Dat a Pat h
PCI Configurat ion Regist ers RO 9
PCI Configurat ion Regist ers RW X X 9
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134
Not e: VFLR wont clear t he VFMAI LBOX. VFU bit . This bit should be cleared by a direct writ e access
or by set t ing PFMailbox. RVFU bit . Refer t o Sect ion 8. 3. 5. 1. 5 for more det ails.
Not es For Pr ev i ous Tabl es:
1. I f AUX_PWR = 0b t he wake up cont ext is reset ( PME_St at us and PME_En bit s should be 0b at reset if t he 82599 does not
support PME from D3cold) .
2. The following regist er fields do not follow t he previous general rules:
ESDP regist ers- reset on LAN Power Good only.
LED configurat ion regist ers.
The Aux Power Det ect ed bit in t he PCI e Device St at us regist er is reset on LAN Power Good and PCI e Reset only.
FLA reset on LAN Power Good only.
RAH/ RAL[ n, where n> 0] , MTA[ n] , VFTA[ n] , FFMT[ n] , FFVT[ n] , TDBAH/ TDBAL, and RDBAH/ RDVAL regist ers have no
default value. I f t he funct ions associat ed wit h t he regist ers are enabled t hey must be programmed by soft ware. Once
programmed, t heir value is preserved t hrough all reset s as long as power is applied.
St at ist ic regist ers ( physical funct ion)
3. The wake up cont ext is defined in t he PCI Bus Power Management I nt erface Specificat ion ( st icky bit s) . I t includes:
PME_En bit of t he Power Management Cont rol/ St at us Regist er ( PMCSR)
PME_St at us bit of t he Power Management Cont rol/ St at us Regist er ( PMCSR)
Aux_En in t he PCI e regist ers
The device request er I D ( since it is required for t he PM_PME TLP)
The shadow copies of t hese bit s in t he Wakeup Cont rol Regist er are t reat ed ident ically.
4. Refers t o bit s in t he Wake Up Cont rol Regist er t hat are not part of t he Wake- Up Cont ext ( t he PME_En and PME_St at us bit s) .
Not e t hat t he WUFC and WUC regist ers are not part of t he Wake Up Cont ext and are reset as part of t he dat a pat h. I nclude also
t he SW_FW_SYNC and t he FWSM regist ers.
5. The Wake Up St at us Regist ers include t he following:
Wake Up St at us Regist er
Wake Up Packet Lengt h
Wake Up Packet Memory
6. The MAC clust er is reset by t he appropriat e event only if manageabilit y unit is disabled and t he host is in a low power st at e wit h
WoL disabled.
Dat a pat h, Memory Space X X X X 2
On- die Memories X X X 7
MAC, PCS, Aut o- Negot iat ion, LinkSec, I Psec X 6 X 6 X 6 X
Virt ual Funct ion Resources X X X 10
Wake Up ( PM) Cont ext 3
Wake Up/ Manageabilit y Cont rol/ St at us Regs 4, 5
Manageabilit y Unit
St rapping Pins
Tabl e 4.6. Reset Ef f ect s - Vi r t ual Funct i on Reset s
Reset Act i v at i on VFLR VF SW Reset Not es
I nt errupt Regist ers X X 11
Queue Disable X X 12
VF Specific PCI e Configurat ion Space X 13
Dat a Pat h
St at ist ics Regist ers 14
Tabl e 4.5. Reset Ef f ect s Per Funct i on Reset s
Reset Act i v at i on D3 or Dr
FLR or
PFLR
SW Reset
Li nk Reset
or Ex i t
f r om LAN
Di sabl e
Not es

135
7. The cont ent s of t he following memories are cleared t o support t he requirement s of PCI e FLR:
The Tx packet buffers
The Rx packet buffers
I Psec Tx SA t ables
I Psec Rx SA t ables
8. The following regist ers are part of t his group:
SWSM
GCR ( only bit 9 is cleared by t his reset while all ot her fields are cleared at LAN Power Good reset )
GSCL_1/ GSCL_2
GSCN_0/ 1/ 2/ 3
9. St icky bit s and hardware init bit s ( indicat ed as HwI nit ) in t he PCI Configurat ion regist ers are cleared only by LAN Power Good
reset .
10. These regist ers include:
VFEI CS
VFEI MS
VFEI AC
VFEI AM
VFEI TR 0- 2
VTI VAR0
VFI VAR_MI SC
VFPBACL
VFMailbox
VFEI CS
VFEI MS
VFEI MC
VFEI AC
VFEI AM
VFEI CR
EI TR 0- 2
VTI VAR0
VFI VAR_MI SC
VFPBACL
PSRTYPE
VFMailbox
VFMBMEM
Specific VF bit s in t he FVRE and FVTE are cleared as well
MSI / MSI -X enable bit s
BME
Error indicat ions
14. Rx and Tx count ers might miss proper count ing due t o VFLR indicat ing more packet s t han t hose ones act ually t ransferred. I t
could happen if t he VFLR happened aft er count ing occurred but before Tx or Rx were complet ed.
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136
4.3 Queue Di sabl e
See Sect ion 4. 6. 7. 1 for det ails on disabling and enabling an Rx queue.
See Sect ion 4. 6. 8. 1 for det ails on disabling and enabling a Tx queue.
4.4 Funct i on Di sabl e
4. 4. 1 Gener al
For a LAN on Mot herboard ( LOM) design, it might be desirable for t he syst em t o provide BI OS- set up
capabilit y for select ively enabling or disabling LAN funct ions. I t enables t he end- user more cont rol over
syst em resource- management and avoids conflict s wit h add- in NI C solut ions. The 82599 provides
support for select ively enabling or disabling one or bot h LAN device( s) in t he syst em.
4.4.2 Ov er v i ew
Device presence ( or non- presence) must be est ablished early during BI OS execut ion, in order t o ensure
t hat BI OS resource- allocat ion ( of int errupt s, of memory or I O regions) is done according t o devices t hat
are present only. This is frequent ly accomplished using a BI OS Configurat ion Values Driven on Reset
( CVDR) mechanism. The 82599 LAN- disable mechanism is implement ed in order t o be compat ible wit h
such a solut ion.
The 82599 provides t wo mechanisms t o disable each of it s LAN port s:
The LANx_DI S_N pins ( one pin per LAN port ) are sampled on reset t o det ermine t he LAN
enablement .
One of t he LAN port s can be disabled using EEPROM configurat ion.
Disabling a LAN port affect s t he PCI funct ion it resides on. When funct ion 0 is disabled ( eit her LAN0 or
LAN1) , t wo different behaviors are possible:
Dummy funct ion mode I n some syst ems, it is required t o keep all t he funct ions at t heir
respect ive locat ion, even when ot her funct ions are disabled. I n dummy funct ion mode, if funct ion
# 0 ( eit her LAN0 or LAN1) is disabled, t hen it does not disappear from t he PCI e configurat ion space.
Rat her, t he funct ion present s it self as a dummy funct ion. The device I D and class code of t his
funct ion changes t o ot her values ( dummy funct ion device I D 0x10A6 and class code 0xFF0000) . I n
addit ion, t he funct ion does not require any memory or I / O space, and does not require an int errupt
line.
Legacy mode When funct ion 0 is disabled ( eit her LAN0 or LAN1) , t hen t he port residing on
funct ion 1 moves t o reside on funct ion 0. Funct ion 1 disappears from t he PCI configurat ion space.
Mapping bet ween funct ion and LAN port s is list ed in t he following t ables.
Tabl e 4.7. PCI Funct i ons Mappi ng ( Legacy Mode)
PCI Funct i on # LAN Funct i on Sel ect Funct i on 0 Funct i on 1
Bot h LAN funct ions are enabled.
0 LAN 0 LAN 1
1 LAN 1 LAN 0
LAN 0 is disabled. x LAN1 Disable
LAN 1 is disabled. x LAN 0 Disable
Bot h LAN funct ions are disabled. Bot h PCI funct ions are disabled. Device is in low power mode.

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The following rules apply t o funct ion disable:
When funct ion 0 is disabled in legacy mode, t he LAN port associat ed originally wit h funct ion 1
appears in funct ion 0. Funct ion 1 disappears from t he PCI configurat ion space.
When funct ion 0 is disabled in dummy funct ion mode, it is convert ed int o a dummy PCI funct ion.
Funct ion 1 is not affect ed.
When funct ion 1 is disabled, it disappears from t he PCI configurat ion space.
The disabled LAN port is st ill available for manageabilit y purposes if disabled t hrough t he EEPROM
mechanism. The disabled LAN port is not available for manageabilit y purposes if disabled t hrough
t he pin mechanism.
Dummy funct ion mode should not be used in PCI I OV mode ( since PF0 is required t o support
cert ain funct ionalit y)
The following EEPROM bit s cont rol funct ion disable:
One PCI funct ion can be enabled or disabled according t o t he EEPROM LAN PCI Disable bit .
The LAN Disable Select EEPROM field indicat es which funct ion is disabled.
The LAN Funct ion Select EEPROM bit defines t he correspondence bet ween LAN Port and PCI
funct ion
The Dummy Funct ion Enable EEPROM bit enables t he dummy funct ion mode. Default value is
disabled.
Tabl e 4. 8. PCI Funct i ons Mappi ng ( Dummy Funct i on Mode)
PCI Funct i on # LAN Funct i on Sel ect Funct i on 0 Funct i on 1
Bot h LAN funct ions are enabled.
0 LAN 0 LAN 1
1 LAN 1 LAN 0
LAN 0 is disabled.
0 Dummy LAN1
1 LAN 1 Disable
LAN 1 is disabled.
0 LAN 0 Disable
1 Dummy LAN 0
Bot h LAN funct ions are disabled. Bot h PCI funct ions are disabled. Device is in low power mode.
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4.4.3 Cont r ol Opt i ons
The funct ions have a separat e enabling mechanism. Any funct ion t hat is not enabled does not funct ion
and does not expose it s PCI configurat ion regist ers.
LAN0 or LAN 1 can be disabled in t he EEPROM by set t ing t he LAN PCI Disable bit in t he PCI e Cont rol 2
word at offset 0x05. The LAN Disable Select bit in t he same word in t he EEPROM select s which LAN is
disabled. Furt hermore, if t he LAN port at funct ion 0 is disabled, t he Dummy Funct ion Enable bit in t he
same word chooses bet ween filling t he disabled funct ion by a dummy funct ion, or moving t he ot her LAN
port t o funct ion 0.
Not e: Mapping LAN0 and LAN1 t o PCI funct ion 0 and PCI funct ion 1 is cont rolled by t he EEPROM
LAN Funct ion Select bit in t he PCI e Cont rol 2 word at offset 0x05.
LAN0 and LAN 1 can be disabled on t he board level by driving t he LAN0_Dis_N and LAN1_Dis_N pins t o
low. These I / O pins have int ernal weak pullup resist ors so leaving t hem unconnect ed or driving t hem
t o high enables t he respect ive LAN port . These pins are st rapping opt ions, sampled at LAN Power Good,
PCI e reset or in- band PCI e reset .
4. 4. 4 Ev ent Fl ow f or Enabl e/ Di sabl e Funct i ons
This sect ion describes t he driving levels and event sequence for device funct ionalit y. Following a Power
on Reset / LAN Power Good/ PCI e Reset / I n- Band Reset , t he LANx_DI S_N signals should be driven high
( or left open) for normal operat ion. I f any of t he LAN funct ions are not required st at ically, it s associat ed
disable st rapping pin can be t ied st at ically t o low.
4. 4. 4. 1 BI OS Di sabl e t he LAN Funct i on at Boot Ti me by Usi ng St r appi ng Opt i on
Assume t hat following a power up sequence LANx_DI S_N signals are driven high.
1. PCI e is est ablished following PCI e reset .
2. BI OS recognizes t hat a LAN funct ion in t he 82599 should be disabled.
3. The BI OS drives t he LANx_DI S_N signal t o t he low level.
4. BI OS issues PCI e reset or an in- band PCI e reset .
5. As a result , t he 82599 samples t he LANx_DI S_N signals and disables t he LAN funct ion and issues
an int ernal reset t o t his funct ion.
6. BI OS might st art wit h t he device enumerat ion procedure ( t he disabled LAN funct ion is invisible
changed t o dummy funct ion) .
7. Proceed wit h normal operat ion.
8. Re- enable could be done by driving t he LANx_DI S_N signal high and t hen request ing t he user t o
issue a warm boot t o init ialize new bus enumerat ion.
4. 4.4. 2 Mul t i - Funct i on Adv er t i sement
I f one of t he LAN devices is disabled and funct ion 0 is t he only act ive funct ion, t he 82599 is no longer a
mult i- funct ion device. The 82599 normally report s a 0x80 in t he PCI configurat ion header, indicat ing
mult i- funct ion capabilit y. However, if a LAN is disabled and only funct ion 0 is act ive, t he 82599 report s
a 0x0 in t his field t o signify single- funct ion capabilit y.

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4. 4. 4. 3 I nt er r upt Ut i l i zat i on
When bot h LAN devices are enabled, t he 82599 uses t he PCI legacy int errupt s of bot h port s for
int errupt report ing. The EEPROM configurat ion cont rols t he I nt errupt Pin field of t he PCI configurat ion
header t o be advert ised for each LAN device t o comply wit h PCI specificat ion requirement s.
However, if eit her LAN device is disabled, t hen t he legacy PCI int errupt of port A must be used for t he
remaining LAN device, t herefore t he EEPROM configurat ion must be set accordingly. Under t hese
circumst ances, t he I nt errupt Pin field of t he PCI configurat ion header always report s a value of 0x1,
indicat ing I NTA# pin usage, which means legacy PCI int errupt of port A is used.
4.4.4.4 Pow er Repor t i ng
When bot h LAN devices are enabled, t he PCI Power Management regist er block has t he capabilit y of
report ing a common power value. The common power value is reflect ed in t he Dat a field of t he PCI
Power Management regist ers. The value report ed as common power is specified via an EEPROM field,
and is reflect ed in t he Dat a field each t ime t he Dat a_Select field has a value of 0x8 ( 0x8 = common
power value select ) .
When only one LAN port is enabled and t he 82599 appears as a single- funct ion device, t he common
power value, if select ed, report s 0x0 ( undefined value) , as common power is undefined for a single-
funct ion device.
4.5 Devi ce Di sabl e
4.5.1 Ov er v i ew
When bot h LAN port s are disabled following a Power on Reset / LAN Power Good/ PCI e Reset / I n- Band
Reset , t he LANx_DI S_N signals should be t ied st at ically t o low. I n t his st at e t he device is disabled, LAN
port s are powered down, all int ernal clocks are shut , and t he PCI e connect ion is powered down ( similar
t o L2 st at e) .
4. 5. 2 BI OS Di sabl e of t he Dev i ce at Boot Ti me by Usi ng t he St r appi ng
Opt i on
Assume t hat following power- up sequence LANx_DI S_N signals are driven high:
1. PCI e is est ablished following PCI e reset .
2. BI OS recognizes t hat t he 82599 should be disabled.
3. The BI OS drives t he LANx_DI S_N signals t o t he low level.
4. BI OS issues PCI e reset or an in- band PCI e reset .
5. As a result , t he 82599 samples t he LANx_DI S_N signals and disables t he LAN port s and t he PCI e
connect ion.
6. Re- enable can be done by driving at least one of t he LANx_DI S_N signals high and t hen issuing a
PCI e reset t o rest art t he device.
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4.6 Sof t w ar e I ni t i al i zat i on and Di agnost i cs
4.6.1 I nt r oduct i on
This sect ion discusses general soft ware not es for t he 82599, especially init ializat ion st eps. This
includes:
General hardware power- up st at e
Basic device configurat ion
I nit ializat ion of t ransmit
Receive operat ion
Link configurat ion
Soft ware reset capabilit y
St at ist ics
Diagnost ic hint s
4. 6. 2 Pow er - Up St at e
When t he 82599 powers up, it aut omat ically reads t he EEPROM. The EEPROM cont ains sufficient
informat ion t o bring t he link up and configure t he 82599 for manageabilit y and/ or APM wakeup.
However, soft ware init ializat ion is required for normal operat ion.
4. 6. 3 I ni t i al i zat i on Sequence
The following sequence of commands is t ypically issued t o t he device by t he soft ware device driver in
order t o init ialize t he 82599 for normal operat ion. The maj or init ializat ion st eps are:
1. Disable int errupt s.
2. I ssue global reset and perform general configurat ion ( see Sect ion 4. 6. 3.2) .
3. Wait for EEPROM aut o read complet ion.
4. Wait for DMA init ializat ion done ( RDRXCTL. DMAI DONE) .
5. Set up t he PHY and t he link ( see Sect ion 4. 6. 4) .
6. I nit ialize all st at ist ical count ers ( see Sect ion 4. 6. 5) .
7. I nit ialize receive ( see Sect ion 4. 6. 7) .
8. I nit ialize t ransmit ( see Sect ion 4. 6. 8) .
9. Enable int errupt s ( see Sect ion 4.6. 3. 1) .
4. 6. 3. 1 I nt er r upt s Dur i ng I ni t i al i zat i on
Most drivers disable int errupt s during init ializat ion t o prevent re- ent rance. I nt errupt s are disabled by
writ ing t o t he EI MC regist ers. Not e t hat t he int errupt s also need t o be disabled aft er issuing a global
reset , so a t ypical driver init ializat ion flow is:
1. Disable int errupt s.
2. I ssue a global reset .
3. Disable int errupt s ( again) .
Aft er init ializat ion complet es, a t ypical driver enables t he desired int errupt s by writ ing t o t he I MS
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4. 6. 3. 2 Gl obal Reset and Gener al Conf i gur at i on
Not e: Global Reset = soft ware reset + link reset .
Device init ializat ion t ypically st art s wit h a soft ware reset t hat put s t he device int o a known st at e and
enables t he device driver t o cont inue t he init ializat ion sequence. Following a Global Reset t he Soft ware
driver should wait at least 10msec t o enable smoot h init ializat ion flow.
To enable flow cont rol, program t he FCTTV, FCRTL, FCRTH, FCRTV and FCCFG regist ers. I f flow cont rol is
not enabled, t hese regist ers should be writ t en wit h 0x0. I f Tx flow cont rol is enabled t hen Tx CRC by
hardware should be enabled as well ( HLREG0.TXCRCEN = 1b) . Refer t o Sect ion 3. 7. 7. 3. 2 t hrough
Sect ion 3. 7. 7. 3. 5 for t he recommended set t ing of t he Rx packet buffer sizes and flow cont rol
t hresholds. Not e t hat if flow cont rol is not enabled but Tx swit ching is enabled, t he FCRTH[ n] . RTH fields
must be set as if flow cont rol is enabled. The FCRTH[ n] . FCEN bit should be set t o 0b as all t he ot her
regist ers previously indicat ed.
The link int erconnect configurat ion according t o t he elect rical specificat ion of t he relevant elect rical
int erface should be set prior t o t he link set up. This configurat ion is done t hrough t he EEPROM by
applying t he appropriat e set t ings t o t he link int erconnect block.
4.6.4 100 Mb/ s, 1 GbE, and 10 GbE Li nk I ni t i al i zat i on
4. 6. 4. 1 BX/ SGMI I Li nk Set up Fl ow
1. BX link elect rical set up is done according t o EEPROM configurat ion t o set t he analog int erface t o t he
appropriat e set t ing.
2. Configure t he Link Mode Select field in t he AUTOC regist er t o t he appropriat e operat ing mode.
3. Configure any int erface fields in t he SERDESC regist er if necessary.
4. Rest art t he link using t he Rest art Aut o Negot iat ion field in t he AUTOC regist er.
5. Verify correct link st at us ( sync, link_up, speed) using t he LI NKS regist er.
4.6.4.2 XAUI / BX4 / CX4 / SFI Li nk Set up Fl ow
1. XAUI / BX4 / CX4 / SFI link elect rical set up is done according t o EEPROM configurat ion t o set t he
analog int erface t o t he appropriat e set t ing.
2. Configure t he Link Mode Select field in t he AUTOC regist er, AUTOC. 10G_PARALLEL_PMA_PMD and
AUTOC2. 10G_PMA_PMD_Serial t o t he appropriat e operat ing mode.
5. Verify correct link st at us ( align, link_up, speed) using t he LI NKS regist er.
4. 6. 4. 3 KX / KX4 / KR Li nk Set up Fl ow Wi t hout Aut o- Negot i at i on
1. KX / KX4 / KR link elect rical set up is done according t o EEPROM configurat ion t o set t he analog
int erface t o t he appropriat e set t ing.
5. Verify correct link st at us ( sync, align, link_up, speed) using t he LI NKS regist er.
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4. 6.4. 4 KX / KX4 / KR Li nk Set up Fl ow Wi t h Aut o- Negot i at i on
1. KX / KX4 / KR link elect rical set up is done according t o EEPROM configurat ion t o set t he analog
int erface t o t he appropriat e set t ing.
4. Configure t he KX_Support field and any ot her aut o- negot iat ion relat ed fields in t he AUTOC regist er.
6. Verify correct link st at us ( sync, align, link_up, speed) using t he LI NKS regist er.
4. 6. 5 I ni t i al i zat i on of St at i st i cs
St at ist ics regist ers are hardware- init ialized t o values as det ailed in each part icular regist er' s
descript ion. The init ializat ion of t hese regist ers begins upon t ransit ion t o D0 act ive power st at e ( when
int ernal regist ers become accessible, as enabled by set t ing t he Memory Access Enable field of t he PCI e
Command regist er) , and is guarant eed t o be complet ed wit hin 1 ms of t his t ransit ion. Not e t hat access
t o st at ist ics regist ers prior t o t his int erval might ret urn indet erminat e values.
All of t he st at ist ical count ers are cleared on read and a t ypical device driver reads t hem ( t hus making
t hem zero) as a part of t he init ializat ion sequence.
Queue count ers are mapped using t he RQSMR regist ers for Rx queues, and TQSM regist ers for Tx
queues. Refer t o Sect ion 8. 2. 3.23. 71 for RQSMR set up, and Sect ion 8. 2. 3. 23. 73 for TQSM set up. Not e
t hat if soft ware requires t he queue count ers, t he RQSMR and TQSM regist ers must be re- programmed
following a device reset .
4.6.6 I nt er r upt I ni t i al i zat i on
Oper at i ng w i t h Legacy or MSI I nt er r upt s:
The soft ware driver associat es bet ween Tx and Rx int errupt causes and t he EI CR regist er by set t ing
t he I VAR[ n] regist ers.
Program SRRCTL[ n] . RDMTS ( per receive queue) if soft ware uses t he receive descript or minimum
t hreshold int errupt .
All int errupt s should be set t o 0b ( no aut o clear in t he EI AC regist er) . Following an int errupt ,
soft ware might read t he EI CR regist er t o check for t he int errupt causes.
Set t he aut o mask in t he EI AM regist er according t o t he preferred mode of operat ion.
Set t he int errupt t hrot t ling in EI TR[ n] and GPI E according t o t he preferred mode of operat ion.
Soft ware enables t he required int errupt causes by set t ing t he EI MS regist er.
Oper at i ng w i t h MSI - X:
The operat ing syst em / BI OS set s t he hardware t o MSI -X mode and programs t he MSI -X t able as
part of t he device enumerat ion procedure.
The soft ware driver associat es bet ween int errupt causes and MSI -X vect ors and t he t hrot t ling
t imers EI TR[ n] by programming t he I VAR[ n] and I VAR_MI SC regist ers.
Program SRRCTL[ n] . RDMTS ( per receive queue) if soft ware uses t he receive descript or minimum
t hreshold int errupt .
The EI AC[ n] regist ers should be set t o aut o clear for t ransmit and receive int errupt causes ( for best
performance) . The EI AC bit s t hat cont rol t he ot her and TCP t imer int errupt causes should be set t o
0b ( no aut o clear) .

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Set t he aut o mask in t he EI AM and EI AM[ n] regist ers according t o t he preferred mode of operat ion.
Set t he int errupt t hrot t ling in EI TR[ n] and GPI E according t o t he preferred mode of operat ion.
Soft ware enables t he required int errupt causes by set t ing t he EI MS[ n] regist ers.
4.6.7 Recei ve I ni t i al i zat i on
I nit ialize t he following regist er t ables before receive and t ransmit is enabled:
Receive Address ( RAL[ n] and RAH[ n] ) for used addresses.
Receive Address High ( RAH[ n] .VAL = 0b) for unused addresses.
Unicast Table Array ( PFUTA) .
VLAN Filt er Table Array ( VFTA[ n] ) .
VLAN Pool Filt er ( PFVLVF[ n] ) .
MAC Pool Select Array ( MPSAR[ n] ) .
VLAN Pool Filt er Bit map ( PFVLVFB[ n] ) .
Program t he Receive Address regist er( s) ( RAL[ n] , RAH[ n] ) per t he st at ion address. This can come from
t he EEPROM or from any ot her means ( for example, it could be st ored anywhere in t he EEPROM or even
in t he plat form PROM for LOM design) .
Set up t he Mult icast Table Array ( MTA) regist ers. This ent ire t able should be zeroed and only t he desired
mult icast addresses should be permit t ed ( by writ ing 0x1 t o t he corresponding bit locat ion) . Set t he
MCSTCTRL. MFE bit if mult icast filt ering is required.
Set up t he VLAN Filt er Table Array ( VFTA) if VLAN support is required. This ent ire t able should be zeroed
and only t he desired VLAN addresses should be permit t ed ( by writ ing 0x1 t o t he corresponding bit
locat ion) . Set t he VLNCTRL. VFE bit if VLAN filt ering is required.
I nit ialize t he flexible filt ers 05 Flexible Host Filt er Table regist ers ( FHFT) .
Aft er all memories in t he filt er unit s previously indicat ed are init ialized, enable ECC report ing by set t ing
t he RXFECCERR0. ECCFLT_EN bit .
Program t he different Rx filt ers and Rx offloads via regist ers FCTRL, VLNCTRL, MCSTCTRL, RXCSUM,
RQTC, RFCTL, MPSAR, RSSRK, RETA, SAQF, DAQF, SDPQF, FTQF, SYNQF, ETQF, ETQS, RDRXCTL,
RSCDBU.
Not e t hat RDRXCTL.CRCSt rip and HLREG0. RXCRCSTRP must be set t o t he same value. At t he same
t ime t he RDRXCTL. RSCFRSTSI ZE should be set t o 0x0 as opposed t o it s hardware default .
Program RXPBSI ZE, MRQC, PFQDE, RTRUP2TC, MFLCN.RPFCE, and MFLCN. RFCE according t o t he DCB
and virt ualizat ion modes ( see Sect ion 4. 6. 11.3) .
Enable j umbo recept ion by set t ing HLREG0. JUMBOEN in one of t he following t wo cases:
1. Jumbo packet s are expect ed. Set t he MAXFRS.MFS t o expect ed max packet size.
2. LinkSec encapsulat ion is expect ed.
I n t hese cases set t he MAXFRS. MFS bit in t he Max Frame Size regist er t o t he expect ed maximum
packet size plus 32 byt es for t he LinkSec encapsulat ion. Refer t o Sect ion 8. 2. 3. 22. 13 for det ails about
t he correct handling of VLAN and double VLAN headers.
Enable receive coalescing if required as described in Sect ion 4. 6. 7. 2.
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The f ol l ow i ng shoul d be done per each r ecei v e queue:
1. Allocat e a region of memory for t he receive descript or list .
2. Receive buffers of appropriat e size should be allocat ed and point ers t o t hese buffers should be
st ored in t he descript or ring.
3. Program t he descript or base address wit h t he address of t he region ( regist ers RDBAL, RDBAL) .
4. Set t he lengt h regist er t o t he size of t he descript or ring ( regist er RDLEN) .
5. Program SRRCTL associat ed wit h t his queue according t o t he size of t he buffers and t he required
header cont rol.
6. I f header split is required for t his queue, program t he appropriat e PSRTYPE for t he appropriat e
headers.
7. Program RSC mode for t he queue via t he RSCCTL regist er.
8. Program RXDCTL wit h appropriat e values including t he queue Enable bit . Not e t hat packet s direct ed
t o a disabled queue are dropped.
9. Poll t he RXDCTL regist er unt il t he Enable bit is set . The t ail should not be bumped before t his bit
was read as 1b.
10. Bump t he t ail point er ( RDT) t o enable descript ors fet ching by set t ing it t o t he ring lengt h minus
one.
11. Enable t he receive pat h by set t ing RXCTRL. RXEN. This should be done only aft er all ot her set t ings
are done following t he st eps below.
Halt t he receive dat a pat h by set t ing SECRXCTRL. RX_DI S bit .
Wait for t he dat a pat hs t o be empt ied by HW. Poll t he SECRXSTAT. SECRX_RDY bit unt il it is
assert ed by HW.
Set RXCTRL. RXEN
Clear t he SECRXCTRL. SECRX_DI S bit s t o enable receive dat a pat h
I f soft ware uses t he receive descript or minimum t hreshold I nt errupt , t hat value should be set .
4. 6. 7. 1 Dy nami c Enabl i ng and Di sabl i ng of Recei v e Queues
Receive queues can be enabled or disabled dynamically using t he following procedure.
4.6.7. 1.1 Enabl i ng
Follow t he per queue init ializat ion described in t he previous sect ion.
4.6.7. 1.2 Di sabl i ng
Disable t he rout ing of packet s t o t his queue by re- configuring t he Rx filt ers. I n order t o ensure t hat
t he receive packet buffer does not cont ain any packet s t o t he specific queue it is required t o follow
t he Flushing t he Packet Buffers procedure described lat er in t his sect ion.
I f RSC is enabled on t he specific queue and VLAN st rip is enabled as well t hen wait 2 I TR expirat ion
t ime ( ensure all open RSC are complet ed) .
Disable t he queue by clearing t he RXDCTL. ENABLE bit . The 82599 st ops fet ching and writ ing back
descript ors from t his queue. Any furt her packet t hat is direct ed t o t his queue is dropped. I f a packet
is being processed, t he 82599 complet es t he current buffer writ e. I f t he packet spreads over more
t han one dat a buffer, all subsequent buffers are not writ t en.
The 82599 clears t he RXDCTL. ENABLE bit only aft er all pending memory accesses t o t he descript or
ring are done. The driver should poll t his bit before releasing t he memory allocat ed t o t his queue.
Once t he RXDCTL. ENABLE bit is cleared t he driver should wait addit ional amount of t ime
( ~ 100 s) before releasing t he memory allocat ed t o t his queue.

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Soft ware might reconfigure t he Rx filt ers back t o t he original set t ing. The Rx pat h can be disabled only
aft er all t he receive queues are disabled.
4.6.7.1.3 Fl ushi ng t he Pack et Buf f er s
Because t here could be addit ional packet s in t he receive packet buffer t arget ed t o t he disabled queue
and t he arbit rat ion could be such t hat it would t ake a long t ime t o drain t hese packet s, if soft ware re-
enables a queue before all packet s t o t hat queue were drained, t he enabled queue could pot ent ially get
packet s direct ed t o t he old configurat ion of t he queue. For example, a Virt ual Machine ( VM) goes down
and a different VM get s t he queue.
The 82599 provides a mechanism for soft ware t o ident ify when t he packet buffers were drained of such
st ale packet s. The read- only RXMEMWRAP regist er cont ains a set of count ers ( one per packet buffer)
t hat increment s each t ime a buffer is overt aken by t he t ail point er. Soft ware must read a count er
repeat edly unt il it s count is increment ed at least by t wo, t o insure t hat t he buffer made at least one
complet e wrap- around. Soft ware should also check t he Empt y bit for t he count er. I f t he bit is set , t he
buffer is empt y and t here is no furt her need t o sample t he buffer count er.
4.6.7.2 RSC Enabl ement
RSC enablement as well as RSC paramet er set t ings are assumed as st at ic. I t should be enabled prior t o
recept ion and can be disabled only aft er t he relevant Rx queue( s) are disabled.
4.6.7.2.1 Gl obal Set t i ng
I n SR- I OV mode RSC must be disabled globally by set t ing t he RFCTL. RSC_DI S bit . I n t his case t he
following st eps in t his sect ion are not required.
Enable global CRC st ripping via HLREG0 ( hardware default set t ing)
Soft ware should set t he RDRXCTL. RSCACKC bit t hat forces RSC complet ion on any change of t he
ACK bit in t he Rx packet relat ive t o t he RSC cont ext .
The SRRCTL[ n] . BSI ZEHEADER ( header buffer size) must be larger t han t he packet header ( even if
header split is not enabled) . A minimum size of 128 byt es for t he header buffer addresses t his
requirement .
NFS packet handling:
NFS header filt ering should be disabled if NFS packet s coalescing are required ( at t he TCP
layer) . The RFCTL. NFSW_DI S and RFCTL. NFSR_DI S bit s should be set t o 1b. Furt hermore, t he
PSR_t ype1 bit in t he PSRTYPE[ n] regist ers ( header split on NFS) must be t urned off in all
queues.
Bot h RFCTL. NFSW_DI S and RFCTL. NFSR_DI S bit s should be cleared t o 0b if NFS coalescing is
not required. The PSR_t ype1 can be set per queue according t o t he required header split .
4. 6.7. 2.2 Per Queue Set t i ng
Enable RSC and configure t he maximum allowed descript ors per RSC by set t ing t he MAXDESC and
RSCEN fields in t he RSCCTL[ n] .
Use non- legacy descript or t ype by set t ing SRRCTL[ n] . DESCTYPE t o non- zero values.
TCP header recognit ion t he PSR_t ype4 in t he PSRTYPE[ n] regist ers should be set .
I nt errupt set t ing:
I nt errupt moderat ion must be enabled by set t ing EI TR[ n] . I TR I nt erval t o a value great er t han
zero. Not e t hat t he I TR I nt erval must be larger t han t he RSC Delay. Also, if t he CNT_WDI S bit is
cleared ( writ e enable) , t hen t he I TR count er should be set t o zero.
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The RSC Delay field in t he GPI E regist er should be set t o t he expect ed syst em lat ency
descript or writ e- back cycles. 4 t o 8 s should be sufficient in most cases. I f soft ware encount ers
many inst ances t hat RSC did not complet e as expect ed following EI TR int errupt assert ion, RSC
Delay might need t o be increased.
Map t he relevant Rx queues t o an int errupt by set t ing t he relevant I VAR regist ers.
4. 6. 8 Tr ansmi t I ni t i al i zat i on
Program t he HLREG0 regist er according t o t he required MAC behavior.
Program TCP segment at ion paramet ers via regist ers DMATXCTL ( while maint aining TE bit cleared) ,
DTXTCPFLGL, and DTXTCPFLGH; and DCA paramet ers via DCA_TXCTRL.
Set RTTDCS.ARBDI S t o 1b.
Program DTXMXSZRQ, TXPBSI ZE, TXPBTHRESH, MTQC, and MNGTXMAP, according t o t he DCB
and virt ualizat ion modes ( see Sect ion 4. 6. 11. 3) .
Clear RTTDCS. ARBDI S t o 0b.
The f ol l ow i ng st eps shoul d be done once per t r ansmi t queue:
1. Allocat e a region of memory for t he t ransmit descript or list .
2. Program t he descript or base address wit h t he address of t he region ( TDBAL, TDBAH) .
3. Set t he lengt h regist er t o t he size of t he descript or ring ( TDLEN) .
4. Program t he TXDCTL regist er wit h t he desired TX descript or writ e back policy ( see
Sect ion 8. 2. 3. 9.10for recommended values) .
5. I f needed, set TDWBAL/ TWDBAH t o enable head writ e back.
6. Enable t ransmit pat h by set t ing DMATXCTL.TE. This st ep should be execut ed only for t he first
enabled t ransmit queue and does not need t o be repeat ed for any following queues.
7. Enable t he queue using TXDCTL. ENABLE. Poll t he TXDCTL regist er unt il t he Enable bit is set .
Not e: The t ail regist er of t he queue ( TDT) should not be bumped unt il t he queue is enabled.
4. 6. 8. 1 Dy nami c Enabl i ng and Di sabl i ng of Tr ansmi t Queues
Transmit queues can be enabled or disabled dynamically if t he following procedure is followed.
4.6.8. 1.1 Enabl i ng
Follow t he per queue init ializat ion described in t he previous sect ion.
4.6.8. 1.2 Di sabl i ng
1. St op st oring packet s for t ransmission in t his queue.
2. The complet ion of t he last t ransmit descript or must be visible t o soft ware in order t o guarant ee t hat
packet s are not lost in st ep 5. Therefore, it s RS bit must be set or WTHRESH must be great er t han
zero. I f none of t hese condit ions are met , soft ware should add a null Tx dat a descript or wit h an
act ive RS bit .
3. Wait unt il t he soft ware head of t he queue ( TDH) equals t he soft ware t ail ( TDT) , indicat ing t he
queue is empt y.
4. Wait unt il all descript ors are writ t en back ( polling DD bit in ring or polling t he Head_WB cont ent ) . I t
might be required t o flush t he t ransmit queue by set t ing TXDCTL[ n] . SWFLSH if t he RS bit in t he last
fet ched descript or is not set or if WTHRESH is great er t han zero.
5. Disable t he queue by clearing TXDCTL. ENABLE.

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6. Any packet s wait ing for t ransmission in t he packet buffer would st ill be sent at a lat er t ime.
The t ransmit pat h can be disabled only aft er all t ransmit queues are disabled.
4. 6. 9 FCoE I ni t i al i zat i on Fl ow
Ordering bet ween t he following st eps is not crit ical as long as it is done before t ransmit and receive
st art s.
The FCoE DDP cont ext t able should be init ialized clearing t he FCBUFF. Valid and FCFLT.Valid bit s of
all cont ext s.
EType Queue Filt er ETQF[ n] : Select a filt er by set t ing t he FCoE bit . The EType field should be set
t o 0x8906 ( FCoE Et hernet Type) . UP Enable and UP should be programmed if VLAN priorit y filt ering
is required. I f FCoE t raffic is expect ed on mult iple VLAN priorit ies t hen mult iple ETQF filt ers might
be required.
EType Queue Select ETQS[ n] : Each ETQF filt er is associat ed t o a queue select regist er. The ETQS
regist ers can be used t o direct t he FCoE t raffic t o specific receive queues. Up t o one queue per
Traffic Class ( TC) as programmed in t he ETQF.
Mult iple receive queues can be enabled by set t ing FCRECTL. ENA and programming t he FCRETA[ n]
regist ers.
Low Lat ency I nt errupt s ( LLI ) for crit ical FCoE frames can be enabled by set t ing t he
FCRXCTRL. FCOELLI bit .
Set t he RDRXCTL. FCOE_WRFI X bit t hat forces a DDP writ e exchange cont ext closure aft er receiving
t he last packet in a sequence wit h an act ive Sequence I nit iat ive bit in t he F_CTL field.
Follow t he rules indicat ed in Sect ion 7. 13. 2. 1 and Sect ion 7. 13. 3. 1 for Tx and Rx cross funct ionalit y
requirement s. These sect ions include requirement s on Et hernet CRC and padding handling, LinkSec
offload, Legacy Rx buffers, and more.
4. 6. 10 Vi r t ual i zat i on I ni t i al i zat i on Fl ow
4.6.10.1 VMDq Mode
4.6.10.1.1 Gl obal Fi l t er i ng and Of f l oad Capabi l i t i es
Select one of t he VMDQ pooling met hods MAC/ VLAN filt ering for pool select ion and eit her DCB or
RSS for t he queue in pool select ion. MRQC. Mult iple Receive Queues Enable = 1000b, 1010b, 1011b,
1100b, or 1101b.
DCB should be init iat ed as described in Sect ion 4. 6. 11. I n RSS mode, t he RSS key ( RSSRK) and
redirect ion t able ( RETA) should be programmed. Not e t hat t he redirect ion t able is common t o all
t he pools and only indicat es t he queue inside t he pool t o use once t he pool is chosen. Each pool can
decide if it uses DCB.
Configure PFVTCTL t o define t he default pool.
Enable replicat ion via PFVTCTL. Rpl_En.
I f needed, enable padding of small packet s via HLREG0. TXPADEN.
The MPSAR regist ers are used t o associat e Et hernet MAC addresses t o pools. Using t he MPSAR
regist ers, soft ware must reprogram RAL[ 0] and RAH[ 0] by t heir values ( soft ware could read t hese
regist ers and t hen writ e t hem back wit h t he same cont ent ) .
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4.6.10.1.2 Mi r r or i ng Rul es
For each mirroring rule t o be act ivat ed:
Set t he t ype of t raffic t o be mirrored in t he PFMRCTL[ n] regist er.
Set t he mirror pool in PFMRCTL[ n] . MP.
For pool mirroring, set t he PFMRVM[ n] regist er wit h t he pools t o be mirrored.
For VLAN mirroring, set PFMRVLAN[ n] wit h t he indexes from t he PFVLVF regist ers of t he VLANs t o
be mirrored.
4.6.10.1.3 Secur i t y Feat ur es
For each pool, t he driver might act ivat e t he MAC and VLAN ant i- spoof feat ures via t he relevant bit in
PFVFSPOOF.MACAS and PFVFSPOOF. VLANAS, respect ively.
4.6.10.1.4 Per Pool Set t i ngs
As soon as a pool of queues is associat ed t o a VM, soft ware should set t he following paramet ers:
Associat e t he unicast Et hernet MAC address of t he VM by enabling t he pool in t he MPSAR regist ers.
I f all t he Et hernet MAC addresses are used, t he Unicast Hash Table ( PFUTA) can be used. Pools
servicing VMs whose address is in t he hash t able should be declared as so by set t ing
PFVML2FLT.ROPE. Packet s received according t o t his met hod didnt pass perfect filt ering and are
indicat ed as such.
Enable t he pool in all t he RAH/ RAL regist ers represent ing t he mult icast Et hernet MAC addresses t his
VM belongs t o.
I f all t he Et hernet MAC addresses are used, t he Mult icast Hash Table ( MTA) can be used. Pools
servicing VMs using mult icast addresses in t he hash t able should be declared as so by set t ing
PFVML2FLT.ROMPE. Packet s received according t o t his met hod didnt pass perfect filt ering and are
indicat ed as such.
Define whet her t his VM should get all mult icast / broadcast packet s in t he same VLAN via
PFVML2FLT.MPE and PFVML2FLT. BAM, and whet her it should accept unt agged packet s via
PFVML2FLT.AUPE.
Enable t he pool in each PFVLVF and PFVLVFB regist ers t his VM belongs t o.
A VM might be set t o receive it s own t raffic in case t he source and t he dest inat ion are in t he same
pool via t he PFVMTXSW. LLE.
Whet her VLAN header and CRC should be st ripped from t he packet . Not e t hat even if t he CRC is
kept , it might not mat ch t he act ual cont ent of t he forwarded packet , because of ot her offloads
applicat ion such as VLAN st rip or LinkSec decrypt ing.
Set which header split is required via t he PSRTYPE regist er.
I n RSS mode, define if t he pool uses RSS via t he proper MRQC. MRQE mode.
Enable t he Pool in t he PFVFRE regist er t o allow Rx Filt ering
To Enable Mult iple Tx queues, Set t he MTQC as described in Sect ion 7. 2. 1.2.1
Enable t he Pool in t he PFVFTE regist er t o allow Tx Filt ering
Enable Rx and Tx queues as described in Sect ion 4. 6. 7 and Sect ion 4. 6. 8.
For each Rx queue a drop/ no drop flag can be set in SRRCTL. DROP_EN and via t he PFQDE regist er,
cont rolling t he behavior if no receive buffers are available in t he queue t o receive packet s. The
usual behavior is t o allow drop in order t o avoid head of line blocking. Set t ing PFQDE per queue is
made by using t he Queue I ndex field in t he PFQDE regist er.

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4. 6. 10. 2 I OV I ni t i al i zat i on
4.6.10.2.1 Physi cal Funct i on ( PF) Dr i v er I ni t i al i zat i on
The PF driver is responsible for t he link set up and handling of all t he filt ering and offload capabilit ies for
all t he VFs as described in Sect ion 4. 6. 10. 1. 1 and t he securit y feat ures as described in
Sect ion 4. 6. 10.1. 3. I t should also set t he bandwidt h allocat ion per t ransmit queue for each VF as
described in Sect ion 4.6. 10.
Not e: The link set up might include t he aut hent icat ion process ( 802. 1X or ot her) , set up of t he
LinkSec channel, and set up of t he DCB paramet ers.
I n I OV mode, VMDq + RSS mode is not available.
Aft er all t he common paramet ers are set , t he PF driver should set all t he VFMailbox[ n] . RSTD bit s by
set t ing CTRL_EXT. PFRSTD.
PF enables VF t raffic via t he PFVFTE and PFVFRE regist ers aft er all VF paramet ers are set as defined in
Sect ion 4. 6. 10.1. 4.
Not e: I f t he operat ing syst em changes t he NumVF set t ing in t he PCI e SR- I OV Num VFs regist er
aft er t he device was act ive, it is required t o init iat e a PF soft ware reset following t his change.
4.6.10.2.1. 1 VF Speci f i c Reset Coor di nat i on
Aft er t he PF driver receives an indicat ion of a VF FLR via t he PFVFLRE regist er, it should enable t he
receive and t ransmit for t he VF only once t he device is programmed wit h t he right paramet ers as
defined in Sect ion 4. 6. 10.1.4. The receive filt ering is enabled using t he PFVFRE regist er and t he
t ransmit filt ering is enabled via t he PFVFTE regist er.
Not e: The filt ering and offloads set up might be based on cent ral I T set t ings or on request s from t he
VF drivers.
4.6.10.2.2 VF Dr i ver I ni t i al i zat i on
Upon init ializat ion, aft er t he PF indicat ed t hat t he global init ializat ion was done via t he VFMailbox. RSTD
bit , t he VF driver should communicat e wit h t he PF, eit her via t he mailbox or via ot her soft ware
mechanisms t o assure t hat t he right paramet ers of t he VF are programmed as described in
Sect ion 4. 6. 10.1. 4. The PF driver might t hen send an acknowledge message wit h t he act ual set up done
according t o t he VF request and t he I T policy.
The VF driver should t hen set up t he int errupt s and t he queues as described in Sect ion 4. 6.6,
Sect ion 4. 6. 7 and Sect ion 4. 6. 8.
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4.6.10.2.3 Ful l Reset Coor di nat i on
A mechanism is provided t o synchronize reset procedures bet ween t he PF and t he VFs. I t is provided
specifically for PF soft ware reset but can be used in ot her reset cases. These reset cases are described
in t he following procedure.
One of t he following reset cases t akes place:
LAN Power Good
PCI e reset ( PERST and in- band)
D3hot - - > D0
FLR
Soft ware reset by t he PF
The 82599 set s t he RSTI bit s in all t he VFMailbox regist ers. Once t he reset complet es, each VF might
read it s VFMailbox regist er t o ident ify a reset in progress.
Once t he PF complet es configuring t he device, it clears t he CTRL_EXT. PFRSTD bit . As a result , t he
82599 clears t he RSTI bit s in all t he VFMailbox regist ers and set s t he RSTD ( Reset Done) bit s in all t he
VFMailbox regist ers.
Unt il a RSTD condit ion is det ect ed, t he VFs should access only t he VFMailbox regist er and should not
at t empt t o act ivat e t he int errupt mechanism or t he t ransmit and receive process.
4.6.11 DCB Conf i gur at i on
Aft er power up or device reset , DCB and any t ype of FC are disabled by default , and a unique TC and
packet buffer ( like PB0) is used. I n t his mode, t he host can exchange informat ion via DCX prot ocol t o
det ermine t he number of TCs t o be configured. Before set t ing t he device t o mult iple TCs, it should be
reset ( soft ware reset ) .
The regist ers concerned wit h set t ing t he number of TCs are: RXPBSI ZE[ 0- 7] , TXPBSI ZE[ 0- 7] ,
TXPBTHRESH, MRQC, MTQC, and RTRUP2TC regist ers along wit h t he following bit s RTRPCS. RAC,
RTTDCS. TDPAC, RTTDCS.VMPAC and RTTPCS. TPPAC.
They cannot be modified on t he fly, but only aft er device reset . Packet buffers wit h a non- null size must
be allocat ed from PB0 and up.
Rat e paramet ers and bandwidt h allocat ion t o VMs can be modified on t he fly wit hout dist urbing t raffic
flows.
4. 6. 11. 1 CPU Lat ency Consi der at i ons
When t he CPU det ect s an idle period of some lengt h, it ent ers a lowpower sleep st at e. When t raffic
arrives from t he net work, it t akes t ime for t he CPU t o wake and respond ( such as t o snoop) . During
t hat period, Rx packet s are not post ed t o syst em memory.
I f t he ent ry t ime t o sleep st at e is t oo short , t he CPU might be get t ing in and out of sleep st at e in
bet ween packet s, t herefore impact ing lat ency and t hroughput . 100 s was defined as a safe margin for
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Each t ime t he CPU is in low power, received packet s need t o be st ored ( or dropped) in t he 82599 for t he
durat ion of t he exit t ime. Given 64 KB Rx packet buffers per TC in t he 82599, Priorit y Flow Cont rol
( PFC) does not spread ( or a packet is not dropped) provided t hat t he CPU exit s it s low power st at e
wit hin
50 s.
4.6.11.2 Li nk Speed Change Pr ocedur e
Each t ime t he link st at us or speed is changed, hardware is aut omat ically updat ing t he t ransmit rat es
t hat were loaded by soft ware relat ively t o t he new link speed. This means t hat if a rat e limit er was set
by soft ware t o 500 Mb/ s for a 10 GbE link speed, it is changed by hardware t o 50 Mb/ s if t he link speed
has changed t o 1 GbE.
Since t ransmit rat es must be considered as absolut e rat e limit at ions ( expressed in Mb/ s, regardless of
t he link speed) , in such occasions soft ware is responsible t o eit her clear all t he t ransmit rat e- limit ers via
t he BCN_CLEAR_ALL bit in RTTBCNRD regist er, and/ or t o reload each t ransmit rat e wit h t he correct
value relat ively t o t he new link speed. I n t he previous example, t he new t ransmit rat e value t o be
loaded by soft ware must be mult iplied by 10 t o maint ain t he rat e limit at ion t o 500 Mb/ s.
4. 6. 11. 3 I ni t i al Conf i gur at i on Fl ow
Only t he following configurat ion modes are allowed.
4.6.11.3.1 Gener al Case: DCB- on, VT- on
1. Configure packet buffers, queues, and t raffic mapping:
8 TCs mode Packet buffer size and t hreshold, t ypically
RXPBSI ZE[ 0- 7] . SI ZE= 0x40
TXPBSI ZE[ 0- 7] .SI ZE= 0x14
but non- symmet rical sizing is also allowed ( see Sect ion 8. 2. 3. 9. 13 for rules)
TXPBTHRESH. THRESH[ 0- 7] = TXPBSI ZE[ 0- 7] . SI ZE Maximum expect ed Tx packet lengt h in
t his TC
4 TCs mode Packet buffer size and t hreshold, t ypically
RXPBSI ZE[ 0- 3] . SI ZE= 0x80, RXPBSI ZE[ [ 4- 7] . SI ZE= 0x0
TXPBSI ZE[ 0- 3] .SI ZE= 0x28, TXPBSI ZE[ 4- 7] . SI ZE= 0x0
but non- symmet rical sizing among TCs[ 0- 3] is also allowed ( see Sect ion 8. 2. 3. 9. 13 for rules)
TXPBTHRESH. THRESH[ 0- 3] = TXPBSI ZE[ 0- 3] . SI ZE Maximum expect ed Tx packet lengt h in
t his TC
TXPBTHRESH. THRESH[ 4- 7] = 0x0
Mult iple Receive and Transmit Queue Cont rol ( MRQC and MTQC)
Set MRQC. MRQE t o 1xxxb, wit h t he t hree least significant bit s set according t o t he number
of VFs, TCs, and RSS mode as described in Sect ion 8. 2. 3. 7. 12.
Set bot h RT_Ena and VT_Ena bit s in t he MTQC regist er.
Set MTQC. NUM_TC_OR_Q according t o t he number of TCs/ VFs enabled as described in
Sect ion 8. 2. 3. 7. 16.
Set t he PFVTCTL. VT_Ena ( as t he MTQC. VT_Ena)
Queue Drop Enable ( PFQDE) I n SR- I O t he QDE bit should be set t o 1b in t he PFQDE regist er
for all queues. I n VMDq mode, t he QDE bit should be set t o 0b for all queues.
Split receive cont rol ( SRRCTL[ 0- 127] ) : Drop_En= 1 drop policy for all t he queues, in order t o
avoid crosst alk bet ween VMs
Rx User Priorit y ( UP) t o TC ( RTRUP2TC)
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Tx UP t o TC ( RTTUP2TC)
DMA TX TCP Maximum Allowed Size Request s ( DTXMXSZRQ) set Max_byt e_num_req =
0x010 = 4 KB
2. Enable PFC and disable legacy flow cont rol:
Enable t ransmit PFC via: FCCFG. TFCE= 10b
Enable receive PFC via: MFLCN. RPFCE= 1b
Disable receive legacy flow cont rol via: MFLCN. RFCE= 0b
Refer t o Sect ion 8.2. 3. 3 for ot her regist ers relat ed t o flow cont rol
3. Configure arbit ers, per TC[ 0- 1] :
Tx descript or plane T1 Config ( RTTDT1C) per queue, via set t ing RTTDQSEL first . Not e t hat t he
RTTDT1C for queue zero must always be init ialized.
Tx descript or plane T2 Config ( RTTDT2C[ 0- 7] )
Tx packet plane T2 Config ( RTTPT2C[ 0- 7] )
Rx packet plane T4 Config ( RTRPT4C[ 0- 7] )
4. Enable TC and VM arbit rat ion layers:
Tx Descript or plane Cont rol and St at us ( RTTDCS) , bit s:
TDPAC= 1b, VMPAC= 1b, TDRM= 1b, BDPM= 1b, BPBFSM= 0b, and set t he LLTC bit only on TC( s)
wit h low lat ency requirement s
Tx Packet Plane Cont rol and St at us ( RTTPCS) : TPPAC= 1b, TPRM= 1b, ARBD= 0x004
Rx Packet Plane Cont rol and St at us ( RTRPCS) : RAC= 1b, RRM= 1b
5. Set t he SECTXMI NI FG. SECTXDCB field t o 0x1F.
4.6.11.3.2 DCB- On, VT- Of f
Set t he configurat ion bit s as specified in Sect ion 4.6. 11.3. 1 wit h t he following except ions:
Configure packet buffers, queues, and t raffic mapping:
MRQC and MTQC
Set MRQE t o 0xxxb, wit h t he t hree least significant bit s set according t o t he number of TCs
and RSS mode
Set RT_Ena bit and clear t he VT_Ena bit in t he MTQC regist er.
Set MTQC. NUM_TC_OR_Q according t o t he number of TCs enabled
Clear PFVTCTL. VT_Ena ( as t he MRQC. VT_Ena)
Allow no- drop policy in Rx:
PFQDE: The QDE bit should be set t o 0b in t he PFQDE regist er for all queues enabling per queue
policy by t he SRRCTL[ n] set t ing.
Split Receive Cont rol ( SRRCTL[ 0- 127] ) : The Drop_En bit should be set per receive queue
according t o t he required drop / no- drop policy of t he TC of t he queue.
Tx descript or plane cont rol and st at us ( RTTDCS) bit s:
TDPAC= 1b, VMPAC= 1b, TDRM= 1b, BDPM= 0b if Tx rat e limit ing is not enabled and 1b if Tx rat e
limit ing is enabled, BPBFSM= 0b, and set t he LLTC bit only on TC( s) wit h low lat ency
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Disable VM arbit rat ion layer:
Clear RTTDT1C regist er, per each queue, via set t ing RTTDQSEL first
RTTDCS. VMPAC= 0b
Set t he SECTXMI NI FG.SECTXDCB field t o 0x1F.
4.6.11.3.3 DCB- Of f , VT- On
Set t he configurat ion bit s as specified in Sect ion 4. 6.11.3.1 wit h t he following except ions:
Disable mult iple packet buffers and allocat e all queues t o PB0:
RXPBSI ZE[ 0] . SI ZE= 0x200, RXPBSI ZE[ 1- 7] . SI ZE= 0x0
TXPBSI ZE[ 0] . SI ZE= 0xA0, TXPBSI ZE[ 1- 7] . SI ZE= 0x0
TXPBTHRESH. THRESH[ 0] = 0xA0 Maximum expect ed Tx packet lengt h in t his TC
TXPBTHRESH. THRESH[ 1- 7] = 0x0
MRQC and MTQC
Set MRQE t o 1xxxb, wit h t he t hree least significant bit s set according t o t he number of VFs
and RSS mode
Clear RT_Ena bit and set t he VT_Ena bit in t he MTQC regist er.
Set MTQC. NUM_TC_OR_Q according t o t he number of VFs enabled
Set PFVTCTL. VT_Ena ( as t he MRQC. VT_Ena)
Rx UP t o TC ( RTRUP2TC) , UPnMAP= 0b, n= 0,. .., 7
Tx UP t o TC ( RTTUP2TC) , UPnMAP= 0b, n= 0, .. .,7
0xFFF = 1 MB
Disable PFC and enabled legacy flow cont rol:
Disable receive PFC via: MFLCN. RPFCE= 0b
Enable t ransmit legacy flow cont rol via: FCCFG. TFCE= 01b
Enable receive legacy flow cont rol via: MFLCN. RFCE= 1b
Configure VM arbit ers only, reset ot hers:
Tx Descript or Plane T1 Config ( RTTDT1C) per pool, via set t ing RTTDQSEL first for t he pool
index. Clear RTTDT1C for ot her queues. Not e t hat t he RTTDT1C for queue zero must always be
init ialized.
Clear RTTDT2C[ 0- 7] regist ers
Clear RTTPT2C[ 0- 7] regist ers
Clear RTRPT4C[ 0- 7] regist ers
Disable TC arbit rat ions while enabling t he packet buffer free space monit or:
Tx Descript or Plane Cont rol and St at us ( RTTDCS) , bit s:
TDPAC= 0b, VMPAC= 1b, TDRM= 0b, BDPM= 1b, BPBFSM= 0b, clear LLTC bit s
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4.6.11.3.4 DCB- Of f , VT- Of f
Set t he configurat ion bit s as specified in Sect ion 4.6. 11.3. 1 wit h t he following except ions:
Disable mult iple packet buffers and allocat e all queues and t raffic t o PB0:
RXPBSI ZE[ 0] . SI ZE= 0x200, RXPBSI ZE[ 1- 7] . SI ZE= 0x0
TXPBSI ZE[ 0] .SI ZE= 0xA0, TXPBSI ZE[ 1- 7] . SI ZE= 0x0
TXPBTHRESH. THRESH[ 0] = 0xA0 Maximum expect ed Tx packet lengt h in t his TC
TXPBTHRESH.THRESH[ 1- 7] = 0x0
MRQC and MTQC
Set MRQE t o 0xxxb, wit h t he t hree least significant bit s set according t o t he RSS mode
Clear bot h RT_Ena and VT_Ena bit s in t he MTQC regist er.
Set MTQC. NUM_TC_OR_Q t o 00b.
Clear PFVTCTL.VT_Ena ( as t he MRQC. VT_Ena)
Rx UP t o TC ( RTRUP2TC) , UPnMAP= 0b, n= 0, .. ., 7
Tx UP t o TC ( RTTUP2TC) , UPnMAP= 0b, n= 0,. .., 7
0xFFF = 1 MB
Allow no- drop policy in Rx:
PFQDE: The QDE bit should be set t o 0b in t he PFQDE regist er for all queues enabling per queue
policy by t he SRRCTL[ n] set t ing.
Split Receive Cont rol ( SRRCTL[ 0- 127] ) : The Drop_En bit should be set per receive queue
according t o t he required drop / no- drop policy of t he TC of t he queue.
Disable PFC and enable legacy flow cont rol:
Disable receive PFC via: MFLCN. RPFCE= 0b
Enable receive legacy flow cont rol via: MFLCN.RFCE= 1b
Enable t ransmit legacy flow cont rol via: FCCFG. TFCE= 01b
Reset all arbit ers:
Clear RTTDT1C regist er, per each queue, via set t ing RTTDQSEL first
Clear RTTDT2C[ 0- 7] regist ers
Clear RTTPT2C[ 0- 7] regist ers
Clear RTRPT4C[ 0- 7] regist ers
Disable TC and VM arbit rat ion layers:
Tx Descript or Plane Cont rol and St at us ( RTTDCS) , bit s:
TDPAC= 0b, VMPAC= 0b, TDRM= 0b, BDPM= 1b, BPBFSM= 1b, clear LLTC bit s

155
4. 6. 11. 4 Tr ansmi t Rat e Schedul er
I n some applicat ions it might be useful t o set up rat e limit ers on Tx queues for ot her usage models
( rat e- limit ing VF t raffic for inst ance) . I n all cases, set t ing a rat e limit er on Tx queue N t o a Target Rat e
requires t he following set t ings:
Gl obal Set t i ng
The Transmit Rat e- scheduler memory for all t ransmit queues must be cleared before rat e limit ing is
enabled on any queue. This memory is accessed by t he RTTBCNRC regist er mapped by t he
RTTDQSEL. TXDQ_I DX.
Set global t ransmit compensat ion t ime t o t he MMW_SI ZE in RTTBCNRM regist er. Typically
MMW_SI ZE= 0x014 if 9.5 KB ( 9728- byt e) j umbo is support ed and 0x004 ot herwise.
Per Queue Set t i ng
Select t he request ed queue by programming t he queue index - RTTDQSEL. TXQ_I DX
Program t he desired rat e as follow
Comput e t he Rat e_Fact or which equals Link_Speed / Target _Rat e. Link_Speed could be eit her
10 Gb/ s or 1 Gb/ s. Not e t hat t he Rat e_Fact or is composed of an int eger number plus a fract ion.
The int eger part is a 10 bit number field and t he fract ion part is a 14 bit binary fract ion number.
I nt eger ( Rat e_Fact or) is programmed by t he RTTBCNRC. RF_I NT[ 9: 0] field
Fract ion ( Rat e_Fact or) is programmed by t he RTTBCNRC. RF_DEC[ 13: 0] field. I t equals
RF_DEC[ 13] * 2
- 1
+ RF_DEC[ 12] * 2
- 2
+ . . . + RF_DEC[ 0] * 2
- 14
Enable Rat e Scheduler by set t ing t he RTTBCNRC. RS_ENA
Numerical Example
Target _Rat e = 240 Mb/ s; Link_Speed = 10 Gb/ s
Rat e_Fact or = 10 / 0. 24 = 41. 6666. . . = 101001. 10101010101011b
RF_DEC = 10101010101011b; RF_I NT = 0000101001b
Therefore, set RTTBCNRC t o 0x800A6AAB
Not e: The I PG pacing feat ure is a parallel feat ure t o t he Tx rat e scheduler where I PG pacing is
applied t o t he ent ire Tx dat a flow while t he Tx rat e scheduler is applied separat ely t o each Tx
queue. Therefore, if a single queue is used, eit her feat ure can be used t o limit t he Tx dat a
rat e; however, if mult iple queues are used, t he I PG pacing feat ure is a bet t er choice for a
homogeneous Tx dat a rat e limit at ion.
4.6.11.5 Conf i gur at i on Rul es
4.6.11.5.1 TC Par amet er s
Tr af f i c Cl ass
Per 802. 1p, priorit y # 7 is t he highest priorit y.
A specific TC can be configured t o receive or t ransmit a specific amount of t he t ot al bandwidt h available
per port .
Bandwidt h allocat ion is defined as a fract ion of t he t ot al available bandwidt h, which can be less t han t he
full Et hernet link bandwidt h ( if it is bounded by t he PCI e bandwidt h or by flow cont rol) .
Low lat ency TC should be configured t o use t he highest priorit y TC possible ( TC 6, 7) . The lowest
lat ency is achieved using TC7.
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156
Bandw i dt h Gr oup ( BWGs)
The main reason for having BWGs is t o represent different t raffic t ypes. A t raffic t ype ( such as st orage,
I PC LAN or manageabilit y) can have more t han one TC ( for example, one for cont rol t raffic and one for
t he raw dat a) , by grouping t hese t wo TC t o a BWG t he user can allocat e bandwidt h t o t he st orage t raffic
so t hat unused bandwidt h by t he cont rol could be used by t he dat a and vise versa. This BWG concept
support s t he converged fabric as each t raffic t ype, t hat is used t o run on a different fabric, can be
configured as a BWG and get s it s resources as if it was on a different fabric.
1. To configure DCB not t o share bandwidt h bet ween TCs, each TC should be configured as a separat e
BWG.
2. There are no limit s on t he TCs t hat can be bundled t oget her as a BWG. All TCs can be configured as
a single BWG.
3. BWG numbers should be sequent ial st art ing from zero unt il t he t ot al number of BWGs minus one.
4. BWG numbers do not imply priorit y, priorit y is only set according t o TCs.
Ref i l l Cr edi t s
Refill credit s regulat e t he bandwidt h allocat ed t o BWG and TC. The rat io bet ween t he credit s of t he
BWGs represent s t he relat ive bandwidt h percent age allocat ed t o each BWG. The rat io bet ween t he
credit s of t he TCs represent s t he relat ive bandwidt h percent age allocat ed t o each TC wit hin a BWG.
Credit s are configured and calculat ed using 64 byt es granularit y.
1. I n any case, t he number of refill credit s assigned per TC should be as small as possible but must be
larger t han t he maximum frame size used and larger t han 1. 5 KB. Using a lower refill value causes
more refill cycles before a packet can be sent . These ext ra cycles unnecessarily increase t he
lat ency.
2. Refill credit s rat io bet ween TCs should be equal t o t he desired rat io of bandwidt h allocat ion bet ween
t he different TCs. Applying rule # 1, means bandwidt h shares are sort ed from t he smaller t o t he
bigger, and j ust one maximum sized frame is allocat ed t o t he smallest .
3. The rat io bet ween t he refill credit s of any t wo TCs should not be great er t han 100.
4. Except ion t o rule # 2 TCs t hat require low lat ency should be configured so t hat t hey are under
subscribed. For example, credit refill value should provide t hese TCs somewhat more bandwidt h
t han what t hey act ually need. Low lat ency TCs should always have credit s so t hey can be next in
line for t he WSP arbit rat ion.
This except ion causes t he low lat ency TC t o always have maximum credit s ( as it st art s wit h
maximum credit s and on average cycle uses less t han t he refill credit s) .
The end point t hat is sending/ receiving packet s of 127 byt es event ually get s double t he bandwidt h it
was configured t o, as we do all t he credit calculat ion by rounding t he values down t o t he next 64 byt e
aligned value.
Max i mum Cr edi t Li mi t
The maximum credit limit value est ablishes a limit for t he number of credit s t hat a TC or BWG can own
at any given t ime. This value prevent s st acking up st ale credit s t hat can be added up over a relat ively
long period of t ime and t hen used by TCs all at once, alt ering fairness and lat ency.
Maximum credit s limit s are configured and calculat ed using 64 byt es granularit y.
1. Maximum credit limit should be bigger t han t he refill credit s allocat ed t o t he TC.
2. Maximum credit limit should be set t o be as low as possible while st ill meet ing ot her rules t o
minimize t he lat ency impact on low lat ency TCs.

157
3. I f a low lat ency TC generat es a burst t hat is larger t han it s maximum credit limit t his TC might
experience higher lat ency since t he TC needs t o wait for allocat ion of addit ional credit s because it
finished all it s credit s for t his cycle. Therefore maximum credit limit for a low lat ency TC must be
set bigger t han t he maximum burst lengt h of t raffic expect ed on t hat TC ( for all t he VMs at once) . I f
TC7 and TC6 are for low lat ency t raffic, it leads t o:
Max( TC7, 6) > = MaxBur st ( TC7, 6) ser ved wi t h l ow l at ency
4. An arbit rat ion cycle can ext end when one or more TCs accumulat e credit s more t han t heir refill
values ( up t o t heir maximum credit limit ) . For such a case, a low lat ency TC should be provided
wit h enough credit s t o cover for t he ext ended cycle durat ion. Since t he low lat ency TC operat es at
maximum credit s ( see rule # 3) it s maximum credit limit should meet t he following formula:
{ Max( TCx) / SUMi = 0. . 7[ Max( TCi ) ] } > = { BW( TCx) / Ful l BW}
The formula applies t o bot h descript or arbit er and dat a arbit er.
5. When in a virt ualized environment , t he low lat ency TC condit ion checked by t he VM WRR arbit er
( see Sect ion 7. 7. 2. 3. 2) induces t he following relat ion bet ween t he maximum credit s of a low
lat ency TC and t he refill credit s of it s at t ached VM arbit er:
Max( TCx) > = 2 x { SUMi = 0. . . 15[ Ref i l l ( VMi ) ] }
6. To ensure bandwidt h for low priorit y TC ( when t hose are allocat ed wit h most of t he bandwidt h) t he
maximum credit value of t he low priorit y TC in t he dat a arbit er needs t o be high enough t o ensure
sync bet ween t he t wo arbit ers. I n t he equat ion t hat follows t he bandwidt h numbers are from t he
descript or arbit er while t he maximum values are of t he dat a arbit er.
{ Max( TCx) / SUMi = x+ 1. . 7[ Max( TCi ) ] } > = { BW( TCx) / Ful l _PCI E_BW}
Not e t hat t he previous equat ion is worst case and covers t he assumpt ion t hat all higher TCs have
t he full maximum t o t ransmit .
Ti p: A simplified maximum credit s allocat ion scheme would be t o find t he minimum number N > =
2 such t hat rules # 3 and # 5 are respect ed, and allocat e
Max( TCi ) = N x Ref i l l ( TCi ) , f or i = 0. . . 7
By maint aining t he same rat ios bet ween t he maximum credit s and t he bandwidt h shares, t he
bandwidt h allocat ion scheme is made more immune t o dist urbing event s such as recept ion of priorit y
pause frames wit h short t imer values.
GSP and LSP
TC Link St rict Priorit y ( TC. LSP) : This bit specifies t hat t he configured TC can t ransmit wit hout any
rest rict ion of credit s. This effect ively means t hat t he TC can t ake up ent ire link bandwidt h, unless
preempt ed by higher priorit y t raffic. The Tx queues associat ed wit h LSP TC must be set as St rict Low
Lat ency in t he TXLLQ[ n] regist ers.
TC St rict Priorit y wit hin group ( TC. GSP) : This bit defines whet her st rict priorit y is enabled or disabled
for t his TC wit hin it s BWG. I f TC. GSP is set t o 1b, t he TC is scheduled for t ransmission using st rict
priorit y. I t does not check for availabilit y of credit s in t he TC. I t does check whet her t he BWG of t his TC
has credit s. For example, t he amount of t raffic generat ed from t his TC is st ill limit ed by t he BWG
allocat ed for t he BWG.
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158
1. TCs wit h t he LSP bit set should be t he first t o be considered by t he scheduler. This implies t hat LSP
should be configured t o t he highest priorit y TCs. For example, st art ing from priorit y 7 and down.
The ot her TCs should be used for groups wit h bandwidt h allocat ion. I t is recommended t o use LSP
only for one TC ( TC7) as t he first LSP TC t akes it s bandwidt h and t here are no guarant ees t o t he
lower priorit y LSPs.
2. GSP can be set t o more t han one TC in a BWG, always from t he highest priorit y TC wit hin t hat BWG
downward. For t he LAN scenario, all TCs could be configured t o be GSP as t heir bandwidt h needs
are not known.
3. To a low lat ency TC for which t he GSP bit is set , non- null refill credit s must be set for at least one
maximum sized frame. I t ensures t hat even aft er having been quiet for a while, some BWG credit s
are left available t o t he GSP TC, for serving it wit h minimum lat ency ( wit hout wait ing for
replenishing) . Bigger refill credit s values ensure longer burst of GSP t raffic served wit h minimum
lat ency.
4.6.11.5.2 VM Par amet er s
Ref i l l Cr edi t s
Refill credit s regulat e t he fract ion of t he TCs bandwidt h t hat is allocat ed t o a VM. The rat io bet ween t he
credit s of t he VMs represent s t he relat ive TC bandwidt h percent age allocat ed t o each VM.
Credit s are configured and calculat ed using 64 byt es granularit y.
1. The number of refill credit s assigned per VM should be as small as possible but st ill larger t han t he
maximum frame size used and larger t han 1. 5 KB in any case. Using a lower refill value causes
more refill cycles before a packet can be sent . These ext ra cycles increase t he lat ency
unnecessarily.
2. Refill credit s rat io bet ween VMs should be equal t o t he desired rat io of bandwidt h allocat ion
bet ween t he different TCs. Applying rule # 1, means bandwidt h shares are sort ed from t he smaller
t o t he bigger, and j ust one maximum sized frame is allocat ed t o t he smallest .
3. The rat io bet ween t he refill credit s of any t wo VMs wit hin t he TC should not be great er t han 10.
VMs t hat are sending/ receiving packet s of 127 byt es event ually get s double t he bandwidt h it was
configured t o as we do all t he credit calculat ion by rounding t he values down t o t he next 64 byt e
aligned value.
4. I n a low lat ency TC, non- null refill credit s must be set t o a VSP VM, for at least one maximum sized
frame. I t ensures t hat even aft er having been quiet for a while, some TC credit s are left available t o
t he VSP VM, for serving it wit h minimum lat ency ( wit hout wait ing for TC t o replenish) . Bigger refill
credit s values ensure longer burst of VSP t raffic served wit h minimum lat ency.
Ex ampl e 1. Ref i l l and Max Cr edi t s Set t i ng Ex ampl e
This example assumes a syst em wit h only four TCs and t hree VMs present , and wit h t he following
bandwidt h allocat ion scheme. Also, full PCI e bandwidt h is evaluat ed t o 15 G.
Tabl e 4.9. Bandw i dt h Shar e Ex ampl e
TCs and VMs
Bandw i dt h
Shar e%
Not es
TC0 Tot al 40 9. 5 KB ( 9728- byt e) j umbo allowed.
VM0 60
VM1 30
VM2 10

159
The rat ios bet ween TC refills were driven by TC0, which was set as 152 for support ing 9. 5 KB j umbos.
The rat io bet ween MaxCredit s and Refill were t aken as 17 for all t he TCs, as driven by TC2 relat ion
bet ween MaxCredit s and MaxBurst TC2.
TC1 Tot al 20 No j umbo.
VM0 34
VM1 33
VM2 33
TC2 Tot al 30
Low lat ency TC. No j umbo.
Bandwidt h share already increased.
MaxBurst TC2= 120 KB
VM0 80
VM1 10
VM2 10
TC3 Tot al 10
Low lat ency LSP TC.
No j umbo.
MaxBurst TC3= 36 KB
VM0 20
VM1 60
VM2 20
Tabl e 4. 10. Ref i l l and Max Cr edi t s Set t i ng
Ref i l l ( 64- By t e
Uni t s)
Max Cr edi t s ( 64- By t e Uni t s)
TC0 Tot al 152 2584
VM0 912
VM1 456
VM2 152
TC1 Tot al 76 1292
VM0 25
VM1 24
VM2 24
TC2 Tot al 114 1938
VM0 192
VM1 24
Tabl e 4. 9. Bandw i dt h Shar e Ex ampl e
TCs and VMs
Bandw i dt h
Shar e%
Not es
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4. 6. 12 Secur i t y I ni t i al i zat i on
Aft er power up or device reset , securit y offload is disabled by default ( bot h LinkSec and I Psec) , and t he
cont ent of SA t ables must be cleared by soft ware.
Securit y offload cannot be enabled if int ernal securit y fuses are not enabled or t he SDP0_4 pin is set t o
0b. I n t his case, bot h I Psec and LinkSec are disabled and t he following securit y relat ed fields are not
writ able:
SECTXCTRL. SECTX_DI S is set t o 1b and read as 1b.
SECRXCTRL.SECRX_DI S is set t o 1b and read as 1b.
I PSTXI DX. I PS_TX_EN is cleared t o 0b and read as 0b.
I PSRXI DX. I PS_RX_EN is cleared t o 0b and read as 0b.
LSECTXCTRL bit s 1: 0 are cleared t o 00b and read as 00b.
LSECRXCTRL bit s 3: 2 are cleared t o 00b and read as 00b.
Securit y offload can be used when enabled by int ernal securit y fuses and when t he SDP0_4 pin is set t o
1b. I n t his case, t he securit y offload can be enabled/ disabled via t he flows described as follows.
4. 6.12. 1 Secur i t y Enabl ement Fl ow
To enable one of t he securit y modes perform t he following st eps:
1. St op t he dat a pat hs by set t ing t he SECTXCTRL. TX_DI S and SECRXCTRL. RX_DI S bit s.
2. Wait for hardware t o empt y t he dat a pat hs. Poll t he SECTXSTAT.SECTX_RDY and
SECRXSTAT.SECRX_RDY bit s unt il t hey are bot h assert ed by hardware.
3. Clear t he SECTXCTRL.SECTX_DI S and SECRXCTRL.SECRX_DI S bit s t o enable t he Tx and Rx crypt o
engines.
When enabling I Psec or LinkSec offload, set SECTXMI NI FG. MI NSECI FG t o 0x3 ext ending back- t o-
back gap t o t he securit y block required for it s funct ionalit y.
When enabling I Psec, set t he SECTXCTRL. STORE_FORWARD bit , since a st ore and forward I Psec
buffer is required for t he processing of AH packet s ( I CV field insert ion is done at t he beginning of
t he frame) . Ot herwise, clear t his bit .
When enabling I Psec, writ e t he SEC buffer almost full t hreshold, regist er
SECTXBUFFAF. buff_af_t hresh, wit h t he value of 0x15.
4. Enable SA lookup:
For I Psec, set t he I PSTXI DX. I PS_TX_EN and t he I PSRXI DX. I PS_RX_EN bit s.
For LinkSec, set t he enable bit s in t he LSECTXCTRL and LSECRXCTRL regist ers.
5. Rest art t he dat a pat hs by clearing t he SECTXCTRL. TX_DI S and SECRXCTRL. RX_DI S bit s.
VM2 24
TC3 Tot al 38 646
VM0 24
VM1 72
VM2 24
Tabl e 4.10. Ref i l l and Max Cr edi t s Set t i ng
Ref i l l ( 64- By t e
Uni t s)
Max Cr edi t s ( 64- By t e Uni t s)

161
4.6.12.2 Secur i t y Di sabl e Fl ow
To disable one of t he securit y modes perform t he following st eps:
1. St op t he dat a pat hs by set t ing t he SECTXCTRL. TX_DI S and SECRXCTRL.RX_DI S bit s.
2. Wait for hardware t o empt y t he dat a pat hs. Poll t he SECTXSTAT.SECTX_RDY and
SECRXSTAT. SECRX_RDY bit s unt il t hey are bot h assert ed by hardware.
3. Disable SA lookup:
For I Psec, clear t he I PSTXI DX. I PS_TX_EN and t he I PSRXI DX. I PS_RX_EN bit s.
For LinkSec, clear t he enable bit s in t he LSECTXCTRL and LSECRXCTRL regist ers.
4. Set t he SECTXCTRL.SECTX_DI S and SECRXCTRL.SECRX_DI S bit s t o disable t he Tx and Rx crypt o
engines.
When disabling I Psec, clear t he SECTXCTRL. STORE_FORWARD bit , t o avoid using t he I Psec buffer
and t hus reducing Tx int ernal lat ency.
When disabling I Psec, writ e t he SEC buffer almost full t hreshold, regist er
SECTXBUFFAF.buff_af_t hresh, wit h t he value of 0x250.
5. Rest art t he dat a pat hs by clearing t he SECTXCTRL. TX_DI S and SECRXCTRL.RX_DI S bit s.
Not e: Disabling t he crypt o engine reduces t he 82599s power consumpt ion.
4.6.13 Al t er nat e MAC Addr ess Suppor t
I n some syst ems, t he MAC address used by a port needs t o be replaced wit h a t emporary MAC address
in a way t hat is t ransparent t o t he soft ware layer. One possible usage is in blade syst ems, t o allow a
st andby blade t o use t he MAC address of anot her blade t hat failed, so t hat t he net work image of t he
ent ire blade syst em does not change.
I n order t o allow t his mode, a management console might change t he MAC address in t he NVM image.
I t is import ant in t his case t o be able t o keep t he original MAC address of t he device as programmed at
t he fact ory.
I n order t o support t his mode, t he 82599 provides t he Alt ernat e Et hernet MAC Address st ruct ure in t he
NVM t o st ore t he original MAC addresses. This st ruct ure is described in Sect ion 6. 2. 6. I n some syst ems,
it might be advant ageous t o rest ore t he original MAC address at power on reset , t o avoid conflict s
where t wo net work cont rollers would have t he same MAC address.
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Pow er Management and Del i v er y I nt el

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5. 0 Pow er Management and Del i v er y
This sect ion defines how power management is implement ed in t he 82599.
5. 1 Pow er Tar get s and Pow er Del i v er y
See Sect ion 11.2.1 for t he current consumpt ion and see Sect ion 11. 4. 1 for t he power supply
specificat ion.
5.2 Pow er Management
5. 2.1 I nt r oduct i on t o t he 82599 Pow er St at es
The 82599 support s t he D0 and D3 power st at es defined in t he PCI Power Management and PCI e
specificat ions. D0 is divided int o t wo subst at es: D0u ( D0 uninit ialized) , and D0a ( D0 act ive) . I n
addit ion, t he 82599 support s a Dr st at e t hat is ent ered when PE_RST_N is assert ed ( including t he
D3cold st at e) .
Figure 5.1 shows t he power st at es and t ransit ions bet ween t hem.
5.2.2 Aux i l i ar y Pow er Usage
The 82599 uses t he AUX_PWR indicat ion t hat auxiliary power is available t o it , and t herefore advert ises
D3cold wake up support . The amount of power required for t he funct ion, which includes t he ent ire
Net work I nt erface Card ( NI C) is advert ised in t he Power Management Dat a regist er, which is loaded
from t he EEPROM.
Fi gur e 5. 1. Pow er Management St at e Di agr am
Dr D0u
D0a D3
Write 11b to
Power State
Write 00b to
Power State
Enable:
Master or
Slave Access
LAN_PWR_GOOD assertion FLR
Hot Reset:
PCIe Reset asserted /
In-Band PCIe Reset
Init done from
EEPROM
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164
I f D3cold is support ed, t he PME_En and PME_St at us bit s of t he Power Management Cont rol/ St at us
Regist er ( PMCSR) , as well as t heir shadow bit s in t he Wake Up Cont rol ( WUC) regist er are reset only by
t he power up reset ( det ect ion of power rising) .
The only effect of set t ing AUX_PWR t o 1b is advert ising D3cold wake up support and changing t he reset
funct ion of PME_En and PME_St at us. AUX_PWR is a st rapping opt ion in t he 82599.
The 82599 t racks t he PME_En bit of t he PMCSR and t he Auxiliary ( AUX) Power PM Enable bit of t he PCI e
Device Cont rol regist er t o det ermine t he power it might consume ( and t herefore it s power st at e) in t he
D3cold st at e ( int ernal Dr st at e) . Not e t hat t he act ual amount of power differs bet ween form fact ors.
5.2.3 Pow er Li mi t s by Cer t ai n For m Fact or s
Table 5. 1 list s t he power limit at ions int roduced by different form fact ors.
Not e: Auxiliary current limit only applies when t he primary 3. 3V volt age source is not available ( t he
card is in a low power D3 st at e) .
The 82599 exceeds t he allocat ed auxiliary power in some configurat ion ( such as bot h port s running at
GbE or 10 GbE speed) . The 82599 must be configured such t hat it meet s t he previously described
requirement s. To do so, link speed can be rest rict ed t o GbE and one of t he LAN port s can be disabled
when operat ing on auxiliary power. See Sect ion 5.2. 5. 4.
5. 2. 4 I nt er connect s Pow er Management
This sect ion describes t he power reduct ion t echniques used by t he 82599s main int erconnect s.
Tabl e 5.1. Pow er Li mi t s by For m- Fact or
For m Fact or
LOM PCI e Car d
Main N/ A 25 W
Auxiliary ( aux enabled) 375 mA @ 3. 3V 375 mA @ 3. 3V
Auxiliary ( aux disabled) 20 mA @ 3. 3V 20 mA @ 3. 3V

165
5.2.4.1 PCI e Li nk Pow er Management
The PCI e link st at e follows t he power management st at e of t he device. Since t he 82599 incorporat es
mult iple PCI funct ions, t he device power management st at e is defined as t he power management st at e
of t he most awake funct ion:
I f any funct ion is in D0 st at e ( eit her D0a or D0u), t he PCI e link assumes t he device is in D0 st at e.
Else,
I f t he funct ions are in D3 st at e, t he PCI e link assumes t he device is in D3 st at e.
Else,
The device is in Dr st at e ( PE_RST_N is assert ed t o all funct ions) .
The 82599 support s all PCI e power management link st at es:
L0 st at e is used in D0u and D0a st at es.
The L0s st at e is used in D0a and D0u st at es each t ime link condit ions apply.
The L1 st at e is used in D0a and D0u st at es each t ime link condit ions apply, as well as in t he D3
st at e.
The L2 st at e is used in t he Dr st at e following a t ransit ion from a D3 st at e if PCI - PM PME is enabled.
The L3 st at e is used in t he Dr st at e following power up, on t ransit ion from D0a and also if PME is
not enabled in ot her Dr t ransit ions.
The 82599 support for Act ive St at e Link Power Management ( ASLPM) is report ed via t he PCI e Act ive
St at e Link PM Support regist er loaded from EEPROM.
Fi gur e 5. 2. Li nk Pow er Management St at e Di agr am
L3
L1
PERST #de-
assertion
PERST #
assertion
PERST #
assertion
PERST #
assertion
Write 11b
to Power State
Write 00b
to Power State
Enable
master Access
LAN_PWR_GOOD
assertion
L2
L0
L0s
Dr D0u
L0
L0s
D0a
D3
L1
L1
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166
While in L0 st at e, t he 82599 t ransit ions t he t ransmit lane( s) int o L0s st at e once t he idle condit ions are
met for a period of t ime defined as follows.
L0s configurat ion fields are:
L0s enable The default value of t he Act ive St at e Link PM Cont rol field in t he PCI e Link Cont rol
regist er is set t o 00b ( bot h L0s and L1 disabled) . Syst em soft ware can lat er writ e a different value
int o t he Link Cont rol regist er. The default value is loaded on any reset of t he PCI configurat ion
regist ers.
The L0S_ENTRY_LAT bit in t he PCI e Cont rol Regist er ( GCR) , det ermines L0s ent ry lat ency. When
set t o 0b, L0s ent ry lat ency is t he same as L0s exit lat ency of t he device at t he ot her end of t he
link. When set t o 1b, L0s ent ry lat ency is ( L0s exit Lat ency of t he device at t he ot her end of t he link
/ 4) . Default value is 0b ( ent ry lat ency is t he same as L0s exit lat ency of t he device at t he ot her end
of t he link) .
L0s exit lat ency ( as published in t he L0s Exit Lat ency field of t he Link Capabilit ies regist er) is loaded
from t he EEPROM. Separat e values are loaded when t he 82599 shares t he same reference PCI e
clock wit h it s part ner across t he link, and when t he 82599 uses a different reference clock t han it s
part ner across t he link. The 82599 report s whet her it uses t he slot clock configurat ion t hrough t he
PCI e Slot Clock Configurat ion bit loaded from t he Slot _Clock_Cfg EEPROM bit .
L0s accept able lat ency ( as published in t he Endpoint L0s Accept able Lat ency field of t he Device
Capabilit ies regist er) is loaded from t he EEPROM.
While in L0s st at e, t he 82599 t ransit ions t he link int o L1 st at e once t he t ransmit lanes or bot h direct ions
of t he link have been in L0s st at e for a period of t ime defined in PCI configurat ion space loaded from
t he PCI e I nit Configurat ion 1 word in t he EEPROM.
The following EEPROM fields cont rol L1 behavior:
Act _St at _PM_Sup I ndicat es support for ASPM L1 in t he PCI e configurat ion space ( loaded int o t he
Act ive St at e Link PM Support field)
PCI e PLL Gat e Disable Cont rols PCI e PLL gat ing while in L1 or L2 st at es
L1_Act _Ext _Lat ency Defines L1 act ive exit lat ency
L1_Act _Acc_Lat ency Defines L1 act ive accept able exit lat ency
Lat ency_To_Ent er_L1 Defines t he period ( in t he L0s st at e) before t ransit ioning int o an L1 st at e
5. 2. 4. 2 Net w or k I nt er f aces Pow er Management
The 82599 t ransit ions any of t he XAUI int erfaces int o a lowpower st at e in t he following cases:
The respect ive LAN funct ion is in LAN disable mode using LANx_DI S_N pin.
The 82599 is in Dr St at e, APM WoL is disabled for t he port , ACPI wake is disabled for t he port and
pass- t hrough manageabilit y is disabled for t he port .
Use of t he LAN port s for pass- t hrough manageabilit y follows t his behavior:
I f manageabilit y is disabled ( MNG Enable bit in t he EEPROM is cleared) , t hen LAN port s are not
allocat ed for manageabilit y.
I f manageabilit y is enabled:
Power up Following EEPROM read, a single port is enabled for manageabilit y, running at t he
lowest speed support ed by t he int erface. I f APM WoL is enabled on a single port , t he same port
is used for manageabilit y. Ot herwise, manageabilit y prot ocols ( like t eaming) det ermine which
port is used.
D0 st at e Bot h LAN port s are enabled for manageabilit y.

167
D3 and Dr st at es A single port is enabled for manageabilit y, running at t he lowest speed
support ed by t he int erface. I f WoL is enabled on a single port , t he same port is used for
manageabilit y. Ot herwise, manageabilit y prot ocols ( like t eaming) det ermine which port is used.
Enabling a port as a result of t he previous causes an int ernal reset of t he port .
When a XAUI int erface is in lowpower st at e, t he 82599 assert s t he respect ive TX_DI S ( SDP0[ 4] and
SDP1[ 4] ) pins t o enable an ext ernal PHY device t o power down as well.
5.2.5 Pow er St at es
5.2.5.1 D0uni ni t i al i zed St at e
The D0u st at e is a lowpower st at e used aft er PE_RST_N is deassert ed following power up ( cold or
warm) , on hot reset ( in- band reset t hrough PCI e physical layer message) or on D3 exit .
When ent ering D0u, t he 82599 disables wake ups. I f t he APM Mode bit in t he EEPROM' s Cont rol Word 3
is set , t hen APM wake up is enabled.
5.2.5.1.1 Ent r y t o a D0u St at e
D0u is reached from eit her t he Dr st at e ( on deassert ion of int ernal PE_RST_N) or t he D3hot st at e ( by
configurat ion soft ware writ ing a value of 00b t o t he Power St at e field of t he PCI PM regist ers) .
De- assert ion of int ernal PE_RST_N means t hat t he ent ire st at e of t he device is cleared, ot her t han
st icky bit s. St at e is loaded from t he EEPROM, followed by est ablishment of t he PCI e link. Once t his is
done, configurat ion soft ware can access t he device.
On a t ransit ion from D3 t o D0u st at e, t he 82599 requires t hat soft ware perform a full re- init ializat ion of
t he funct ion including it s PCI configurat ion space.
5.2.5.2 D0act i v e St at e
Once memory space is enabled, t he 82599 ent ers an act ive st at e. I t can t ransmit and receive packet s if
properly configured by t he driver. Any APM wake up previously act ive remains act ive. The driver can
deact ivat e APM wake up by writ ing t o t he Wake Up Cont rol ( WUC) regist er, or act ivat e ot her wake up
filt ers by writ ing t o t he Wake Up Filt er Cont rol ( WUFC) regist er.
5.2.5.2.1 Ent r y t o D0a St at e
D0a is ent ered from t he D0u st at e by writ ing a 1b t o t he Memory Access Enable or t he I / O Access
Enable bit of t he PCI Command regist er. The DMA, MAC, and PHY of t he appropriat e LAN funct ion are
enabled.
5.2.5.3 D3 St at e ( PCI - PM D3hot )
The 82599 t ransit ions t o D3 when t he syst em writ es a 11b t o t he Power St at e field of t he PMCSR. Any
wakeup filt er set t ings t hat were enabled before ent ering t his reset st at e are maint ained. Upon
t ransit ioning t o D3 st at e, t he 82599 clears t he Memory Access Enable and I / O Access Enable bit s of t he
PCI Command regist er, which disables memory access decode. I n D3, t he 82599 only responds t o PCI
configurat ion accesses and does not generat e mast er cycles.
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168
Configurat ion and message request s are t he only PCI e TLPs accept ed by a funct ion in t he D3hot st at e.
All ot her received request s must be handled as unsupport ed request s, and all received complet ions can
opt ionally be handled as unexpect ed complet ions. I f an error caused by a received TLP ( such as an
unsupport ed request ) is det ect ed while in D3hot , and report ing is enabled, t he link must be ret urned t o
L0 if it is not already in L0 and an error message must be sent . See sect ion 5.3.1. 4. 1 in t he PCI e Base
Specificat ion.
A D3 st at e is followed by eit her a D0u st at e ( in preparat ion for a D0a st at e) or by a t ransit ion t o Dr
st at e ( PCI - PM D3cold st at e) . To t ransit ion back t o D0u, t he syst em writ es a 00b t o t he Power St at e field
of t he PMCSR. Transit ion t o Dr st at e is t hrough PE_RST_N assert ion.
5.2.5. 3.1 Ent r y t o D3 St at e
Transit ion t o D3 st at e is t hrough a configurat ion writ e t o t he Power St at e field of t he PCI - PM regist ers.
Prior t o t ransit ion from D0 t o t he D3 st at e, t he device driver disables scheduling of furt her t asks t o t he
82599; it masks all int errupt s, it does not writ e t o t he Transmit Descript or Tail regist er or t o t he Receive
Descript or Tail regist er and operat es t he mast er disable algorit hm as defined in Sect ion 5. 2. 5.3.2. I f
wakeup capabilit y is needed, t he driver should set up t he appropriat e wakeup regist ers and t he
syst em should writ e a 1b t o t he PME_En bit of t he PMCSR or t o t he Auxiliary ( AUX) Power PM Enable bit
of t he PCI e Device Cont rol regist er prior t o t he t ransit ion t o D3.
I f all PCI funct ions are programmed int o D3 st at e, t he 82599 brings it s PCI e link int o t he L1 link st at e.
As part of t he t ransit ion int o L1 st at e, t he 82599 suspends scheduling of new TLPs and wait s for t he
complet ion of all previous TLPs it has sent . The 82599 clears t he Memory Access Enable and I / O Access
Enable bit s of t he PCI Command regist er, which disables memory access decode. Any receive packet s
t hat have not been t ransferred int o syst em memory is kept in t he device ( and discarded lat er on D3
exit ) . Any t ransmit packet s t hat have not be sent can st ill be t ransmit t ed ( assuming t he Et hernet link is
up) .
I n preparat ion t o a possible t ransit ion t o D3cold st at e, t he device driver might disable one of t he LAN
port s ( LAN disable) and/ or t ransit ion t he link( s) t o GbE speed ( if support ed by t he net work int erface) .
See Sect ion 5. 2. 4. 2 for a descript ion of net work int erface behavior in t his case.
5.2.5. 3.2 Mast er Di sabl e
Syst em soft ware can disable mast er accesses on t he PCI e link by eit her clearing t he PCI Bus Mast er bit
or by bringing t he funct ion int o a D3 st at e. From t hat t ime on, t he device must not issue mast er
accesses for t his funct ion. Due t o t he full- duplex nat ure of PCI e, and t he pipelined design in t he 82599,
it might happen t hat mult iple request s from several funct ions are pending when t he mast er disable
request arrives. The prot ocol described in t his sect ion insures t hat a funct ion does not issue mast er
request s t o t he PCI e link aft er it s mast er enable bit is cleared ( or aft er ent ry t o D3 st at e) .
Two configurat ion bit s are provided for t he handshake bet ween t he device funct ion and it s driver:
PCI e Mast er Disable bit in t he Device Cont rol ( CTRL) regist er When t he PCI e Mast er Disable bit is
set , t he 82599 blocks new mast er request s by t his funct ion. The 82599 t hen proceeds t o issue any
pending request s by t his funct ion. This bit is cleared on mast er reset ( LAN Power Good all t he way
t o soft ware reset ) t o enable mast er accesses.

169
PCI e Mast er Enable St at us bit s in t he Device St at us regist er Cleared by t he 82599 when t he PCI e
Mast er Disable bit is set and no mast er request s are pending by t he relevant funct ion ( set
ot herwise) . I ndicat es t hat no mast er request s are issued by t his funct ion as long as t he PCI e Mast er
Disable bit is set . The following act ivit ies must end before t he 82599 clears t he PCI e Mast er Enable
St at us bit :
Mast er request s by t he t ransmit and receive engines.
All pending complet ions t o t he 82599 are received.
Not e: The device driver disables any recept ion t o t he Rx queues as described in Sect ion 4. 6. 7.1.
Then t he device driver set s t he PCI e Mast er Disable bit when not ified of a pending mast er
disable ( or D3 ent ry) . The 82599 t hen blocks new request s and proceeds t o issue any
pending request s by t his funct ion. The driver t hen polls t he PCI e Mast er Enable St at us bit .
Once t he bit is cleared, it is guarant eed t hat no request s are pending from t his funct ion.
The driver might t ime out if t he PCI e Mast er Enable St at us bit is not cleared wit hin a given
t ime. Examples for cases t hat t he device might not clear t he PCI e Mast er Enable St at us bit for
a long t ime are cases of flow cont rol, link down, or DMA complet ions not making it back t o
t he DMA block. I n t hese cases, t he driver should check t hat t he Transact ion Pending bit ( bit
5) in t he Device St at us regist er in t he PCI config space is clear before proceeding. I n such
cases t he driver might need t o init iat e t wo consecut ive soft ware reset s wit h a larger delay
t han 1 s bet ween t he t wo of t hem.
The PCI e Mast er Disable bit must be cleared t o enable mast er request t o t he PCI e link. This
bit should be cleared t hrough reset .
5.2.5.4 Dr St at e
Transit ion t o Dr st at e is init iat ed on several occasions:
On syst em power up Dr st at e begins wit h t he assert ion of t he int ernal power det ect ion circuit
( LAN_PWR_GOOD) and ends wit h deassert ion of PE_RST_N.
On t ransit ion from a D0a st at e During operat ion t he syst em can assert PE_RST_N at any t ime. I n
an ACPI syst em, a syst em t ransit ion t o t he G2/ S5 st at e causes a t ransit ion from D0a t o Dr st at e.
On t ransit ion from a D3 st at e The syst em t ransit ions t he device int o t he Dr st at e by assert ing
PCI e PE_RST_N.
Any wakeup filt er set t ings t hat were enabled before ent ering t his reset st at e are maint ained.
The syst em can maint ain PE_RST_N assert ed for an arbit rary t ime. The deassert ion ( rising edge) of
PE_RST_N causes a t ransit ion t o D0u st at e.
While in Dr st at e, t he 82599 can maint ain funct ionalit y ( for WoL or manageabilit y) or can ent er a Dr
Disable st at e ( if no WoL and no manageabilit y) for minimal device power. The Dr Disable mode is
described in t he sect ions t hat follow.
5.2.5.4.1 Dr Di sabl e Mode
The 82599 ent ers a Dr disable mode on t ransit ion t o D3cold st at e when it does not need t o maint ain
any funct ionalit y. The condit ions t o ent er eit her st at e are:
The device ( all PCI funct ions) is in Dr st at e
APM WOL is inact ive for bot h LAN funct ions
Pass- t hrough manageabilit y is disabled
ACPI PME is disabled for all PCI funct ions
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170
Ent ry int o Dr disable is usually done on assert ion of PCI e PE_RST_N. I t can also be possible t o ent er Dr
disable mode by reading t he EEPROM while already in Dr st at e. The usage model for t his lat er case is
on syst em power up, assuming t hat manageabilit y and wake up are not required. Once t he device
ent ers Dr st at e on power up, t he EEPROM is read. I f t he EEPROM cont ent s det ermine t hat t he
condit ions t o ent er Dr disable are met , t he device t hen ent ers t his mode ( assuming t hat PCI e
PE_RST_N is st ill assert ed) .
Exit from Dr disable is t hrough deassert ion of PCI e PE_RST_N.
I f Dr disable mode is ent ered from D3 st at e, t he plat form can remove t he 82599 power. I f t he plat form
removes t he 82599 power, it must remove all power rails from t he device if it needs t o use t his
capabilit y. Exit from t his st at e is t hrough power- up cycle t o t he 82599. Not e t hat t he st at e of t he
TX_DI S ( SDP0[ 4] and SDP1[ 4] ) pins is undefined once power is removed from t he device.
5.2.5. 4.2 Ent r y t o Dr St at e
Dr- ent ry on plat form power up is as follows:
Assert ion of t he int ernal power det ect ion circuit ( LAN_PWR_GOOD) . Device power is kept t o a
minimum by keeping t he XAUI int erfaces in low power.
The EEPROM is t hen read and det ermines device configurat ion.
I f t he APM Enable bit in t he EEPROM' s Cont rol Word 3 is set , t hen APM wake up is enabled ( for each
port independent ly) .
I f t he MNG Enable bit in t he EEPROM word is set , pass- t hrough manageabilit y is not enabled.
Each of t he LAN port s can be enabled if required for WoL or manageabilit y. See Sect ion 5.2. 4. 2 for
exact condit ion t o enable a port .
The PCI e link is not enabled in Dr st at e following syst em power up ( since PE_RST_N is assert ed) .
Ent ry t o Dr st at e from D0a st at e is t hrough assert ion of t he PE_RST_N signal. An ACPI t ransit ion t o t he
G2/ S5 st at e is reflect ed in a device t ransit ion from D0a t o Dr st at e. The t ransit ion can be orderly ( such
as a user select ed a shut down operat ing syst em opt ion) , in which case t he device driver can have a
chance t o int ervene. Or, it can be an emergency t ransit ion ( like power but t on override) , in which case,
t he device driver is not not ified.
Transit ion from D3 st at e t o Dr st at e is done by assert ion of PE_RST_N signal. Prior t o t hat , t he syst em
init iat es a t ransit ion of t he PCI e link from L1 st at e t o eit her t he L2 or L3 st at e ( assuming all funct ions
were already in D3 st at e) . The link ent ers L2 st at e if PCI - PM PME is enabled.
5.2.6 Ti mi ng of Pow er - St at e Tr ansi t i ons
The following sect ions give det ailed t iming for t he st at e t ransit ions. I n t he diagrams t he dot t ed
connect ing lines represent t he 82599 requirement s, while t he solid connect ing lines represent t he
82599 guarant ees.
Not e: The t iming diagrams are not t o scale. The clocks edges are shown t o indicat e running clocks
only and are not used t o indicat e t he act ual number of cycles for any operat ion.

171
5. 2. 6. 1 Tr ansi t i on Fr om D0a To D3 and Back Wi t hout PE_RST_N
5. 2. 6. 2 Tr ansi t i on Fr om D0a To D3 And Back Wi t h PE_RST_N
Not e
1 Writ ing 11b t o t he Power St at e field of t he PMCSR t ransit ions t he 82599 t o D3.
2 The syst em can keep t he 82599 in D3 st at e for an arbit rary amount of t ime.
3 To exit D3 st at e t he syst em writ es 00b t o t he Power St at e field of t he PMCSR.
4 APM wake up or manageabilit y can be enabled based on what is read in t he EEPROM.
5 Aft er reading t he EEPROM, t he LAN port s are enabled and t he 82599 t ransit ions t o D0u st at e.
6 The syst em can delay an arbit rary t ime before enabling memory access.
7
Writ ing a 1b t o t he Memory Access Enable bit or t o t he I / O Access Enable bit in t he PCI Command regist er t ransit ions t he
82599 from D0u t o D0 st at e.
PCIe Reference
Clock
PE_RSTn
PHY Reset
PCIe Link
Reading EEPROM Read EEPROM
DState D3 D0u D0
Wake Up Enabled
Memory Access Enable
L0
D3 write
APM / SMBus Any mode
D0 Write
D0a
2
L1
L0
TX_DIS power-managed
tee
1
3
4
5
6
7
td0mem
PCIe Reference Clock
PE_RSTn
DState
TX_DIS
D0u
D0a
power-managed
PCIe Link
Wakeup Enabled
Dr
Any mode APM/SMBus
D3 write
D0a D3
14
L0 L1 L 2 / L3 L0
1
2
6
12
13
3
4a
4b
11
Internal PCIe Clock (
2.5Ghz)
Internal PwrGd
9
7
8
10
tee
tppg-clkint
tpgtrn
tpgres tpgcfg
tclkpr
tpgdl
tl2clk
tclkpg tPWRGD-CLK
tl2pg
5
L0
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5. 2. 6. 3 Tr ansi t i on Fr om D0a To Dr And Back Wi t hout Tr ansi t i on To D3
Not e
1
Writ ing 11b t o t he Power St at e field of t he PMCSR t ransit ions t he 82599 t o D3. PCI e link t ransit ions t o L1 st at e. Possible
indicat ion t o ext ernal PHYs t o ent er lowpower mode.
2
The syst em can delay an arbit rary amount of t ime bet ween set t ing D3 mode and t ransit ioning t he link t o an L2 or L3
st at e.
3 Following link t ransit ion, PE_RST_N is assert ed.
4
The syst em must assert PE_RST_N before st opping t he PCI e reference clock. I t must also wait t l2clk aft er link t ransit ion
t o L2/ L3 before st opping t he reference clock.
5 On assert ion of PE_RST_N, t he 82599 t ransit ions t o Dr st at e.
6 The syst em st art s t he PCI e reference clock t
PWRGD- CLK
before deassert ion PE_RST_N.
7 The int ernal PCI e clock is valid and st able t
ppg- clkint
from PE_RST_N deassert ion.
8 The PCI e int ernal PWRGD signal is assert ed t clkpr aft er t he ext ernal PE_RST_N signal.
9 Assert ion of int ernal PCI e PWRGD causes t he EEPROM t o be re- read and disables wake up.
10 APM wakeup mode can be enabled based on what is read from t he EEPROM. Ext ernal PHYs are enabled.
11 Link t raining st art s aft er t pgt rn from PE_RST_N deassert ion.
12 A first PCI e configurat ion access can arrive aft er t
pgcfg
13 A first PCI configurat ion response can be sent aft er t pgres from PE_RST_N deassert ion.
14 Writ ing a 1b t o t he Memory Access Enable bit in t he PCI Command regist er t ransit ions t he device from D0u t o D0 st at e.
PCIe Reference Clock
PE_RSTn
DState
TX_DIS
D0u
D0a
power-managed
PCIe Link
Wake Up Enabled
Dr
8
Any mode APM/SMBus
D0a
12
L0 L0
2
3
10
11
1
9
Internal PCI e Clock )
2.5Ghz(
Internal PwrGd ) PLL(
6
4
5
7
tee
tppg-clkint
tpgtrn
tpgres tpgcfg
tclkpr
tpgdl
tclkpg tPWRGD-CLK

173
5. 2. 6. 4 Ti mi ng Requi r ement s
The 82599 requires t he following st art up and power st at e t ransit ions.
Not e
1
The syst em must assert PE_RST_N before st opping t he PCI e reference clock. I t must also wait t l2clk aft er link t ransit ion
t o L2/ L3 before st opping t he reference clock.
2
On assert ion of PE_RST_N, t he 82599 t ransit ions t o Dr st at e and t he PCI e link t ransit ion t o elect rical idle. Possible
indicat ion t o ext ernal PHYs t o ent er lowpower mode.
3 The syst em st art s t he PCI e reference clock t
PWRGD- CLK
before deassert ion PE_RST_N.
4 The int ernal PCI e clock is valid and st able t
ppg- clkint
5 The PCI e int ernal PWRGD signal is assert ed t clkpr aft er t he ext ernal PE_RST_N signal.
6 Assert ion of int ernal PCI e PWRGD causes t he EEPROM t o be re- read and disables wake up.
7 APM wakeup mode can be enabled based on what is read from t he EEPROM.
8 Aft er reading t he EEPROM, ext ernal PHYs are enabled.
9 Link t raining st art s aft er t pgt rn from PE_RST_N deassert ion.
10 A first PCI e configurat ion access can arrive aft er t
pgcfg
11 A first PCI configurat ion response can be sent aft er t pgres from PE_RST_N deassert ion
12 Writ ing a 1b t o t he Memory Access Enable bit in t he PCI Command regist er t ransit ions t he device from D0u t o D0 st at e.
Tabl e 5. 2. St ar t Up and Pow er St at e Tr ansi t i ons
t
xog
Xosc st able from power
st able
10 ms
t
PWRGD- CLK
PCI e clock valid t o PCI e
power good
100 s - According t o PCI e specificat ion.
t
PVPGL
Power rails st able t o PCI e
PE_RST_N inact ive
100 ms - According t o PCI e specificat ion.
t
pgcfg
Ext ernal PE_RST_N signal
t o first configurat ion cycle
100 ms According t o PCI e specificat ion.
t d0mem
Device programmed from
D3h t o D0 st at e t o next
device access
10 ms According t o PCI power management specificat ion.
t l2pg
L2 link t ransit ion t o
PE_RST_N assert ion
0 ns According t o PCI e specificat ion.
t l2clk
L2 link t ransit ion t o removal
of PCI e reference clock
t clkpg
PE_RST_N assert ion t o
removal of PCI e reference
clock
t pgdl PE_RST_N assert ion t ime 100 s According t o PCI e specificat ion.
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5. 2.6. 5 Ti mi ng Guar ant ees
The 82599 guarant ees t he following st art up and power st at e t ransit ion relat ed t iming paramet ers.
5.3 Wak e Up
5. 3. 1 Adv anced Pow er Management Wak e Up
Advanced Power Management Wake Up, or APM Wake Up, was previously known as Wake on LAN
( WoL) . I t is a feat ure t hat has exist ed in t he 10/ 100 Mb/ s NI Cs for several generat ions. The basic
premise is t o receive a broadcast or unicast packet wit h an explicit dat a pat t ern, and t hen t o assert a
signal t o wake up t he syst em. I n t he earlier generat ions, t his was accomplished by using a special
signal t hat ran across a cable t o a defined connect or on t he mot herboard. The NI C would assert t he
signal for approximat ely 50 ms t o signal a wake up. The 82599 uses ( if configured t o) an in- band
PM_PME message for t his.
At power up, t he 82599 reads t he APM Enable bit from t he EEPROM int o t he APM Enable ( APME) bit s of
t he GRC regist er. This bit cont rol t he enabling of APM wake up.
When APM wake up is enabled, t he 82599 checks all incoming packet s for Magic Packet s. See
Sect ion 18.1. 3 for a definit ion of Magic Packet s.
Once t he 82599 receives a mat ching Magic Packet , it :
Set s t he PME_St at us bit in t he PMCSR.
Assert s PE_WAKE_N.
I ssues a PM_PME message.
APM wake up is support ed in all power st at es and only disabled if a subsequent EEPROM read result s in
t he APM Wake Up bit being cleared.
5. 3. 2 ACPI Pow er Management Wak e Up
The 82599 support s ACPI power management - based wake up. I t can generat e syst em wakeup event s
from t hree sources:
Recept ion of a Magic Packet .
Tabl e 5.3. St ar t - up and Pow er St at e Tr ansi t i on Ti mi ng Par amet er s
t
xog
Xosc st able from power
st able
10 ms
t
ppg
I nt ernal power good delay
from valid power rail
35 ms 35 ms
t
ee
EEPROM read durat ion 20 ms
t
ppg- clkint
PCI e PE_RST_N t o int ernal
PLL lock
- 50 s
t
clkpr
I nt ernal PCI e PWGD from
ext ernal PCI e PE_RST_N
50 s
t pgt rn
PCI e PE_RST_N t o st art of
link t raining
20 ms According t o PCI e specificat ion.
t pgres
Ext ernal PE_RST_N t o
response t o first
configurat ion cycle
1 second According t o PCI e specificat ion.

175
Recept ion of a net work wakeup packet .
Det ect ion of a link change of st at e.
Act ivat ing ACPI power management wake up requires t he following st eps:
The operat ing syst em ( at configurat ion t ime) writ es a 1b t o t he PME_En bit of t he PMCSR ( bit
8) .
The driver programs t he Wake Up Filt er Cont rol ( WUFC) regist er t o indicat e t he packet s it needs
t o wake up and supplies t he necessary dat a t o t he I Pv4/ v6 Address Table ( I P4AT, I P6AT) ,
Flexible Host Filt er Table ( FHFT) regist ers. I t can also set t he Link St at us Change Wake Up
Enable ( LNKC) bit in t he WUFC regist er t o cause wake up when t he link changes st at e. I f t he
SW driver enables any of t he wakeup opt ions above it should also set t he WUC. PME_En bit as
well.
Once t he 82599 wakes t he syst em, t he driver needs t o clear WUFC unt il t he next t ime t he
syst em goes t o a low power st at e wit h wake up.
Normally, aft er enabling wake up, t he operat ing syst em writ es ( 11b) t o t he lower t wo bit s of t he PMCSR
t o put t he 82599 int o lowpower mode.
Once wake up is enabled, t he 82599 monit ors incoming packet s, first filt ering t hem according t o it s
st andard address filt ering met hod, t hen filt ering t hem wit h all of t he enabled wakeup filt ers. I f a
packet passes bot h t he st andard address filt ering and at least one of t he enabled wakeup filt ers, t he
82599:
Set s t he PME_St at us bit in t he PMCSR.
I f t he PME_En bit in t he PMCSR is set , assert s PE_WAKE_N.
I f enabled, a link st at e change wake up causes similar result s, set t ing PME_St at us, assert ing
PE_WAKE_N when t he link goes up or down.
PE_WAKE_N remains assert ed unt il t he operat ing syst em eit her writ es a 1b t o t he PME_St at us bit of
t he PMCSR regist er or writ es a 0b t o t he PME_En bit .
Aft er receiving a wakeup packet or link change event , t he 82599 ignores any subsequent wakeup
packet s or link change event s unt il t he driver clears t he WUS regist er.
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5.3.3 Wak e- Up Pack et s
The 82599 support s various wakeup packet s using t wo t ypes of filt ers:
Pre- defined filt ers
Flexible filt ers
Each of t hese filt ers are enabled if t he corresponding bit in t he WUFC regist er is set t o 1b.
Not e: When VLAN filt ering is enabled, packet s t hat passed any of t he receive wakeup filt ers should
only cause a wakeup event if it also passed t he VLAN filt ering.
5. 3. 3. 1 Pr e- Def i ned Fi l t er s
The following packet s are support ed by t he 82599' s pre- defined filt ers:
Direct ed Packet ( including exact , mult icast indexed, and broadcast )
Magic Packet
ARP/ I Pv4 Request Packet
Direct ed I Pv4 Packet
Direct ed I Pv6 Packet
Each of t hese filt ers are enabled if t he corresponding bit in t he WUFC regist er is set t o 1b.
The explanat ion of each filt er includes a t able showing which byt es at which offset s are compared t o
det ermine if t he packet passes t he filt er. Bot h VLAN frames and LLC/ SNAP can increase t he given
offset s if t hey are present .
5.3.3. 1.1 Di r ect ed Ex act Pack et
The 82599 generat es a wakeup event aft er receiving any packet whose dest inat ion address mat ches
one of t he 128 valid programmed receive addresses if t he Direct ed Exact Wake Up Enable bit is set in
t he Wake Up Filt er Cont rol ( WUFC. EX) regist er.
5.3.3. 1.2 Di r ect ed Mul t i cast Pack et
For mult icast packet s, t he upper bit s of t he incoming packet ' s dest inat ion address index a bit vect or, t he
Mult icast Table Array ( MTA) t hat indicat es whet her t o accept t he packet . I f t he Direct ed Mult icast Wake
Up Enable bit set in t he Wake Up Filt er Cont rol ( WUFC. MC) regist er and t he indexed bit in t he vect or is
one, t hen t he 82599 generat es a wakeup event . The exact bit s used in t he comparison are
programmed by soft ware in t he Mult icast Offset field of t he Mult icast Cont rol ( MCSTCTRL. MO) regist er.
Of f set
# of
by t es
Fi el d Val ue Act i on Comment
0 6 Dest inat ion Address Compare Mat ch any pre- programmed address.
Of f set
# of
by t es
0 6 Dest inat ion Address Compare See previous paragraph.

177
5.3.3.1.3 Br oadcast
I f t he Broadcast Wake Up Enable bit in t he Wake Up Filt er Cont rol ( WUFC. BC) regist er is set , t he 82599
generat es a wakeup event when it receives a broadcast packet .
5.3.3.1.4 Magi c Pack et
A Magic Packet ' s dest inat ion address must mat ch t he address filt ering enabled in t he configurat ion
regist ers wit h t he except ion t hat broadcast packet s are considered t o mat ch even if t he Broadcast
Accept bit of t he Receive Cont rol ( FCTRL. BAM) regist er is 0b. I f APM wake up is enabled in t he EEPROM,
t he 82599 st art s up wit h t he Receive Address Regist er 0 ( RAH0, RAL0) loaded from t he EEPROM. This is
t o enable t he 82599 t o accept packet s wit h t he mat ching I EEE address before t he driver comes up.
Not e: Accept ing broadcast Magic Packet s for wakeup purposes when t he Broadcast Accept bit of
t he Receive Cont rol ( FCTRL. BAM) regist er is 0b is a change from 82544, which init ialized
FCTRL. BAM t o 1b if APM was enabled in t he EEPROM, but t hen required t hat bit t o be 1b t o
accept broadcast Magic Packet s, unless broadcast packet s passed anot her perfect or
mult icast filt er.
5.3.3.1.5 ARP/ I Pv 4 Request Pack et
The 82599 support s recept ion of ARP request packet s for wake up if t he ARP bit is set in t he WUFC
regist er. Four I Pv4 addresses are support ed, which are programmed in t he I Pv4 Address Table ( I P4AT) .
A successfully mat ched packet must pass L2 address filt ering, a prot ocol t ype of 0x0806, an ARP
opcode of 0x01, and one of t he four programmed I Pv4 addresses. The 82599 also handles ARP request
packet s t hat have VLAN t agging on bot h Et hernet I I and Et hernet SNAP t ypes.
Of f set
# of
by t es
0 6 Dest inat ion Address FF* 6 Compare
Of f set
# of
By t es
0 6 Dest inat ion Address Compare
MAC header processed by main address
filt er.
6 6 Source Address Skip
12 4 Possible VLAN Tag Skip
12 8 Possible Len/ LLC/ SNAP Header Skip
12 2 Type Skip
Any 6 Synchronizing St ream FF* 6+ Compare
any+ 6 96 16 Copies of Node Address A* 16 Compare
Compar ed t o Receive Address Regist er 0
( RAH0, RAL0)
Of f set
# of
By t es
filt er.
12 4 Possible VLAN Tag Compare
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5.3.3. 1.6 Di r ect ed I Pv4 Pack et
The 82599 support s recept ion of direct ed I Pv4 packet s for wake up if t he I PV4 bit is set in t he WUFC
regist er. Four I Pv4 addresses are support ed, which are programmed in t he I Pv4 Address Table ( I P4AT) .
A successfully mat ched packet must pass L2 address filt ering, a prot ocol t ype of 0x0800, and one of t he
four programmed I Pv4 addresses. The 82599 also handles direct ed I Pv4 packet s t hat have VLAN
t agging on bot h Et hernet I I and Et hernet SNAP t ypes.
12 2 Type 0x0806 Compare ARP.
14 2 Hardware Type 0x0001 Compare
16 2 Prot ocol Type 0x0800 Compare
18 1 Hardware Size 0x06 Compare
19 1 Prot ocol Address Lengt h 0x04 Compare
20 2 Operat ion 0x0001 Compare
22 6 Sender Hardware Address - I gnore
28 4 Sender I P Address - I gnore
32 6 Target Hardware Address - I gnore
38 4 Target I P Address I P4AT Compare Can mat ch any of four values in I P4AT.
Of f set
# of
Byt es
filt er.
12 2 Type 0x0800 Compare I P
14 1 Version/ HDR lengt h 0x4X Compare Check I Pv4.
15 1 Type of Service - I gnore
16 2 Packet Lengt h - I gnore
18 2 I dent ificat ion - I gnore
20 2 Fragment I nformat ion - I gnore
22 1 Time t o Live - I gnore
23 1 Prot ocol - I gnore
24 2 Header Checksum - I gnore
26 4 Source I P Address - I gnore
30 4 Dest inat ion I P Address I P4AT Compare Can mat ch any of four values in I P4AT.
Of f set
# of
By t es

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5. 3.3. 1.7 Di r ect ed I Pv 6 Pack et
The 82599 support s recept ion of direct ed I Pv6 packet s for wake up if t he I PV6 bit is set in t he WUFC
regist er. One I Pv6 address is support ed, which is programmed in t he I Pv6 Address Table ( I P6AT) . A
successfully mat ched packet must pass L2 address filt ering, a prot ocol t ype of 0x0800, and t he
programmed I Pv6 address. The 82599 also handles direct ed I Pv6 packet s t hat have VLAN t agging on
bot h Et hernet I I and Et hernet SNAP t ypes.
5. 3. 3. 2 Fl ex i bl e Fi l t er
The 82599 support s a t ot al of six host flexible filt ers. Each filt er can be configured t o recognize any
arbit rary pat t ern wit hin t he first 128 byt es of t he packet . To configure t he flexible filt er, soft ware
programs t he required values int o t he Flexible Host Filt er Table ( FHFT) . These cont ain separat e values
for each filt er. Soft ware must also enable t he filt er in t he WUFC regist er, and enable t he overall wakeup
funct ionalit y must be enabled by set t ing t he PME_En bit in t he PMCSR or t he WUC regist er.
Once enabled, t he flexible filt ers scan incoming packet s for a mat ch. I f t he filt er encount ers any byt e in
t he packet where t he mask bit is one and t he byt e doesn' t mat ch t he byt e programmed in FHFT t hen
t he filt er fails t hat packet . I f t he filt er reaches t he required lengt h wit hout failing t he packet , it passes
t he packet and generat es a wakeup event . I t ignores any mask bit s set t o one beyond t he required
lengt h.
Packet t hat passed a wakeup flexible filt er should cause a wakeup event only if it is direct ed t o t he
82599 ( passed L2 and VLAN filt ering) .
Not e: The flexible filt ers are t emporarily disabled when read from or writ t en t o by t he host . Any
packet received during a read or writ e operat ion is dropped. Filt er operat ion resumes once
t he read or writ e access complet es.
The following packet s are list ed for reference purposes only. The flexible filt er could be used t o filt er
t hese packet s.
Of f set
# of
By t es
filt er.
12 2 Type 0x0800 Compare I P.
14 1 Version/ Priorit y 0x6X Compare Check I Pv6.
15 3 Flow Label - I gnore
18 2 Payload Lengt h - I gnore
20 1 Next Header - I gnore
21 1 Hop Limit - I gnore
22 16 Source I P Address - I gnore
38 16 Dest inat ion I P Address I P6AT Compare Mat ch value in I P6AT.
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5.3.3. 2.1 I PX Di agnost i c Responder Request Pack et
An I PX diagnost ic responder request packet must cont ain a valid Et hernet MAC address, a prot ocol t ype
of 0x8137, and an I PX diagnost ic socket of 0x0456. I t can also include LLC/ SNAP headers and VLAN
t ags. Since filt ering t his packet relies on t he flexible filt ers, which use offset s specified by t he operat ing
syst em direct ly, t he operat ing syst em must account for t he ext ra offset LLC/ SNAP Headers and VLAN
t ags.
5.3.3. 2.2 Di r ect ed I PX Pack et
A valid direct ed I PX packet cont ains t he st at ion' s Et hernet MAC address, a prot ocol t ype of 0x8137, and
an I PX node address t hat equals t o t he st at ion' s Et hernet MAC address. I t can also include LLC/ SNAP
headers and VLAN t ags. Since filt ering t his packet relies on t he flexible filt ers, which use offset s
specified by t he operat ing syst em direct ly, t he operat ing syst em must account for t he ext ra offset LLC/
SNAP headers and VLAN t ags.
5.3.3. 2.3 I Pv6 Nei ghbor Di scov er y Fi l t er
I n I Pv6, a neighbor discovery packet is used for address resolut ion. A flexible filt er can be used t o check
for a neighborhood discovery packet .
Of f set
# of
By t es
12 2 Type 0x8137 Compare I PX.
14 16 Some I PX I nformat ion - I gnore
30 2 I PX Diagnost ic Socket 0x0456 Compare
Of f set
# of
By t es
filt er.
12 2 Type 0x8137 Compare I PX.
14 10 Some I PX I nformat ion - I gnore
24 6 I PX Node Address
Receive
Address 0
Compare Must mat ch Receive Address 0.

181
5.3.4 Wak e Up and Vi r t ual i zat i on
When operat ing in a virt ualized environment , all wakeup capabilit ies are managed by a single ent it y
( such as t he VMM or an I OVM) . I n an I OV archit ect ure, t he physical driver cont rols wake up and none of
t he Virt ual Machines ( VMs) has direct access t o t he wakeup regist ers. The wakeup regist ers are not
replicat ed.
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Non- Vol at i l e Memor y Map I nt el

183
6. 0 Non- Vol at i l e Memor y Map
6.1 EEPROM Gener al Map
The following t able list s t he EEPROM map used by t he 82599. This t able list s common modules for t he
EEPROM including: hardware point ers, soft ware and firmware. Blocks are det ailed in t he following
sect ions. All addresses and point ers in t his t able are absolut e in word unit s.
Wor d Addr ess
Used
By
Fi el d Name LAN 0 / 1 Reser v ed
0x00 HW EEPROM Cont rol Word 1 Sect ion 6. 3. 2. 1 Shared Logic
0x03 HW PCI e Analog Configurat ion Module Point er Sect ion 6. 3. 3 Shared Logic
0x04 HW Core 0 Analog Configurat ion Module Point er Sect ion 6. 3. 4 Port 0
0x05 HW Core 1 Analog Configurat ion Module Point er Sect ion 6. 3. 4 Port 1
0x06 HW PCI e General Configurat ion Module Point er Sect ion 6. 3. 5 Shared Logic
0x07 HW PCI e Configurat ion Space 0 Module Point er Sect ion 6. 3. 6 Funct ion 0
0x08 HW PCI e Configurat ion Space 1 Module Point er Sect ion 6. 3. 6 Funct ion 1
0x09 HW LAN Core 0 Module Point er Sect ion 6. 3. 7 Port 0
0x0A HW LAN Core 1 Module Point er Sect ion 6. 3. 7 Port 1
0x0B HW MAC 0 Module Point er Sect ion 6. 3. 8 Port 0
0x0C HW MAC 1 Module Point er Sect ion 6. 3. 8 Port 1
0x0D HW CSR 0 Aut o Configurat ion Module Point er Sect ion 6. 3. 9 Port 0
0x0E HW CSR 1 Aut o Configurat ion Module Point er Sect ion 6. 3. 9 Port 1
0x0F FW Firmware Module Point er Sect ion 6. 4 FW
0x10 0x14 SW SW Compat ibilit y Module Sect ion 6. 2. 1 SW
0x15 0x16 SW PBA Byt es 1. . . 4 Sect ion 6. 2. 2 SW
0x17 SW iSCSI Boot Configurat ion St art Address Sect ion 6. 2. 3 SW
0x18 0x27 SW Soft ware Reserved SW
0x28 SW SAN MAC Addresses Point er SW
0x29 - 0x2E SW Soft ware Reserved SW
0x2F OEM VPD Point er Sect ion 6. 2. 4 Shared Logic
0x30 0x36 PXE PXE Word 0 ( Soft ware Use) Configurat ion Sect ion 6. 2. 5 SW
0x37 SW Alt ernat e Et hernet MAC Addresses Point er Sect ion 6. 2. 6 SW
0x39 0x3E HW Hardware Reserved Reserved
0x3F SW Soft ware Checksum, Words 0x00 0x3F Shared Logic
I nt el
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184
6.2 EEPROM Sof t w ar e
6.2.1 SW Compat i bi l i t y Modul e Wor d Addr ess 0x 10- 0x 14
Five words in t he EEPROM image are reserved for compat ibilit y informat ion. New bit s wit hin t hese fields
are defined as t he need arises for det ermining soft ware compat ibilit y bet ween various hardware
revisions.
6. 2. 2 PBA Number Modul e Wor d Addr ess 0x 15- 0x 16
The nine- digit Print ed Board Assembly ( PBA) number used for I nt el manufact ured Net work I nt erface
Cards ( NI Cs) is st ored in t he EEPROM.
Not e t hat t hrough t he course of hardware ECOs, t he suffix field is increment ed. The purpose of t his
informat ion is t o enable cust omer support ( or any user) t o ident ify t he revision level of a product .
Net work driver soft ware should not rely on t his field t o ident ify t he product or it s capabilit ies.
Current PBA numbers have exceeded t he lengt h t hat can be st ored as hex values in t hese t wo words.
For t hese PBA numbers t he high word is a flag ( 0xFAFA) indicat ing t hat t he PBA is st ored in a separat e
PBA block. The low word is a point er t o a PBA block.
The PBA block is point ed t o by word 0x16.
The PBA block cont ains t he complet e PBA number including t he dash and t he first digit of t he 3- digit
suffix. For example:
Older PBA numbers st art ing wit h ( A, B, C, D, E) are st ored direct ly in words 0x15 and 0x16. The dash
it self is not st ored nor is t he first digit of t he 3- digit suffix, as it is always 0b for relevant product s.
6.2.3 i SCSI Boot Conf i gur at i on Wor d Addr ess 0x 17
The iSCSI Boot configurat ion module is locat ed using t he Word point er iSCSI Boot Configurat ion
Address field in word 0x17. The block lengt h is embedded in t he iSCSI Boot module.
PBA Number Wor d 0x 15 Wor d 0x 16
G23456- 003 FAFA Point er t o PBA Block
Wor d Of f set Descr i pt i on Reser v ed
0x0 Lengt h in words of t he PBA block ( default 0x6) .
0x1 . . . 0x5 PBA number st ored in hexadecimal ASCI I values.
PBA Number Wor d Of f set 0 Wor d Of f set 1 Wor d Of f set 2 Wor d Of f set 3 Wor d Of f set 4 Wor d Of f set 5
G23456- 003 0006 4732 3334 3536 2D30 3033
PBA Number By t e 1 By t e 2 By t e 3 By t e 4
123456- 003 12 34 56 03

185
6. 2. 4 VPD Modul e Poi nt er Wor d Addr ess 0x 2F
The Vit al Product Dat a ( VPD) module is locat ed using t he Word point er VPD Point er field in word 0x2F.
The block lengt h is embedded in t he VPD module. The VPD sect ion size is usually 64 words, and is
init ialized t o 0x0 or 0xFFFF. Cust omers writ e t heir own dat a in t his module. During run t ime t his module
is accessible t hrough t he VPD capabilit y in t he PCI configurat ion space.
6.2.5 EEPROM PXE Modul e Wor d Addr ess 0x 30- 0x 36
Words 0x30 t hrough 0x36 are reserved for configurat ion and version values used by PXE code.
The configurat ion of t he Boot Agent soft ware is cont rolled by several words in t he EEPROM. The main
set up opt ions for Port 0 are st ored in t his word. These opt ions are t hose t hat can be changed by t he
user using t he Cont rol- S set up menu.
6. 2. 6 Al t er nat e Et her net MAC Addr ess Wor d Addr ess 0x 37
This word is used as a point er t o an EEPROM block t hat cont ains t he space for t wo MAC addresses. The
first t hree words of t he EEPROM block are used t o st ore t he MAC address for t he first port ( PCI Funct ion
0) . The second t hree words of t he EEPROM block is used t o st ore t he MAC address for t he second port
( PCI Funct ion 1) . I nit ial and default values in t he EEPROM block should be set t o 0xFFFF ( for bot h
addresses) indicat ing t hat no alt ernat e MAC address is present . See Sect ion 4.6. 13 for more det ails.
Not e: Word 0x37 must be set t o 0xFFFF if alt ernat e MAC addresses are not used. Also, alt ernat e
MAC addresses are ignored by hardware and require specific soft ware support for act ivat ion.
6.2.7 Check sum Wor d Cal cul at i on ( Wor d 0x 3F)
The checksum word ( 0x3F) is used t o ensure t hat t he base EEPROM image is a valid image. The value
of t his word should be calculat ed such t hat aft er adding all t he words ( 0x00: 0x3F) , including t he
checksum word it self, t he sum should be 0xBABA. This word is used st rict ly by soft ware. Hardware does
not calculat e or check it s cont ent but inst ead checks t he Signat ure field in EEPROM Cont rol Word 1.
The first 63 words of t he EEPROM have a collect ion of point ers t o ot her sect ions of t he EEPROM. To
ensure t he int egrit y of t he addit ional configurat ion paramet ers, t heir cont ent should be included in t he
EEPROM checksum word at offset 0x3F. As a result , t he new algorit hm for det ermining t he checksum is
as follows:
Wor d Addr ess Descr i pt i on Reser ved
0x30 PXE Word 0 ( Soft ware Use) Configurat ion
0x31 PXE Word 1 ( Soft ware Use) Configurat ion
0x32 PXE Word ( Soft ware Use) PXE Version
0x33 PXE Word ( Soft ware Use) EFI Version
0x34 0x36 Addit ional PXE Reserved words ( Soft ware Use)
Wor d Of f set Descr i pt i on Reser ved
0x0 . . . 0x2 Alt ernat e Et hernet MAC Address 1 ( port 0)
0x3 . . . 0x5 Alt ernat e Et hernet MAC Address 2 ( port 1)
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186
1. Perform an EEPROM checksum of t he first 63 words at 0x0- 0x3E.
2. St art ing wit h word offset 0x03 ( PCI E_ANALOG_PTR) read t he point er value.
3. I f t he value of t he point er is 0x0 or 0xFFFF t hen move on t o t he next point er.
4. I f t he point er has a value, t hen read t he cont ent of where t he point er point s t o.
For example, if t he point er is 0x308, read t he value at word offset 0x308. The value in t he first word
point ed t o is t he lengt h of t hat part icular configurat ion dat a sect ion. Not e t hat t he lengt h value is NOT
added t o t he checksum value. I f t he value at 0x308 was 5, dont add 5 t o t he checksum value. I nst ead
t he lengt h is used t o det ermine how many words aft er t he count value should be added t o t he
checksum. I n t his example, 5 words are added t o t he checksum, st art ing at word offset 0x309. This
same logic applies t o t he point ers in locat ions 0x4 t hrough 0xE. The result of t he checksum is t hen
subt ract ed from 0xBABA and compared t o t he value at word offset 0x3F. I f t he values mat ch t hen t he
checksum is valid, if not , t hen t he checksum is invalid.
The checksum word ( 0x3F) is used t o ensure t hat t he base EEPROM image is a valid image. The
following document s t he calculat ion.
#define IXGBE_EEPROM_CHECKSUM 0x3F
#define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_PCIE_ANALOG_PTR 03
#define IXGBE_FW_PTR 0F
static u16 ixgbe_eeprom_calc_checksum(struct ixgbe_hw *hw)
{
u16 i;
u16 j;
u16 checksum = 0;
u16 length = 0;
u16 pointer = 0;
u16 word = 0;
/* Include 0x0-0x3F in the checksum */
for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
if (ixgbe_eeprom_read(hw, i, &word) != IXGBE_SUCCESS) {
DEBUGOUT("EEPROM read failed\n");
break;
}
checksum += word;
}
/* Include all data from pointers except for the fw pointer */
for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
ixgbe_eeprom_read(hw, i, &pointer);
/* Make sure the pointer seems valid */
if (pointer != 0xFFFF && pointer != 0) {
ixgbe_eeprom_read(hw, pointer, &length);

187
if (length != 0xFFFF && length != 0) {
for (j = pointer+1; j <= pointer+length; j++) {
ixgbe_eeprom_read(hw, j, &word);
checksum += word;
}
}
}
}
checksum = (u16)IXGBE_EEPROM_SUM checksum;
return checksum;
}
6. 2. 8 SAN MAC Addr esses Poi nt er Wor d Addr ess 0x 28
Word 0x28 point s t o t he Permanent SAN MAC Address block used for FCoE ( SPMA and FPMA) and DCB.
6. 3 EEPROM Har dw ar e Sect i ons
This module cont ains address cont rol words and hardware point ers indicat ed as HW in t he t able of
Sect ion 6.1.
6.3.1 EEPROM Har dw ar e Sect i on Aut o- Load Sequence
The following t able list s sect ions of aut o- read following device reset event s.
Wor d Of f set Descr i pt i on Reser ved
0x0 . . . 0x2 SAN ( FCoE) MAC Address 1 ( port 0)
0x3 . . . 0x5 SAN ( FCoE) MAC Address 1 ( port 1)
Tabl e 6. 1. EEPROM Sect i on Aut o- Read
LAN_PWR
_GOOD
PCI e Reset
or PCI e
I nband
Reset
D3 t o D0
t r ansi t or
FLR ( per
por t )
SW Reset
( per por t )
Li nk Reset
( per por t )
For ce TCO
PCI e Analog Configurat ion X
PCI e General Configurat ion X
PCI e Funct ion 0/ 1 Config Space
( for each LAN port )
X X
LAN Core and CSRs ( for each
LAN port )
X X X X X
MAC Module ( for each LAN port ) X ( 1) X ( 2) X ( 2) X ( 2) X
1. The MAC module is aut o- read only if manageabilit y or wake up are enabled.
2. The MAC module is aut o- read only if t he manageabilit y unit is not enabled.
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6. 3. 2 EEPROM I ni t Modul e
The init sect ion ( EEPROM cont rol word 0x1, 0x2, and 0x38) are read aft er a LAN_PWR_GOOD reset and
PCI e Reset .
6. 3.2. 1 EEPROM Cont r ol Wor d 1 Addr ess 0x 00
6. 3.2. 2 EEPROM Cont r ol Wor d 2 Addr ess 0x 01
Bi t s Name Def aul t Descr i pt i on Reser v ed
15: 12 Reserved 0x0 Reserved
11: 8 EEPROM Size 0010b
These bit s indicat e t he EEPROMs act ual size. Mapped t o
EEC. EE_Size ( see field definit ion in t he EEC regist er sect ion) .
7: 6 Signat ure 01b
The Signat ure field indicat es t o t he 82599 t hat t here is a valid
EEPROM present . I f t he Signat ure field is not 01b, t he ot her bit s in
t his word are ignored, no furt her EEPROM read is performed, and
t he default values are used for t he configurat ion space I Ds.
5 MNG Enable 0b
Manageabilit y Enable. When set , indicat es t hat t he manageabilit y
block is enabled. When cleared, t he manageabilit y block is disabled
( clock gat ed) .
Mapped t o GRC. MNG_EN
4 EEPROM Prot ect ion 0b I f set t o 1, EEPROM prot ect ion schemes are enabled.
3: 0 HEPSize 0b
Hidden EEPROM Block Size. This field defines t he EEPROM area
accessible only by manageabilit y firmware. I t can also be used t o
st ore secured dat a and ot her manageabilit y funct ions. The size in
byt es of t he secured area equals:
0 byt es ( if HEPSize equals zero) , or 2^ HEPSize byt es ( 2 byt es, 4
byt es, 32 KB. )
15: 7 Reser ved 0x0 Reserved
6 Core KR PLL Gat e Disable 0b
When set disable t he gat ing of t he Core KR_PLL in device low
power st at es and Non- KR Modes
Not e: I n case KR_Dis bit is set , KR- PLL is disabled regardless
t he value of t his bit
5: 3 Reserved 001b Reserved
2 Core XAUI Gat e Disable 0b
When set disables t he gat ing of t he Core XAUI PLL in device
low power st at es and Non-XAUI Modes.
1 Core Clocks Gat e Disable 0b
During nominal operat ion t his bit should be zero enabling core
clock gat ing.
When set disables t he gat ing of t he core clock in low power
st at e. Set t ing t his bit also has side affect s disabling aut o link
down ( when bot h MNG and WOL are disabled) and also keeps
t he LEDs act ive.
0 PCI e PLL Gat e Disable 0b When set disables t he gat ing of t he PCI e PLL in L1/ 2 st at es.

189
6.3.2.3 EEPROM Cont r ol Wor d 3 Addr ess 0x 38
Not e: Bit s 1: 0 should not be set if t he respect ive port is disabled by PCI e Cont rol 2 word bit s 1: 0.
6.3.3 PCI e Anal og Conf i gur at i on Modul e
These sect ions are loaded only aft er LAN_PWR_GOOD only. These sect ions cont ain t he analog default
configurat ions for t he 82599' s PCI e analog part s. Word 0x3 is t he point er for t his sect ion ( t he EEPROM
address, in words) .
The st ruct ure of t his sect ion is list ed in t he following t able.
6.3. 3.1 Sect i on Lengt h Of f set 0x 00
The sect ion lengt h word cont ains t he lengt h of t he sect ion in words. Not e t hat sect ion lengt h does not
include a count for t he sect ion lengt h word.
6.3. 3.2 PCI e Anal og Addr ess Of f set 0x 01, 0x 03, 0x 05. . .
Each odd offset word in t he PCI e analog sect ion is t he regist er address. The PCI e analog regist ers are 2
words wide wit h a 12- bit address widt h. Bit s 11: 2 are t he regist er address ( in Dwords) and bit 1 select
t he upper/ lower word of t he Dword regist er.
6.3.3.3 PCI e Anal og Dat a Of f set 0x 02, 0x 04, 0x 06...
Each even offset word in t he PCI e analog sect ion is t he regist er dat a. Aft er reading a pair of address
word and dat a word, t he regist er specified in t he address word is loaded wit h t he dat a from t he dat a
word.
1 APM Enable Port 1 0b
I nit ial value of advanced power management wake up enable
in t he General Receive Cont rol regist er ( GRC. APME) . Mapped
t o GRC. APME of port 1.
I f t he LAN PCI disable bit in t he NVM is set for Port 1, t hen t he
APM bit must be cleared.
0 APM Enable Port 0 0b
I nit ial value of advanced power management wake up enable
in t he General Receive Cont rol regist er ( GRC. APME) . Mapped
t o GRC. APME of port 0.
I f t he LAN PCI disable bit in t he NVM is set for Port 0, t hen t he
APM bit must be cleared.
Wor d Of f set Descr i pt i on
0x0 Sect ion Lengt h
0x1 PCI e Analog Address 1
0x2 PCI e Analog Dat a 1
0x3 PCI e Analog Address 2
0x4 PCI e Analog Dat a 2
.
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6.3.4 Cor e 0/ 1 Anal og Conf i gur at i on Modul es
These modules are loaded aft er LAN_PWR_GOOD only. They cont ain t he analog default configurat ions
for t he 82599' s XAUI / KR analog part s. Words 0x4- 0x5 are t he point ers for t hese sect ions ( t he EEPROM
address, in words) .
The st ruct ure of all sect ions is similar t o t he following st ruct ure.
6.3.4. 1 Sect i on Lengt h Of f set 0x 00
6. 3.4. 2 Dat a and Addr ess Wor ds Of f set 0x 01, 0x 02, 0x 03. . .
Each word in t he analog configurat ion sect ion has t he same st ruct ure: bit s 15: 8 are t he regist er
address and bit s 7: 0 are t he regist er s dat a. The analog regist ers are eight bit s wide wit h an 8- bit
address widt h. Aft er reading t he EEPROM word, t he regist er specified in bit s 15: 8 is loaded wit h t he
dat a from bit s 7: 0.
6.3.5 PCI e Gener al Conf i gur at i on Modul e
This sect ion is loaded aft er a PCI e Reset . I t cont ains general configurat ion for t he PCI e int erface ( not
funct ion specific) and is point ed t o by word 0x06 in t he EEPROM ( full- byt e address; must be word
aligned) .

Wor d of f set Bi t s Descr i pt i on Reser v ed
0x0 15: 0 Sect ion Lengt h Sect ion 6. 3. 4. 1.
0x1 15: 8 Configurat ion Address Sect ion 6. 3. 4. 2
0x1 7: 0 Configurat ion Dat a Sect ion 6. 3. 4. 2
0x2 15: 8 Configurat ion Address Sect ion 6. 3. 4. 2
0x2 7: 0 Configurat ion Dat a Sect ion 6. 3. 4. 2
.
Of f set Descr i pt i on
0x00 Sect ion Lengt h - Sect ion 6. 3. 5. 1.
0x01 PCI e I nit Configurat ion 1 - Sect ion 6. 3. 5. 2
0x04 PCI e Cont rol 1 - Sect ion 6. 3. 5. 5
0x06 PCI e LAN Power Consumpt ion - Sect ion 6. 3. 5. 7
0x08 PCI e Sub- Syst em I D - Sect ion 6. 3. 5. 9
0x09 PCI e Sub- Syst em Vendor I D - Sect ion 6. 3. 5. 10
0x0A PCI e Dummy Device I D - Sect ion 6. 3. 5. 11

191
6. 3. 5. 2 PCI e I ni t Conf i gur at i on 1 Of f set 0x 01
0x0B PCI e Device Revision I D - Sect ion 6. 3. 5. 12
0x0C I OV Cont rol Word 1 - Sect ion 6. 3. 5. 13
0x0D I OV Cont rol Word 2 - Sect ion 6. 3. 5. 14
0x0E Reserved
0x0F Reserved
0x10 Reserved
0x11 Serial Number Et hernet MAC Address - Sect ion 6. 3. 5. 15
0x14 PCI e L1 Exit lat encies - Sect ion 6. 3. 5. 18
0x15 Spare - Sect ion 6. 3. 5. 19
15: 0 Sect ion Lengt h Sect ion Lengt h in words.
15 Reserved 0b Reserved
14: 12 L0s accept able lat ency 011b
Loaded t o t he Endpoint L0s Accept able Lat ency field in t he
Device Capabilit ies regist er as part of t he PCI e Configurat ion
regist ers at power up.
11: 9 L0s G2 Sep exit lat ency 111b
L0s exit lat ency G2S. Loaded t o L0s Exit Lat ency field in t he
Link Capabilit ies regist er as part of t he PCI e Configurat ion
regist ers in PCI e V2. 0 ( 5GT/ s) syst em wit h a separat e clock
set t ing.
8: 6 L0s G2 Com exit lat ency 100b
L0s exit lat ency G2C. Loaded t o L0s Exit Lat ency field in t he
regist ers in PCI e V2. 0 ( 5GT/ s) syst em wit h a common clock
set t ing.
5: 3 L0s G1 Sep exit lat ency 111b
L0s exit lat ency G1S. Loaded t o L0s Exit Lat ency field in t he
regist ers in PCI e v2. 0 ( 2. 5GT/ s) syst em wit h a separat e clock
set t ing.
2: 0 L0s G1 Com exit lat ency 011b
L0s exit lat ency G1C. Loaded t o L0s Exit Lat ency field in t he
regist ers in PCI e v2. 0 ( 2. 5GT/ s) syst em wit h a common clock
set t ing.
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6. 3.5. 5 PCI e Cont r ol 1 Of f set 0x 04
12 FLR delay disable 0b Disable t he FLR value in t he FLR Delay field in t his word.
11: 8 FLR delay 0x1
FLR response t ime in cycles defines t he delay from FLR
assert ion t o it s affect .
7: 6 PCI - E capabilit y version 10b
PCI e Capabilit y Version. This field must be set t o 10b t o use
ext ended configurat ion capabilit y ( used for a t imeout
mechanism) . This field is mapped t o
GCR. PCI e_Capabilit y_Version.
5 ECRC generat ion enable 1b
Loaded int o t he ECRC Generat ion Capable bit of t he PCI e
Configurat ion regist ers. At 1b t he device is capable of
generat ing ECRC.
4 ECRC check enable 1b
Loaded int o t he ECRC Check Capable bit of t he PCI e
Configurat ion regist ers. At 1b t he device is capable of checking
ECRC.
3 FLR capabilit y enable 1b
FLR Capabilit y Enable bit is loaded t o t he PCI e Configurat ion
regist ers via t he Device Capabilit ies regist er.
2 Cache line size 0b
Cache Line Size
0b = 64 byt es.
1b = 128 byt es.
1: 0 Max payload size 10b
Maximum payload size support for TLPs. Loaded t o t he PCI e
Configurat ion regist ers via t he Device Capabilit ies regist er.
3 PCI e Down Reset Disable 0b Disables a core and reset when t he PCI e link goes down.
2: 1 Act _St at _PM_Sup 11b
Act ive St at e Link PM Support is loaded t o t he PCI e
Configurat ion regist ers via t he Link Capabilit ies field.
0 Slot _Clock_Cfg 1b
Slot Clock Configurat ion. When set , t he 82599 uses t he PCI e
reference clock supplied on t he connect or ( for add- in solut ions) .
This bit is loaded t o t he PCI e configurat ion regist ers - > Link
St at us.
4
DI S Clock Gat ing in
DI SABLE
1b
Disable clock gat ing when LTSSM is in a disable st at e.
3 DI S Clock Gat ing in L2 1b Disable clock gat ing when LTSSM is at L2 st at e.
2 DI S Clock Gat ing in L1 1b Disable clock gat ing when LTSSM is at L1 st at e.
1 DI S Clock Gat ing in G2 1b Disable clock gat ing in PCI e V2. 0 ( 5GT/ s) .
0 DI S Clock Gat ing in G1 1b Disable clock gat ing in PCI e v2. 0 ( 2. 5GT/ s) .

193
6.3. 5.6 PCI e Cont r ol 2 Of f set 0x 05
6.3. 5.7 PCI e LAN Pow er Consumpt i on Of f set 0x 06
6.3. 5.8 PCI e Cont r ol 3 Of f set 0x 07
15
Complet ion Timeout
Resend
0b
When set , enables a response t o a request once t he complet ion
t imeout expired. This bit is mapped t o
GCR. Complet ion_Timeout _Resend.
0b = Do not resend request on complet ion t imeout .
1b = Resend request on complet ion t imeout .
3 LAN Funct ion Select 0b
When t he LAN Funct ion Select field = 0b, LAN 0 is rout ed t o PCI
funct ion 0 and LAN 1 is rout ed t o PCI funct ion 1.
I f t he LAN Funct ion Select field = 1b, LAN 0 is rout ed t o PCI
funct ion 1 and LAN 1 is rout ed t o PCI funct ion 0.
This bit is mapped t o FACTPS[ 30] .
2 Dummy Funct ion Enable 1b
Cont rols t he behavior of funct ion 0 when disabled. See
Sect ion 4. 4.
0b = Legacy Mode.
1b = Dummy Funct ion Mode.
1 LAN PCI Disable 0b
LAN PCI Disable. When set t o 1b, one LAN port is disabled. The
funct ion t hat is disabled is det ermined by t he LAN Disable Select
bit . I f t he disabled funct ion is funct ion 0, it act s as a dummy
funct ion or t he ot her LAN funct ion depending on t he Dummy
Funct ion Enable set t ing.
0 LAN Disable Select 0b
LAN Disable Select
0b = LAN 0 is disabled.
1b = LAN 1 is disabled.
Bi t s Name Def aul t Descr i pt i on
Reser v ed
15: 8 LAN D0 Power
The value in t his field is reflect ed in t he PCI Power Management
Dat a regist er of t he LAN funct ions for D0 power consumpt ion and
dissipat ion ( Dat a_Select = 0 or 4) .
Power is defined in 100 mW unit s. The power includes also t he
ext ernal logic required for t he LAN funct ion.
7: 5
Funct ion 0 Common
Power
Dat a regist er of funct ion 0 when t he Dat a_Select field is set t o 8
( common funct ion) . The MSBs in t he Dat a regist er t hat reflect s t he
power values are padded wit h zeros. When one port is used t his
field should be set t o 0.
4: 0 LAN D3 Power
Dat a regist er of t he LAN funct ions for D3 power consumpt ion and
dissipat ion ( Dat a_Select = 3 or 7) .
Power is defined in 100 mW unit s. The power includes also t he
ext ernal logic required for t he LAN funct ion. The MSBs in t he Dat a
regist er t hat reflect s t he power values are padded wit h zeros.
12 I O_Sup 1b
I / O Support ( affect s I / O BAR request ) . When set t o 1b, I / O is
support ed. When cleared t he I / O Access Enable bit in t he Command
regist er ( as part of t he Mandat ory PCI Configurat ion) is RO at 0b.
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6.3.5. 9 PCI e Sub- Sy st em I D Of f set 0x 08
I f t he load subsyst em I Ds in offset 0x7 of t his sect ion is set , t his word is read in t o init ialize t he sub-
syst em I D. The default value is 0x0.
6. 3.5. 10 PCI e Sub- Sy st em Vendor I D Of f set 0x 09
I f t he load subsyst em I Ds in offset 0x7 of t his sect ion is set , t his word is read in t o init ialize t he sub-
syst em vendor I D. The default value is 0x8086.
6. 3.5. 11 PCI e Dummy Dev i ce I D Of f set 0x 0A
I f t he Load Device I D in offset 0x7 of t his sect ion is set , t his word is read in t o init ialize t he device I D of
t he dummy device in t his funct ion ( if enabled) . The default value is 0x10A6.
6. 3.5. 12 PCI e Dev i ce Rev i si on I D Of f set 0x 0B
10: 8 Flash Size 010b
I ndicat es a Flash size of 64 KB * 2 ^
Flash Size
. The Flash size impact s
t he request ed memory space for t he Flash and expansion ROM
BARs in PCI e configurat ion space.
1 Load Subsyst em I Ds 1b
When set t o 1b, indicat es t hat t he funct ion is t o load it s PCI e sub-
syst em I D and subsyst em vendor I D from t he EEPROM ( offset 0x8
and 0x9 in t his sect ion) .
0 Load Device I D 1b
When set t o 1b, indicat es t hat t he funct ion is t o load it s PCI device
I D from t he EEPROM ( offset 0x0A in t his sect ion for dummy device
I D and offset 2 in PCI e configurat ion space 0/ 1 sect ion for act ive
funct ions) .
Bi t s Name Def aul t Descr i pt i on Reser ved
15: 0 Sub Syst em I D 0x0
15: 0 Sub Syst em Vendor 0x8086
15: 0 Sub Device_I D 0x10A6
15: 8 Reserved 0x0 Set t o 0x0
7: 0 DEVREVI D 0x1
Device Rev I D. The act ual device revision I D is t he EEPROM value
XORed wit h t he hardware value ( 0x0 for t he 82599 A- 0 and 0x1 for
t he 82599 B- 0) .

195
6.3. 5.13 I OV Cont r ol Wor d 1 Of f set 0x 0C
This word cont rols t he behavior of I OV funct ionalit y.
6.3. 5.14 I OV Cont r ol Wor d 2 Of f set 0x 0D
This word defines t he device I D for virt ual funct ions.
6.3. 5.15 Ser i al Number Et her net MAC Addr ess Of f set 0x 11
6.3. 5.16 Ser i al Number Et her net MAC Addr ess Of f set 0x 12
10: 5 Max VFs 0x63
Defines t he value of MaxVFs exposed in t he I OV st ruct ure. Valid
values are 0- 62. The value exposed, is t he value of t his field + 1.
4: 3 MSI -X t able 0x2
Defines t he size of t he MSI -X t able ( number of request ed MSI -X
vect ors) valid values are 0- 2.
2 64- Bit Adver t isement 1b
0b = VF BARs advert ise 32 bit size.
1b = VF BARs advert ise 64 bit size.
1 Prefet chable 0b
0b = I OV memory BARS ( 0 and 3) are declared as non-
prefet chable.
1b = I OV memory BARS ( 0 and 3) are declared as prefet chable.
0 I OV Enabled 1b
0b = I OV and ARI capabilit y st ruct ures are not exposed as part of
t he capabilit ies link list .
1b = I OV and ARI capabilit y st ruct ures are exposed as part of t he
capabilit ies link list .
15: 0 VDev I D 0x10ED Virt ual funct ion device I D.
15: 8
Serial Number Et hernet
MAC Address 0, Byt e 1
Part of t he Et hernet MAC address used t o generat e t he PCI e serial
number. See Sect ion 9. 4. 2.
7: 0
15: 8
7: 0
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6. 3.5. 17 Ser i al Number Et her net MAC Addr ess Of f set 0x 13
6. 3. 5. 18 PCI e L1 Ex i t l at enci es Of f set 0x 14
6. 3.5. 19 Reser v ed Of f set 0x 15
6. 3. 6 PCI e Conf i gur at i on Space 0/ 1 Modul es
Word 0x7 point s t o t he PCI e configurat ion space default s of funct ion 0 while word 0x8 point s t o funct ion
1 default s. Bot h sect ions are loaded aft er PCI e reset and D3 t o D0 t ransit ion of t he specific funct ion.
The st ruct ures of bot h funct ions are ident ical as list ed in t he following t able.
15: 8
number. See Sect ion 9. 4. 2
7: 0
14: 12 L1_Act _Acc_Lat ency 110b
Loaded t o t he Endpoint L1 Accept able Lat ency field in t he Device
Capabilit ies regist er as part of t he PCI e Configurat ion regist ers at
power up.
11: 9 L1 G2 Sep exit lat ency 101b
L1 exit lat ency G2S. Loaded t o t he Link Capabilit ies regist er via t he
L1 Exit Lat ency field in PCI e V2. 0 ( 5GT/ s) syst ems t hat have a
separat e clock set t ing.
8: 6 L1 G2 Com exit lat ency 011b
L1 exit lat ency G2C. Loaded t o t he Link Capabilit ies regist er via t he
L1 Exit Lat ency field in PCI e V2. 0 ( 5GT/ s) syst ems t hat have a
common clock set t ing.
5: 3 L1 G1 Sep exit lat ency 100b
L1 exit lat ency G1S. Loaded t o t he Link Capabilit ies regist er via t he
L1 Exit Lat ency field in PCI e v2. 0 ( 2. 5GT/ s) syst ems t hat have a
separat e clock set t ing.
2: 0 L1 G1 Com exit lat ency 010b
L1 exit lat ency G1C. Loaded t o t he Link Capabilit ies regist er via t he
L1 Exit Lat ency field in PCI e v2. 0 ( 2. 5GT/ s) syst ems t hat have a
common clock set t ing.
1 MSI X Memory 1b MSI X memory ECC enable.
0 CDQ Memory 1b CDQ memory ECC enable.
0x00 Sect ion Lengt hSect ion 6. 3. 6. 1.
0x1 Cont rol WordSect ion 6. 3. 6. 2
0x2 Device I DSect ion 6. 3. 6. 3
0x3 CDQM Memory Base 0/ 1 LowSect ion 6. 3. 6. 4
0x4 CDQM Memory Base 0/ 1 HighSect ion 6. 3. 6. 5
0x5 Reser vedSect ion

197
6.3. 6.2 Cont r ol Wor d Of f set 0x 01
6.3.6.3 Dev i ce I D Of f set 0x 02 Dev i ce I D
6.3.6.4 CDQM Memor y Base 0/ 1 Low Of f set 0x 03 [ Reser v ed]
6.3. 6.5 CDQM Memor y Base 0/ 1 Hi gh Of f set 0x 04 [ Reser v ed]
6.3. 6.6 EEPROM PCI e Conf i gur at i on Space 0/ 1 - Of f set 0x 05 [ Reser v ed]
15: 0 Sect ion Lengt h 0x0 Sect ion lengt h in words.
13: 12 I nt errupt Pin
0b for
LAN0
1b for
LAN1
Cont rols t he value advert ised in t he I nt errupt Pin field of t he PCI
configurat ion header for t his device/ funct ion. Values of 00b, 01b,
10b and 11b correspond t o I NTA# , I NTB# , I NTC# and I NTD#
respect ively. When one port is used t his field must be set t o 00b
( using I NTA# ) t o comply wit h PCI spec requirement s.
11 St orage Class 0b
When set , t he class code of t his port is set t o 0x010000 ( SCSI ) .
When cleared, t he class code of t his port is set t o 0x020000 ( LAN) .
10 MSI Mask 1b
MSI per- vect or masking set t ing. This bit is loaded t o t he masking
bit ( bit 8) in t he Message Cont rol of t he MSI Configurat ion
Capabilit y st ruct ure.
8 LAN Boot Disable 1b
A value of 1b disables t he expansion ROM BAR in t he PCI
configurat ion space.
7 Reserved 0b Reser ved
6: 0 MSI _X_N 0x3F
This field specifies t he number of ent ries in t he MSI -X t ables for
t his funct ion. MSI _X_N is equal t o t he number of ent ries minus
one. For example, a ret urn value of 0x7 means eight vect ors are
available. This field is loaded int o t he PCI e MSI -X capabilit ies
st ruct ure. The MSI _X_N must not exceed 0x3F ( 64 MSI -X vect ors) .
15: 0 Device_I D 0x10D8
I f t he Load Device I D in offset 0x7 of t he PCI e General
configurat ion sect ion is set , t his word is loaded t o t he device I D of
t he LAN funct ion.
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6.3.7 LAN Cor e 0/ 1 Modul es
Word 0x9 point s t o t he core configurat ion default s of LAN port 0 while word 0xA point s t o LAN port 1
default s. The sect ion of each funct ion is loaded at t he deassert ion of it s core mast er reset : PCI e reset ,
D3 t o D0 t ransit ion, soft ware reset and link reset . The st ruct ures of bot h funct ions are ident ical as list ed
in t he following t able.
6.3.7. 1 Sect i on Lengt h Of f set 0x 00
6. 3. 7. 2 Et her net MAC Addr ess Regi st er s
The Et hernet I ndividual Address ( I A) is a 6- byt e field t hat must be unique for each NI C or LOM and
must also be unique for each copy of t he EEPROM image. The first t hree byt es are vendor specific. For
example, t he I A is equal t o [ 00 AA 00] or [ 00 A0 C9] for I nt el product s. The value of t his field is loaded
int o t he Receive Address regist er 0 ( RAL0/ RAH0) .
For t he purpose of t his dat asheet , t he numbering convent ion is as follows:
Of f set Hi gh By t e[ 15: 8] Low By t e[ 7: 0] Sect i on
0x0 Sect ion Lengt h - Sect ion 6. 3. 7. 1.
0x1 Et hernet MAC Address Byt e 2 Et hernet MAC Address Byt e 1 Sect ion 6. 3. 7. 2. 1
0x4 LED 1 configurat ion LED 0 Configurat ion Sect ion 6. 3. 7. 3. 1
0x5 LED 3 Configurat ion LED 2 Configurat ion Sect ion 6. 3. 7. 3. 2
0x6 SDP Cont rol Sect ion 6. 3. 7. 4
0x7 Filt er Cont rol Sect ion 6. 3. 7. 5
15: 0 Sect ion Lengt h 0x0 Sect ion lengt h in words.
Vendor 1 2 3 4 5 6
I nt el original 00 AA 00 Variable Variable Variable
I nt el new 00 A0 C9 Variable Variable Variable

199
6. 3.7. 2.1 Et her net MAC Addr ess Regi st er 1 Of f set 0x 01
6. 3. 7. 3 LED Conf i gur at i on
The LEDCTL regist er ( Sect ion 8. 2. 3. 1. 5) default s are loaded from t wo words as list ed in t he following
t ables.
6.3.7.3.1 LED Cont r ol Low er Wor d Of f set 0x 04
6.3.7.3.2 LED cont r ol Upper Wor d Of f set 0x 05
Not e: The cont ent of t he EEPROM words is similar t o t he regist er cont ent .
15: 8 Et h_Addr_Byt e2 0x0 Et hernet MAC address byt e 2.
Reser v ed
15: 8 LEDCTL1 0x0 LED 1 cont rol.
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200
6. 3.7. 4 SDP Cont r ol Of f set 0x 06
6. 3. 7. 5 Fi l t er Cont r ol Of f set 0x 07
6.3.8 MAC 0/ 1 Modul es
Word 0xB point s t o t he LAN MAC configurat ion default s of funct ion 0 while word 0xC point s t o funct ion
1 default s. Bot h sect ions are loaded at t he deassert ion of t heir core mast er reset . The st ruct ures of
bot h sect ions are ident ical; as list ed in t he following t able.
15 SDP1_NATI VE 0b
Defines t he SDP1 operat ing mode t hat is mapped t o
ESDP. SDP1_NATI VE loaded at power up:
0b= Operat es as generic soft ware cont rolled I O.
1b = Nat ive mode operat ion ( hardware funct ion) .
14: 12 Reserved 000b Set t o 000b.
11 SDPDI R[ 3] 0b
SDP3 Pin. I nit ial direct ion is mapped t o ESDP. SDP3_I ODI R loaded
at power up.
10 SDPDI R[ 2] 0b
at power up.
9 SDPDI R[ 1] 0b
at power up.
8 SDPDI R[ 0] 0b
at power up.
3 SDPVAL[ 3] 0b
SDP3 Pin. I nit ial out put value is mapped t o ESDP. SDP3_DATA
loaded at power up.
2 SDPVAL[ 2] 0b
SDP2 Pin. I nit ial out put value is mapped t o ESDP. SDP2_DATA loaded
at power up.
1 SDPVAL[ 1] 0b
at power up.
0 SDPVAL[ 0] 0b
at power up.
Of f set Cont ent Sect i on
Sect ion Lengt h = 0x5
0x1 Link Mode Configurat ion Sect ion 6. 3. 8. 2
0x2 Swap Configurat ion Sect ion 6. 3. 8. 3
0x3 Swizzle and Polarit y Configurat ion Sect ion 6. 3. 8. 4
0x4 Aut o Negot iat ion Default Bit s Sect ion 6. 3. 8. 5
0x5 AUTOC2 Upper Half Sect ion 6. 3. 8. 6
0x6 SGMI I C Lower Half Sect ion 6. 3. 8. 7
0x7 KR- PCS configurat ions Sect ion 6. 3. 8. 8

201
The sect ion lengt h word cont ains t he lengt h of t he sect ion in words. Not e t hat t he sect ion lengt h does
not include a count for t he sect ion lengt h word.
6.3.8.2 Li nk Mode Conf i gur at i on Of f set 0x 01
Reser v ed
15: 0 Sect ion_lengt h 0x0 Sect ion lengt h in words.
15: 13 Link Mode Select 100b
000b = 1 Gb/ s link ( no aut o- negot iat ion) .
001b = 10 Gb/ s parallel link ( no aut o- negot iat ion) .
010b = 1 Gb/ s link wit h clause 37 aut o- negot iat ion enable.
011b = 10 Gb/ s serial link ( no aut o- negot iat ion) . Support s
SFI wit hout backplane aut o- negot iat ion.
100b = KX/ KX4/ KR backplane aut o- negot iat ion enable.
1 Gb/ s ( Clause 37) aut o- negot iat ion disable.
101b = SGMI I 1G/ 100M link.
1 Gb/ s ( Clause 37) aut o- negot iat ion enable.
SGMI I 1 Gb/ s or 100 Mb/ s ( in KX) enable. These bit s are
mapped t o AUTOC. LMS
12 Rest art AN 0b
Rest art s t he KX/ KX4/ KR backplane aut o- negot iat ion
process ( selfclearing bit ) . Mapped t o AUTOC. Rest art _Aut o
Negot iat ion.
11 RATD 0b
Rest art s backplane aut o- negot iat ion on a t ransit ion t o Dx.
Mapped t o AUTOC. RATD and applied t o AUTOC. RATD.
10 D10GMP 0b
Disables 10 Gb/ s ( KX4/ KR) on Dx ( Dr/ D3) wit hout main
power. Mapped t o AUTOC. D10GMP.
9 1G PMA_PMD 1b
PMA/ PMD used for 1 Gb/ s. Mapped t o
AUTOC. 1G_PMA_PMD.
8: 7 10G PMA_PMD_ PARALLEL 01b
PMA/ PMD used for 10 Gb/ s over four different ial pairs for
TX and RX each. Mapped t o
AUTOC. 10G_PMA_PMD_PARALLEL.
6: 2 ANSF 00001b AN Select or Field ( Debug mode) . Mapped t o AUTOC. ANSF
1 ANACK2 0b
AN Ack2 field. This value is t ransmit t ed in t he
Achnowledge2 field of t he Null Next Page t hat is
t ransmit t ed during next page handshake. Mapped t o
AUTOC. ANACK2
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202
6. 3.8. 3 SWAP Conf i gur at i on Of f set 0x 02
15: 14 Swap_Rx_Lane_0 00b
Det ermines which core lane is mapped t o MAC Rx lane 0.
00b = Core Rx lane 0 t o MAC Rx lane 0.
10b = Core Rx lane 2 t o MAC rx lane 0.
Mapped t o SERDESC. swap_rx_lane_0.
7: 6 Swap_Tx_Lane_0 00b
Det ermines t he core dest inat ion t x lane for MAC Tx lane 0.
00b = MAC t x lane 0 t o Core Tx lane 0.
Mapped t o SERDESC. swap_t x_lane_0.

203
6. 3. 8. 4 Sw i zzl e and Pol ar i t y Conf i gur at i on Of f set 3
6.3.8.5 Aut o Negot i at i on Def aul t s Of f set 4
15: 12 Swizzle_Rx 0x0
Swizzle_Rx[ 0] Swizzles t he bit s of MAC Rx lane 0.
Swizzles t he bit s if set t o 1b.
Mapped t o SERDESC. Swizzle_Rx_lanes.
11: 8 Swizzle_Tx 0x0
Swizzle_Tx[ 0] Swizzles t he bit s of MAC Tx lane 0.
Swizzles t he bit s if set t o 1b.
Mapped t o SERDESC. Swizzle_Tx_lanes.
7: 4 Polarit y_Rx 0x0
Polarit y_Rx[ 0] Changes t he bit polarit y of MAC Rx lane 0
Changes bit polarit y if set t o 1b.
Mapped t o SERDESC. Rx_lanes_polarit y.
3: 0 Polarit y_Tx 0x0
Polarit y_Tx[ 0] Changes t he bit polarit y of MAC Tx lane 0.
Changes bit polarit y if set t o 1b.
Mapped t o SERDESC. Tx_lanes_polarit y.
15: 14 KX Support 1b
The value of t hese EEPROM set t ings are shown in bit s A0: A1 of t he
Technology Abilit y field of t he backplane aut o- negot iat ion word
while A2 field is configur ed in t he KR_support bit :
00b: A0 = 0 A1 = 0. KX not support ed. KX4 not support ed. Value is
illegal if KR is also not support ed ( AUTOC. KR_support = 0b) .
01b: A0 = 1 A1 = 0. KX support ed. KX4 not support ed.
10b: A0 = 0 A1 = 1. KX not support ed. KX4 support ed.
11b: A0 = 1 A1 = 1. KX support ed. KX4 support ed.
Mapped t o AUTOC. KX_support .
13: 12 Pause Bit s 0b
The value of t hese bit s is loaded t o bit s D11: D10 of t he link code
word ( pause dat a) . Bit 12 is loaded t o D11. Mapped t o AUTOC. PB.
11 RF 0b
This bit is loaded t o t he RF bit in t he backplane aut o- negot iat ion
word. Mapped t o AUTOC. RF.
10: 9 AN Parallel Det ect Timer 00b
Configures t he parallel det ect count ers.
00b = 1 ms.
01b = 2 ms.
10b = 5 ms.
11b = 8 ms.
Mapped t o AUTOC. ANPDT.
8 AN RX Loose Mode 0b
Enables less rest rict ed funct ionalit y ( allow 9/ 11 bit symbols) .
0b = Disables loose mode.
1b = Enables loose mode.
Mapped t o AUTOC. ANRXLM.
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204
6. 3. 8. 6 AUTOC2 Upper Hal f Of f set 5
7 AN RX Drift Mode 1b
Enables t he drift caused by PPM in t he RX dat a.
0b = Disables drift mode.
1b = Enables drift mode.
Mapped t o AUTOC. ANRXDM.
6: 3 AN RX Align Threshold 0011b
Set s t he t hreshold t o det ermine t hat t he alignment is st able. Set s
how many st able symbols t o find before declaring t he AN_RX.
10b symbol st able.
Mapped t o AUTOC. ANRXAT.
2 FEC Abilit y 1b
FEC Abilit y. Configures t he F0 bit in t he backplane aut o- negot iat ion
base link code word. Should be set t o 1b only if KR abilit y is set t o
1b ( AUTOC. KR = 1b) .
0b = FEC not support ed.
1b = FEC support ed.
Mapped t o AUTOC. FECA.
1 FEC Request ed 0b
FEC request ed. Configures t he F1 bit in t he backplane aut o-
negot iat ion base link code word. Should be set t o 1b only if KR
abilit y is set t o 1b ( AUTOC. KR = 1b) .
0b = FEC not request ed from link part ner.
1b= FEC request ed from link part ner.
Mapped t o AUTOC. FECR.
0 KR Support 1b
Configures t he A2 bit of t he Technology Abilit y Field in t he
backplane aut o- negot iat ion word while t he A0: A1 field is configured
according t o t he KX_support field ( bit s 31: 30) :
0b= KR not support ed. Value is illegal if KX and KX4 are also not
support ed ( AUTOC. KX_support = 00b) .
1b = KR support ed.
Mapped t o AUTOC. KR_Support .
15 Force FEC Enable 0b
Force FEC Enable. Enables FEC wit hout dependency on t he aut o-
negot iat ion resolut ion. Debug mode only. Mapped t o
AUTOC2. FORCE_FEC.
14 Parallel Det ect Disable 0b
Disables t he parallel det ect part in t he KX/ KX4/ KR backplane aut o-
negot iat ion process. Mapped t o AUTOC2. PDD.
13 ANI GNRRXRF 1b AN I gnore Received RF Field. Mapped t o SGMI I C. ANI GNRRXRF
7
Lat ch High 10G Aligned
I ndicat ion
0b
Override any deskew alignment failures in t he 10 Gb/ s link ( by
lat ching high) . Mapped t o AUTOC2. LH1GAI .
6 Reser ved 0b Reserved.
5 AN 1G TI MEOUT EN 1b
Aut o Negot iat ion1 Gb/ s Timeout Enable. Mapped t o PCS1GLCTL. AN
1G TI MEOUT EN
4 Reser ved 0b Reserved
3
MAC DFT Override
Comma Align
0b
Override I nt ernal Comma- Align Cont rol. Mapped t o MDFTC2.
MACDOCA.
2 DDPT 0b
Loaded t o t he Disable DME Pages Transmit bit in t he AUTOC2
regist er.
1: 0
10G PMA/ PMD serial
operat ion
00b
PMA/ PMD used for 10 Gb/ s serial link. Mapped t o
AUTOC2. 10G_PMA_PMD_Serial.


205
6. 3. 8. 7 SGMI I C Low er Hal f Of f set 6
6.3. 8.8 KR- PCS conf i gur at i ons Of f set 7
6.3.9 CSR 0/ 1 Aut o Conf i gur at i on Modul es
Word 0xD point s t o t he CSR aut o configurat ion of funct ion 0 while word 0xE point s t o funct ion 1. Bot h
sect ions are loaded at t he deassert ion of t heir core mast er reset .
The st ruct ures of bot h sect ions are ident ical; t he st ruct ure is list ed in t he following t able.
Not e: The 82599 blocks any writ e t o t he Analog Configurat ion regist ers t hrough t hese sect ions.
15 ANSLNKTMR 0b AN SGMI I Link-Timer. Mapped t o SGMI I C. ANSLNKTMR.
14 ANSTRI G 0b AN SGMI I Trigger. Mapped t o SGMI I C. ANSTRI G.
13 ANSBYP 0b AN SGMI I Bypass. Mapped t o SGMI I C. ANSBYP.
12 ANSFLU100 0b AN SGMI I Force Link Up 100 Mb/ s. Mapped t o SGMI I C. ANSFLU100.
11: 8 STXRASMP 0x0 Shift TX Rat e-Adapt Sampling. Mapped t o SGMI I C. STXRASMP.
7: 4 SRXRARSMP 0x0
Shift RX Rat e-Adapt Replicat ed Dat a Sampling. Mapped t o
SGMI I C. SRXRARSMP.
3: 0 SRXRASSMP 0x0
Shift RX Rat e-Adapt Single Dat a Sampling. Mapped t o
SGMI I C. SRXRASSMP.
15 I E3_MODE 1b I EEE sync mode ( debug mode) . Mapped t o KRPCSFC. I E3_MODE.
10 BYP_FEC_SI G_DET 0b
Bypass FEC signal det ect ( Debug mode) . Mapped t o KRPCSFC.
BYP_FEC_SI G_DET.
Of f set Hi gh Byt e[ 15: 8] Low By t e[ 7: 0] Sect i on
0x0 Sect ion Lengt h = 3* n
0x1 CSR Address Sect ion 6. 3. 9. 2
0x2 Dat a LSB Sect ion 6. 3. 9. 3
0x3 Dat a MSB Sect ion 6. 3. 9. 4
3* n 2 CSR Address Sect ion 6. 3. 9. 2

3* n 1 Dat a LSB Sect ion 6. 3. 9. 3
3* n Dat a MSB Sect ion 6. 3. 9. 4
I nt el

206
6. 3.9. 1 Sect i on Lengt h Of f set 0x 0
6.3.9. 2 CSR Addr ess Of f set 0x 1, 0x 4, 0x 7...
6.3.9. 3 CSR Dat a LSB Of f set 0x 2, 0x 5, 0x 8...
6. 3.9. 4 CSR Dat a MSB Of f set 0x 3, 0x 6, 0x 9. . .
6.4 Fi r mw ar e Modul e
The following t able list s t he EEPROM global offset s used by t he 82599 firmware.
15: 0 Sect ion_lengt h 0x0 Sect ion lengt h in words.
15: 0 CSR_ADDR 0x0 CSR address.
15: 0 CSR_Dat a_LSB 0x0 CSR dat a LSB.
15: 0 CSR_Dat a_MSB 0x0 CSR dat a MSB.
Gl obal MNG
Wor d Of f set
Descr i pt i on
0x0 Test Configurat ion Point er - Sect ion 6. 4. 1
0x1 Loader Pat ch Point er - Sect ion 6. 4. 2
0x2 Reserved
0x3 Common Firmware Paramet ers - Sect ion 6. 4. 2
0x4 Pass Through Pat ch Configurat ion Point er ( Pat ch st ruct ure ident ical t o t he Loader Pat ch) - Sect ion 6. 4. 2
0x5 Pass Through LAN 0 Configurat ion Point er - Sect ion 6. 4. 3
0x6 SideBand Configurat ion Point er - Sect ion 6. 4. 4
0x7 Flexible TCO Filt er Configurat ion Point er - Sect ion 6. 4. 5
0x8 Pass Through LAN 1 Configurat ion Point er - Sect ion 6. 4. 3
0x9 NC- SI Microcode Download Point er - Sect ion 6. 4. 6
0xA NC- SI Configurat ion Point er - Sect ion 6. 4. 7

207
6.4.1 Test Conf i gur at i on Modul e
6.4.1.1 Sect i on Header Of f set 0x 0
6.4.1.2 SMBus Addr ess Of f set 0x 1
6.4.1.3 Loopback Test Conf i gur at i on Of f set 0x 2
6. 4. 2 Common Fi r mw ar e Par amet er s ( Gl obal MNG Of f set 0x 3)
15: 8 Block CRC
7: 0 Block Lengt h Block lengt h in words
15: 9 Reser ved
8
SMBus I nt erface
Number
7: 0 SMBus Slave Address
15: 2 Reser ved
1
Loopback Test Use SDP
Out put
0 Loopback Test Enable
15 Reserved 0b Reserved, should be set t o 0b.
14
Redirect ion Sideband
I nt erface
0b = SMBus.
1b = NC- SI .
10: 8 Manageabilit y Mode
0x0 = None.
0x1 = Reserved.
0x2 = Pass Through ( PT) mode.
0x3 = Reserved.
0x4: 0x7 = Reserved.
7
Port 1 Manageabilit y
Capable
0 = Not capable
1 = Bit s 3 is applicable t o port 1.
6
Port 0 Manageabilit y
Capable
0 = Not capable
1 = Bit s 3 is applicable t o port 0.
5
LAN1 Force TCO Reset
Disable
0b
0b = Enable Force TCO reset on LAN1.
1b = Disable Force TCO reset on LAN1.
4
LAN0 Force TCO Reset
Disable
0b
0b = Enable Force TCO reset on LAN0.
1b = Disable Force TCO reset on LAN0.
3 Pass Through Capable
0b = Disable.
1b = Enable.
I nt el

208
6.4.3 Pass Thr ough LAN 0/ 1 Conf i gur at i on Modul es
The following sect ions describe point ers and st ruct ures dedicat ed t o pass- t hrough mode for LAN 0 and
LAN 1. LAN 0 st ruct ure is point ed by t he Firmware Module point er at offset 0x5. LAN 1 st ruct ure is
point ed by t he Firmware Module point er at offset 0x8.
6. 4.3. 1 Sect i on Header Of f set 0x 0
6. 4.3. 2 LAN 0/ 1 I Pv 4 Addr ess 0 ( LSB) MI PAF0 Of f set 0x 01
6.4.3. 3 LAN 0/ 1 I Pv 4 Addr ess 0 ( MSB) ( MI PAF0) Of f set 0x 02
6. 4.3. 4 LAN 0/ 1 I Pv 4 Addr ess 1 MI PAF1 Of f set 0x 03: 0x 04
Same st ruct ure as LAN0 I Pv4 Address 0.
6. 4.3. 7 LAN 0/ 1 Et her net MAC Addr ess 0 ( LSB) MMAL0 Of f set 0x 09
This word is loaded by Firmware t o t he 16 LS bit s of t he MMAL[ 0] regist er.
6. 4.3. 8 LAN 0/ 1 Et her net MAC Addr ess 0 ( Mi d) MMAL0 Of f set 0x 0A
This word is loaded by Firmware t o t he 16 MS bit s of t he MMAL[ 0] regist er.
15: 8 Block CRC8
7: 0 Block Lengt h Block lengt h in words.
15: 8 LAN 0/ 1 I Pv4 Address 0, Byt e 1.
15: 8 LAN 0/ 1 Et hernet MAC Address 0, Byt e 1.

209
6.4.3.9 LAN 0/ 1 Et her net MAC Addr ess 0 ( MSB) MMAH0 Of f set 0x 0B
This word is loaded by Firmware t o t he MMAH[ 0] regist er.
6.4. 3.10 LAN 0/ 1 Et her net MAC Addr ess 1 MMAL/ H1 Of f set 0x 0C: 0x 0E
Same st ruct ure as LAN0 Et hernet MAC Address 0. Loaded t o MMAL[ 1] , MMAH[ 1] .
6.4. 3.11 LAN 0/ 1 Et her net MAC Addr ess 2 MMAL/ H2 Of f set 0x 0F: 0x 11
6.4. 3.12 LAN 0/ 1 Et her net MAC Addr ess 3 MMAL/ H3 Of f set 0x 12: 0x 14
6. 4. 3. 13 LAN 0/ 1 UDP Fl ex i bl e Fi l t er Por t s 0: 15 ( MFUTP Regi st er s) - Of f set
0x 15: 0x 24
Of f set Bi t s Descr i pt i on Reser ved
0x15 15: 0 LAN UDP Flexible Filt er Value Port 0.
0x1A 15: 0 LAN UDP Flexible Filt er Value Port 5.
0x1B 15: 0 LAN UDP Flexible Filt er Value Port 6.
0x1C 15: 0 LAN UDP Flexible Filt er Value Port 7.
0x1D 15: 0 LAN UDP Flexible Filt er Value Port 8.
0x1E 15: 0 LAN UDP Flexible Filt er Value Port 9.
0x1F 15: 0 LAN UDP Flexible Filt er Value Port 10.
I nt el

210
6. 4.3. 14 LAN 0/ 1 VLAN Fi l t er 0 7 ( MAVTV Regi st er s) - Of f set 0x 25: 0x 2C
6. 4. 3. 15 LAN 0/ 1 Manageabi l i t y Fi l t er s Val i d ( MFVAL LSB) Of f set 0x 2D
6. 4. 3. 16 LAN 0/ 1 Manageabi l i t y Fi l t er s Val i d ( MFVAL MSB) Of f set 0x 2E
Of f set Bi t s Descr i pt i on Reser v ed
0x25 15: 12 Reserved
0x25 11: 0 LAN 0/ 1 VLAN filt er 0 value.
0x2A 15: 12 Reserved
0x2A 11: 0 LAN 0/ 1 VLAN filt er 5 value.
0x2B 15: 12 Reserved
0x2B 11: 0 LAN 0/ 1 VLAN filt er 6 value.
0x2C 15: 12 Reserved
0x2C 11: 0 LAN 0/ 1 VLAN filt er 7 value.
15: 8 VLAN
I ndicat es if t he VLAN filt er regist ers ( MAVTV) cont ain valid VLAN
t ags. Bit 8 corresponds t o filt er 0, et c.
7: 4 Reserved
3: 0 MAC
I ndicat es if t he MAC unicast filt er regist ers ( MMAH, MMAL) cont ain
valid Et hernet MAC Addresses. Bit 0 corresponds t o filt er 0, et c.
15: 12 Reserved
11: 8 I Pv6
I ndicat es if t he I Pv6 address filt er regist ers ( MI PAF) cont ain valid
I Pv6 addresses. Bit 8 corresponds t o address 0, et c. Bit 11 ( filt er 3)
applies only when I Pv4 address filt ers are not enabled
( MANC. EN_I Pv4_FI LTER= 0) .
7: 4 Reserved Reserved
3: 0 I Pv4
I ndicat es if t he I Pv4 address filt ers ( MI PAF) cont ain a valid I Pv4
address. These bit s apply only when I Pv4 address filt ers are
enabled ( MANC. EN_I Pv4_FI LTER= 1) .

211
6.4. 3.17 LAN 0/ 1 MANC v al ue LSB ( LMANC LSB) Of f set 0x 2F
6.4.3.18 LAN 0/ 1 MANC Val ue MSB ( LMANC MSB) Of f set 0x 30
6.4. 3.19 LAN 0/ 1 Recei v e Enabl e 1 ( LRXEN1) Of f set 0x 31
6.4. 3.20 LAN 0/ 1 Recei v e Enabl e 2 ( LRXEN2) Of f set 0x 32
6.4.3.21 LAN 0/ 1 MANC2H Val ue ( LMANC2H LSB) Of f set 0x 33
15: 9 Reserved Reserved.
8
Enable I Pv4 Address
Filt ers
This bit is loaded t o t he EN_I Pv4_FI LTER bit in t he MANC regist er.
7
Enable Xsum Filt ering t o
MNG
This bit is loaded t o t he EN_XSUM_FI LTER bit in t he MANC regist er.
6 VLAN MNG Filt ering This bit is loaded t o t he Bypass VLAN bit in t he MANC regist er.
5
Enable MNG Packet s t o
Host Memory
This bit is loaded t o t he EN_MNG2HOST bit in t he MANC regist er.
15: 8 Receive Enable Byt e 12 BMC SMBus slave address.
7
Enable BMC Dedicat ed
MAC
6 Reserved Reserved. Must be set t o 1b.
5: 4 Not ificat ion Met hod
00b = SMBus alert .
01b = Asynchronous not ify.
10b = Direct receive.
11b = Reserved.
3 Enable ARP Response
2 Enable St at us Report ing
1 Enable Receive All
0 Enable Receive TCO
15: 8 Receive Enable byt e 14 0x0 Alert value.
7: 0 Receive Enable byt e 13 0x0 I nt erface dat a.
15: 8 Reserved
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6. 4.3. 22 LAN 0/ 1 MANC2H Val ue LMANC2H MSB - Of f set 0x 34
6. 4. 3. 23 Manageabi l i t y Deci si on Fi l t er s MDEF0 ( 1) - Of f set 0x 35
6. 4. 3. 27 Manageabi l i t y Deci si on Fi l t er s MDEF1- 6 ( 1- 4) - Of f set 0x 39: 0x 50
Same as words 0x035. . . 0x38 for MDEF[ 1] and MDEF_EXT[ 1] . . . MDEF[ 6] and MDEF_EXT[ 6]
6. 4. 3. 28 Manageabi l i t y Et her t y pe Fi l t er 0. 1 METF0 ( 1) - Of f set 0x 51
6. 4. 3. 29 Manageabi l i t y Et her t y pe Fi l t er 0. 2 METF0 ( 2) - Of f set 0x 52
7: 0 Host Enable
When set , indicat es t hat packet s rout ed by t he manageabilit y filt ers
t o t he manageabilit y block are also sent t o t he host . Bit 0
corresponds t o decision rule 0, et c.
15: 0 MDEF0_L Loaded t o 16 LS bit s of MDEF[ 0] regist er.
15: 0 MDEF0_M Loaded t o 16 MS bit s of MDEF[ 0] regist er.
15: 0 MDEFEXT0_L Loaded t o 16 LS bit s of MDEF_EXT[ 0] regist er.
15: 0 MDEF0EXT_M Loaded t o 16 MS bit s of MDEF_EXT[ 0] regist er.
15: 0 METF0_L Loaded t o 16 LS bit s of METF[ 0] regist er.
15: 0 METF0_M
Loaded t o 16 MS bit s of METF[ 0] regist er ( reserved bit s in t he METF
regist ers should be set in t he EEPROM t o t he regist er s default
values) .

213
6.4. 3.30 Manageabi l i t y Et her t y pe Fi l t er 1. . . 3 ( 1 and 2) METF1: 3 - Of f set
0x 53: 0x 58
Same as words 0x51 and 0x52 for METF[ 1] . . . METF[ 3] regist ers.
6.4.3.31 ARP Response I Pv 4 Addr ess 0 ( LSB) Of f set 0x 59
6.4. 3.32 ARP Response I Pv 4 Addr ess 0 ( MSB) Of f set 0x 5A
6.4. 3.33 LAN 0/ 1 I Pv 6 Addr ess 0 ( n= 0. . . 7) ( MI PAF. I PV6ADDR0) Of f set
0x 5B: 0x 62
6.4.3.34 LAN 0/ 1 I Pv 6 Addr ess 1 ( MI PAF.I PV6ADDR1) Of f set 0x 63: 0x 6A
Same st ruct ure as LAN 0/ 1 I Pv6 Address 0.
6.4.3.35 LAN 0/ 1 I Pv 6 Addr ess 2 ( MI PAF) Of f set 0x 6B- 0x 72
Same st ruct ure as LAN 0/ 1 I Pv6 Address 0.
6. 4. 4 Si deband Conf i gur at i on Modul e
This module is point ed t o by global offset 0x06 of t he manageabilit y cont rol t able.
6.4.4.2 SMBus Max i mum Fr agment Si ze Of f set 0x 01
15: 0 ARP Response I Pv4 Address 0, Byt e 1 ( firmware use) .
15: 0
Loaded t o MI PAF regist ers I PV6ADDR0: Dword offset n/ 2 t o t he
lower 16 bit s for even n and upper 16 bit s for odd n. For n =
0. . . 7.
15: 8 Block CRC8 0x0
7: 0 Block Lengt h 0x0 Sect ion lengt h in words.
15: 0 Max Fragment Size 0x0 SMBus Maximum Fragment Size ( byt es)
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214
6. 4.4. 3 SMBus Not i f i cat i on Ti meout and Fl ags Of f set 0x 02
6. 4.4. 4 SMBus Sl av e Addr esses Of f set 0x 03
6. 4. 4. 5 Fai l - Ov er Regi st er ( Low Wor d) Of f set 0x 04
15: 8
SMBus Not ificat ion
Timeout ( ms)
7: 6 SMBus Connect ion Speed
00b = St andard SMBus connect ion.
01b = Reserved.
10b = Reserved.
11b = Reserved.
5
SMBus Block Read
Command
0b = Block read command is 0xC0.
1b = Block read command is 0xD0.
4 SMBus Addressing Mode
0b = Single address mode.
1b = Dual address mode.
3 Reserved Reserved
2
Disable SMBus ARP
Funct ionalit y
1 SMBus ARP PEC
0 Reserved Reserved
15: 9 SMBus 1 Slave Address Dual address mode only.
8 Reserved Reserved
7: 1 SMBus 0 Slave Address
0 Reserved Reserved
15: 12 Grat uit ous ARP Count er
9
Enable Teaming Fail-
Over on DX
8
Remove Promiscuous on
DX
7 Enable MAC Filt ering
6
Enable Repeat ed
Grat uit ous ARP
5 Reserved Reserved
4 Enable Preferr ed Primar y
3 Preferred Primary Port
2 Transmit Port

215
6. 4. 4. 6 Fai l - Ov er Regi st er ( Hi gh Wor d) Of f set 0x 05
6.4.4.7 NC- SI Conf i gur at i on Of f set 0x 06
6.4.4.8 Reser v ed Wor ds Of f set 0x 07 - 0x 0C
Reserved for fut ure use.
6. 4. 5 Fl ex i bl e TCO Fi l t er Conf i gur at i on Modul e
This module is point ed t o by global offset 0x07 of t he manageabilit y cont rol sect ion.
6. 4. 5. 2 Fl ex i bl e Fi l t er Lengt h and Cont r ol Of f set 0x 01
15: 8
Grat uit ous ARP
Transmission I nt erval
( seconds)
7: 0
Link Down Fail- Over
Time
10 Flow Cont rol 0b 0b = Not support ed.
9
NC- SI HW Arbit rat ion
Enable
0b = Not support ed. Must be set t o 0b.
1b = Support ed.
8
NC- SI HW- based Packet
Copy Enable
1b
0b = Disable.
1b = Enable.
7: 5 Package I D 000b
4: 0
LAN 0 I nt ernal Channel
I D
0x0
15: 8
Flexible Filt er Lengt h
( byt es)
7: 5 Reser ved Reserved
4 Last Filt er
3: 2 Filt er I ndex ( 0- 3)
1 Apply Filt er t o LAN 1
0 Apply Filt er t o LAN 0
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6. 4. 5. 3 Fl ex i bl e Fi l t er Enabl e Mask Of f set 0x 02 - 0x 09
6. 4. 5. 4 Fl ex i bl e Fi l t er Dat a Of f set 0x 0A - Bl ock Lengt h
Not e: This sect ion loads all of t he flexible filt ers, The cont rol + mask + filt er dat a are repeat able as
t he number of filt ers. Sect ion lengt h in offset 0 is for all filt ers.
6. 4. 6 NC- SI Mi cr ocode Dow nl oad Modul e
This module is point ed t o by global offset 0x09 of t he manageabilit y cont rol t able.
6. 4.6. 1 Pat ch Dat a Si ze Of f set 0x 0
6. 4.6. 2 Rx and Tx Code Si ze Of f set 0x 1
6.4.6. 3 Dow nl oad Dat a Of f set 0x 2 - Dat a Si ze
6.4.7 NC- SI Conf i gur at i on Modul e
This module is point ed t o by global offset 0x0A of t he manageabilit y cont rol t able.
6. 4.7. 1 Sect i on Header Of f set 0x 0
6. 4.7. 2 Rx Mode Cont r ol 1 ( RR_CTRL[ 15: 0] ) Of f set 0x 1
15: 0
Flexible Filt er Enable
Mask
15: 0 Flexible Filt er Dat a
15: 8 Rx Code Lengt h 0x0 Rx Code lengt h in Dwords.
7: 0 Tx Code Lengt h 0x0 Tx Code lengt h in Dwords.
15: 8 Download Dat a 0x0 Download dat a.
15: 8 Reserved Set t o 0x0.

217
6.4.7.3 Rx Mode Cont r ol 2 ( RR_CTRL[ 31: 16] ) Of f set 0x 2
6.4.7.4 Tx Mode Cont r ol 1 ( RT_CTRL[ 15: 0] ) Of f set 0x 3
6.4.7.5 Tx Mode Cont r ol 2 ( RT_CTRL[ 31: 16] ) Of f set 0x 4
6. 4. 7. 6 MAC Tx Cont r ol Reg1 ( Tx Cnt r l Reg1 ( 15: 0] ) Of f set 0x 5
3 NC- SI Speed
When set , t he NC- SI MAC speed is 100 Mb/ s. When reset , NC- SI
MAC speed is 10 Mb/ s.
2
Receive Wit hout Leading
Zeros
I f set , packet s wit hout leading zeros ( J/ K/ symbols) bet ween TXEN
assert ion and TXD t he first preamble byt e can be received.
1 Clear Rx Error
Should be set when t he Rx pat h is st uck because of an overflow
condit ion.
0 NC- SI Loopback Enable
When set , enables NC- SI Tx- t o- Rx loop. All dat a t hat is t ransmit t ed
from NC- SI is ret urned t o it . No dat a is act ually t ransmit t ed from
NC- SI .
15: 0 Reserved 0x0
15: 3 Reserved Set t o 0x0.
2
Transmit Wit h Leading
Zeros
When set , sends leading zeros ( J/ K/ symbols) from CRS_DV
assert ion t o t he st art of preamble ( PHY mode) . When deassert ed,
does not send leading zeros ( MAC mode) .
1 Clear Tx Error
Should be set when Tx pat h is st uck because of an underflow
condit ion. Cleared by hardware when released.
0 Enable Tx Pads
When set , t he NC- SI TX pads are driving; ot herwise, t hey are
isolat ed.
15: 0 Reserved 0x0 Set t o 0x0.
6 NC- SI _enable
Enable t he MAC int ernal NC- SI mode of operat ion ( disables ext ernal
NC- SI gasket ) .
5 Two_part _deferral When set , performs t he opt ional t wo part deferral.
4 Append_fcs When set , comput es and appends t he FCS on Tx frames.
3 Pad_enable Pad t he TX frames, which are less t han t he minimum frame size.
0 Tx_ch_en
Tx Channel Enable.
This bit can be used t o enable t he Tx pat h of t he MAC. This bit is for
debug only and t he recommended way t o enable t he Tx pat h is via
t he RT_UCTL_CTRL. TX_enable bit .
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6. 4.7. 7 MAC Tx Cont r ol Reg2 ( Tx Cnt r l Reg1 ( 31: 16] ) Of f set 0x 6
6. 4.7. 8 NC- SI Set t i ngs Of f set 0x 7
15: 0 Reserved Reserved. Should be set t o 0x0.
8: 7 RMM Out Slew Rat e 01b
Configurat ion of t he NC- SI out slew- rat e cont rol.
00b = Slowest
01b = Slow
10b= Fast
11b= Fast est

6: 1 RMM Out Buffer St rengt h 011111b
Configurat ion of t he NC- SI out buffer st rengt h.
000001b= 2 mA
000011b = 4 mA
000111b = 6 mA
001111b = 8 mA
011111b = 10 mA
111111b = 12 mA
0 Reserved 0b Set t o 0b.
I nl i ne Funct i ons I nt el

219
7.0 I nl i ne Funct i ons
7.1 Recei ve Funct i onal i t y
Packet recept ion consist s of:
Recognizing t he presence of a packet on t he wire
Performing address filt ering
DMA queue assignment
St oring t he packet in t he receive dat a FI FO
Transferring t he dat a t o assigned receive queues in host memory
Updat ing t he st at e of a receive descript or.
A received packet goes t hrough t hree st ages of filt ering as depict ed in Figure 7. 1. The Figure describes
a swit ch- like st ruct ure t hat is used in virt ualizat ion mode t o rout e packet s bet ween t he net work port
( t op of drawing) and one of many virt ual port s ( bot t om of drawing) , where each virt ual port might be
associat ed wit h a Virt ual Machine ( VM) , an I OVM, a VMM, or t he like. The t hree st ages are:
1. First st age Ensure t hat t he packet should be received by t he port . This is done by a set of L2
filt ers and is described in det ail in Sect ion 7. 1. 1.
2. Second st age This st age is specific t o virt ualizat ion environment s and defines t he virt ual port s
( called pools in t his document ) t hat are t he t arget s for t he Rx packet . A packet can be associat ed
wit h any number of port s/ pools and t he select ion process is described in Sect ion 7. 1. 2. 2.
3. Third st age A receive packet t hat successfully passed t he Rx filt ers is associat ed wit h one of
many receive descript or queues as described in t his sect ion.
I n addit ion t o t he filt ering rules, a packet must also meet t he following crit eria:
1. Normally, only good packet s are received ( packet s wit h none of t he following errors: Under Size
Error, Over Size Error, Packet Error, Lengt h Error and CRC Error) . However, if t he st ore- bad- packet
bit is set ( FCTRL. SBP) , t hen bad packet s t hat don' t pass t he filt er funct ion are st ored in host
memory. Packet errors are indicat ed by error bit s in t he receive descript or ( RDESC. ERRORS) . I t is
possible t o receive all packet s, regardless of whet her t hey are bad, by set t ing t he promiscuous
enables bit and t he st ore- bad- packet bit .
2. Min Packet Size ( Runt packet s) Rx packet s, smaller t han 21 byt es, cannot be post ed t o host
memory regardless of save bad frame set t ing.
3. Max Packet Size Any Rx packet post ed from t he MAC unit t o t he DMA unit cannot exceed
15. 5 KB.
Not e: CRC errors before t he SFD are ignored. All packet s must have a valid SFD in order t o be
recognized by t he device ( even bad packet s) .
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220
Fi gur e 7.1. St ages i n Pack et Fi l t er i ng
7.1.1 Pack et Fi l t er i ng
The receive packet filt ering role is t o det ermine which of t he incoming packet s are allowed t o pass t o
t he local machine and which of t he incoming packet s should be dropped since t hey are not t arget ed t o
t he local machine. Received packet s t hat are t arget ed for t he local machine can be dest ined t o t he host ,
t o a manageabilit y cont roller, or t o bot h. This sect ion describes how host filt ering is done, and t he
int eract ion wit h management filt ering.
As depict ed in Figure 7.1, host filt ering is done in t hree st ages:
1. Packet s are filt ered by L2 filt ers ( Et hernet MAC address, unicast / mult icast / broadcast ) . See
Sect ion 7. 1. 1. 1.
2. Packet s are filt ered by VLAN if a VLAN t ag is present . See Sect ion 7. 1. 1. 2.
3. Packet s are filt ered by t he manageabilit y filt ers ( port , I P, flex, ot her) . See Sect ion 10.3.
A packet is not forwarded t o t he host if any of t he following occurs:
The packet does not pass L2 filt ers, as described in Sect ion 7.1. 1. 1.
The packet does not pass VLAN filt ering, as described in Sect ion 7. 1. 1. 2.
The packet passes manageabilit y filt ering and t he manageabilit y filt ers det ermine t hat t he packet
should not pass t o t he host as well ( see MANC2H regist er) .
L2 Filters
Pool Select
Queue Select

221
7. 1. 1. 1 L2 Fi l t er i ng
A packet passes successfully t hrough L2 Et hernet MAC address filt ering if any of t he following
condit ions are met :
Unicast packet filt ering Promiscuous unicast filt ering is enabled ( FCTRL. UPE= 1b) or t he packet
passes unicast MAC filt ers ( host or manageabilit y) .
Mult icast packet filt ering Promiscuous mult icast filt ering is enabled by eit her t he host or
manageabilit y ( FCTRL. MPE= 1b or MANC. MCST_PASS_L2 = 1b) or t he packet mat ches one of t he
mult icast filt ers.
Fi gur e 7.2. Rx Fi l t er i ng Fl ow Char t
V
L
A
N
F
i
l
t
e
r
M
N
G
F
i
l
t
e
r
L
2
F
i
l
t
e
r
To MNG To Host
Fail
MANC2H
Reveive Packet
Pass
Pass
Fail
Pass
Fail
Discard
Packets
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Broadcast packet filt ering t o host Promiscuous mult icast filt ering is enabled ( FCTRL. MPE= 1b) or
Broadcast Accept Mode is enabled ( FCTRL. BAM = 1b) .
Broadcast packet filt ering t o manageabilit y Always enabled depending on t he MDEF filt ers.
7.1.1. 1.1 Uni cast Fi l t er
The Et hernet MAC address is checked against t he 128 host unicast addresses, 4 KB hash- based unicast
address filt ers and four management unicast addresses ( if enabled) . The host unicast addresses are
cont rolled by t he host int erface ( t he manageabilit y cont roller must not change t hem) . The ot her four
addresses are dedicat ed t o management funct ions and are only accessed by t he manageabilit y. The
dest inat ion address of an incoming packet must exact ly mat ch one of t he pre- configured host address
filt ers or t he manageabilit y address filt ers. These addresses can be unicast or mult icast . Those filt ers
are configured t hrough Receive Address Low ( RAL) , Receive Address High ( RAH) , Manageabilit y
Et hernet MAC Address Low ( MMAL) and Manageabilit y Et hernet MAC Address High ( MMAH) regist ers. I n
addit ion, t here are 4 KB unicast hash filt ers used for host defined by t he PFUTA regist ers. The unicast
hash filt ers are useful mainly for virt ualizat ion set t ings in t hose cases t hat more t han 128 filt ers might
be required.
Promiscuous Unicast Receive all unicast s. Promiscuous unicast mode can be set / cleared only t hrough
t he host int erface ( not by t he manageabilit y cont roller) and it is usually used when t he LAN device is
used as a sniffer.
7.1.1. 1.2 Mul t i cast Fi l t er ( Par t i al )
The 12- bit port ion of t he incoming packet mult icast address must exact ly mat ch t he mult icast filt er
address in order t o pass mult icast filt er. These bit s ( out of 48 bit s of t he dest inat ion address) can be
select ed by t he MO field in t he MCSTCTRL regist er. The ent ries can be configured only by t he host
int erface and cannot be cont rolled by t he manageabilit y cont roller.
Promiscuous Mult icast Receive all mult icast s. Promiscuous mult icast mode can be set / cleared only
t hrough t he host int erface ( not by t he manageabilit y cont roller) and it is usually used when t he LAN
device is used as a sniffer.
7. 1. 1. 2 VLAN Fi l t er i ng
The 82599 provides exact VLAN filt ering for host t raffic and manageabilit y t raffic, as follows:
Host VLAN filt ers are programmed by t he VFTA[ n] regist ers.
Manageabilit y VLAN filt ers are act ivat ed by t he MDEF filt ers. One of eight VLAN t ags are
programmed by t he MAVTV[ 7: 0] regist ers while enabled by t he MFVAL regist er.
A VLAN mat ch might relat e t o t he CFI bit in t he VLAN header. I t is enabled for host filt ering only by
t he VLNCTRL. CFI EN while t he expect ed value is defined by t he VLNCTRL. CFI .
I f double VLAN is enabled ( see Sect ion 7. 4. 5) , filt ering is done on t he second ( int ernal) VLAN t ag. All
t he filt ering funct ions of t he 82599 ignore t he first ( ext ernal) VLAN in t his mode.
Receive packet t hat passes L2 layer filt ering successfully is subj ect ed t o VLAN header filt ering as
illust rat ed in Figure 7.3:
1. I f t he packet does not have a VLAN header, it passes t o t he next filt ering st age.
2. Else, if t he packet is broadcast and MANC. RCV_TCO_EN bit is set , t hen it passes t o t he next filt ering
st age.
3. Else, if t he packet passes a valid manageabilit y VLAN filt er and at least one VLAN_AND bit is set in
t he MDEF[ n] regist ers, t hen it passes t o t he next filt ering st age.

223
4. Else, if host VLAN filt ers are not enabled ( VLNCTRL. VFE = 0b) , t he packet is forwarded t o t he next
filt ering st age.
5. Else, if t he packet mat ches an enabled host VLAN filt er and CFI checking ( if enabled) , t he packet is
forwarded t o t he next filt ering st age.
6. Else, if manageabilit y VLAN filt ering is not required ( MANC. Bypass_VLAN is set ) , t he packet is
forwarded t o t he next filt ering st age as a pot ent ial candidat e only for manageabilit y.
7. Ot herwise, t he packet is dropped.
Fi gur e 7. 3. VLAN Fi l t er i ng
Packet has
VLAN header
MNG VLAN filtering
is enabled & Pass Rx VLAN
YES
NO
YES
NO
Candidate only for MNG
Host VLAN
filtering
is enabled
NO
Pass Host
VLAN filtering
YES
YES
Bypass MNG
VLAN filtering
YES
NO
MAC Address Filtering
FAIL - Discard Packet
NO
Pass to MNG / Host
Filtering
Active MANC.22
(Bypass VLAN)
Active MDEF[n].2 at least in
one register & Match to a
valid MAVTV[n]
VLNCTRL.VFE
is set
Match to a valid
VFTA[n]
Broadcast
packet and RCV
TCO enabled
YES
MANC.RCV_TCO_EN
NO
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7. 1. 1. 3 Manageabi l i t y / Host Fi l t er i ng
Packet s t hat pass t he MAC address filt ers and VLAN address filt ers described in t he previous sect ions
are subj ect ed t o MNG / Host filt ering shown in Figure 7. 4. The Manageabilit y filt ers are described in
Sect ion 10.3. Packet s t hat are not accept ed for Manageabilit y become aut omat ically candidat es for t he
host queue filt ers described in Sect ion 7. 1.2. Packet s t hat pass t he Manageabilit y filt ers may st ill be
post ed t o t he host as well if t hey mat ch t he BMC t o host filt ers defined by t he MANC2H regist er.
7. 1. 2 Rx Queues Assi gnment
The following filt ers/ mechanisms det ermine t he dest inat ion of a received packet . These filt ers are
described briefly while more det ailed descript ions are provided in t he following sect ions:
Virt ualizat ion I n a virt ual environment , DMA resources are shared bet ween more t han one
soft ware ent it y ( operat ing syst em and/ or device driver) . This is done by allocat ing receive
descript or queues t o virt ual part it ions ( VMM, I OVM, VMs, or VFs) . Allocat ing queues t o virt ual
part it ions is done in set s, each wit h t he same number of queues, called queue pools, or pools.
Virt ualizat ion assigns t o each received packet one or more pool indices. Packet s are rout ed t o a pool
based on t heir pool index and ot her considerat ions such as DCB and RSS. See Sect ion 7. 1. 2. 2 for
more on rout ing for virt ualizat ion.
DCB DCB provides QoS t hrough priorit y queues, priorit y flow cont rol, and congest ion
management . Packet s are classified int o one of several ( up t o eight ) Traffic Classes ( TCs) . Each TC
is associat ed wit h a single unique packet buffer. Packet s t hat reside in a specific packet buffer are
t hen rout ed t o one of a set of Rx queues based on t heir TC value and ot her considerat ions such as
RSS and virt ualizat ion. See Sect ion 7. 7 for det ails on DCB.
DCB is enabled via t he RT Enable bit
Receive Side Scaling ( RSS) RSS dist ribut es packet processing bet ween several processor cores
by assigning packet s int o different descript or queues. RSS assigns t o each received packet an RSS
index. Packet s are rout ed t o one of a set of Rx queues based on t heir RSS index and ot her
considerat ions such as DCB and virt ualizat ion. See Sect ion 7.1. 2. 8 for det ails.
L2 Et hert ype Filt ers These filt ers ident ify packet s by t heir L2 Et hert ype and assigns t hem t o
receive queues. Examples of possible uses are LLDP packet s, and 802. 1X packet s. See
Sect ion 7. 1. 2. 3 for det ails. The 82599 incorporat es eight Et hert ype filt ers.
FCoE Redirect ion Table FCoE packet s t hat mat ch t he L2 filt ers might be direct ed t o a single
legacy Rx queue or mult iple queues t o ease mult i- core processing. See Sect ion 7. 1. 2. 4 for det ails.
See also Sect ion 7. 13. 3. 3 for Large FC receive and direct dat a placement .
Fi gur e 7.4. Manageabi l i t y / Host Fi l t er i ng
MNG / Host Filtering
Pass
MNG Filters
Packet to Host Packet to MNG
NO YES
Pass
MNG to Host
Criteria
YES

225
L3/ L4 5- t uple Filt ers These filt ers ident ify specific L3/ L4 flows or set s of L3/ L4 flows. Each filt er
consist s of a 5- t uple ( prot ocol, source and dest inat ion I P addresses, source and dest inat ion TCP/
UDP port ) and rout es packet s int o one of t he Rx queues. The 82599 incorporat es 128 such filt ers.
See Sect ion 7. 1. 2. 5 for det ails.
Flow Direct or Filt ers These filt ers are an expansion of t he L3/ L4 5- t uple filt ers t hat provides up
t o addit ional 32 K filt ers. See Sect ion 7.1. 2. 7 for det ails.
TCP SYN Filt ers The 82599 might rout e TCP packet s wit h t heir SYN flag set int o a separat e
queue. SYN packet s are oft en used in SYN at t acks t o load t he syst em wit h numerous request s for
new connect ions. By filt ering such packet s t o a separat e queue, securit y soft ware can monit or and
act on SYN at t acks. See Sect ion 7. 1. 2.6 for det ails.
A received packet is allocat ed t o a queue based on t he above crit eria and t he following order:
Queue by L2 Et hert ype filt ers ( if mat ch)
Queue by FCoE redirect ion t able ( relevant for FCoE packet s)
I f SYNQF. SYNQFP is zero, t hen
Queue by L3/ L4 5- t uple filt ers ( if mat ch)
Queue by SYN filt er ( if mat ch)
I f SYNQF. SYNQFP is one, t hen
Queue by SYN filt er ( if mat ch)
Queue by L3/ L4 5- t uple filt ers ( if mat ch)
Queue by flow direct or filt ers
Define a pool ( in case of virt ualizat ion)
Queue by DCB and/ or RSS as described in Sect ion 7. 1. 2.1 and Sect ion 7. 1. 2. 2.
7. 1. 2. 1 Queui ng i n a Non- v i r t ual i zed Env i r onment
Table 7.1 list s t he queuing schemes. Table 7. 2 list s t he queue indexing. Select ing a scheme is done via
t he Mult iple Receive Queues Enable field in t he MRQ regist er.
Tabl e 7. 1. Rx Queui ng Schemes Suppor t ed ( No Vi r t ual i zat i on)
DCB RSS DCB / RSS Queues Speci al Fi l t er s
1
1. Special filt ers include: L2 filt ers, FCoE redirect ion, SYN filt er and L3/ L4 5- t uple filt ers. When possible, it is recommended t o assign
Rx queues not used by DCB/ RSS queues.
No No
1 queue
Rx queue 0
Support ed
No Yes 16 RSS queues Support ed
Yes No
8 TCs x 1 queue
4 TCs x 1 queue
RSS assign Rx queue 0 of each TC
Support ed
Yes Yes
8 TCs x 16 RSS
4 TCs x 16 RSS
Support ed
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226
A received packet is assigned t o a queue accordingt o t he ordering shown in Figure 7. 6) :
DCB and RSS filt ers and FCoE redirect ion Packet s t hat do not meet any of t he filt ering condit ions
described in Sect ion 7. 1. 2 are assigned t o one of 128 queues as list ed in Table 7. 1. The following
modes are support ed:
No DCB, No RSS and No FCoE redirect ion Queue 0 is used for all packet s.
RSS only A set of 16 queues is allocat ed for RSS. The queue is ident ified t hrough t he RSS
index. Not e t hat it is possible t o use a subset of t hese queues.
DCB only A single queue is allocat ed per TC t o a t ot al of eight queues ( if t he number of TCs
is eight ) , or t o a t ot al of four queues ( if t he number of TCs is four) . The queue is ident ified
t hrough t he TC index.
DCB wit h RSS A packet is assigned t o one of 128 queues ( 8 TCs x 16 RSS) or one of 64
queues ( 4 TCs x 16 RSS) t hrough t he DCB t raffic class of t he packet and t he RSS index. The TC
index is used as t he MS bit of t he Rx queue index, and t he LSBit s are defined by t he RSS index.
FCoE redirect ion Up t o eight queues can be allocat ed for FCoE t raffic by t he FCoE redirect ion
t able defined by FCRETA[ n] regist ers.
When operat ing in conj unct ion wit h DCB, t he number of RSS queues can vary per DCB TC. Each TC can
be configured t o a different number of RSS queues ( 0/ 1/ 2/ 4 queues) . The out put of t he RSS redirect ion
t able is masked accordingly t o generat e an RSS index of t he right widt h. When configured t o less t han
t he maximum number of queues, t he respect ive MS bit s of t he RSS index are set t o zero. The number
of RSS queues per TC is configured in t he RQTC regist er.
Example Assume a 4 TCs x 16 RSS configurat ion and t hat t he number of RSS queues for TC= 3 is
set t o 4. The queue numbers for TC= 3 are 32, 33, 34, and 35 ( decimal) .
Figure 7. 5 depict s an example of allocat ion of Rx queues by t he various queue filt ers previously
described for t he following case:
DCB and RSS enabled t o 4 TCs x 16 RSS queues
RSS is used at various widt h per TC
SYN filt er allocat ed
Et hert ype filt ers are used
Tabl e 7.2. Queue I ndex i ng I l l ust r at i on i n Non- vi r t ual i zat i on Mode
Queue I ndex bi t s 6 5 4 3 2 1 0
RSS 0 0 0 RSS
DCB( 4) + RSS TC 0 RSS
DCB( 8) + RSS TC RSS

227
5- t uple filt ers are used
Fi gur e 7. 5. Ex ampl e of Rx Queue Al l ocat i on ( Non- Vi r t ual i zed)
0 15 32 47 64 79 96
127
TC0 TC1 TC2 TC3
RSS
RSS RSS RSS
SYN
EtherType 5- tuple
5- tuple
5- tuple
16 31 48 63 80 95 112
111
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7. 1.2. 2 Queui ng i n a Vi r t ual i zed Env i r onment
The 128 Rx queues are allocat ed t o a pre- configured number of queue set s, called pools. I n non- I OV
mode, syst em soft ware allocat es t he pools t o t he VMM, an I OVM, or t o VMs. I n I OV mode, each pool is
associat ed wit h a VF.
I ncoming packet s are associat ed wit h pools based on t heir L2 charact erist ics as described in
Sect ion 7. 10. 3. This sect ion describes t he following st age, where an Rx queue is assigned t o each
replicat ion of t he Rx packet as det ermined by it s pools associat ion.
Table 7. 3 list s t he queuing schemes support ed wit h virt ualizat ion. Table 7. 4 list s t he queue indexing.
Fi gur e 7.6. Rx Queui ng Fl ow ( Non- Vi r t ual i zed)
Rx Packet
Match SYN
filter
Rx queue is defined by
the L2 Ethertype filter
Match
5-tuple filters
Match L2
filters
Yes
No
Yes
Rx queue is defined
by the SYN filter
No
Yes
Rx queue is defined
by the 5-Tuple filters
No
Rx queue is defined
by the FCoE filters
Match FCoE
filters
Yes
No
Note: Filter Match in this flow
diagram means that Rx packets
match filters that assigns Rx queue
for these packets
Queue num = TC Index | RSS Index
Rx Queue
Assigned
RSS Index =
RSS queue, Packet match RSS criteria and RSS enabled
0, Else
TC Index =
Rx User Priority, Reedtown enabled
0, Else
Match
Flow Director
filters
Yes
Rx queue is defined by
the Flow Director filters
No

229
.
Select ing a scheme is done in t he following manner:
Non- I OV mode
Select ed via t he Mult iple Receive Queues Enable field in t he MRQC regist er.
I OV mode
Det ermine t he number of pools: t he number must support t he value configured by t he
operat ing syst em in t he PCI e NumVFs field ( see Sect ion 9. 4. 4. 5) . Therefore, t he number of
pools is min of { 16, 32, 64} t hat is st ill > = NumVFs.
Det ermine DCB mode via t he RT Enable CSR field.
Not e t hat RSS is not support ed in I OV mode since t here is only a single RSS hash funct ion in
t he hardware.
A received packet is assigned t o anabsolut e queue indexaccording t o t he ordering shown in Figure 7. 7) .
I t is soft ware responsibilit y t o define a queue t hat belongs t o t he mat ched pool.
Tabl e 7. 3. Rx Queui ng Schemes Suppor t ed w i t h Vi r t ual i zat i on
DCB RSS DCB / RSS Queues Speci al Fi l t er s
1
1. Special filt ers include: L2 filt ers, FCoE redirect ion, SYN filt er and L3/ L4 5- t uble filt ers. When possible, it is recommended t o assign
Rx queues not used by DCB/ RSS queues.
No No
16 pools x 1 queue
32 pools x 1 queue
64 pools x 1 queue
- - Rx queue 0 of each pool
Support ed
No Yes
2
2. RSS might not be useful for I OV mode since t he 82599 support s a single RSS t able for t he ent ire device.
32 pools x 4 RSS
64 pools x 2 RSS
Support ed
Yes No
16 pools x 8 TCs
32 pools x 4 TCs
Support ed
Yes Yes Not support ed
Tabl e 7. 4. Queue I ndex i ng I l l ust r at i on i n Vi r t ual i zat i on Mode
Queue I ndex bi t s 6 5 4 3 2 1 0
VT( 64) + RSS VF I ndex RSS
VT( 32) + RSS VF I ndex RSS
VT( 16) + RSS Not Support ed
VT( 32) + DCB( 4) VF I ndex TC
VT( 16) + DCB( 8) VF I ndex TC
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DCB and RSS filt ers The support ed modes are list ed in Table 7.3 and det ailed as follows. The
associat ed queue indexes are list ed in Table 7. 4.
No DCB, No RSS A single queue is allocat ed per pool wit h eit her 32 or 64 pools enabled. I n
64 pools set t ing, queues ' 2xN' .. .' 2xN+ 1' are allocat ed t o pool ' N' ; I n 32 pools set t ing, queues
' 4xN' . . . ' 4xN+ 3' are allocat ed t o pool ' N' .
RSS only All 128 queues are allocat ed t o pools. Several configurat ions are support ed: 32
pools wit h 4 RSS queues each, and 64 pools wit h 2 queues each. Not e t hat it is possible t o use
a subset of t he RSS queues in each pool. The LSBit s of t he queue indexes are defined by t he
RSS index, and t he pool index is used as t he MS bit s.
DCB only All 128 queues are allocat ed t o pools. Several configurat ions are support ed: 16
pools wit h 8 TCs each, or 32 pools wit h 4 TCs each. The LSBit s of t he queue indexes are defined
by t he TC index, and t he pool index is used as t he MS bit s.
When operat ing in conj unct ion wit h RSS, t he number of RSS queues can vary per pool as defined by t he
PSRTYPE[ n] . RQPL. Each pool can be configured t o a different number of RSS queues ( 0/ 1/ 2/ 4 queues)
up t o t he maximum possible queues in t he select ed mode of operat ion. The out put of t he RSS
redirect ion t able is masked accordingly t o generat e an RSS index of t he right widt h. When configured t o
less t han t he maximum number of queues, t he respect ive MS bit s of t he RSS index are set t o zero.
Fi gur e 7.7. Rx Queui ng Fl ow ( Vi r t ual i zat i on Case)
Match L2
filters
Match SYN
filter
Rx queue is defined by the
L2 Ethertype filter
SYN filter
Match
5-tuple filters
Rx Queue = Pool Index |
Queue Index defined by
the 5-tuple filters
Rx Queue
Assigned
VT pool list
empty
Discard packet
Rx Packet
Yes
Yes
Yes
Yes
No
No
No
No
Rx Queue =
FCoE filters
Match FCoE
filters
Yes
No
Pool Index | RSS queue, VT + RSS mode & Packet match RSS criteria
Pool Index | Rx User Priority, VT + DCB mode & VLAN header present
Pool Index | 0, Else
Note: Filter Match in this flow diagram
means that Rx packets match filters that
assigns Rx queue for these packets
Match
Flow Director
filters
Yes Rx queue is defined by the
Flow Director filters
No

231
7.1.2.3 L2 Et her t y pe Fi l t er s
These filt ers ident ify packet s by t heir L2 Et hert ype, 802. 1Q user priorit y and opt ionally assign t hem t o
a receive queue. The following possible usages have been ident ified at t his t ime:
DCB LLDP packet s I dent ifies DCB cont rol packet s
I EEE 802. 1X packet s Ext ensible Aut hent icat ion Prot ocol ( EAPOL) over LAN
Time sync packet s ( such as I EEE 1588) I dent ifies Sync or Delay_Req packet s
FCoE packet s ( possibly t wo UP values)
The L2 t ype filt ers should not be set t o I P packet t ype as t his might cause unexpect ed result s
The 82599 incorporat es eight Et hert ype filt ers defined by a set of t wo regist ers per filt er: ETQF[ n] and
ETQS[ n] .
The L2 packet t ype is defined by comparing t he Et her- Type field in t he Rx packet wit h t he
ETQF[ n] . EType ( regardless of t he pool and UP mat ching) . The Packet Type field in t he Rx descript or
capt ures t he filt er number t hat mat ched wit h t he L2 Et hert ype. See Sect ion 7. 1. 6. 2 for a descript ion of
t he Packet Type field.
The following flow is used by t he Et hert ype filt ers:
1. I f t he Filt er Enable bit is cleared, t he filt er is disabled and t he following st eps are ignored.
2. Receive packet mat ches any ETQF filt ers if t he Et herType field in t he packet mat ches t he EType
field of t he filt er and User Priorit y field in t he packet mat ches t he UP field in t he filt er. The User
Priorit y field is meaningful only if t he UP Enable bit in t he filt er is set . Not e t hat t he following st eps
are ignored if t he packet does not mat ch t he ETQF filt ers.
3. Packet s t hat mat ch any ETQF filt ers is a candidat e for t he host . I f t he packet also mat ches t he
manageabilit y filt ers, it is direct ed t o t he host as well regardless of t he MANC2H regist er set t ing.
4. I f t he FCoE field is set , t he packet is ident ified as an FCoE packet .
5. I f t he 1588 Time St amp field is set , t he packet is ident ified as an I EEE 1588 packet .
6. I f t he Queue Enable bit is cleared, t he filt er complet ed it s act ion on t he packet . Else, t he filt er is
also used for queuing purposes as described in t he sect ions t hat follow.
7. I f t he Pool Enable field is set , t he Pool field of t he filt er det ermines t he t arget pool for t he packet .
The packet can st ill be mirrored or replicat ed t o ot her pools as described in Sect ion 7. 10. 3. See t he
sect ions t hat follow for more det ails on t he use of t he Pool field.
8. The RX Queue field det ermines t he dest inat ion queue for t he packet . I n case of mirroring or
replicat ion, only t he copy of t he packet t hat is t arget ed t o t he pool defined by t he Pool field in t he
ETQF regist er is rout ed according t o t he Rx Queue field.
Set t ing t he ETQF[ n] regist ers is described as follows:
The Filt er Enable bit enables ident ificat ion of Rx packet s by Et hert ype according t o t his filt er. I f t his
bit is cleared, t he filt er is ignored.
The EType field cont ains t he 16- bit Et hert ype compared against all L2 t ype fields in t he Rx packet .
The UP Enable bit enables filt ering by 802. 1Q user priorit y as defined by t he UP field. When
enabled, an Rx packet must mat ch bot h t he EType field and t he UP field.
The FCoE bit indicat es t hat t he Et hert ype defined in t he EType field is an FCoE EType. Packet s t hat
mat ch t his filt er are ident ified as FCoE packet s.
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232
The 1588 Time St amp bit indicat es t hat t he Et hert ype defined in t he EType field is ident ified as I EEE
1588 EType. Packet s t hat mat ch t his filt er are t ime st amped according t o t he I EEE 1588
specificat ion.
The Pool field defines t he t arget pool for a packet t hat mat ches t he filt er.
I t applies only in virt ualizat ion modes. The pool index is meaningful only if t he Pool Enable bit is
set .
I f t he Pool Enable bit is set t hen t he Queue Enable bit in t he ETQS regist er must be set as well.
I n t his case, t he Rx Queue field in t he ETQS must be part of t he pool number defined in t he
ETQF.
Set t ing t he ETQS[ n] regist ers is described as follows:
The Queue Enable bit enables rout ing of t he Rx packet t hat mat ch t he filt er t o Rx queue as defined
by t he Rx Queue field.
The Rx Queue field cont ains t he dest inat ion queue ( one of 128 queues) for t he packet .
The Low Lat ency I nt errupt bit enables LL int errupt assert ion by t he Rx packet t hat mat ches t his
filt er.
Special considerat ions for virt ualizat ion modes:
Packet s t hat mat ch an Et hert ype filt er are divert ed from t heir original pool ( as defined by t he VLAN
and Et hernet MAC address filt ers) t o t he pool defined in t he Pool field in t he ETQF regist ers.
The same applies for mult icast packet s. A single copy is post ed t o t he pool defined by t he filt er.
Mirroring rules
I n case of a pool being mirrored, t he Pool field is used t o det ermine if a packet t hat mat ches t he
filt er should be mirrored.
The Et hert ype filt er does not t ake part in t he decision on t he dest inat ion of t he replicat ed
packet ( such as t he packet generat ed by mirroring) .
7. 1.2. 4 FCoE Redi r ect i on Tabl e
The FCoE redirect ion t able is a mechanism t o dist ribut e received FCoE packet s int o several descript or
queues. Soft ware might assign each queue t o a different processor, sharing t he load of packet
processing among mult iple processors. The FCoE redirect ion t able assigns Rx queues t o packet s t hat
are ident ified as FCoE in t he ETQF[ n] regist ers but not assigned t o queues in t he ETQS[ n] regist ers.
Figure 7. 8 illust rat es t he comput ing of t he assigned Rx queue index by t he FCoE redirect ion t able.
The Rx packet is parsed ext ract ing t he OX_I D or t he RX_I D depending on t he Exchange Cont ext in
t he F_CTL field in t he FC header. At zero t he RX_I D is used; at one t he OX_I D is used.
The t hree LSBit s of t he OX_I D or RX_I D are used as an address t o t he redirect ion t able ( FCRETA[ n]
regist er index) .
The FCoE redirect ion t able is enabled by t he FCRECTL. ENA bit . I f enabled, t he cont ent of t he
select ed FCRETA[ n] regist er is t he assigned Rx queue index.

233
7.1.2.5 L3/ L4 5- t upl e Fi l t er s
These filt ers ident ify specific L3/ L4 flows or set s of L3/ L4 flows and rout es t hem t o dedicat ed queues.
Each filt er consist s of a 5- t uple ( prot ocol, source and dest inat ion I P addresses, source and dest inat ion
TCP/ UDP/ SCTP port ) and rout es packet s int o one of t he Rx queues.
The 82599 incorporat es 128 such filt ers, used also t o init iat e Low Lat ency I int errupt s ( LLI ) . The specific
filt ering rules are:
Filt ering rules for I Pv6 packet s:
I f a filt er defines at least one of t he I P source and dest inat ion addresses, t hen an I Pv6 packet
always misses such a filt er.
I f a filt er masks bot h t he I P source and dest inat ion addresses, t hen an I Pv6 packet is compared
against t he remaining fields of t he filt er.
Packet s wit h t unneling ( any combinat ion of I Pv4 and I Pv6) miss t he 5- t uple filt ers.
Fragment ed packet s miss t he 5- t uple filt ers.
I n a virt ualized environment , any 5- t uple filt ers is associat ed wit h a unique pool:
The packet must first mat ch t he L2 filt ers described in Sect ion 7.10.3.3 and Sect ion 7.10.3.4. The
out come of t he L2 filt ers is a set of pool values associat ed wit h t he packet . The Pool field of t he 5-
t uple filt er is t hen compared against t he set of pools t o which t he packet is st eered. A filt er mat ch is
considered only t o t he indicat ed pool in t he filt er.
I f a packet mat ches more t han one 5- t uple filt er, t hen:
For queuing decision The priorit y field ident ifies t he winning filt er and t herefore t he dest inat ion
queue.
For queuing decision I f t he packet mat ches mult iple filt ers wit h t he same priorit y, t he filt ers
wit h t he lower index t akes affect .
For Low Lat ency I nt errupt ( LLI ) An LLI is issued if one or more of t he mat ching filt ers are set for
LLI .
Fi gur e 7. 8. FCoE Redi r ect i on Tabl e
3 LS bits
Rx OX_ID, FC Initiator
Rx RX_ID, FC Responder
Redirection
Table
16
7
FCRETA[0]
FCRETA[7]
Assigned Rx Queeu
Index
FCRETA[1]
. . .
Flow ID
9 LS bits
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The 5- t uple filt ers are configured via t he FTQF, SDPQF, L34TI MI R, DAQF, and SAQF regist ers, as follows
( described by filt er) :
Prot ocol I dent ifies t he I P prot ocol, part of t he 5- t uple. Enabled by a bit in t he mask field.
Support ed prot ocol fields are TCP, UDP, SCTP or ot her ( neit her TCP nor UDP nor SCTP) .
Source address I dent ifies t he I P source address, part of t he 5- t uple. Enabled by a bit in t he
mask field. Only I Pv4 addresses are support ed.
Dest inat ion address I dent ifies t he I P dest inat ion address, part of t he 5- t uple. Enabled by a bit
in t he mask field. Only I Pv4 addresses are support ed.
Source port I dent ifies t he TCP/ UDP/ SCTP source port , part of t he 5- t uple. Enabled by a bit in
t he mask field.
Dest inat ion port I dent ifies t he TCP/ UDP/ SCTP dest inat ion port , part of t he 5- t uple queue filt ers.
Enabled by a bit in t he mask field.
Queue Enable Enables t he packet s rout ing t o queues based on t he Rx Queue index of t he filt er.
Rx Queue Det ermines t he Rx queue for packet s t hat mat ch t his filt er.
Pool Applies only in t he virt ualized case ( while Pool Mask bit = 0b) . This field must mat ch one of
t he pools enabled for t his packet in t he L2 filt ers.
I n non- virt ualized case t he Pool Mask bit must be set t o 1b.
I n t he virt ualized case, t he pool must be defined ( Pool Mask = 0b and Pool = valid index) . The
Rx Queue field defines t he absolut e queue index. I n case of mirroring or replicat ion, only t he
copy of t he packet dest ined t o t he mat ched pool in t he filt er is rout ed according t o t he Rx
Queue field.
Mask A 5- bit field t hat masks each of t he fields in t he 5- t uple ( L4 prot ocol, I P addresses, TCP/
UDP port s) . The filt er is a logical AND of t he non- masked 5- t uple fields. I f all 5- t uple fields are
masked, t he filt er is not used for queue rout ing.
Priorit y A 3- bit field t hat defines one of seven priorit y levels ( 001b- 111b) , wit h 111b as t he
highest priorit y. Soft ware must insure t hat a packet never mat ches t wo or more filt ers wit h t he
same priorit y value.
Not e: There are 128 different 5- t uple filt er configurat ion regist ers set s, wit h indexes [ 0] t o [ 127] .
The mapping t o a specific Rx queue is done by t he Rx Queue field in t he L34TI MI R regist er,
and not by t he index of t he regist er set .
7. 1. 2. 6 SYN Pack et Fi l t er s
The 82599 might rout e TCP packet s whose SYN flag is set int o a separat e queue. SYN packet s are used
in SYN at t acks t o load t he syst em wit h numerous request s for new connect ions. By filt ering such
packet s t o a separat e queue, securit y soft ware can monit or and act on SYN at t acks.
The following rules apply:
A single SYN filt er is provided.
The SYN filt er is configured via t he SYNQF regist er as follows:
The Queue Enable bit enables SYN filt ering capabilit y.
The Rx Queue field cont ains t he dest inat ion queue for t he packet ( one of 128 queues) . I n case of
mirroring ( in virt ualizat ion mode) , only t he original copy of t he packet is rout ed according t o t his
filt er.

235
7. 1. 2. 7 Fl ow Di r ect or Fi l t er s
The flow direct or filt ers ident ify specific flows or set s of flows and rout es t hem t o specific queues. The
flow direct or filt ers are programmed by FDI RCTRL and all ot her FDI R regist ers. The 82599 shares t he
Rx packet buffer for t he st orage of t hese filt ers. Basic rules for t he flow direct or filt ers are:
I P packet s are candidat es for t he flow direct or filt ers ( meaning non- I P packet s miss all filt ers)
Packet s wit h t unneling ( any combinat ion of I Pv4 and I Pv6) miss all filt ers
Fragment ed packet s miss all filt ers
I n VT mode, t he Pool field in FDI RCMD must be valid. I f t he packet is replicat ed, only t he copy t hat
goes t o t he pool t hat mat ches t he Pool field is impact ed by t he filt er.
The flow direct or filt ers cover t he following fields:
VLAN header
Source I P and dest inat ion I P addresses
Source port and dest inat ion port numbers ( for UDP and TCP packet s)
I Pv4 / I Pv6 and UDP / TCP or SCTP prot ocol mat ch
Flexible 2- byt e t uple anywhere in t he first 64 byt es of t he packet
Target pool number ( relevant only for VT mode)
The 82599 support t wo t ypes of filt ering modes ( st at ic set t ing by t he FDI RCTRL. Perfect - Mat ch bit ) :
Perfect mat ch filt ers The hardware checks a mat ch bet ween t he masked fields of t he received
packet s and t he programmed filt ers. Masked fields should be programmed as zeros in t he filt er
cont ext . The 82599 support up t o 8 K - 2 perfect mat ch filt ers.
Signat ure filt ers The hardware checks a mat ch bet ween a hash- based signat ure of t he masked
fields of t he received packet . The 82599 support s up t o 32 K - 2 signat ure filt ers.
Denot e The Perfect Mat ch fields and Signat ure field are denot ed as Flow I D fields.
The 82599 support s masking / range for t he previously described fields. These masks are defined
globally for all filt ers in t he FDI RM regist er.
The following fields can be masked per bit enabling power of t wo ranges up t o complet e enable /
disable of t he fields: I Pv4 addresses and L4 port numbers.
The following fields can be masked per byt e enabling lower granularit y ranges up t o complet e
enable / disable of t he fields: I Pv6 addresses. Not e t hat in perfect mat ch filt ers t he dest inat ion I Pv6
address can only be compared as a whole ( wit h no range support ) t o t he I P6AT.
The following fields can be eit her enabled or disabled complet ely for t he mat ch funct ionalit y: VLAN
I D t ag; VLAN Priorit y + CFI bit ; Flexible 2- byt e t uple and t arget pool. Target pool can be enabled by
soft ware only when VT is enabled as well.
Flow direct or filt ers have t he following funct ionalit y in virt ualizat ion mode:
Flow direct or filt ers are programmed by t he regist ers in t he PF described in Sect ion 7. 1. 2.7.11 and
Sect ion 7. 1. 2. 7. 12.
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236
7.1.2. 7.1 Fl ow Di r ect or Fi l t er s Act i ons
Flow direct or filt ers might have one of t he following act ions programmed per filt er in t he FDI RCTRL
regist er:
Drop packet or pass t o host as defined by t he Drop bit .
Mat ched packet s t o a flow direct or filt er is direct ed t o t he assigned Rx queue only if t he packet
does not mat ch t he L2 filt ers for queue assignment nor t he SYN filt er for queue assignment nor
t he 5- t uple filt ers for queue assignment .
Packet s t hat mat ch pass filt ers are direct ed t o t he Rx queue defined in t he filt er cont ext as
programmed by t he FDI RCMD. Rx- Queue. I n a non- VT set t ing, t he Rx Queue field defines t he
absolut e queue number. I n VT set t ing, t he Rx Queue field defines t he relat ive queue number
wit hin t he pool.
Packet s t hat mat ch drop filt ers are direct ed t o t he Rx queue defined per all filt ers in t he
FDI RCTRL. DROP- Queue. The 82599 drops t hese packet s if soft ware does not enable t he
specific Rx queue.
Trigger low lat ency int errupt is enabled by t he I NT bit .
Mat ched packet s t o a flow direct or filt er can generat e LLI if t he packet does not mat ch t he L2
filt ers for queue assignment nor t he SYN filt er for queue assignment nor t he 5- t uple filt ers for
queue assignment .
7.1.2. 7.2 Fl ow Di r ect or Fi l t er s St at us Repor t i ng
Shared st at us indicat ions for all packet s:
The 82599 increment s t he FDI RMATCH count er for packet s t hat mat ch a flow direct or filt er. I t also
increment s t he FDI RMI SS count er for packet s t hat do not mat ch any flow direct or filt er.
The Flow Direct or Filt er Mat ch ( FLM) bit in t he Ext ended St at us field of t he Rx descript or is set for
packet s t hat mat ch a flow direct or filt er.
The flow I D paramet ers are report ed in t he Flow Direct or Filt er I D field in t he Rx descript or if
enabled by t he FDI RCTRL. Report - St at us. When t he Report - St at us bit is set , t he RXCSUM. PCSD bit
should be set as well. This field is indicat ed for all packet s t hat mat ch or do not mat ch t he flow
direct or filt ers. Not e t hat it is required t o set t he FDI RCTRL. Report - St at us bit t o enable t he FLM
st at us indicat ion as well as any Flow Direct or error indicat ions in t he receive descript or.
For packet s t hat do not mat ch a flow direct or filt er, t he Flow Direct or Filt er I D field can be used
by soft ware for fut ure programming of a mat ched filt er.
For packet s t hat mat ch a flow direct or filt er, t he Flow Direct or Filt er I D field can be used by
soft ware t o ident ify t he flow of t he Rx packet .
Too long linked list except ion ( linked list and t oo long t erms are illust rat ed in Figure 7.9) :
The maximum recommended linked list lengt h is programmed in t he FDI RCTRL. Max- Lengt h field
The lengt h except ion is report ed in t he FDI RErr field in t he Rx descript or
Packet s t hat do not mat ch any flow direct or filt er, report s t his except ion if t he lengt h of t he exist ing
linked list is already at t he maximum recommended lengt h. Soft ware can use it t o avoid furt her
programming of addit ional filt ers t o t his linked list before ot her filt ers are removed.
Packet s t hat mat ch a pass filt er report t his except ion if t he dist ance of t he mat ched filt er from t he
beginning of t he linked list is higher t han t he above recommended lengt h.
Packet s t hat mat ch a drop filt er are post ed t o t he Rx queue programmed in t he filt er cont ext
inst ead of t he global FDI RCTRL.Rx- Queue. The drop except ion is report ed in addit ion t o t he lengt h
except ion ( in t he same field in t he Rx descript or) .

237
Collision except ion:
Packet s t hat mat ches a collided filt er report t his except ion in t he FDI RErr field in t he Rx descript or.
Collision event s for signat ure- based filt ers should be rare. St ill it might happen because mult iple
flows can have t he same hash and signat ure values. Soft ware might leave t he set t ing as is while
t he collided flows are handled according t o t he act ions of t he first programmed flow. On t he ot her
hand, soft ware might choose t o resolve t he collision by programming t he collided flows in t he 5-
t uples filt ers. Only one flow ( out of t he collided ones) might remain in t he flow direct or filt ers. I n
order t o clear t he collision indicat ion in t he programmed filt er, soft ware should remove t he filt er and
t hen reprogram it once again.
Collision event s for a perfect mat ch filt er should never happen. A collision error might indicat e a
programming fault t hat soft ware might decide t o fix.
7.1.2.7.3 Fl ow Di r ect or Fi l t er s Bl ock Di agr am
The following figure shows a block diagram of t he flow direct or filt ers. Received flows are ident ified t o
bucket s by a hash funct ion on t he relevant t uples as defined by t he FDI R. .. M regist ers. Each bucket is
organized in a linked list indicat ed by t he hash lookup t able. Bucket s can have a variable lengt h while
t he last filt er in each bucket is indicat ed as a last . There is no upper limit for a linked list lengt h during
programming; however, a received packet t hat mat ches a filt er t hat exceeds t he FDI RCTRL. Max- Lengt h
are report ed t o soft ware ( see Sect ion 7. 1. 2.7.5) .
Fi gur e 7.9. Fl ow Di r ect or Fi l t er s Bl ock Di agr am
Logic AND of Rx Packet tuples with
the Flexible filters Mask registers
15 bit address
~350
Hash Lookup Table
Shares the Rx
packet buffer memory space
Hash
15 bit output
Addr
0
M
. . .
2
1
Bucket Valid First Filter PTR
. . .
Hash-Index = 0
Flow ID fields
Next Filter PTR
Collision flag
Filter Action
Hash-Index = 1
Flow ID fields
Next Filter PTR
Collision flag
Filter Action
Hash-Index = N
Flow ID fields
Next Filter PTR
Collision flag
Filter Action
. . .
Max recommended linked list length
(FDIRCTRL.Max-Length)
Hash-Index = N+1
Flow ID fields
Next Filter PTR
Collision flag
Filter Action
. . .
Hash-Index = 0
Flow ID fields
Next Filter PTR
Collision flag
Filter Action
Hash-Index = 1
Flow ID fields
Next Filter PTR
Collision flag
Filter Action
32K
. . .
. . .
Bucket M (linked list M)
Bucket 0 (linked list 0)
too long
Linked list
Flexible Filters table - Shares the Rx packet buffer memory space
Hash (Signature)
15 bit output
Flow ID Field in Signature mode
Flow ID Fields in Perfect Match mode
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7.1.2. 7.4 Rx Pack et Buf f er Al l ocat i on
Flow direct or filt ers can consume zero space ( when disabled) up t o ~ 256 KB of memory. As shown in
Figure 7. 9, flow direct or filt ers share t he same memory wit h t he Rx packet buffer. Set t ing t he PBALLOC
field in t he FDI RCTRL regist er, t he soft ware might enable and allocat e memory for t he flow direct or
filt ers. The memory allocat ed t o recept ion is t he remaining part of t he Rx packet buffer.
Not e: I t is t he user responsibilit y t o ensure t hat sufficient buffer space is left for recept ion. The
required buffer space for recept ion is a funct ion of t he number of t raffic classes, flow cont rol
t hreshold values and remaining buffer space in bet ween t he t hresholds. I f flow direct or is
enabled ( such as PBALLOC > 0) , soft ware should set t he RXPBSI ZE[ n] regist ers according t o
t he t ot al remaining part of t he Rx packet buffer for recept ion.
For example, if PBALLOC equals one and t here is only one buffer in t he syst em, soft ware
should set RXPBSI ZE[ 0] t o 0x70000 ( 448 K) and RXPBSI ZE[ 1. .. 7] t o zero. Anot her example
is if PBALLOC equals t wo and DCB is enabled wit h four t raffic classes t hen soft ware might set
RXPBSI ZE[ 0. .. 3] t o 0x10000 ( 64 K) and RXPBSI ZE[ 4. . . 7] t o zero. Refer t o Sect ion 3.7. 7. 3. 2
t hrough Sect ion 3. 7. 7.3.5 for recommended set t ing of t he Rx packet buffer sizes and flow
cont rol t hresholds.
7.1.2. 7.5 Fl ow Di r ect or Fi l t er i ng Recept i on Fl ow
Rx packet is digest ed by t he filt er unit which parse t he packet ext ract ing t he relevant t uples for t he
filt ering funct ionalit y.
The 82599 calculat es a 15- bit hash value out of t he masked t uples ( logic mask of t he t uples and t he
relevant mask regist ers) using t he hash funct ion described in Sect ion 7. 1. 2. 7. 15.
The address in t he hash lookup t able point s t o t he select ed linked list of t he flow direct or filt ers.
The 82599 checks t he Bucket Valid flag. I f it is inact ive, t hen t he packet does not mat ch any filt er.
Ot herwise, Bucket Valid flag is act ive, proceed for t he next st eps.
The 82599 checks t he linked list unt il it reaches t he last filt er in t he linked list or unt il a mat ched
filt er is found.
Case 1: mat ched filt er is found:
I ncrement t he FDI RMATCH st at ist ic count er.
Process t he filt er' s act ions ( queue assignment and LLI ) according t o queue assignment priorit y.
Meaning, t he act ions defined in t his filt er t akes place only if t he packet did not mat ch any L2
filt er or SYN filt er or 5- t uple filt er t hat assigns an Rx queue t o t he packet .
Rx queue assignment according t o t he filt er cont ext t akes place if Queue- EN is set . I n VT mode,
t he Rx queue in t he filt er cont ext defines a relat ive queue wit hin t he pool.
LLI is generat ed if t he I NT bit is set in t he filt er cont ext .
Post t he packet t o host including t he flow direct or filt er mat ch indicat ions as described in
Sect ion 7. 1. 2. 7.2.
Tabl e 7.5. Rx Pack et Buf f er Al l ocat i on
PBALLOC ( 2)
Ef f ect i v e Rx Pack et
Buf f er Si ze
( see f ol l ow i ng not e)
Fl ow Di r ect or
Fi l t er s Memor y
Suppor t ed Fl ow Di r ect or Fi l t er s
Si gnat ur e Per f ect Mat ch
Fi l t er s Buck et Hash Fi l t er s Buck et Hash
00
Flow Direct or is disabled
512 KB 0 0 n/ a 0 n/ a
01 448 KB 64 KB 8 K - 2 13 bit s 2 K - 2 11 bit s
10 384 KB 128 KB 16 K - 2 14 bit s 4 K - 2 12 bit s
11 256 KB 256 KB 32 K - 2 15 bit s 8 K - 2 13 bit s

239
Case 2: mat ched filt er is not found:
I ncrement t he FDI RMI SS st at ist ic count er.
Post t he packet t o host including t he flow direct or filt er miss indicat ions as described in
Sect ion 7. 1. 2. 7. 2.
7. 1.2. 7.6 Add Fi l t er Fl ow
The soft ware programs t he filt ers paramet ers in t he regist ers described in Sect ion 7. 1. 2. 7.12 and
Sect ion 7. 1. 2. 7. 13 while keeping t he FDI RCMD. Filt er- Updat e bit inact ive. As a result , t he 82599 checks
t he bucket valid indicat ion in t he hash lookup t able ( t hat mat ches t he FDI RHASH. Hash) for t he
presence of an exist ing linked list . Following are t he t wo programming flows t hat handle a presence of
an exist ing linked list or creat ing a new linked list .
Case 1: Add a filt er t o exist ing linked list :
The 82599 checks t he linked list unt il it reaches t he last filt er in t he list or unt il a mat ched filt er is
found. Handle t he filt er programming in one of t he following cases:
Mat ched filt er is found ( equal flow I D) wit h t he same act ion paramet ers The programming is
discarded silent ly. This is a successful case since t he programmed flow is t reat ed as request ed.
Mat ched filt er is found ( equal flow I D) wit h different act ion paramet ers The 82599 keeps t he
old set t ing of t he filt er while set t ing t he Collision flag in t he filt er cont ext and increment s t he
COLL count er in t he FDI RFREE regist er ( see Sect ion 7. 1. 2.7.2 for soft ware handling of collision
during packet recept ion) .
Mat ched filt er is found ( equal flow I D) wit h different act ion paramet ers and t he Collision flag is
already set The programming is discarded silent ly. Soft ware get s t he same indicat ions as t he
previous case.
Mat ched filt er is not found ( no collision) The 82599 checks for a free space in t he flow
direct or filt ers t able.
No space case Discard programming; increment t he FADD count er in t he FDI RFSTAT regist er
and assert t he flow direct or int errupt . Following t his int errupt soft ware should read t he
FDI RFSTAT regist er and FDI RFREE. FREE field, for checking t he int errupt cause.
Free space is found Good programming case: Add t he new filt er at t he end of t he linked list
while indicat ing it as t he last one. Program t he Next Filt er PTR field and t hen clear t he Last flag
in t he filt er t hat was previously t he last one.
Case 2 Creat e a new linked list :
The 82599 looks for an empt y space in t he flow direct or filt ers t able:
Handle no empt y space t he same as in Case 1.
Good programming case: Add t he new filt er while indicat ing it as t he last one in t he linked list .
Then, program t he hash lookup t able ent ry by set t ing t he Valid flag and t he First Filt er PTR
point ing t o t he new programmed filt er.
Addit ional successful add flow indicat ions:
I ncrement t he ADD st at ist ic count er in t he FDI RUSTAT regist er.
Reduce t he FREE count er in t he FDI RFREE regist er and t hen indicat e t he number of free filt ers. I f
t he FREE count er crosses t he full- t hresh value in t he FDI RCTRL regist er, t hen assert t he flow
direct or filt er int errupt . Following t his int errupt soft ware should read t he FDI RFSTAT regist er and
FDI RFREE.FREE field, for checking t he int errupt cause.
Compare t he lengt h of t he new linked list wit h MAXLEN in t he FDI RLEN regist er. I f t he new linked
list is longer t han MAXLEN, updat e t he FDI RLEN by t he new flow.
Not e: The 82599 also report s t he number of collided filt ers in FDI RFREE. COLL. Soft ware might
monit or t his field periodically as an indicat ion for t he filt ers efficiency.
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7.1.2. 7.7 Updat e Fi l t er Fl ow
I n some applicat ions, it is useful t o updat e t he filt er paramet ers, such as t he dest inat ion Rx queue.
Programing filt er paramet ers is described in Sect ion 7. 1.2.7.6.
Set t ing t he Filt er- Updat e bit in t he FDI RCMD regist er has t he following act ion:
Case 1: Mat ched filt er does not exist in t he filt er t able Set t ing t he Filt er- Updat e bit has no impact
and t he command is t reat ed as add filt er.
Case 2: Mat ched filt er already exist s in t he filt er t able Set t ing t he Filt er- Updat e bit enables filt er
paramet er s updat e while keeping t he collision indicat ion as is.
7.1.2. 7.8 Remov e Fi l t er Fl ow
Soft ware programs t he filt er Hash and Signat ure / Soft ware- I ndex in t he FDI RHASH regist er. I t t hen
should set t he FDI RCMD.CMD field t o Remove Flow. Soft ware might use a single 64- bit access t o t he
t wo regist ers for at omic operat ion. As a result , t he 82599 follows t hese st eps:
Check if such a filt er exist s in t he flow direct or filt ers t able.
I f t here is no flow, t hen increment t he FREMOVE count er in t he FDI RFSTAT regist er and skip t he
next st eps.
I f t he request ed filt er is t he only filt er in t he linked list , t hen invalidat e it s ent ry in t he hash lookup
t able by clearing t he Valid bit .
Else, if t he request ed filt er is t he last filt er in t he linked list , t hen invalidat e t he ent ry by set t ing t he
Last flag in t he previous filt er in t he linked list .
Else, invalidat e it s ent ry by programming t he Next Filt er PTR in t he previous filt er in t he linked list ,
point ing it t o t he filt er t hat was linked t o t he removed filt er.
Addit ional indicat ions for successful filt er removal:
I ncrement t he remove st at ist ic count er in t he FDI RUSTAT regist er.
I ncrement t he FREE count er in t he FDI RFREE regist er.
7.1.2. 7.9 Remov e al l Fl ow Di r ect or Fi l t er s
I n some cases t here is a need t o clear t he ent ire flow direct or t able. I t might be useful in some
applicat ions t hat might cause t he flow direct or t able becoming t oo occupied. Then, soft ware might clear
t he ent ire t able enabling it s re- programming wit h new act ive flows.
Following are st eps required t o clear t he flow direct or t able:
Poll t he FDI RCMD.CMD unt il it is zero indicat ing any previous pending commands t o t he flow
direct or t able is complet ed ( at worst case t he FDI RCMD. CMD should be found cleared on t he second
read cycle) . Not e t hat t he soft ware must not init iat e any addit ional commands ( add / remove /
query) before t his st ep st art s and unt il t his flow complet es.
Clear t he FDI RFREE regist er ( set t he FREE field t o 0x8000 and COLL field t o zero) .
Set FDI RCMD.CLEARHT t o 1b and t hen clear it back t o 0b
Clear t he FDI RHASH regist er t o zero
Re- writ e FDI RCTRL by it s previous value while clearing t he I NI T- Done flag.
Poll t he I NI T- Done flag unt il it is set t o one by hardware.
Clear t he following st at ist ic regist ers: FDI RUSTAT; FDI RFSTAT; FDI RMATCH; FDI RMI SS; FDI RLEN
( not e t hat some of t hese regist ers are read clear and some are read writ e) .

241
7.1.2.7.10 Fl ow Di r ect or Fi l t er s I ni t i al i zi ng Fl ow
Following a device reset , t he flow direct or is enabled by programming t he FDI RCTRL regist er, as
follows:
Set PBALLOC t o non- zero value according t o t he required buffer allocat ion t o recept ion and flow
direct or filt er ( see Sect ion 7. 1.2.7.4) . All ot her fields in t he regist er should be valid as well
( according t o required set t ing) while t he FDI RCTRL regist er is expect ed t o be programmed by a
single cycle. Any furt her programming of t he FDI RCTRL regist er wit h non- zero value PBALLOC
init ializes t he flow direct or t able once again.
Poll t he I NI T- Done flag unt il it is set t o one by hardware ( expect ed init ializat ion flow should t ake
about 55 s at 10 Gb/ s and 550 s at 1 Gb/ s ( it is 5. 5 ms at 100 Mb/ s; however, t his speed is not
expect ed t o be act ivat ed unless t he 82599 is in a sleep st at e) .
7. 1.2. 7.11 Quer y Fi l t er Fl ow
Soft ware might query specific filt er set t ings and bucket lengt h using t he Query command.
Program t he filt er Hash and Signat ure/ Soft ware- I ndex in t he FDI RHASH regist er and set t he CMD
field in t he FDI RCMD regist er t o 11b ( Query Command) . A single 64- bit access can be used for t his
st ep.
As a result , t he 82599 provides t he query result in t he FDI RHASH, FDI RCMD and FDI RLEN regist ers
( described in t he sect ions as follows) .
Hardware indicat es query complet ion by clearing t he FDI RCMD. CMD field. The following t able list s
t he query result .
7. 1.2. 7.12 Si gnat ur e Fi l t er Regi st er s
The signat ure flow direct or filt er is programmed by set t ing t he FDI RHASH and FDI RCMD regist ers.
These regist ers are locat ed in consecut ive 8- byt e aligned addresses. Soft ware should use a 64- bit
regist er t o set t hese t wo regist ers in a single at omic operat ion. Table 7. 6 list s t he recommended
set t ing.
Quer y Out come
FDI RHASH - >
Buck et Val i d
FDI RCMD - >
Fi l t er Val i d
FDI RLEN - >
Buck et Lengt h
FDI RCMD - >
Fi l t er I D Fi el ds
FDI RCMD - >
Fi l t er Act i on
Empt y Bucket 0 0 0 0 0
Valid Bucket , Mat ched
Filt er Not Found
1 0
Bucket linked list
lengt h
0 0
Found Signat ure Filt er 1 1
Filt er index wit hin
t he linked list
0 Filt er' s paramet ers
Found perfect Mat ch
Filt er
1 1
Filt er index wit hin
t he linked list
Filt er' s paramet ers Filt er' s paramet ers
Tabl e 7. 6. Si gnat ur e Mat ch Fi l t er Par amet er s
Fi l t er Buck et Par amet er s FDI RHASH
Hash
Hash funct ion used t o define a bucket of filt ers. This paramet er is part of t he flow direct or filt er I D t hat
can be report ed in t he Rx descript or. The size of t his field can be 15 bit s, 14 bit s or 13 bit s as explained in
Sect ion 7. 1. 2. 7. 4. Non- used upper bit s ( MS bit s) should be set t o zero.
Valid Should be set t o 1b.
Fl ow I D FDI RHASH
Signat ure
16- bit hash funct ion used as t he flow mat ching field. This paramet er is also part of t he flow direct or filt er
I D t hat can be report ed in t he Rx descript or.
FDI RCMD Pr ogr ammi ng Command and Fi l t er act i on Set Sect i on 8. 2. 3. 21. 22 for all fields descript ions.
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7.1.2. 7.13 Per f ect Mat ch Fi l t er Regi st er s
Perfect mat ch filt ers are programmed by t he following regist ers: FDI RSI Pv6[ n] ; FDI RVLAN; FDI RPORT;
FDI RI PDA; FDI RI PSA; FDI RHASH; FDI RCMD. Set t ing t he FDI RCMD regist er, generat es t he act ual
programming of t he filt er. Therefore, writ e access t o t his regist er must be t he last cycle aft er all ot her
regist ers cont ain a valid cont ent . Table 7. 7 list s t he recommended set t ing.
Not e: Soft ware filt er programming must be an at omic operat ion. I n a mult i- core environment ,
soft ware must ensure t hat all regist ers are programmed in a sequence wit h no possible
int erference by ot her cores.
7.1.2. 7.14 Mul t i pl e CPU Cor es Consi der at i ons
Perfect mat ch filt ers programming and any query cycles requires access t o mult iple regist ers. I n order
t o avoid races bet ween mult iple cores, soft ware might need t o use one of t he following programming
met hods:
Use a soft ware- based semaphore bet ween t he mult iple cores for gaining cont rol over t he relevant
CSR regist ers for complet e programming or query cycles.
Manage all programming and queries of t he flow direct or filt ers by a single core.
Programming signat ure filt ers requires only t he FDI RHASH and FDI RCMD regist ers. These t wo regist ers
are locat ed in 8- byt e aligned adj acent addresses. Soft ware could use an 8- byt e regist er for t he
programming of t hese regist ers in a single at omic operat ion, which avoids t he need for any semaphore
bet ween mult iple cores.
Tabl e 7.7. Per f ect Mat ch Fi l t er Par amet er s
Fi l t er Buck et Par amet er s and Sof t w ar e I ndex FDI RHASH
Hash
Hash funct ion used t o define a bucket of filt ers. This paramet er is part of t he flow direct or filt er I D t hat
can be report ed in t he Rx descript or. The size of t his field can be 13 bit s, 12 bit s or 11 bit s as explained
in Sect ion 7. 1. 2. 7. 4. Non- used upper bit s ( MS bit s) should be set t o zero.
Valid Should be set t o 1b.
Soft ware- I ndex
15- bit index provided by soft ware at filt er programming used by soft ware t o ident ify t he mat ched flow.
This paramet er is also part of t he flow direct or filt er I D t hat can be report ed in t he Rx descript or.
Not e t hat t he Soft ware- I ndex is used as t he filt er ident ifier. Therefore, it must be wit hin t he range of
support ed filt ers while any filt er must have a single unique Soft ware- I ndex value.
FDI RCMD Pr ogr ammi ng Command and Fi l t er Act i on See Sect i on 8. 2. 3. 21. 22 f or Al l Fi el ds Descr i pt i ons
Fl ow I D Per f ect Mat ch Fl ow I D Par amet er s ar e Li st ed i n t he Fol l ow i ng Regi st er s and Fi el ds
FDI RSI Pv6[ 02] . I P6SA
Three MS DWord of t he source I Pv6. Meaningful for I Pv6 flows depending on t he FDI RI P6M. SI PM
set t ing.
FDI RVLAN. VLAN VLAN fields are meaningful depending on t he FDI RM. VLANI D and FDI RM. VLANP set t ing.
FDI RVLAN. FLEX Flexible 2- byt e field at offset FDI RCTRL. Flex- Offset . Meaningful depending on FDI RM. FLEX set t ing.
FDI RPORT. Source
L4 source port . Meaningful for TCP and UDP packet s depending on t he FDI RTCPM. Sport M and
FDI RUDPM. Sport M set t ing.
FDI RPORT. Dest inat ion
L4 dest inat ion port . Meaningful for TCP and UDP packet s depending on t he FDI RTCPM. Sport M and
FDI RUDPM. Sport M set t ing.
FDI RI PDA. I P4DA I Pv4 dest inat ion address. Meaningful depending on t he FDI RDI P4M. I P- EN set t ing.
FDI RI PSA. I P4SA
I Pv4 source address or LS DWord of t he source I Pv6 address. Meaningful for I Pv4 flows depending on
t he FDI RSI P4M. I P- EN set t ing and for I Pv6 flows depending on t he FDI RI P6M. SI PM set t ing.

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7.1.2.7.15 Fl ow Di r ect or Hash Funct i on
The 82599 support s programmable 16- bit hash funct ions based on t wo 32- bit keys, one for t he lookup
t able ident ifying a bucket of filt ers and anot her one for t he signat ure ( FDI RHKEY and FDI RSKEY) . The
hash funct ion is described in t he sect ions t hat follow. I n some cases, a smaller hash value t han 16 bit s
is required. I n such cases, t he LS bit s of t he hash value are used.
For ( i= 0 t o 350) { if ( Ext _K[ i] ) t hen Hash[ 15 : 0] = Hash[ 15 : 0] XOR Ext _S[ 15+ i : i] }
While using t he following not at ions:
' XOR' - Bit wise XOR of t wo equal lengt h st rings
I f ( xxx ) - Equals t rue if xxx = 1 and equals false if xxx = 0
S[ 335: 0] - The input bit st ring of t he flow direct or t uples: 42 byt es list ed in Table 7. 8 AND- logic
wit h t he filt ers masks.
Ext _S[ n] - S[ 14: 0] | S[ 335: 0] | S[ 335: 321] / / concat enat ed
K[ 31: 0] - The hash key as defined by t he FDI RHKEY or FDI RSKEY regist ers.
Tmp_K[ 11* 32- 1: 0] - ( Temp Key) equals K[ 31: 0] | K[ 31: 0] . . . / / concat enat ed Key 11 t imes
Ext _K[ 350: 0] - ( Ext ended Key) equals Tmp_K[ 351: 1]
The input bit st ream for t he hash calculat ion is list ed in t he Table 7. 8 while byt e 0 is t he MSByt e ( first
on t he wire) of t he VLAN, byt e 2 is t he MSByt e of t he source I P ( I Pv6 case) and so on.
7.1.2.8 Recei v e- Si de Scal i ng ( RSS)
RSS is a mechanism t o dist ribut e received packet s int o several descript or queues. Soft ware t hen
assigns each queue t o a different processor, t herefore sharing t he load of packet processing among
several processors.
As described in Sect ion 7. 1, t he 82599 uses RSS as one ingredient in it s packet assignment policy ( t he
ot hers are t he various filt ers, DCB and virt ualizat ion) . The RSS out put is an RSS index. The 82599
global assignment uses t hese bit s ( or only some of t he LSBs) as part of t he queue number.
Figure 7.10 shows t he process of comput ing an RSS out put :
1. The receive packet is parsed int o t he header fields used by t he hash operat ion ( such as I P
addresses, TCP port , et c. )
2. A hash calculat ion is performed. The 82599 support s a single hash funct ion, as defined by MSFT
RSS. The 82599 t herefore does not indicat e t o t he device driver which hash funct ion is used. The
32- bit result is fed int o t he packet receive descript or.
Tabl e 7. 8. I nput Bi t St r eam f or Hash Cal cul at i on
By t es Fi el d
Byt es 01 VLAN t ag
Byt es 217 Source I P ( 16 byt es for I Pv6; 12 byt es of zero' s | source I P for I Pv4)
Byt es 1833 Dest inat ion I P ( 16 byt es for I Pv6; 12 byt es of zero' s | source I P for I Pv4)
34. . . 37
L4 source port number | L4 dest inat ion port number
Meaningful for TCP and UDP packet s and zero byt es for SCTP packet s
38. . . 39 Flexible byt es
40 00b | pool number ( as defined by FDI RCMD. Pool)
41 00000b | I Pv6/ I Pv4 t ype | L4 t ype ( as defined by FDI RCMD. I PV6 and FDI RCMD. L4TYPE, respect ively)
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3. The seven LSBs of t he hash result are used as an index int o a 128- ent ry redirect ion t able. Each
ent ry provides a 4- bit RSS out put index.
When RSS is enabled, t he 82599 provides soft ware wit h t he following informat ion as:
1. Required by Microsoft * ( MSFT) RSS
2. Provided for device driver assist :
A Dword result of t he MSFT RSS hash funct ion, t o be used by t he st ack for flow classificat ion, is
writ t en int o t he receive packet descript or ( required by MSFT RSS) .
A 4- bit RSS Type field conveys t he hash funct ion used for t he specific packet ( required by MSFT
RSS) .
Enabling rules:
RSS is enabled in t he MRQC regist er.
RSS enabling cannot be done dynamically while it must be preceded by a soft ware reset .
RSS st at us field in t he descript or writ e- back is enabled when t he RXCSUM. PCSD bit is set ( fragment
checksum is disabled) . RSS is t herefore mut ually exclusive wit h UDP fragment at ion checksum
offload.
Support for RSS is not provided when legacy receive descript or format is used.
Disabling rules:
Disabling RSS on t he fly is not allowed, and t he 82599 must be reset aft er RSS is disabled.
When RSS is disabled, packet s are assigned an RSS out put index = zero.
When mult iple request queues are enabled in RSS mode, un- decodable packet s are assigned an RSS
out put index = zero. The 32- bit t ag ( normally a result of t he hash funct ion) equals zero.
Fi gur e 7.10. RSS Bl ock Di agr am
RSS hash
7 LS
bits
Packet Descriptor
Parsed receive packet
7
32
RSS Disable or (RSS
& not decodable)
4
0
4
RSS output index
Redirection Table
128 x 4

245
7.1.2.8.1 RSS Hash Funct i on
This sect ion provides a verificat ion suit e used t o validat e t hat t he hash funct ion is comput ed according
t o MSFT nomenclat ure.
The 82599s hash funct ion follows t he MSFT definit ion. A single hash funct ion is defined wit h several
variat ions for t he following cases:
TcpI Pv4 The 82599 parses t he packet t o ident ify an I Pv4 packet cont aining a TCP segment per
t he following crit eria. I f t he packet is not an I Pv4 packet cont aining a TCP segment , RSS is not done
for t he packet .
I Pv4 The 82599 parses t he packet t o ident ify an I Pv4 packet . I f t he packet is not an I Pv4
packet , RSS is not done for t he packet .
TcpI Pv6 The 82599 parses t he packet t o ident ify an I Pv6 packet cont aining a TCP segment per
t he following crit eria. I f t he packet is not an I Pv6 packet cont aining a TCP segment , RSS is not done
for t he packet .
I Pv6 The 82599 parses t he packet t o ident ify an I Pv6 packet . I f t he packet is not an I Pv6
packet , RSS is not done for t he packet .
Not e: Tunneled I P t o I P packet s are considered for t he RSS funct ionalit y as I P packet s. The RSS
logic ignores t he L4 header while using t he out er ( first ) I P header for t he RSS hash.
The following addit ional cases are not part of t he MSFT RSS specificat ion:
UdpI PV4 The 82599 parses t he packet t o ident ify a packet wit h UDP over I Pv4.
UdpI PV6 The 82599 parses t he packet t o ident ify a packet wit h UDP over I Pv6.
A packet is ident ified as cont aining a TCP segment if all of t he following condit ions are met :
The t ransport layer prot ocol is TCP ( not UDP, I CMP, I GMP, et c. ) .
The TCP segment can be parsed ( such as I Pv4 opt ions or I Pv6 ext ensions can be parsed, packet not
encrypt ed, et c. ) .
The packet is not fragment ed ( even if t he fragment cont ains a complet e L4 header) .
Bit s[ 31: 16] of t he Mult iple Receive Queues Command ( MRQC) regist er enable each of t he above hash
funct ion variat ions ( several might be set at a given t ime) . I f several funct ions are enabled at t he same
t ime, priorit y is defined as follows ( skip funct ions t hat are not enabled) :
I Pv4 packet
Try using t he TcpI Pv4 funct ion
Try using UdpI Pv4 funct ion
Try using t he I Pv4 funct ion
I Pv6 packet
Try using t he TcpI Pv6 funct ion.
Try using UdpI Pv6 funct ion.
Try using t he I Pv6 funct ion
The following combinat ions are current ly support ed:
Any combinat ion of I Pv4, TcpI Pv4, and UdpI Pv4.
And/ Or:
Any combinat ion of eit her I Pv6, TcpI Pv6, and UdpI Pv6.
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When a packet cannot be parsed by t he previous rules, it is assigned an RSS out put index = zero. The
32- bit t ag ( normally a result of t he hash funct ion) equals zero.
The 32- bit result of t he hash comput at ion is writ t en int o t he packet descript or and also provides an
index int o t he redirect ion t able.
The following not at ion is used t o describe t he following hash funct ions:
Ordering is lit t le endian in bot h byt es and bit s. For example, t he I P address 161. 142. 100. 80
t ranslat es int o 0xa18e6450 in t he signat ure.
A " ^ " denot es bit - wise XOR operat ion of same- widt h vect ors.
@x- y denot es byt es x t hrough y ( including bot h of t hem) of t he incoming packet , where byt e 0 is
t he first byt e of t he I P header. I n ot her words, we consider all byt e- offset s as offset s int o a packet
where t he framing layer header has been st ripped out . Therefore, t he source I Pv4 address is
referred t o as @12- 15, while t he dest inat ion v4 address is referred t o as @16- 19.
@x- y, @v- w denot es concat enat ion of byt es x- y, followed by byt es v- w, preserving t he order in
which t hey occurred in t he packet .
All hash funct ion variat ions ( I Pv4 and I Pv6) follow t he same general st ruct ure. Specific det ails for each
variat ion are described in t he following sect ion. The hash uses a random secret key of lengt h 320 bit s
( 40 byt es) ; t he key is st ored in t he RSS Random Key Regist er ( RSSRK) .
The algorit hm works by examining each bit of t he hash input from left t o right . Our nomenclat ure
defines left and right for a byt e- array as follows: Given an array K wit h k byt es, our nomenclat ure
assumes t hat t he array is laid out as follows:
K[ 0] K[ 1] K[ 2] K[ k- 1]
K[ 0] is t he left - most byt e, and t he MSB of K[ 0] is t he left - most bit . K[ k- 1] is t he right - most byt e, and
t he LSB of K[ k- 1] is t he right - most bit .
Comput eHash( input [ ] , N)
For hash-input input[] of length N bytes (8N bits) and a random secret key K of 320 bits
Result = 0;
For each bit b in input[] {
if (b == 1) then Result ^= (left-most 32 bits of K);
shift K left 1 bit position;
}
return Result;
7.1.2. 8.1.1 Pseudo- Code Ex ampl es
The following four pseudo- code examples are int ended t o help clarify exact ly how t he hash is t o be
performed in four cases, I Pv4 wit h and wit hout abilit y t o parse t he TCP header, and I Pv6 wit h and
wit hout a TCP header.
Hash for I Pv4 wit h TCP
Concat enat e SourceAddress, Dest inat ionAddress, SourcePort , Dest inat ionPort int o one single byt e-
array, preserving t he order in which t hey occurred in t he packet : I nput [ 12] = @12- 15, @16- 19, @20-
21, @22- 23.
Result = ComputeHash(Input, 12);

247
Hash for I Pv4 wit h UDP
Concat enat e SourceAddress, Dest inat ionAddress, SourcePort , Dest inat ionPort int o one single byt e-
array, preserving t he order in which t hey occurred in t he packet : I nput [ 12] = @12- 15, @16- 19, @20-
21, @22- 23.
Result = ComputeHash(Input, 12);
Hash for I Pv4 wit hout TCP
Concat enat e SourceAddress and Dest inat ionAddress int o one single byt e- array
Input[8] = @12-15, @16-19
Result = ComputeHash(Input, 8)
Hash for I Pv6 wit h TCP
Similar t o above:
Input[36] = @8-23, @24-39, @40-41, @42-43
Hash for I Pv6 wit h UDP
Similar t o above:
Input[36] = @8-23, @24-39, @40-41, @42-43
Hash for I Pv6 wit hout TCP
Input[32] = @8-23, @24-39
7. 1.2. 8.2 Redi r ect i on Tabl e
The redirect ion t able is a 128- ent ry st ruct ure, indexed by t he seven LSBs of t he hash funct ion out put .
Syst em soft ware might updat e t he redirect ion t able during run t ime. Such updat es of t he t able are not
synchronized wit h t he arrival t ime of received packet s. Therefore, it is not guarant eed t hat a t able
updat e t akes effect on a specific packet boundary.
7.1.2.8.3 RSS Ver i f i cat i on Sui t e
Assume t hat t he random key byt e- st ream is:
0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
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The I Pv6 address t uples are only for verificat ion purposes, and may not make sense as a t uple.
7.1.3 MAC Lay er Of f l oads
7. 1.3. 1 CRC St r i p
The 82599 pot ent ially st rips t he L2 CRC on incoming packet s.
CRC st rip is enabled by t he HLREG0. RXCRCSTRP bit . When set , CRC is st ripped from all received
packet s.
The policy for CRC st rip is as follows:
When RSC is enabled on any queue, t he global CRC st rip bit should be set ( HLREG0. RXCRCSTRP =
1) .
When eit her LinkSec or I Psec are enabled, t he global CRC st rip bit should be set
( HLREG0. RXCRCSTRP= 1b) , since t he payload of t he packet changes and t he CRC value is st ale due
t o it .
7.1.4 Recei v e Dat a St or age i n Sy st em Memor y
The 82599 post s receive packet s int o dat a buffers in syst em memory.
The following cont rols are provided for t he dat a buffers:
The SRRCTL[ n] . BSI ZEPACKET field defines t he dat a buffer size. See sect ion Sect ion 7. 1. 2 for
packet filt ering by size.
The SRRCTL.BSI ZEHEADER field defines t he size of t he buffers allocat ed t o headers ( advanced
descript ors only) .
Each queue is provided wit h a separat e SRRCTL regist er.
Receive memory buffer addresses are word ( 2 x byt e) aligned ( bot h dat a and headers) .
Tabl e 7.9. I Pv4
Dest i nat i on Addr ess/ Por t Sour ce Addr ess/ Por t I Pv 4 onl y I Pv 4 w i t h TCP
161. 142. 100. 80 : 1766 66. 9. 149. 187 : 2794 0x323e8fc2 0x51ccc178
65. 69. 140. 83 : 4739 199. 92. 111. 2 : 14230 0xd718262a 0xc626b0ea
12. 22. 207. 184 : 38024 24. 19. 198. 95 : 12898 0xd2d0a5de 0x5c2b394a
209. 142. 163. 6 : 2217 38. 27. 205. 30 : 48228 0x82989176 0xafc7327f
202. 188. 127. 2 : 1303 153. 39. 163. 191 : 44251 0x5d1809c5 0x10e828a2
Tabl e 7.10. I Pv6
Dest i nat i on Addr ess/ Por t Sour ce Addr ess/ Por t I Pv6 onl y I Pv 6 w i t h TCP
3ffe: 2501: 200: 3: : 1 ( 1766) 3ffe: 2501: 200: 1fff: : 7 ( 2794) 0x2cc18cd5 0x40207d3d
ff02: : 1 ( 4739) 3ffe: 501: 8: : 260: 97ff: fe40: efab ( 14230) 0x0f0c461c 0xdde51bbf
fe80: : 200: f8ff: fe21: 67cf ( 38024)
3ffe: 1900: 4545: 3: 200: f8ff: fe21: 67cf
( 44251)
0x4b61e985 0x02d1feef

249
7. 1. 5 Legacy Recei v e Descr i pt or For mat
A receive descript or is a dat a st ruct ure t hat cont ains t he receive dat a buffer address and fields for
hardware t o st ore packet informat ion. Upon receipt of a packet for t his device, hardware st ores t he
packet dat a int o t he indicat ed buffer and writ es t he lengt h, st at us and errors t o t he receive descript or.
I f SRRCTL[ n] . DESCTYPE = zero, t he 82599 uses t he Legacy Rx descript or as list ed in Table 7. 11. The
shaded areas indicat e fields t hat are modified by hardware upon packet recept ion ( so- called descript or
writ e- back) .
Legacy descript ors should not be used when advanced feat ures are enabled: SCTP, Virt ualizat ion, DCB,
LinkSec, I PSec, FCoE or RSC. Packet s t hat mat ch t hese cases might be dropped from queues t hat use
legacy receive descript ors.
Refer t o Table 7.11 and t he field descript ions t hat follow.
Buffer Address ( 64- bit offset 0, 1st line)
Physical address in host memory of t he received packet buffer.
Lengt h Field ( 16- bit offset 0, 2nd line)
The lengt h indicat ed in t his field covers t he dat a writ t en t o a receive buffer including CRC byt es ( if any) .
Soft ware must read mult iple descript ors t o det ermine t he complet e lengt h for packet s t hat span
mult iple receive buffers.
Fragment Checksum ( 16- bit offset 16, 2nd line)
This field is used t o provide t he fragment checksum value. This field is equal t o t he unadj ust ed 16- bit
ones complement of t he packet . Checksum calculat ion st art s at t he L4 layer ( aft er t he I P header) unt il
t he end of t he packet excluding t he CRC byt es. I n order t o use t he fragment checksum assist t o offload
L4 checksum verificat ion, soft ware might need t o back out some of t he byt es in t he packet . For more
det ails see Sect ion 7. 1. 13.
St at us Field ( 8- bit offset 32, 2nd line)
St at us informat ion indicat es whet her t he descript or has been used and whet her t he referenced buffer is
t he last one for t he packet . Error st at us informat ion is list ed in Table 7.13.
EOP ( End of Packet ) and DD ( Descript or Done)
Refer t o t he following t able:
Tabl e 7. 11. Legacy Recei v e Descr i pt or ( RDESC) Lay out
63 48
47 40 39 32 31 16 15 0
0 Buffer Address [ 63: 0]
8 VLAN Tag Errors St at us Fragment Checksum Lengt h
Tabl e 7. 12. Recei ve St at us ( RDESC.STATUS) Layout
7 6 5 4 3 2 1 0
PI F I PCS L4CS UDPCS VP Reserved EOP DD
DD EOP Descr i pt i on
0 0 Soft ware set t ing of t he descript or when it hands it t o t he hardware.
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VP ( VLAN Packet )
The VP field indicat es whet her t he incoming packet ' s t ype is a VLAN ( 802. 1q) . I t is set if t he
packet t ype mat ches VLNCTRL.VET while RXDCTL. VME bit is set . I t also indicat es t hat VLAN
has been st ripped in t he 802. 1q packet . For a furt her descript ion of 802. 1q VLANs please see
Sect ion 7. 4.
I PCS ( I pv4 Checksum) , L4CS ( L4 Checksum) , UDPCS ( UDP Checksum)
t hese bit s are described in t he following t able. I n I / O mode: swit ched packet s from a local VM
t hat do not use t he Tx I P checksum offload by hardware have t he I PCS equal t o zero;
swit ched packet s from a local VM t hat do not use t he Tx L4 checksum offload by hardware
have t he L4CS and UDPCS equal t o zero.
See Sect ion 7. 1. 11 for a descript ion of support ed packet t ypes for receive checksum
offloading. I Pv6 packet s do not have t he I PCS bit set , but might have t he L4CS bit and UDPCS
bit set if t he 82599 recognizes t he t ransport header.
PI F ( Non Unicast Address)
The PI F bit is set on packet s wit h a non- unicast dest inat ion Et hernet MAC address
mult icast and broadcast .
Error Field ( 8- bit offset 40, 2nd line)
Table 7. 13 and t he following t ext describes t he possible errors report ed by t he hardware.
I PE ( I pv4 Checksum Error)
The I P checksum error is valid only when t he I PCS bit in t he St at us field is set ( indicat ing t hat
t he hardware validat ed t he I P checksum) . This bit is meaningful only on t he last descript or of
a packet while t he EOP bit is set as well. Packet s wit h I P error are post ed t o host memory
regardless of t he st ore bad packet set t ing ( FCTRL. SBP) .
0 1 Reserved ( invalid opt ion) .
1 0
A complet ion st at us indicat ion for non- last descript or of a packet t hat spans across mult iple
descript ors. I t means t hat t he hardware is done wit h t he descript or and it s buffers while only
t he Lengt h fieldis valid on t his descript or.
1 1
A complet ion st at us indicat ion of t he ent ire packet . Soft ware might t ake ownership of it s
descript ors while all fields in t he descript or are valid.
L4CS UDPCS I PCS Funct i onal i t y
0 0 0 Hardware does not provide checksum offload.
0 0 1
Hardware provides I Pv4 checksum offload. Pass/ fail indicat ion is
pr ovided in t he Error field I PE.
1 0 1 / 0
Hardware provides I Pv4 checksum offload if I PCS is act ive along wit h
TCP checksum offload. Pass/ fail indicat ion is provided in t he Error field
I PE and TCPE
1 1 1 / 0
Hardware provides I Pv4 checksum offload if I PCS is act ive along wit h
UDP checksum offload. Pass/ fail indicat ion is pr ovided in t he Error field
I PE and TCPE
Tabl e 7.13. Recei ve Er r or s ( RDESC.ERRORS) Layout
7 6 5 4 3 2 1 0
I PE TCPE Reserved Reserved Reserved Reserved Reserved RXE

251
TCPE ( TCP/ UDP Checksum Error)
The TCP/ UDP checksum error is valid only when t he L4CS bit in t he St at us field is set
( indicat ing t hat t he hardware validat ed t he L4 checksum) . This bit is meaningful only on t he
last descript or of a packet while t he EOP bit is set as well. Packet s wit h a TCP/ UDP error are
post ed t o host memory regardless of t he st ore bad packet set t ing ( FCTRL. SBP) .
RXE
The RXE error bit is an indicat ion for any MAC error. I t is a logic or funct ion of t he following
errors:
CRC or symbol error might be a result of receiving a / V/ symbol on t he TBI int erface, / FE/
symbol on t he GMI I / XGMI I int erface, RX_ER assert ion on GMI I int erface, bad EOP or loss of
sync during packet recept ion.
Undersize frames short er t han 64 byt es.
Oversize frames larger t han t he MFS definit ion in t he MAXFRS regist er.
Lengt h error in 802. 3 packet format . Packet s wit h an RXE error are post ed t o host memory
only when st ore bad packet bit ( FCTRL. SBP) is set .
VLAN Tag Field ( 16- bit offset 48, 2nd line)
I f t he RXDCTL. VME is set and t he received packet t ype is 802. 1q ( as defined by VLNCTRL. VET) t hen t he
VLAN header is st ripped from t he packet dat a st orage. I n t his case t he 16 bit s of t he VLAN t ag, priorit y
t ag and CFI from t he received packet are post ed t o t he VLAN Tag field in t he receive descript or.
Ot herwise, t he VLAN Tag field cont ains 0x0000.
Priorit y and CFI are part of 803. 1Q specificat ions. The VLAN field is provided in net work order.
7.1.6 Adv anced Recei v e Descr i pt or s
7.1. 6.1 Adv anced Recei v e Descr i pt or s Read For mat
Table 7.15 list s t he advanced receive descript or programming by t he soft ware. The SRRCTL[ n] .
DESCTYPE should be set t o a value ot her t han 000 when using t he advanced descript or format .
Tabl e 7. 14. VLAN Tag Fi el d Lay out ( f or 802.1q Pack et )
15 13 12 11 0
PRI CFI VLAN
Tabl e 7. 15. Descr i pt or Read For mat
63 1 0
0 Packet Buffer Address [ 63: 1] A0/ NSE
8 Header Buffer Address [ 63: 1] DD
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Packet Buffer Address ( 64)
This is t he physical address of t he packet buffer. The lowest bit is A0 ( LSB of t he address) .
Header Buffer Address ( 64)
The physical address of t he header buffer wit h t he lowest bit being Descript or Done ( DD) . When a
packet spans in mult iple descript ors, t he header buffer address is used only on t he first descript or.
During t he programming phase, soft ware must set t he DD bit t o zero ( see t he descript ion of t he DD bit
in t his sect ion) . This means t hat header buffer addresses are always word aligned.
When a packet spans in more t han one descript or, t he header buffer address is not used for t he second,
t hird, et c. descript ors; only t he packet buffer address is used in t his case.
Not e: The 82599 does not support null descript ors meaning packet or header addresses are zero.
7. 1.6. 2 Adv anced Recei v e Descr i pt or s Wr i t e- Back For mat
When t he 82599 writ es back t he descript ors, it uses t he format list ed in Table 7. 16. The SRRCTL[ n] .
DESCTYPE should be set t o a value ot her t han 000 when using t he advanced descript or format .
RSS Type ( 4- bit offset 0, 1st line)
The 82599 must ident ify t he packet t ype and t hen choose t he appropriat e RSS hash funct ion t o be used
on t he packet . The RSS t ype report s t he packet t ype t hat was used for t he RSS hash funct ion.
Tabl e 7.16. Descr i pt or Wr i t e- Back For mat
63 . . . . . . . . 48 47 . .. . . . 32 31 30 . . . . 21 20 . 17 16 .. . . . . . 4 3.. . . . 0
0
RSS Hash / Fragment Checksum / RTT /
PCoE_PARAM / Flow Direct or Filt ers I D
SPH HDR_LEN RSCCNT Packet Type RSS Type
8 VLAN Tag PKT_LEN Ext ended Error Ext ended St at us / NEXTP
63 . . . . . . . . 48 47 . .. . . . 32 31 . . . . . . . . . . . 20 19 . . . . . . . . . . . . . . . .. 0
RSS Ty pe Descr i pt i on
0x0 No hash comput at ion done for t his packet
0x1 HASH_TCP_I Pv4
0x2 HASH_I Pv4
0x3 HASH_TCP_I Pv6
0x4 Reserved
0x5 HASH_I Pv6
0x6 Reserved
0x7 HASH_UDP_I Pv4
0x8 HASH_UDP_I Pv6
0x9 0xE Reserved
0xF Packet report s flow direct or filt ers st at us

253
Packet Type ( 13- bit at offset 4, 1st line)
The Packet Type field report s t he packet t ype ident ified by t he hardware as follows. Not e t hat some of
t he fields in t he receive descript or are valid for specific packet t ypes. For example, t he FCOE_PARAM
field ( mult iplexed wit h t he RSS) is valid only for FCoE packet s.
Not e: UDP, TCP and I Pv6 indicat ions are not set in an I Pv4 fragment ed packet .
I n I OV mode, packet s might be received from ot her local VMs. t he 82599 does not check t he
L5 header for t hese packet s and does not report NFS header. I f such packet s carry I P
t unneling ( I Pv4 I Pv6) , t hey are report ed as I PV4E. The packet s received from local VM
are indicat ed by t he LB bit in t he st at us field.
RSC Packet Count - RSCCNT ( 4- bit offset 17, 1st line)
The RSCCNT field is valid only for RSC descript ors while in non- RSC it equals zero. RSCCNT minus one
indicat es t he number of coalesced packet s t hat st art in t his descript or. RSCCNT might count up t o 14
packet s. Once 14 packet s are coalesced in a single buffer, RSC is closed enabling accurat e coalesced
packet count . I f t he RSCCNTBP bit in RDRXCTL is set , coalescing might proceed beyond t he 14 packet s
per buffer while RSCCNT st ops increment ing beyond 0xF.
Not e: Soft ware can ident ify RSC descript ors by checking t he RSCCNT field for non- zero value.
HDR_LEN ( 10- bit offset 21, 1st line)
The HDR_LEN reflect s t he size of t he packet header in byt e unit s ( if t he header is decoded by t he
hardware) . This field is meaningful only in t he first descript or of a packet and should be ignored in any
subsequent descript ors. Header split is explained in Sect ion 7. 1. 10 while t he packet t ypes for t his
funct ionalit y are enabled by t he PSRTYPE[ n] regist ers.
Bi t I ndex Bi t 11 = 0 Bi t 11 = 1 ( L2 pack et )
0 I PV4 I Pv4 header present
Et hert ype ETQF regist er index t hat mat ches t he
packet . Special t ypes are defined for 802. 1x, 1588, and
FCoE.
1 I PV4E I Pv4 wit h ext ensions
2 I PV6 I Pv6 header present
3 I PV6E- I Pv6 wit h ext ensions Reserved for ext ension of t he Et herType field.
4 TCP TCP header present Reserved for ext ension of t he Et herType field.
5 UDP UDP header present Reserved
6 SCTP SCTP header Reserved
7 NFS NFS header Reserved
8 I PSec ESP I PSec encapsulat ion Reserved
9 I PSec AH I PSec encapsulat ion Reserved
10 LinkSec LinkSec encapsulat ion LinkSec LinkSec encapsulat ion
11 0b = non L2 packet 1b = L2 packet
12 Reserved Reserved
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Split Header SPH ( 1- bit offset 31, 1st line)
When set t o 1b, indicat es t hat t he hardware has found t he lengt h of t he header. I f set t o 0b, t he header
buffer may be used only in split always mode. The header buffer lengt h as well as split header support
is indicat ed in t he following t able. I f t he received header size is great er or equal t o 1024 byt es, t he SPH
bit is not set and header split funct ionalit y is not support ed. The SPH bit is meaningful only on t he first
descript or of a packet . See addit ional det ails on SPH, PKT_LEN and HDR_LEN as a funct ion of split
modes in Table 7.20.
RSS Hash or FCOE_PARAM or Flow Direct or Filt ers I D ( 32- bit offset 32, 1st line) / Fragment Checksum
( 16- bit offset 48, 1st line)
This field has mult iplexed funct ionalit y according t o t he received packet t ype ( report ed on t he Packet
Type field in t his descript or) and device set t ing.
FCoE_PARAM
For FCoE packet s t hat mat ches a valid DDP cont ext , t his field holds t he PARAM field in t he
DDP cont ext aft er processing t he received packet . I f t he Relat ive Offset Present bit in t he
F_CTL was set in t he dat a frames, t he PARAM field indicat es t he size in byt es of t he ent ire
exchange inclusive t he frame report ed by t his descript or.
Fragment Checksum
For non- FCoE packet s, t his field might hold t he UDP fragment checksum ( described in
Sect ion 7. 1. 13) if bot h t he RXCSUM. PCSD bit is cleared and RXCSUM. The I PPCSE bit is also
set . This field is meaningful only for UDP packet s when t he UDPV bit in t he Ext ended St at us
word is set .
RSS Hash / Flow Direct or Filt ers I D
For non- FCoE packet s, t his field might hold t he RSS hash value or flow direct or filt ers I D if
t he RXCSUM. PCSD bit is set . Furt her more, if t he FDI RCTRL. Report - St at us bit is set , t hen t he
flow direct or filt ers I D is report ed; ot herwise, t he RSS hash is report ed.
RSS Hash
The RSS hash value is required for RSS funct ionalit y as described in Sect ion 7. 1. 2. 8.
Pack et Type
Header Lengt h ( i ncl udes al l f i el ds up t o
t he f i el d speci f i ed)
Header Spl i t
Unrecognized Et hert ype only wit h / wit hout SNAP
and wit h / wit hout VLAN or
packet s t hat mat ch t he L2 filt ers ( MTQF) ot her
t han FCoE wit h / wit hout VLAN.
VLAN header( s) if present
Else, Et herType field
No
FCoE packet wit hout ESP opt ion header FC header including FC opt ions N/ A ( 1)
FCoE packet wit h ESP opt ion header FC header excluding FC opt ions N/ A ( 1)
I Pv4 only or fragment ed I Pv4 wit h any payload
including I Pv4- I Pv6 t unneling
I Pv4 header Enabled
Non- fragment ed I Pv4, TCP / UDP / SCTP L4 header Enabled
I Pv4- I Pv6, only or fragment ed I Pv4- I Pv6 at I Pv6
header wit h any payload
I Pv6 header ( up t o t he fragment ext ension
header if exist )
Enabled
I Pv4- I Pv6, TCP / UDP / SCTP L4 header Enabled
I Pv4 / I Pv6 / I Pv4- I Pv6, TCP / UDP, NFS L5 header Enabled
Not es: ( 1) Header split is not permit t ed in queues t hat might receive FCoE packet s.

255
Flow Direct or Filt ers I D
The flow direct or filt ers I D is report ed only when t he received packet mat ches a flow direct ory
filt er ( see Sect ion 7. 1. 2. 7) . The flow direct or filt er I D field has a different st ruct ure for
signat ure- based filt ers and perfect mat ch filt ers as follows:
Bucket Hash
A hash value t hat ident ifies a flow direct or bucket . When t he flow direct or t able is
smaller t han 32 K filt ers t he bucket hash is smaller t han 15 bit s. I n t his case t he upper
bit ( s) are set t o zero.
Signat ure
A hash value used t o ident ify flow wit hin a bucket .
SW- I ndex
The SW- I ndex t hat is t aken from t he filt er cont ext , programmed by soft ware. I t is
meaningful only when t he FLM bit in t he Ext ended St at us is set as well.
Rsv
Reserved.
Ext ended St at us / NEXTP ( 20- bit offset 0, 2nd line)
St at us informat ion indicat es whet her t he descript or has been used and whet her t he referenced buffer is
t he last one for t he packet . Table 7. 17 list s t he ext ended st at us word in t he last descript or of a packet
( EOP bit is set ) . Table 7. 18 list s t he ext ended st at us word in any descript or but t he last one of a packet
( EOP bit is cleared) .
Rsv ( 8) , Rsv ( 15: 12) , Rsv( 19) Reserved at zero.
FLM( 2) Flow direct or filt er mat ch indicat ion is set for packet s t hat mat ch t hese filt ers.
VP( 3) , PI F ( 7) These bit s are described in t he legacy descript or format in Sect ion 7. 1. 5.
EOP ( 1) and DD ( 0) End of Packet and Done bit s are list ed in t he following t able:
Fi l t er Ty pe 31 30 .29 28 . . 16 15 . . 13 12 . . . 0
Hash- based Flow Direct or Filt er I D Rsv Bucket Hash Signat ure
Perfect Mat ch Flow Direct or Filt er I D Rsv Hash Rsv SW- I ndex
Tabl e 7. 17. Recei ve St at us ( RDESC.STATUS) Layout of Last Descr i pt or
19 18 17 16 15 14 13 12 11 10
Rsv LB SECP TS Rsv LLI NT UDPV
VEXT Rsv PI F
I PCS L4I UDPCS
VP FLM EOP DD
FCEOFs FCSTAT
9 8 7 6 5 4 3 2 1 0
Tabl e 7. 18. Recei ve St at us ( RDESC.STATUS) Layout of Non- Last Descr i pt or
19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 : 2 1 0
Next Descript or Point er NEXTP Rsv EOP = 0b DD
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256
UDPCS( 4) , L4I ( 5) / FCSTAT ( 5: 4) This field has mult iplexed funct ionalit y for FCoE and
non- FCoE packet s. Hardware ident ifies FCoE packet s in t he filt er unit and indicat es it in t he
Packet Type field in t he Rx descript or. For non- FCoE packet s t his field is UDPCS and L4I . The
UDPCS ( UDP checksum) is set when hardware provides UDP checksum offload. The L4I ( L4
I nt egrit y) is set when hardware provides any L4 offload as: UDP checksum, TCP checksum or
SCTP CRC offload. For FCoE packet s, t his field represent s t he FCSTAT ( FCoE St at us) as
follows:
I PCS( 6) , FCEOFs ( 6) This bit has mult iplexed funct ionalit y for FCoE and non- FCoE
packet s. The hardware ident ifies FCoE packet s in t he filt er unit and indicat es it in t he Packet
Type field in t he Rx descript or. For non- FCoE packet s it is I PCS as described in Legacy Rx
descript or ( in Sect ion 7. 1. 5) . For FCoE packet s, t his bit and t he FCEOFe bit in t he Ext ended
Error field indicat es t he received EOF code as follows:
VEXT ( 9) Out er- VLAN is found on a double VLAN packet . This bit is valid only when
CTRL_EXT. EXTENDED_VLAN is set . See more det ails in Sect ion 7. 4.5.
UDPV ( 10) The UDP Checksum Valid bit indicat es t hat t he incoming packet cont ains a
valid ( non- zero value) checksum field in an incoming fragment ed ( non- t unneled) UDP I Pv4
packet . I t means t hat t he Fragment Checksum field in t he receive descript or cont ains t he UDP
checksum as described in Sect ion 7. 1. 13. When t his field is cleared in t he first fragment t hat
cont ains t he UDP header, it means t hat t he packet does not cont ain a valid UDP checksum
and t he checksum field in t he Rx descript or should be ignored. This field is always cleared in
incoming fragment s t hat do not cont ain t he UDP header.
0 0 Soft ware set t ing of t he descript or when it hands it t o hardware.
0 1 Reserved ( invalid opt ion)
1 0
A complet ion st at us indicat ion for a non last descript or of a packet ( or mult iple packet s in t he case of
RSC) t hat spans across mult iple descript ors. I n a single packet case t he DD bit indicat es t hat t he
hardware is done wit h t he descript or and it s buffers. I n t he case of RSC, t he DD bit indicat es t hat
t he hardware is done wit h t he descript or but might st ill use it s buffers ( for t he coalesced header)
unt il t he last descript or of t he RSC complet es.
Only t he Lengt h fields are valid on t his descript or. I n t he RSC case, t he next descript or point er is
valid as well.
1 1
A complet ion st at us indicat ion of t he ent ire packet ( or t he mult iple packet s in t he case of RSC) and
soft ware might t ake ownership of it s descript ors.
All fields in t he descript or are valid ( report ed by t he hardware) .
FCSTAT Meani ng
00 No mat ch t o any act ive FC cont ext
01
FCoE frame mat ches an act ive FC cont ext wit h no DDP. The ent ire frame is post ed t o t he receive buffer
indicat ed by t his descript or.
10
FCP_RSP frame received t hat invalidat es an FC read cont ext or last dat a packet in a sequence wit h
sequence init iat ive set t hat invalidat es an FC writ e cont ext .
11
FCoE frame mat ches an act ive FC cont ext and found liable for DDP by t he filt er unit . The packet ' s dat a
was post ed direct ly t o t he user buffers if no errors were found by t he DMA unit as report ed in t he FCERR
field. I f any error is found by t he DMA unit t he ent ire packet is post ed t o t he legacy queues.
FCEOFe FCEOFs Descr i pt i on and Di gest ed meani ng and Dev i ce Behavi or
0 0 EOFn. Nominal operat ion, DDP is enabled.
0 1 EOFt . Nominal operat ion ( end of sequence) , DDP is enabled.
1 0
Unexpect ed EOFn- EOFt or SOFi- SOFn. No DDP while filt er cont ext is updat ed by t he
packet .
1 1 EOFa, EOFni or unrecognized EOF / SOF. No DDP while filt er cont ext is invalidat ed.

257
LLI NT ( 11) The Low Lat ency I nt errupt bit indicat es t hat t he packet caused an immediat e
int errupt via t he low lat ency int errupt mechanism.
TS ( 16) The Time St amp bit is set when t he device recognized a t ime sync packet . I n such
a case t he hardware capt ures it s arrival t ime and st ores it in t he Time St amp regist er. For
more det ails see Sect ion 7. 9.
SECP ( 17) Securit y processing bit indicat es t hat t he hardware ident ified t he securit y
encapsulat ion and processed it as configured.
LinkSec processing This bit is set each t ime LinkSec processing is enabled
regardless if a mat ched SA was found.
I Psec processing This bit is set only if a mat ched SA was found. Not e t hat hardware
does not process packet s wit h an I Pv4 opt ion or I Pv6 ext ension header and t he SECP
bit is not set . This bit is not set for I Pv4 packet s short er t han 70 byt es, I Pv6 ESP
packet s short er t han 90 byt es, or I Pv6 AH packet s short er t han 94 byt es ( all excluding
CRC) . Not e t hat t hese packet sizes are never expect ed and set t he lengt h error
indicat ion in t he SECERR field.
LB ( 18) This bit provides a loopback st at us indicat ion which means t hat t his packet is sent
by a local VM ( VM t o VM swit ch indicat ion) .
NEXTP ( 19: 4) Large receive might be composed of mult iple packet s and packet s might
span in mult iple buffers ( descript ors) . These buffers are not guarant eed t o be consecut ive
while t he NEXTP field is a point er t o t he next descript or t hat belongs t o t he same RSC. The
NEXTP field is defined in descript or unit ( t he same as t he head and t ail regist ers) . The NEXTP
field is valid for any descript or of a large receive ( t he EOP bit is not set ) except t he last one.
I t is valid even in consecut ive descript ors of t he same packet . I n t he last descript or ( on which
t he EOP bit is set ) , NEXTP is not indicat ed but rat her all ot her st at us fields previously
described in t his sect ion.
Ext ended Error ( 12- bit offset 21, 2nd line)
Table 7.19 and t he following t ext describe t he possible errors report ed by hardware.
t
FCERR ( 2: 0) Defines error cases for FCoE packet s. Not e t hat hardware indicat es FCoE packet
recognit ion on t he Packet Type field in t he Rx descript or. Packet s wit h FCERR are post ed t o host
memory regardless of t he st ore bad packet set t ing in t he Filt er Cont rol regist er.
Tabl e 7. 19. Recei ve Er r or s ( RDESC.ERRORS) Layout
11 10 9 8: 7 6: 4 3 2: 0
I PE
L4E RXE
Rsv
Rsv HBO
Rsv
FCEOFe SECERR FCERR / FDI RERR
FCERR Code Meani ng
000 No except ion errors found
001 Bad FC CRC. Hardware does not check any ot her FC fields in t he packet .
010
One of t he following error indicat ions found by t he filt er unit ( hardware aut o- invalidat es a mat ched DDP filt er
cont ext if exist s) :
1. Received non-zero abort sequence condit ion in t he F_CTL field in FC read packet .
2. Received EOFa or EOFni or any unrecognized EOF or SOF flags.
011
The DMA unit get s FCoE packet s t hat mat ch a DDP cont ext while it missed t he packet t hat was marked as first
by t he filt er unit . Filt er cont ext paramet ers might be updat ed while DMA cont ext paramet ers are left int act ( see
error code 101b) .
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258
FDI RERR ( 2: 0) This field is relevant for non- FCoE packet s when t he flow direct or filt ers are
enabled.
FDI REr r ( 0) - Lengt h I f t he flow direct or filt er mat ches t he Lengt h bit , t his indicat es t hat t he
dist ance of t he mat ched filt er from t he hash t able exceeds t he FDI RCTRL. Max- Lengt h. I f t here is no
mat ched filt er, t he Lengt h bit is set if t he flow direct or linked list of t he mat ched hash value exceeds t he
FDI RCTRL. Max- Lengt h.
FDI REr r ( 1) - Dr op The Drop bit indicat es t hat a received packet mat ched a flow direct or filt er wit h
a drop act ion. I n t he case of perfect mode filt ering, it is expect ed t o find t he drop indicat ion only when
t he linked list in t he flow direct or bucket exceeds t he permit t ed Max- Lengt h. I n t his case, t he packet is
not dropped. I nst ead, it is post ed t o t he Rx queue ( indicat ed in t he filt er cont ext ) for soft ware handling
of t he Max- Lengt h except ion. I n t he case of hash mode filt ering, it is expect ed t hat t he drop queue is
always a valid queue so all packet s t hat mat ch t he drop filt er are visible t o soft ware.
FDI REr r ( 2) - Col l A mat ched flow direct or filt er wit h a collision indicat ion was found. The collision
indicat es t hat soft ware at t empt ed t o st ep over t his filt er wit h a different act ion t hat was already
programmed.
HBO ( 3) The Header Buffer Overflow bit is set if t he packet header ( calculat ed by hardware) is
bigger t han t he header buffer ( defined by PSRCTL. BSI ZEHEADER) . HBO report ing might be used by
soft ware t o allocat e bigger buffers for t he headers. I t is meaningful only if t he SPH bit in t he receive
descript or is set as well. The HDR_LEN field is valid even when t he HBO bit is set . Packet s wit h HBO
error are post ed t o host memory regardless of t he st ore bad packet set t ing ( FCTRL. SBP) . Packet DMA
t o it s buffers when t he HBO bit is set , depends on t he device set t ings as follows:
Rsv ( 5: 4) Reserved at zero.
SECERR ( 8: 7) : Securit y error indicat ion for LinkSec or I Psec. This field is meaningful only if t he SECP
bit in t he ext ended st at us is set .
100
One of t he following cases:
1. Unsupport ed FCoE version. FCSTAT equals t o 00b.
2. Out of order recept ion ( SEQ_CNT does not mat ch expect ed value) of a packet t hat mat ches an act ive DDP
cont ext . The filt er unit might set t he FCSTAT t o 01b, 10b or 11b.
101
No DMA resources due t o one of t he following cases list ed while t he hardware aut o- invalidat es t he DDP DMA
cont ext . Soft ware should invalidat e t he filt er cont ext before it can reuse it .
( 1) Last buffer exhaust ed ( no space in t he user buffers) .
( 2) Legacy receive queue is not enabled or no legacy receive descript or.
( 3) Some cases of a missed packet as described in FCERR code 011b.
This code should be ignored when FCSTAT equals 00b ( meaning no cont ext mat ch) .
110
Filt er cont ext valid and DMA cont ext invalid. I ndicat es t hat some packet ( s) were lost by t he DMA cont ext due t o
lack of legacy receive descript ors or were missed by t he Rx packet buffer. Not e t hat t he soft ware might ignore
t his error when FCSTAT equals 00b.
111 Reserved
SRRCTL. DESCTYPE DMA Funct i onal i t y
Header Split ( 010b) The header is post ed wit h t he rest of t he packet dat a t o t he packet buffer.
Always Split Mode ( 101b)
The header buffer is used as part of t he dat a buffers and cont ains t he first PSRCTL. BSI ZEHEADER
byt es of t he packet .
FCERR Code Meani ng

259
RXE ( 9) RXE is described in t he legacy descript or format in Sect ion 7. 1. 5.
L4E ( 10) L4 int egrit y error is valid only when t he L4I bit in t he St at us field is set . I t is act ive if L4
processing fails ( TCP checksum or UDP checksum or SCTP CRC) . Packet s wit h L4 int egrit y error are
post ed t o host memory regardless of t he st ore bad packet set t ing ( FCTRL. SBP) .
FCEOFe( 11) / I PE( 11) This bit has mult iplexed funct ionalit y. FCoE packet s are indicat ed as such
in t he Packet Type field in t he Rx descript or.
PKT_LEN ( 16- bit offset 32, 2nd line)
PKT_LEN holds t he number of byt es post ed t o t he packet buffer. The lengt h covers t he dat a writ t en t o a
receive buffer including CRC byt es ( if any) . Soft ware must read mult iple descript ors t o det ermine t he
complet e lengt h for packet s t hat span mult iple receive buffers. I f SRRCTL. DESCTYPE = 2 ( advanced
descript or header split t ing) and t he buffer is not split because t he header is bigger t han t he allocat ed
header buffer, t his field reflect s t he size of t he dat a writ t en t o t he dat a buffer ( header + dat a) .
VLAN Tag ( 16- bit offset 48, 2nd line)
This field is described in t he legacy descript or format in Sect ion 7. 1. 5.
7.1.7 Recei v e Descr i pt or Fet chi ng
7.1.7.1 Fet ch On Demand
The 82599 implement s a fet ch- by- demand mechanism for descript or fet ch. Descript ors are not fet ched
in advance, but rat her fet ched aft er a packet is received. Such a st rat egy eliminat es t he need t o st ore
descript ors on- die for each and every descript or queue in ant icipat ion for packet arrival.
SECERR Li nk Sec Er r or Repor t i ng I Psec Er r or Repor t i ng
00
No errors found or no securit y
processing
No errors found while an act ive SA found or no securit y processing.
01 No SA mat ch
I nvalid I Psec Prot ocol: I Psec prot ocol field ( ESP or AH) in t he received I P header
does not mat ch expect ed one st ored in t he SA t able.
10 Replay error
Lengt h error: ESP packet is not 4- byt es aligned or AH/ ESP header is t runcat ed ( for
example, a 28- byt e I Pv4 packet wit h I Pv4 header + ESP header t hat cont ains only
SPI and SN) or AH Lengt h field in t he AH header is different t han 0x07 for I Pv4 or
0x08 for I Pv6 or t he ent ire packet size excluding CRC is short er t han 70 byt es for
I Pv4 or 90 byt es for I Pv6 ESP or 94 byt es for I Pv6 AH.
11
Aut hent icat ion failed: Bad
signat ure
Aut hent icat ion failed: Bad signat ure.
Non- FCoE Pack et FCoE Pack et
I PE ( I Pv4 checksum error)
is described in
Sect ion 7. 1. 5.
FC EOF Except ion ( FCEOFe) . This bit indicat es unexpect ed EOF or SOF flags. The specific error is
defined by t he FCEOF bit in t he ext ended st at us previously described.
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260
7.1.8 Recei v e Descr i pt or Wr i t e- Back
The 82599 writ es back t he receive descript or immediat ely following t he packet writ e int o syst em
memory. I t is t herefore possible for a single descript or t o be writ t en at a t ime int o memory. However, if
aggregat ion occurs during descript or fet ch ( see Sect ion 7. 1. 7) , t hen t he descript ors fet ched in t he
aggregat ed operat ion are writ t en back in a single writ e- back operat ion. I n Receive Coalescing ( RSC) , all
t he descript ors except t he last one are writ t en back when t hey are complet ed. This does not have t o be
on packet boundaries but rat her when t he next descript or of t he same RSC is fet ched. See
Sect ion 7. 11. 5. 1 for more on RSC.
Not e: Soft ware can det ermine if a packet has been received by checking t he receive descript or DD
bit in memory or by checking t he value of t he receive head point er in t he RDH/ RDL regist ers.
Checking t hrough DD bit s eliminat es a pot ent ial race condit ion: all descript or dat a is post ed
int ernally prior t o increment ing t he head regist er and a read of t he head regist er could
pot ent ially pass t he descript or wait ing inside t he 82599.
7. 1. 9 Recei v e Descr i pt or Queue St r uct ur e
Figure 7. 11 shows t he st ruct ure of each of t he receive descript or rings. Not e t hat each ring uses a
cont iguous memory space.
Fi gur e 7.11. Recei v e Descr i pt or Ri ng St r uct ur e

Circular Buffer Queues

Head
Base + Size
Base
Receive
Queue
Tail

261
Soft ware insert s receive descript ors by advancing t he t ail point er( s) t o refer t o t he address of t he ent ry
j ust beyond t he last valid descript or. This is accomplished by writ ing t he descript or t ail regist er( s) wit h
t he offset of t he ent ry beyond t he last valid descript or. The 82599 adj ust s it s int ernal t ail point er( s)
accordingly. As packet s arrive, t hey are st ored in memory and t he int ernal head point er( s) is
increment ed by t he 82599.
When RSC is not enabled, t he visible ( ext ernal) head point er( s) reflect t he int ernal ones. On any
receive queue t hat enables RSC, updat ing t he ext ernal head point er might be delayed unt il int errupt
assert ion. When t he head point er( s) is equal t o t he t ail point er( s) , t he queue( s) is empt y. The 82599
st ops st oring packet s in syst em memory unt il soft ware advances t he t ail point er( s) , making more
receive buffers available.
The 82599 writ es back used descript ors j ust prior t o advancing t he head point er( s) . Head and t ail
point ers wrap back t o base when t he number of descript ors corresponding t o t he size of t he descript or
ring have been processed.
Fi gur e 7. 12. Descr i pt or s and Memor y Ri ngs
Head
Tail
Head &Tail
Together
Software writes a
descriptor to the
memory ring and
moves the tail
Software writes another
descriptor to the memory ring
Head
Tail

Tail
Head and
Tail
Together
Base
Base +1
Base +2
Base + size
Head
Tail
oldest first to
be added
newest latest
to be added
The tail moves down after the newest
descriptor was inserted between the old tail
location and the new tail location
Head
Tail
oldest first to
be added
newest latest
to be added
Second
descriptor to
be added
Head moves towards the tail and
frees-up the buffer to the SW.
Head moves towards the tail and
frees-up the buffer to the SW
Tail
1 2
3 4
5 6
7 8
Previous Head
location
Previous Head location
Original Head location
First Descriptor added
Data from the packet represented by
this descriptor is stored in memory
Data from the packet represented by
this descriptor is stored in memory
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262
The receive descript or head and t ail point ers reference t o 16- byt e blocks of memory. Shaded boxes in
Figure 7. 12 represent descript ors t hat have st ored incoming packet s but have not yet been recognized
by soft ware. Soft ware can det ermine if a receive buffer is valid by reading descript ors in memory rat her
t han by I / O reads. Any descript or wit h a DD bit set has been used by t he hardware, and is ready t o be
processed by soft ware.
Not e: The head point er point s t o t he next descript or t hat is t o be writ t en back. At t he complet ion of
t he descript or writ e- back operat ion, t his point er is increment ed by t he number of descript ors
writ t en back. Hardware owns all descript ors bet ween [ head. . . t ail] . Any descript or not in t his
range is owned by soft ware.
The receive descript or rings are described by t he following regist ers:
Receive Descript or Base Address regist ers ( RDBA) This regist er indicat es t he st art of t he
descript or ring buffer; t his 64- bit address is aligned on a 16- byt e boundary and is st ored in t wo
consecut ive 32- bit regist ers. Hardware ignores t he lower 4 bit s.
Receive Descript or Lengt h regist ers ( RDLEN) This regist er det ermines t he number of byt es
allocat ed t o t he circular buffer. This value must be a mult iple of 128 ( t he maximum cache line size) .
Since each descript or is 16 byt es in lengt h, t he t ot al number of receive descript ors is always a
mult iple of 8.
Receive Descript or Head regist ers ( RDH) This regist er holds a value t hat is an offset from t he
base, and indicat es t he in- progress descript or. There can be up t o 64K- 8 descript ors in t he circular
buffer. Hardware maint ains a shadow copy t hat includes t hose descript ors complet ed but not yet
st ored in memory.
Soft ware can det ermine if a packet has been received by eit her of t wo met hods: reading t he DD bit
in t he receive descript or field or by performing a PI O read of t he Receive Descript or Head regist er.
Checking t he descript or DD bit in memory eliminat es a pot ent ial race condit ion. All descript or dat a
is writ t en t o t he I / O bus prior t o increment ing t he head regist er, but a read of t he head regist er
could pass t he dat a writ e in syst ems performing I / O writ e buffering. Updat es t o receive descript ors
use t he same I / O writ e pat h and follow all dat a writ es. Consequent ly, t hey are not subj ect t o t he
race.
Receive Descript or Tail regist ers ( RDT) This regist er holds a value t hat is an offset from t he
base, and ident ifies t he locat ion beyond t he last descript or hardware can process. This is t he
locat ion where soft ware writ es t he first new descript or.
For t est abilit y purpose only: I f t he t ail point er is larger t hen t he ring lengt h, t hen t he 82599 reads
t he descript or ring in an endless loop unt il t he queue is disabled. Prior t o set t ing such a t ail point er
value, it is required t o init ialize all t he descript ors of t he ring and set t he RDWBOFST regist er.
During recept ion, hardware does not writ e back t he Rx descript ors on t he Rx ring since t hey are
needed for t he endless recept ion. I nst ead, hardware writ es back t he Rx descript ors at t he Rx
descript or offset plus RDWBOFST. RDWBOFST is defined in descript or unit s as t he head and t ail
regist ers while t hat t here is a single value defined for all Rx descript or rings.
I f soft ware st at ically allocat es buffers, and uses a memory read t o check for complet ed descript ors, it
simply has t o zero t he st at us byt e in t he descript or t o make it ready for reuse by hardware. This is not
a hardware requirement , but is necessary for performing an in- memory scan. This is relevant only t o
legacy descript ors.
All t he regist ers cont rolling t he descript or rings behavior should be set before receive is enabled, apart
from t he t ail regist ers which are used during t he regular flow of dat a.
7. 1. 9. 1 Low Recei v e Descr i pt or s Thr eshol d
As previously described, t he size of t he receive queues is measured by t he number of receive
descript ors. During run t ime, soft ware processes descript ors and upon complet ion of descript ors,
increment s t he Receive Descript or Tail regist ers. At t he same t ime, t he hardware may post new
received packet s increment ing t he Receive Descript or Head regist ers for each used descript or.

263
The number of usable ( free) descript ors for t he hardware is t he dist ance bet ween t he Tail and Head
regist ers. When t he t ail reaches t he head, t here are no free descript ors and furt her packet s might be
eit her dropped or block t he receive FI FO. I n order t o avoid t his sit uat ion, t he 82599 might generat e a
low lat ency int errupt ( associat ed t o t he relevant Rx queue) once t here are less equal free descript ors
t han specified by a low level t hreshold. The t hreshold is defined in 64 descript ors granularit y per queue
in t he SRRCTL[ n] . RDMTS field.
7. 1. 10 Header Spl i t t i ng
7.1.10.1 Pur pose
This feat ure consist s of split t ing a packet header t o a different memory space. This helps t he host t o
fet ch headers only for processing: headers are post ed t hrough a regular snoop t ransact ion in order t o
be processed by t he host CPU. I t is recommended t o perform t his t ransact ion wit h DCA enabled ( see
Sect ion 7.5) .
The packet ( header + payload) is st ored in memory. Lat er, an I OAT t ransact ion moves t he payload from
t he driver space t o t he applicat ion memory.
The 82599s support for header split is cont rolled by t he DESCTYPE field of t he Split Receive Cont rol
regist ers ( SRRCTL) . The following modes exist in bot h split and non- split modes:
000b: Legacy mode - Legacy descript ors are used, headers and payloads are not split .
001b: Advanced mode, no split - Advanced descript ors are in use, header and payload are not split .
010b: Advanced mode, header split - Advanced descript ors are in use, header and payload are split
t o different buffers.
101b: Advanced mode, split always - Advanced descript ors are in use, header and payload are split
t o different buffers. I f no split is done, t he first part of t he packet is st ored in t he header buffer.
When using a split always descript or t ype, t he header buffer size ( BSI ZEHEADER) should be set t o
four which equals t o 256 byt es.
The 82599 uses packet split t ing when t he SRRCTL[ n] . DESCTYPE is great er t han one.
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264
7. 1.10. 2 Descr i pt i on
The physical address of each buffer is writ t en in t he Buffer Addresses fields:
The packet buffer address includes t he address of t he buffer assigned t o t he packet dat a.
The header buffer address includes t he address of t he buffer t hat cont ains t he header informat ion.
The receive DMA module st ores t he header port ion of t he received packet s int o t his buffer.
The sizes of t hese buffers are st at ically defined in t he SRRCTL[ n] regist ers:
The BSI ZEPACKET field defines t he size of t he buffer for t he received packet .
The BSI ZEHEADER field defines t he size of t he buffer for t he received header. I f header split is
enabled, t his field must be configured t o a non- zero value. The 82599 only writ es t he header
port ion int o t he header buffer. The header size is det ermined by t he opt ions enabled in t he PSRTYPE
regist ers.
When header split is select ed, t he packet is split only on select ed t ypes of packet s. A bit exist s for each
opt ion in PSRTYPE[ n] regist ers, so several opt ions can be used in conj unct ion. I f one or more bit s are
set , t he split t ing is performed for t he corresponding packet t ype. See Sect ion 8. 2. 3.7.4 for det ails on
t he possible header t ypes support ed. I n virt ualizat ion mode, a separat e PSRTYPE regist er is provided
per pool up t o t he number of pools enabled. I n non- virt ualizat ion mode, only PSRTYPE[ 0] is used.
Rules regarding header split :
Packet s t hat have headers bigger t han 1023 byt es are not split .
The header of a fragment ed I Pv6 packet is defined unt il t he fragment ed ext ension header.
Header split must not be used in a queue used for a FCoE large receive.
An I P packet wit h more t han a single I P header ( such as any combinat ion of I Pv4 and I Pv6
t unneling) is not split .
Packet header cannot span across buffers, t herefore, t he size of t he header buffer must be larger
t han any expect ed header size. I n case of header split mode ( SRRCTL. DESCTYPE = 010b) , a packet
wit h a header larger t han t he header buffer is not split .
Fi gur e 7.13. Header Spl i t t i ng Di agr am
Payload
Header
Data
Buffer
Header
Buffer
Host memory
Packet Payload
Packet Header
Packet Buffer address
Header Buffer address
0
8
0 31 32 63

265
I f an I Psec header is present in t he receive packet , t he following rules apply:
I Psec packet s handled in t he 82599 always include I Psec header in a split done at I P boundary.
I Psec packet s handled in soft ware must never do header split .
Table 7.20 list s t he behavior of t he 82599 in t he different modes.
7. 1.11 Recei v e Check sum Of f l oadi ng
The 82599 support s t he offloading of t hree receive checksum calculat ions: t he fragment checksum, t he
I Pv4 header checksum, and t he TCP/ UDP checksum.
For support ed packet / frame t ypes, t he ent ire checksum calculat ion can be offloaded t o t he 82599. The
82599 calculat es t he I Pv4 checksum and indicat es a pass/ fail indicat ion t o soft ware via t he I Pv4
Checksum Error bit ( RDESC. I PE) in t he ERROR field of t he receive descript or. Similarly, t he 82599
calculat es t he TCP or UDP checksum and indicat es a pass/ fail condit ion t o soft ware via t he TCP/ UDP
Checksum Error bit ( RDESC. TCPE) . These error bit s are valid when t he respect ive st at us bit s indicat e
t he checksum was calculat ed for t he packet ( RDESC. I PCS and RDESC. L4CS, respect ively) .
Similarly, if RFCTL. I pv6_DI S and RFCTL. I P6Xsum_DI S are cleared t o zero, t he 82599 calculat es t he TCP
or UDP checksum for I Pv6 packet s. I t t hen indicat es a pass/ fail condit ion in t he TCP/ UDP Checksum
Error bit ( RDESC. TCPE) .
Support ed frame t ypes:
Et hernet I I
Et hernet SNAP
Tabl e 7. 20. Behavi or i n Header Spl i t Modes
DESCTYPE Condi t i on SPH HBO PKT_LEN HDR_LEN Header and Pay l oad DMA
Split
1. Header can' t be decoded 0 0
Min( packet lengt h,
buffer size)
0x0
Header + Payload --> Packet
Buffer
2. Header < =
BSI ZEHEADER
1 0
Min ( payload lengt h,
buffer size)
3
Header size
Header --> Header Buffer
Payload --> Packet Buffer
3. Header > BSI ZEHEADER 1 1
Min ( packet lengt h,
buffer size)
Header size
5
Header + Payload --> Packet
Buffer
Split always
use header
buffer
1. Header can' t be decoded
and packet lengt h < =
BSI ZEHEADER
0 0 0x0 Packet lengt h
Header + Payload --> Header
Buffer
2. Header can t be decoded
and packet lengt h >
BSI ZEHEADER
0 0
Min ( packet lengt h
BSI ZEHEADER, dat a
buffer size)
Undefined
Header + Payload --> Header +
Packet Buffers
4
3. Header < =
BSI ZEHEADER
1 0
Min ( payload lengt h,
dat a buffer size)
Header Size
Header --> Header Buffer
Payload --> Packet Buffer
4. Header > BSI ZEHEADER 1 1
Min ( packet lengt h
BSI ZEHEADER, dat a
buffer size)
Header Size
5
Header + Payload --> Header +
Packet Buffer
Not es:
1. Part ial means up t o BSI ZEHEADER.
2. HBO is set t o 1b if t he header size is bigger t han BSI ZEHEADER and zero ot herwise.
3. I n a header only packet ( such as TCP ACK packet ) , t he PKT_LEN is zero.
4. I f t he packet spans more t han one descript or, only t he header buffer of t he first descript or is used.
5. HDR_LEN doesn' t reflect t he act ual dat a size st ored in t he header buffer. I t reflect s t he header size det ermined by t he parser.
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266
The previous t able list s general det ails about what packet s are processed. I n more det ail, t he packet s
are passed t hrough a series of filt ers t o det ermine if a receive checksum is calculat ed.
Et hernet MAC Address Filt er
This filt er checks t he MAC dest inat ion address t o be sure it is valid ( t hat is I A mat ch, broadcast ,
mult icast , et c. ) . The receive configurat ion set t ings det ermine which Et hernet MAC addresses are
accept ed. See t he various receive cont rol configurat ion regist ers such as FCTRL, MCSTCTRL ( RTCL. UPE,
MCSTCTRL. MPE, FCTRL. BAM) , MTA, RAL, and RAH for det ails.
SNAP/ VLAN Filt er
This filt er checks t he next headers looking for an I P header. I t is capable of decoding Et hernet I I ,
Et hernet SNAP, and I EEE 802. 3ac headers. I t skips past any of t hese int ermediat e headers and looks
for t he I P header. The receive configurat ion set t ings det ermine which next headers are accept ed. See
t he various receive cont rol configurat ion regist ers such as VLNCTRL. VFE, VLNCTRL. VET, and VFTA for
more det ails.
I Pv4 Filt er
This filt er checks for valid I Pv4 headers. The version field is checked for a correct value ( 4) .
I Pv4 headers are accept ed if t hey are any size great er t han or equal t o five ( Dwords) . I f t he I Pv4
header is properly decoded, t he I P checksum is checked for validit y.
Tabl e 7.21. Suppor t ed Recei ve Check sum Capabi l i t i es
Pack et Ty pe
Har dw ar e I P
Check sum Cal cul at i on
Har dw ar e TCP/ UDP
Check sum Cal cul at i on
I P header s prot ocol field cont ains a prot ocol # ot her t han TCP or UDP. Yes No
I Pv4 + TCP/ UDP packet s. Yes Yes
I Pv6 + TCP/ UDP packet s. No ( N/ A) Yes
I Pv4 packet has I P opt ions ( I P header is longer t han 20 byt es) . Yes Yes
I Pv6 packet wit h next header opt ions:
Hop- by- hop opt ions.
Dest inat ions opt ions ( wit hout home address) .
Dest inat ions opt ions ( wit h home address) .
Rout ing ( wit h segment left 0) .
Rout ing ( wit h segment left > 0) .
Fragment .
No ( N/ A)
No ( N/ A)
No ( N/ A)
No ( N/ A)
No ( N/ A)
No ( N/ A)
Yes
Yes
No
Yes
No
No
Packet has TCP or UDP opt ions. Yes Yes
I pv4 t unnels:
I Pv4 packet in an I Pv4 t unnel.
No
Yes ( I Pv4)
No
No
I Pv6 t unnels:
No
No
No
No
Packet is an I Pv4 fragment . Yes UDP checksum assist
Packet is great er t han 1522 byt es. Yes Yes
Packet has 802. 3ac t ag. Yes Yes

267
I Pv6 Filt er
This filt er checks for valid I Pv6 headers, which are a fixed size and have no checksum. The I Pv6
ext ension headers accept ed are: Hop- by- hop, dest inat ion opt ions, and rout ing. The maximum
ext ension header size support ed is 256 byt es. The maximum t ot al header size support ed is 1 KB.
I Pv6 Ext ension Headers
I Pv4 and TCP provide header lengt hs, which enable hardware t o easily navigat e t hrough t hese headers
on packet recept ion for calculat ing checksum and CRC, et c. For receiving I Pv6 packet s, however, t here
is no I P header lengt h t o help hardware find t he packet ' s ULP ( such as TCP or UDP) header. One or
more I Pv6 ext ension headers might exist in a packet bet ween t he basic I Pv6 header and t he ULP
header. Hardware must skip over t hese ext ension headers t o calculat e t he TCP or UDP checksum for
received packet s.
The I Pv6 header lengt h wit hout ext ensions is 40 byt es. The I Pv6 field Next Header Type indicat es what
t ype of header follows t he I Pv6 header at offset 40. I t might be an upper layer prot ocol header such as
TCP or UDP ( next header t ype of 6 or 17, respect ively) , or it might indicat e t hat an ext ension header
follows. The final ext ension header indicat es wit h it ' s Next Header Type field t he t ype of ULP header for
t he packet .
I Pv6 ext ension headers have a specified order. However, dest inat ions must be able t o process t hese
headers in any order. Also, I Pv6 ( or I Pv4) might be t unneled using I Pv6, and t hus anot her I Pv6 ( or
I Pv4) header and pot ent ially it s ext ension headers might be found aft er t he ext ension headers.
The I Pv4 next header t ype is at byt e offset 9. I n I Pv6, t he first next header t ype is at byt e offset 6.
All I Pv6 ext ension headers have t he next header t ype in t heir first eight bit s. Most have t he lengt h in
t he second eight bit s ( Offset Byt e[ 1] ) as follows:
Table 7.23 list s t he encoding of t he Next Header Type field and informat ion on det ermining each header
t ype' s lengt h. Ot her I Pv6 ext ension headers - not indicat ed in Table 7. 23 - are not recognized by t he
82599. Any processing of packet cont ent t hat follows such ext ension headers is not support ed.
Tabl e 7. 22. Typi cal I Pv 6 Ex t ended Header For mat ( Tr adi t i onal Repr esent at i on)
1
0 1 2 3 4 5 6 7 8 9 0
2
0 1 2 3 4 5 6 7 8 9 0
3
0 1 2 3 4 5 6 7 8 9 0
Next Header Type Lengt h
Tabl e 7. 23. Header Ty pe Encodi ng and Lengt hs
Header Nex t Header Ty pe
Header Lengt h ( uni t s ar e by t es unl ess
ot her w i se speci f i ed)
I Pv6 6 Always 40 byt es
I Pv4 4
Offset bit s[ 7: 4]
Unit = 4 byt es
TCP 6
Offset Byt e[ 12] . Bit s[ 7: 4]
Unit = 4 byt es
UDP 17 Always 8 byt es
Hop- by- Hop Opt ions 0 - Not e 1 8+ Offset Byt e[ 1]
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268
UDP/ TCP Filt er
This filt er checks for a valid UDP or TCP header. The prot ot ype next header values are 0x11 and 0x06,
respect ively.
7. 1. 12 SCTP Recei v e Of f l oad
I f a receive packet is ident ified as SCTP, t he 82599 checks t he CRC32 checksum of t his packet and
ident ifies t his packet as SCTP. Soft ware is not ified of t he CRC check via t he L4I and L4E bit s in t he
Ext ended St at us field and Ext ended Error field in t he Rx descript or. The det ect ion of an SCTP packet is
indicat ed via t he SCTP bit in t he Packet Type field of t he Rx descript or. SCTP CRC uses t he CRC32c
polynomial as follows ( 0x11EDC6F41) :
X
32
+X
28
+X
27
+X
26
+X
25
+X
23
+X
22
+X
20
+X
19
+X
18
+X
14
+X
13
+X
11
+X
10
+X
9
+X
8
+X
6
+X
0
The checker assumes t he following SCTP packet format .
7.1.13 Recei v e UDP Fr agment at i on Check sum
The 82599 might provide a receive fragment ed UDP checksum offload for I Pv4 non- t unneled packet s.
The RXCSUM. PCSD bit should be cleared and t he RXCSUM. I PPCSE bit should be set t o enable t his
mode.
The following t able list s t he out come descript or fields for t he following incoming packet s t ypes.
Dest inat ion Opt ions 60 8+ Offset Byt e ( not e 1)
Rout ing 43 8+ Offset Byt e ( not e 1)
Fragment 44 Always 8 byt es
Aut hent icat ion 51 Not e 3
Encapsulat ing Securit y Payload 50 Not e 3
No Next Header 59 Not e 2
Not es:
1. Hop- by- hop opt ions header is only found in t he first next header t ype of an I Pv6 header.
2. When no next header t ype is found, t he rest of t he packet should not be processed.
3. Encapsulat ed securit y payload packet handled by soft ware The 82599 cannot offload packet s wit h t his header t ype.
Tabl e 7.24. SCTP Header
0 1 2 3 4 5 6 7
0 0 1
8 9 0 1 2 3 4 5
1 1 1 0 2
6 7 8 9 0 1 2 3
2 2 2 2 2 2 3
4 5 6 7 8 9 0 1
Source Port Dest inat ion Port
Verificat ion Tag
CRC Checksum ( CRC32c)
Chunks 1. . n
Tabl e 7.23. Header Ty pe Encodi ng and Lengt hs
Header Nex t Header Ty pe
Header Lengt h ( uni t s ar e by t es unl ess
ot her w i se speci f i ed)

269
When t he driver comput es t he 16- bit ones complement sum on t he incoming packet s of t he UDP
fragment s, it should expect a value of 0xFFFF. Refer t o Sect ion 7. 1. 2. 8. 3 for support ed packet format s.
I ncomi ng Pack et Type Fr agment Check sum UDPV UDPCS / L4CS
Non- I P packet 0 0 0
I Pv6 Packet
0 0
Depends on t ransport
UDP: 1 / 1
TCP: 0 / 1
Non fragment ed I Pv4 packet
Fragment ed I Pv4 wit h prot ocol =
UDP, first fragment ( UDP prot ocol
present )
The unadj ust ed 1s complement
checksum of t he I P payload
1 if t he UDP header
checksum is valid ( not
0)
1 / 0
Fragment ed I Pv4, when not first
fragment
The unadj ust ed 1s complement
checksum of t he I P payload
0 1 / 0
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271
7.2 Tr ansmi t Funct i onal i t y
7.2.1 Pack et Tr ansmi ssi on
Transmit packet s are made up of dat a buffers in host memory t hat are indicat ed t o hardware by point er
and lengt h pairs. These point er and lengt h pairs are named as t ransmit descript ors t hat are st ored in
host memory as well.
Soft ware prepares memory st ruct ures for t ransmission by assembling a list of descript ors. I t t hen
indicat es t his list t o hardware for updat ing t he on- chip t ransmit t ail point er. Hardware t ransmit s t he
packet only aft er it has complet ely fet ched all packet dat a from host memory and deposit ed it int o t he
on- chip t ransmit FI FO. This st ore and forward scheme enables hardware- based offloads such as TCP or
UDP checksum comput at ion, and many ot her ones det ailed in t his document while avoiding any
pot ent ial PCI e under- runs.
7.2.1.1 Tr ansmi t St or age i n Sy st em Memor y
A packet ( or mult iple packet s in t ransmit segment at ion) can be composed of one or mult iple buffers.
Each buffer is indicat ed by a descript or. Descript ors of a single packet are consecut ive, while t he first
one point s t o t he first buffer and t he last one point s t o t he last buffer ( see Figure 7.14) . The following
rules must be kept :
Address alignment of t he dat a buffers can be on any byt e boundary.
Dat a buffers of any t ransmit t ed packet must include at least t he 12 byt es of t he source and
dest inat ion Et hernet MAC addresses as well as t he 2 byt es of t he Type/ Len field.
A packet ( or mult iple packet s in t ransmit segment at ion) can span any number of buffers ( and t heir
descript ors) up t o a limit of 40 minus WTHRESH minus 2 ( see Sect ion 7. 2. 3.3 for Tx Ring det ails
and sect ion Sect ion 7.2. 3. 5.1 for WTHRESH det ails) . For best performance it is recommended t o
minimize t he number of buffers as possible.
7.2.1.2 Tr ansmi t Pat h i n t he 82599
The t ransmit pat h in t he 82599 consist s of t he following st ages:
Descript or plane
The 82599 maint ains a set of 128 on- die descript or queues. Each queue is associat ed wit h a
single descript or ring in syst em memory. See Sect ion 7. 2. 3. 3 for more det ails on t he Tx
descript or rings. Each on- die descript or queue must be able t o st ore up t o 40 descript ors in
order t o achieve t he desired performance.
Fi gur e 7. 14. Tx Pack et i n Host Memor y
. . .
Tx Data in host memory
Tx Buffer 1 Tx Buffer 2 Tx Buffer N
Tx Descriptor 1
Tx Descriptor N
Tx Descriptor 2
. . .
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A fet ch mechanism loads Tx descript ors from t he descript or rings in syst em memory t o t he
respect ive descript or queues in t he 82599. A descript or fet ch arbit er det ermines t he order in
which descript ors are fet ched int o t he various on- die descript or queues. See Sect ion 7.2. 3. 4 for
more det ails on t he fet ch mechanism.
An arbit rat ion scheme det ermines t he order in which descript ors are processed and request s
are generat ed for dat a reads. These request s load packet dat a from syst em memory int o a set
of Tx packet buffers. The arbit rat ion mechanism varies wit h configurat ion and is shown in
Figure 7. 17.
Once a packet has been fet ched int o a packet buffer, st at us is ( opt ionally) writ t en back int o
syst em memory. See Sect ion 7. 2. 3. 5 for more det ails.
Packet plane ( dat a plane)
Packet dat a is st ored in up t o eight packet buffers. The number and size of packet buffers vary
wit h t he mode of operat ion and is described in Sect ion 7. 2. 1. 2. 2.
I f more t han a single packet buffer is enabled, an arbit rat ion scheme det ermines t he order in
which packet s are t aken out of t he packet buffers and sent t o t he MAC for t ransmission. The
arbit rat ion mechanism is shown in Figure 7. 17.
7.2.1. 2.1 Tx Queues Assi gnment
The 82599 support s a t ot al of 128 queues per LAN port . Each Tx queue is associat ed wit h a packet
buffer and t he associat ion varies wit h t he operat ional mode. The following mechanisms impact t he
associat ion of t he Tx queues. These are described briefly in t his sect ion, and in full det ails in separat e
sect ions:
Virt ualizat ion ( VT) - I n a virt ualized environment , DMA resources are shared bet ween more t han
one soft ware ent it y ( operat ing syst em and/ or device driver) . This is done t hrough allocat ion of
t ransmit descript or queues t o virt ual part it ions ( VMM, I OVM, VMs, or VFs) . Allocat ion of queues t o
virt ual part it ions is done in set s of queues of t he same size, called queue pools, or pools. A pool is
associat ed wit h a single virt ual part it ion. Different queues in a pool can be associat ed wit h different
packet buffers. For example, in a DCB syst em, each of t he queues in a pool might belong t o a
different TC and t herefore t o a different packet buffer. The PFVFTE regist er cont ains a bit per VF.
When t he bit is set t o 0b, packet t ransmission from t he VF is disabled. When set t o 1b, packet
t ransmission from t he VF is enabled.
DCB DCB provides QoS t hrough priorit y queues, priorit y flow cont rol, and congest ion
management . Queues are classified int o one of several ( up t o eight ) Traffic Classes ( TCs) . Each TC
is associat ed wit h a single unique packet buffer.
Transmit fanout A single descript or queue might be enough for a given funct ionalit y. For
example, in a VT syst em, a single Tx queue can be allocat ed per VM. However, it is oft en t he case
t hat t he dat a rat e achieved t hrough a single buffer is limit ed. This is especially t rue wit h
10 GbE, and t raffic needs t o be divided int o several Tx queues in order t o reach t he desired dat a
rat e. Therefore, mult iple queues might be provided for t he same funct ionalit y.
Table 7. 25 list s t he queuing schemes. Select ion of a scheme is done via t he MTQC regist er.

273
Not e: Soft ware can use any number of queues per each TC or per each pool wit hin t he allocat ed
ranges previously described by disabling any unused queue.
Not e: Programming MTQC must be done only during t he init phase while soft ware must also set
RTTDCS.ARBDI S before configuring MTQC and t hen clear RTTDCS.ARBDI S aft erwards.
Allocat ing descript or queues t o VFs uses a consist ent indexing over t he different Tx queuing schemes.
The most significant bit s of t he queue index represent t he VF index, and t he least significant bit s are
eit her t he TC index or are used by soft ware t o dispat ch t raffic according t o a Transmit Side Scaling
( TSS) algorit hm similar t o RSS in t he Rx pat h.
The Tx queue numbers associat ed wit h t he TCs are list ed in t he following t ables: Table 7.26 and
Table 7.27.
Tabl e 7. 25. Tx Queui ng Schemes
VT DCB Queues Al l ocat i on Pack et Buf f er s al l ocat i on
No No
A single set of 64 queues is assigned t o a
single packet buffer. Queues 64127 should
not be used.
A single packet buffer for all t raffic
No Yes
Eight TCs mode allocat ion of 32- 32- 16- 16-
8- 8- 8- 8 queues for TC0-TC1- - TC7,
respect ively.
Four TCs mode allocat ion of 64- 32- 16- 16
queues for TC0-TC1- - TC3, respect ively.
A separat e packet buffer is allocat ed t o each
TC ( t ot al of four or eight ) .
Yes No
32 pools x 4 queues, or
64 pools x 2 queues
A single packet buffer for all t raffic.
Yes Yes
16 pools x 8 TCs, or
32 pools x 4 TCs
A separat e packet buffer is allocat ed t o each
TC ( t ot al of four or eight ) .
Tabl e 7. 26. Tx Queues I ndex i ng When VT- on
VT mode Al l ocat i on of queue i ndex bi t s accor di ng t o
6 5 4 3 2 1 0
64 VFs + TSS VF ( 63. . 0) TSS
32 VFs + TSS or 4 TCs VF ( 31 . . 0) TSS / TC
16 VFs + 8 TCs VF ( 15 . . 0) TC
Tabl e 7. 27. Tx Queues I ndex i ng When VT- of f and DCB- on
TC mode TCn # of Qs Queues at t ached t o TCn
4 TCs
TC0 64 0xxxxxx
TC1 32 10xxxxx
TC2 16 110xxxx
TC3 16 111xxxx
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Not e: x refers t o bot h 0 or 1, and is used by soft ware t o dispat ch Tx flows via TSS algorit hm.
7.2.1. 2.2 Tx Pack et Buf f er s
As previously described, t he following modes exist for t he 82599 packet buffers:
A single 160 KB packet buffer t hat serves all Tx descript or queues, leading t o one single ( or no) TC
enabled, TC0
Four 40 KB packet buffers, one per enabled TC, leading t o four TCs, TC0 t o TC3
Eight 20 KB packet buffers, one per enabled TC, leading t o eight TCs, TC0 t o TC7
The size of t he Tx packet buffer( s) is programmed via t he TXPBSI ZE regist ers, one regist er per TC.
Null- sized packet buffer corresponds t o a disabled TC.
Not e: Set t ing t he packet buffers size leads t o a different part it ion of a shared int ernal memory and
must be done during boot , prior t o communicat ing, and followed by a soft ware reset .
8 TCs
TC0 32 00xxxxx
TC1 32 01xxxxx
TC2 16 100xxxx
TC3 16 101xxxx
TC4 8 1100xxx
TC5 8 1101xxx
TC6 8 1110xxx
TC7 8 1111xxx
Tabl e 7.27. Tx Queues I ndex i ng When VT- of f and DCB- on ( Cont i nued)
TC mode TCn # of Qs Queues at t ached t o TCn

275
7.2.1.2.3 Tx Ar bi t r at i on Schemes
There are basically four Tx arbit rat ion schemes, one per each combinat ion of t he DCB and Virt ualizat ion
( VT) enabled/ disabled modes. They are configured via t he MTQC. MTQE regist er field.
DCB- on/ VT- on
When bot h DCB and virt ualizat ion are enabled, queues are allocat ed t o t he packet buffers in a fixed
manner, t he same number of queues per each TC. Two DCB modes are support ed, four TCs or eight TCs
mode, according t o coherent configurat ion made in regist ers TXPBSI ZE and MTQC.
Descr i pt or Pl ane Ar bi t er s and Schedul er s:
Tr ansmi t Rat e- Schedul er Once a frame has been fet ched out from a t ransmit rat e- limit ed
queue, t he next t ime anot her frame could be fet ched from t hat queue is regulat ed by t he t ransmit
rat e- scheduler. I n t he meant ime, t he queue is considered as if it was empt y ( such as swit ched- off )
for t he subsequent arbit rat ion layers.
Fi gur e 7. 15. Tx Ar bi t r at i on Schemes
LAN Port 0 / 1
Tx
queue
0
Tx
queue
1
Tx
queue
127
Transmit Descriptor Rings (queues). Each queue has a cache of 40 descriptors
The 82599 Has up to 8 Packet
Buffers
The size of all of the packet buffers together is 160 KB
The 82599 can have any number of packet buffers less than or
equal to eight.
The packet buffer size is specified for each packet buffer in the
TXPBSI ZE regist ers.
Tx
queue
2
Tx
queue
3
Tx
queue
4
Tx
queue
5
Tx
queue
6
Tx
queue
7
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VM Wei ght ed Round Robi n Ar bi t er Descript ors are fet ched out from queues at t ached t o t he
same TC in a frame- by- frame weight ed round- robin manner, while t aking int o account any rat e
limit at ion as previously described. Weight s or credit s allocat ed t o each queue are configured via t he
RTTDT1C regist er. Bandwidt h unused by one queue is reallocat ed t o t he ot her queues wit hin t he TC,
proport ionally t o t heir relat ive bandwidt h shares. TC bandwidt h limit at ion is dist ribut ed across all
t he queues at t ached t o t he TC, proport ionally t o t heir relat ive bandwidt h shares. Det ails on
weight ed round- robin arbit er bet ween t he queues can be found in Sect ion 7. 7. 2. 3. I t is assumed
t raffic is dispat ched across t he queues at t ached t o a same TC in a st raight forward manner,
according t o t he VF t o which it belongs.
TC Wei ght ed St r i ct Pr i or i t y Ar bi t er Descript ors are fet ched out from queues at t ached t o
different TCs in a frame- by- frame weight ed st rict - priorit y manner. Bandwidt h unused by one TC is
reallocat ed t o t he ot hers, proport ionally t o t heir relat ive bandwidt h shares. Link bandwidt h
limit at ion is dist ribut ed across all t he TCs, proport ionally t o t heir relat ive bandwidt h shares. Det ails
on weight ed st rict - priorit y arbit er bet ween t he TCs can be found at Sect ion 7. 7. 2. 3. I t is assumed
( each) driver dispat ches t raffic across t he TCs according t o t he 802. 1p User Priorit y field insert ed by
t he operat ing syst em and according t o a user priorit y- t o-TC Tx mapping t able.
Pack et Pl ane Ar bi t er s:
TC Wei ght ed St r i ct Pr i or i t y Ar bi t er Packet s are fet ched out from t he different packet buffers
in a frame- by- frame weight ed st rict - priorit y manner. Weight s or credit s allocat ed t o each TC ( such
as t o each packet buffer) are configured via RTTPT2C regist ers, wit h t he same allocat ion done at
t he descript or plane. Bandwidt h unused by one TC and link bandwidt h limit at ion is dist ribut ed over
t he TCs as in t he descript or plane. Det ails on weight ed st rict - priorit y arbit er bet ween t he TCs can
be found in Sect ion 7.7. 2. 3.
Pr i or i t y Fl ow Cont r ol packet s are insert ed wit h st rict priorit y over any ot her packet s.
Manageabi l i t y packet s are insert ed wit h st rict priorit y over dat a packet s from t he same TC, wit h
respect t o t he bandwidt h allocat ed t o t he concerned TC. TCs t hat belong t o manageabilit y packet s
are cont rolled by MNGTXMAP. MAP.

277
Not e: Replicat ion of TC arbit ers before and aft er t he packet buffers is required t o provide arbit rat ion
whet her PCI bandwidt h is smaller or great er t han t he link bandwidt h, respect ively.
DCB- on/ VT- off
When DCB is enabled and virt ualizat ion disabled, queues are allocat ed t o t he packet buffers in a fixed
manner according t o t he number of TCs. Two DCB modes are support ed, four TCs or eight TCs mode,
according t o coherent configurat ion made in regist ers TXPBSI ZE and MTQC. I n Figure 7.17, eight TCs
mode is shown.
The unique difference wit h t he DCB- on/ VT- on arbit rat ion scheme previously described is t hat t he
VM weight ed round- robin arbit ers are degenerat ed int o simple frame- by- frame round- robin arbit ers
across t he queues at t ached t o t he same TC. I t is assumed driver dispat ches t raffic across t he
queues at t ached t o a same TC according t o hashing performed on MAC dest inat ion addresses. This
is aimed t o minimize crosst alk bet ween t ransmit rat e- limit ed and non- rat e- limit ed flows.
Fi gur e 7. 16. Tr ansmi t Ar chi t ect ur e DCB- on/ VT- on Ei ght TCs Mode
D
Q
0
PB
0
PB
7
BCN
Rate-Scheduler
Packet
Buffers
Flow Control per TC
Manageability packets
Descriptor
Fetch Arbiter
D
Q
120
D
Q
7
D
Q
127
Descriptor
Queues
Weighted
Strict Priority
Weighted
Strict Priority
Data read
request
Data
MAC
Traffic Class 0 Traffic Class 7
VM Arbiters,
one per TC
Weighted
Round-Robin
Weighted
Round-Robin
Descriptor Plane
TC Arbiter
Packet Plane
TC Arbiter
D
Q
8
D
Q
15
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DCB- off/ VT- on
When DCB is disabled and virt ualizat ion enabled, all t he 128 queues are allocat ed t o a single packet
buffer PB( 0) . Queues are grouped int o 32 or 64 pools of 4 or 2 queues, respect ively. The number of
queue pools corresponds t o t he number of VFs exposed. Queues are at t ached t o pools according t o
consecut ive indexes
For t he 32 pools case, queues 0, 1, 2, 3 are at t ached t o VF0, queues 4, 5, 6, 7 are at t ached t o
VF1, and so fort h up t o VF31.
For t he 64 pools case, queues 0 and 1 are at t ached t o VF0, queues 2 and 3 are at t ached t o VF1,
and so fort h up t o VF63.
Descr i pt or Pl ane Ar bi t er s:
Descr i pt or Queues Round Robi n Ar bi t er Descript ors are fet ched out from t he int ernal
descript or queues at t ached t o t he same pool in a frame- by- frame round- robin manner. I t is
assumed driver dispat ches t raffic across t he queues of a same pool according t o some Transmit
Side Scaling ( TSS) algorit hm similarly t o what is done by hardware in t he Rx pat h wit h RSS.
Fi gur e 7.17. Tr ansmi t Ar chi t ect ur e DCB- on/ VT- of f Ei ght TCs Mode
D
Q
0
PB
0
PB
7
BCN
Rate-Scheduler
Packet
Buffers
Flow Control per TC
Descriptor
Fetch Arbiter
D
Q
31
D
Q
120
D
Q
127
Descriptor
Queues
Weighted
Strict Priority
Weighted
Strict Priority
Data read
request
Data
MAC
Traffic Class 0 Traffic Class 7
Queues Arbiters,
one per TC
Round-Robin
Round-Robin
Descriptor Plane
TC Arbiter
Packet Plane
TC Arbiter
D
Q
1
D
Q
121

279
VM Wei ght ed Round Robi n Ar bi t er Descript ors are fet ched out from queues at t ached t o
different pools in a frame- by- frame weight ed round- robin manner. Weight s or credit s allocat ed t o a
pool are t hose allocat ed for t he lowest queue of t he pool via t he RTTDT1C regist er. Bandwidt h
unused by one pool is reallocat ed t o t he ot hers proport ionally t o t heir relat ive bandwidt h shares.
Link bandwidt h limit at ion is dist ribut ed across all t he pools, proport ionally t o t heir relat ive
bandwidt h shares. Det ails on weight ed round- robin arbit er bet ween t he pools can be found in
Sect ion 7. 7. 2. 3.
Pack et Pl ane Ar bi t er :
Manageabi l i t y packet s are insert ed wit h st rict priorit y over dat a packet s.
When bot h DCB and virt ualizat ion feat ures are disabled, a single set of up t o 64 queues is allocat ed t o
a single packet buffer PB( 0) .
Descr i pt or Pl ane Ar bi t er :
Descr i pt or Queues Round Robi n Ar bi t er Descript ors are fet ched out from t he int ernal
descript or queues in a frame- by- frame round- robin manner. I t is assumed driver dispat ches t raffic
across t he queues according t o some TSS algorit hm similarly t o what is done by hardware in t he Rx
pat h wit h RSS.
Pack et Pl ane Ar bi t er :
Manageabi l i t y packet s are insert ed wit h st rict priorit y over dat a packet s.
Fi gur e 7. 18. Tr ansmi t Ar chi t ect ur e DCB- of f / VT- on 32 VFs
D
Q
0
PB
0
Packet
Buffer
Descriptor
Fetch Arbiter
D
Q
3
Descriptor
Queues
Strict Priority
Data read
request Data
MAC
D
Q
1
Pool 0
Round-Robin
D
Q
4
D
Q
7
D
Q
5
Pool 1
D
Q
124
D
Q
127
D
Q
125
Pool 31
VM Arbiter
Weighted
Round-Robin
Queues Arbiters,
one per VF
Round-Robin Round-Robin
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7. 2. 2 Tr ansmi t Cont ex t s
The 82599 provides hardware checksum offload and TCP segment at ion facilit ies. These feat ures enable
TCP and UDP packet t ypes t o be handled more efficient ly by performing addit ional work in hardware,
t hus reducing t he soft ware overhead associat ed wit h preparing t hese packet s for t ransmission. Part of
t he paramet ers used t o cont rol t hese feat ures are handled t hrough cont ext s.
A cont ext refers t o a set of paramet ers providing a part icular offload funct ionalit y. These paramet ers
are loaded by unique descript ors named t ransmit cont ext descript ors. A t ransmit cont ext descript or is
ident ified by t he DTYP field ( described lat er in t his sect ion) equals t o 0x2.
The 82599 support s t wo cont ext s for each of it s 128 t ransmit queues. The I DX bit cont ains an index t o
one of t hese t wo cont ext s. Each advanced dat a descript or t hat uses any of t he advanced offloading
feat ures must refer t o a cont ext by t he I DX field.
Cont ext s can be init ialized wit h a t ransmit cont ext descript or and t hen used for a series of relat ed
t ransmit dat a descript ors. Soft ware can use t hese cont ext s as long lived ones, while one of t he t wo
cont ext s is used for checksum offload and t he ot her one for t ransmit segment at ion det ailed in t he
following sect ions. The cont ext s should be modified when new offload paramet ers are required.
Fi gur e 7.19. Tr ansmi t Ar chi t ect ur e DCB- of f / VT- of f
D
Q
0
PB
0
Packet
Buffer
Descriptor
Fetch Arbiter
D
Q
63
Descriptor
Queues
Round-Robin
Strict Priority
Data read
request Data
MAC
Queues Arbiter
D
Q
1

281
7. 2. 3 Tr ansmi t Descr i pt or s
7.2.3.1 I nt r oduct i on
The 82599 support s legacy descript ors and advanced descript ors.
Legacy descript ors are int ended t o support legacy drivers, in order t o enable fast plat form power up
and t o facilit at e debug. The legacy descript ors are recognized as such based on DEXT bit ( see t he
sect ions t hat follow) . Legacy descript ors are not support ed t oget her wit h DCB, virt ualizat ion, LinkSec,
and I Psec. These modes are recognized by a dedicat ed enable bit for each.
I n addit ion, t he 82599 support s t wo t ypes of advanced t ransmit descript ors:
1. Advanced t ransmit cont ext descript or, DTYP = 0010b
2. Advanced t ransmit dat a descript or, DTYP = 0011b
Not e: DTYP = 0000b and 0001b are reserved values.
The t ransmit dat a descript or ( bot h legacy and advanced) point s t o a block of packet dat a t o be
t ransmit t ed. The advanced t ransmit cont ext descript or does not point t o packet dat a. I t cont ains
cont rol/ cont ext informat ion t hat is loaded int o on- chip regist ers t hat affect t he processing of packet s for
t ransmission. The following sect ions describe t he descript or format s.
7. 2. 3. 2 Tr ansmi t Descr i pt or s For mat s
7.2.3.2.1 Not at i ons
This sect ion defines t he st ruct ure of descript ors t hat cont ain fields carried over t he net work. At t he
moment , t he only relevant field is t he VLAN Tag field.
The rule for VLAN t ag is t o use net work ordering ( also called big endian) . I t appears in t he following
manner in t he descript or:
7.2.3.2.2 Legacy Tr ansmi t Descr i pt or For mat
To select legacy mode operat ion, bit 29 ( TDESC. DEXT) should be set t o 0b. I n t his case, t he descript or
format is defined as list ed in Table 7.29. Address and lengt h must be supplied by soft ware on all
descript ors. Bit s in t he command byt e are opt ional, as are t he CSO, and CSS fields.
Tabl e 7. 28. VLAN Tag
By t e addr ess N + 1 - > f i r st by t e on t he w i r e
Bi t 7 - - - - - f i r st on t he w i r e < - Bi t 0
By t e addr ess N - > second byt e on t he w i r e
Bi t 7 - > l ast on t he w i r e - - - - - - Bi t 0
PRI ( 3 bit s) CFI VI D ( 4 bit s) VI D ( 8 bit s)
Tabl e 7. 29. Tr ansmi t Descr i pt or ( TDESC) Lay out Legacy Mode
63 48 47 40 39 36 35 32 31 24 23 16 15 0
0 Buffer Address [ 63: 0]
8 VLAN CSS Rsvd STA CMD CSO Lengt h
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Buffer Address ( 64) and Lengt h ( 16)
The buffer address is a byt e- aligned address. Lengt h ( TDESC. LENGTH) specifies t he lengt h in byt es t o
be fet ched from t he buffer address provided. The maximum lengt h associat ed wit h a single descript or is
15. 5 KB while t he t ot al frame size must meet t he maximum support ed frame size. There is no limit at ion
for t he minimum buffer size.
Not e: Descript ors wit h zero lengt h ( null descript ors) t ransfer no dat a. Null descript ors might appear
only bet ween packet s and must have t heir EOP bit s set .
Checksum Offset and St art CSO ( 8) and CSS ( 8)
A Checksum Offset ( TDESC. CSO) field indicat es where, relat ive t o t he st art of t he packet , t o insert a
TCP checksum if t his mode is enabled. A Checksum St art ( TDESC. CSS) field indicat es where t o begin
comput ing t he checksum. Not e t hat CSO and CSS are meaningful only in t he first descript or of a
packet .
Bot h CSO and CSS are in unit s of byt es. These must bot h be in t he range of dat a provided t o t he device
in t he descript or. This means for short packet s t hat are padded by soft ware, CSO and CSS must be in
t he range of t he unpadded dat a lengt h, not t he event ual padded lengt h ( 64 byt es) . The allowed ranges
for CSO and CSS are:
14 s CSS s unpadded packet lengt h minus 1
CSS + 2 s CSO s unpadded packet lengt h minus 4
For t he 802. 1Q header, t he offset values depend on t he VLAN insert ion enable bit t he VLE bit . I f t hey
are not set ( VLAN t agging included in t he packet buffers) , t he offset values should include t he VLAN
t agging. I f t hese bit s are set ( VLAN t agging is t aken from t he packet descript or) , t he offset values
should exclude t he VLAN t agging.
Hardware does not add t he 802. 1q Et hert ype or t he VLAN field following t he 802. 1Q Et hert ype t o t he
checksum. So for VLAN packet s, soft ware can comput e t he values t o back out only on t he encapsulat ed
packet rat her t han on t he added fields.
Not e: UDP checksum calculat ion is not support ed by t he legacy descript or because t he legacy
descript or does not support t he t ranslat ion of a checksum result of 0x0000 t o 0xFFFF needed
t o different iat e bet ween an UDP packet wit h a checksum of zero and an UDP packet wit hout
checksum.
Because t he CSO field is eight bit s wide, it put s a limit on t he locat ion of t he checksum t o 255 byt es
from t he beginning of t he packet .
Not e: CSO must be larger t han CSS.
Soft ware must comput e an offset t ing ent ry t o back out t he byt es of t he header t hat should not be
included in t he TCP checksum and st ore it in t he posit ion where t he hardware comput ed checksum is t o
be insert ed.
Tabl e 7.30. Tr ansmi t Descr i pt or Wr i t e- Back For mat Legacy Mode
63 48 47 40 39 36 35 32 31 24 23 16 15 0
0 Reserved Reserved
8 VLAN CSS Rsvd STA CMD CSO Lengt h

283
Hardware adds t he checksum at t he byt e offset indicat ed by t he CSO field. Checksum calculat ions are
for t he ent ire packet st art ing at t he byt e indicat ed by t he CSS field. The byt e offset is count ed from t he
first byt e of t he packet fet ched from host memory.
Command Byt e CMD ( 8)
The CMD byt e st ores t he applicable command and has t he fields list ed in Table 7.31.
RSV ( bit 7) Reserved
VLE ( bit 6) VLAN Packet Enable
When set t o 1b, VLE indicat es t hat t he packet is a VLAN packet and hardware adds t he VLAN header
t o t he Tx packet . The VLAN Et hert ype is t aken from DMATXCTL. VT and t he 802. 1q VLAN t ag is
t aken from t he VLAN field in t he Tx descript or. See Sect ion 7. 4. 5 for det ails about double VLAN.
Not e: This t able is relevant only if VMVI R.VLANA = 00b ( use descript or command) for t he queue.
DEXT ( bit 5) Descript or ext ension ( zero for legacy mode)
RSV ( bit 4) Reserved
RS ( bit 3) Report St at us - RS signals hardware t o report t he DMA complet ion st at us indicat ion as
well as t riggering I TR. Hardware indicat es a DMA complet ion by set t ing t he DD bit in t he Rx
descript or when TDWBAL[ n] . Head_WB_En = 0b or by Head Writ e- back if Head_WB_En = 1b ( see
Sect ion 7. 2. 3. 5. 2) . The RS bit is permit t ed only on descript ors t hat has t he EOP bit set ( last
descript or of a packet ) .
Not e: Soft ware should not set t he RS bit when TXDCTL. WTHRESH is great er t han zero. I nst ead, t he
hardware report s t he DMA complet ion according t o t he WTHRESH rules ( explained in
Sect ion 7. 2. 3. 5. 1) . This not e is relevant only for descript or writ e back while in head writ e-
back mode. WTRESH must also be set t o zero.
When TXDCTL. WTHRESH = zero, soft ware must set t he RS bit on t he last descript or of every
packet .
There are some except ions for descript or complet ion indicat ion in head writ e- back mode. For
more det ails see Sect ion 7.2. 3. 5.2.
I C ( bit 2) I nsert Checksum - Hardware insert s a checksum at t he offset indicat ed by t he CSO
field if t he I nsert Checksum bit ( I C) is set .
I FCS ( bit 1) I nsert FCS - When set , hardware appends t he MAC FCS at t he end of t he packet .
When cleared, soft ware should calculat e t he FCS for proper CRC check. There are several cases in
which soft ware must set I FCS as follows:
Transmit t ing a short packet while padding is enabled by t he HLREG0. TXPADEN bit .
Checksum offload is enabled by t he I C bit in t he TDESC.CMD.
Tabl e 7. 31. Tr ansmi t Command ( TDESC.CMD) Layout
7 6 5 4 3 2 1 0
RSV VLE DEXT RSV RS I C I FCS EOP
Tabl e 7. 32. VLAN Tag I nser t i on Deci si on Tabl e f or VLAN Mode Enabl ed
VLE Act i on
0 Send generic Et hernet packet .
1
Send 802. 1Q packet ; t he Et hernet Type field comes from t he VET field of t he VLNCTRL regist er and t he VLAN dat a
comes from t he VLAN field of t he TX descript or.
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VLAN header insert ion enabled by t he VLE bit in t he TDESC. CMD or by t he PFVMVI R regist ers.
TSO or TCP/ I P checksum offload using a cont ext descript or.
LinkSec offload is request ed.
Not e t hat TSO, Transmit Rat e Scheduler, and LinkSec offload are relevant only t o advanced Tx
descript ors.
EOP ( bit 0) End of Packet - A packet can be composed of mult iple buffers ( each of t hem indicat ed
by it s own descript or) . When EOP is set , it indicat es t he last descript or making up t he packet .
Not e: VLE, I FCS, and I C fields should be set in t he first descript or of a packet . The RS bit can be set
only on t he last descript or of a packet . The DEXT bit must be set t o zero for all descript ors.
The EOF bit is meaningful in all descript ors.
Transmit t ed. St at us STA ( 4)
DD ( bit 0) Descript or Done St at us
This bit provides a st at us indicat ion t hat t he DMA of t he buffer has complet ed. Soft ware might reuse
descript ors wit h t he DD bit set and any ot her descript ors processed by t he hardware before t his one.
The ot her bit s in t he STA field are reserved.
Rsvd Reserved ( 4)
VLAN ( 16)
The VLAN field is used t o provide t he 802. 1q/ 802. 1ac t agging informat ion. The VLAN field is qualified
on t he first descript or of each packet when t he VLE bit is set t o 1b. The VLAN field is provided in
net work order and is meaningful in t he first descript or of a packet . See Sect ion 7. 2. 3.2.1 for more
det ails.
7.2.3. 2.3 Advanced Tr ansmi t Cont ex t Descr i pt or
Tabl e 7.33. VLAN Fi el d ( TDESC.VLAN) Layout
15 13 12 11 0
PRI CFI VLAN
Tabl e 7.34. Tr ansmi t Cont ex t Descr i pt or ( TDESC) Lay out ( Ty pe = 0010)
63 48 47 42 41 32 31 16 15 9 8 0
0 RSV FCoEF I Psec SA I ndex VLAN MACLEN I PLEN/ HEADLEN
8 MSS L4LEN RSV
I
D
X
BCNTLEN
D
E
X
T
RSV DTYP TUCMD I Psec ESP_LEN
63 48 47 40
3
9
3
7
3
6
35 30
2
9
28 24
2
3
2
0
19 9 8 0

285
I PLEN/ HEADLEN ( 9)
I PLEN for I P packet s:
This field holds t he value of t he I P header lengt h for t he I P checksum offload feat ure. I f an offload
is request ed, I PLEN must be great er t han or equal t o 20, and less t han or equal t o 511. For I P
t unnel packet s ( I Pv4- I Pv6) I PLEN must be defined as t he lengt h of t he t wo I P headers. The
hardware is able t o offload t he L4 checksum calculat ion while soft ware should provide t he I Pv4
checksum. For I Psec packet s, it is t he sum of I P header lengt h plus I Psec header lengt h.
HEADLEN for FCoE packet s:
This field indicat es t he size ( in byt es) of t he FCoE frame header. The frame header includes t he MAC
header, opt ional VLAN and FCoE header( s) as shown in Figure 7. 47. HEADLEN does not include t he
LinkSec header if it exist s. HEADLEN is meaningful only if t ransmit FCoE offload is enabled by
set t ing t he FCoE bit in t he TUCMD field. HEADLEN t hat mat ches Figure 7. 47 equals 56 or 64 for
packet s wit hout FC ext ended headers or packet s wit h VFT header respect ively. The 82599 support s
FC ext ended headers only for single send. Segment at ion offload can be used only when ext ended
headers are not present .
MACLEN ( 7)
For nonFCoE packet s:
This field indicat es t he lengt h of t he MAC header. When an offload is request ed, t he TSE bit ( in t he
advanced t ransmit dat a descript or) or I XSM bit or TXSM bit are set , MACLEN must be larger t han or
equal t o 14, and less t han or equal t o 127. This field should include only t he part of t he L2 header
supplied by t he driver and not t he part s added by hardware. The following t able list s t he value of
MACLEN in t he different cases.
For FCoE packet s:
This field is a byt e offset t o t he last Dword of t he FCoE header ( supplied by t he driver) t hat includes
t he SOF flag. The FC frame header st art s four byt es aft er t he MACLEN as shown in Figure 7.47. The
MACLEN t hat mat ches Figure 7. 47 equals 28.
VLAN ( 16)
This field cont ains t he 802.1Q VLAN t ag t o be insert ed in t he packet during t ransmission. This VLAN t ag
is insert ed when a packet using t his cont ext has it s DCMD. VLE bit is set . This field should include t he
ent ire 16- bit VLAN field including CFI and priorit y fields as list ed in Table 7. 33.
Not e t hat t he VLAN field is provided in net work order. See Sect ion 7. 2. 3.2.1.
I psec SA I DX ( 10) I Psec SA I ndex. I f an I Psec offload is request ed for t he packet ( I PSEC bit is set
in t he advanced Tx dat a descript or) , indicat es t he index in t he SA t able where t he I Psec key and SALT
are st ored for t hat flow.
SNAP Regul ar VLAN Ex t ended VLAN MACLEN
No By hardware or no No 14
No By hardware or no Yes 18
No By soft ware No 18
No By soft ware Yes 22
Yes By hardware or no No 22
Yes By hardware or no Yes 26
Yes By soft ware No 26
Yes By soft ware Yes 30
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FCoEF ( 6) see t he following:
EOF ( bit s 1: 0) End of frame delimit er index.
ORI E ( bit 4) Orient at ion relat ive t o t he last frame in an FC sequence.
The EOF and ORI E fields define t he EOF t hat is insert ed by hardware. I n a single packet send, t he EOF
field is defined complet ely by t he EOF set t ing while in TSO mode, t he EOF field is defined by t he EOF
and t he ORI E bit s as list ed in t he following t able. The values EOF0.. .EOF3 are t aken from t he EOFF
regist er.
SOF ( bit 2) St art of frame delimit er index.
ORI S ( bit 5) Orient at ion relat ive t o t he first frame in an FC sequence.
I n a single packet send, SOF is t aken from t he dat a buffer. I n TSO, hardware places t he SOF in t he
t ransmit t ed packet replacing t he dat a buffer cont ent . The SOF and ORI S bit s in t he cont ext descript or
define t he SOF t hat is placed by t he hardware as list ed in t he following t able. The values SOF0. .. SOF3
are t aken from t he SOFF regist er.
PARI NC ( bit 3) When t his bit is set , hardware relat es t o t he PARAM field in t he FC header as
relat ive offset . I n t his case, hardware increment s t he PARAM field in TSO by an MSS value on each
t ransmit t ed packet of t he TSO. Soft ware should set t he PARI NC bit when it set s t he Relat ive Offset
Present bit in t he F_CTL.
RSV( 16)
Reserved
I PS_ESP_LEN( 9) - Size of t he ESP t railer and ESP I CV appended by soft ware. Meaningful only if t he
I PSEC_TYPE bit is set in t he TUCMD field and t o single send packet s for which t he I PSEC bit is set in
t heir advanced Tx dat a descript or.
EOF bi t s ( 1: 0) ORI E bi t ( 4)
E- EOF code i n a
si ngl e pack et
send
FCoE Lar ge send
E- EOF code i n t he
l ast f r ame
E- EOF code i n ot her
f r ames
TSO t hat ends
up i n a si ngl e
pack et
00 ( EOFn)
0 ( not a sequence
end)
EOF0 ( EOFn) EOF0 ( EOFn) EOF0 ( EOFn) EOF0 ( EOFn)
00 ( EOFn) 1 ( sequence end) EOF0 ( EOFn) EOF1 ( EOFt ) EOF0 ( EOFn) EOF1 ( EOFt )
01 ( EOFt ) 1 ( dont care) EOF1 ( EOFt ) n/ a n/ a EOF1 ( EOFt )
10 ( EOFni) 1 ( dont care) EOF2 ( EOFni) n/ a n/ a EOF2 ( EOFni)
11 ( EOFa) 1 ( dont care) EOF3 ( EOFa) n/ a n/ a EOF3 ( EOFa)
SOF bi t ( 2) ORI S bi t ( 5)
SOF code i n t he f i r st
f r ame
SOF code i n ot her
f r ames
SOF code i n a si ngl e
pack et
1 ( Class 3) 1 ( sequence st art ) SOF1 ( SOFi3) SOF3 ( SOFn3) SOF1 ( SOFi3)
1 ( Class 3) 0 ( not a sequence st art ) SOF3 ( SOFn3) SOF3 ( SOFn3) SOF3 ( SOFn3)

287
TUCMD ( 11)
RSV ( bit 10- 7) Reserved
FCoE ( bit 6) This bit defines t he cont ext descript or and t he associat ed dat a descript ors as FCoE
frame t ype. See Sect ion 7. 13. 2 for a descript ion of t he offload provided by t he hardware while
t ransmit t ing a single frame and TSO.
Encrypt ion ( bit 5) ESP encrypt ion offload is required. Meaningful only t o packet s for which t he
I PSEC bit is set in t heir advanced Tx dat a descript or.
I PSEC_TYPE ( bit 4) Set for ESP. Cleared for AH. Meaningful only t o packet s for which t he I PSEC
bit is set in t heir advanced Tx dat a descript or.
L4T ( bit 3: 2) L4 Packet TYPE ( 00: UDP; 01: TCP; 10: SCTP; 11: RSV)
I PV4( bit 1) I P Packet Type: When 1b, I Pv4; when 0b, I Pv6
SNAP ( bit 0) SNAP indicat ion
DTYP ( 4)
This field is always 0010b for t his t ype of descript or.
RSV( 1)
Reserved
DEXT ( 1) Descript or ext ension ( one for advanced mode)
BCNTLEN( 6) For rat e limit ed queues t his field must be set t o 0x3F
I DX ( 1)
The cont ext descript or is post ed t o a cont ext t able in hardware. There are t wo cont ext t ables per
queue. The I DX is t he index of t he cont ext t ables.
Not e: Because t he 82599 support s only t wo cont ext descript ors per queue, t he t wo MS bit s are
reserved and should be set t o 0b.
RSV( 1)
L4LEN( 8)
This field holds t he layer 4 header lengt h. I f TSE is set , t his field must be great er t han or equal t o 8 and
less t han or equal t o 255. Ot herwise, t his field is ignored. Not e t hat for UDP segment at ion t he L4
header size equals 8 and for TCP segment at ion ( wit h no TCP opt ions) it equals 20.
MSS ( 16)
This field cont rols t he Maximum Segment Size. This specifies t he maximum prot ocol payload segment
sent per frame, not including any header. MSS is ignored when DCMD. TSE is not set .
TCP / UDP Segment at ion
The t ot al lengt h of each frame ( or segment ) excluding Et hernet CRC as follows. Not e t hat t he last
packet of a TCP segment at ion might be short er.
MACLEN + 4( if VLE set ) + I PLEN + L4LEN + MSS + [ PADLEN + 18] ( if ESP packet )
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288
PADLEN ranges from zero t o t hree in Tx and is t he cont ent of t he ESP Padding Lengt h field t hat is
comput ed when offloading ESP in cipher blocks of 16 byt es ( AES- 128) wit h respect t o t he following
alignment formula:
[ L4LEN + MSS + PADLEN + 2] modulo( 4) = 0
For a single send t he I PS_ESP_LEN equals t o PADLEN + 18.
Not e: The headers lengt hs must meet t he following: MACLEN + I PLEN + L4LEN < = 512
FCoE Segment at i on
The t ot al lengt h of each frame ( or segment ) excluding Et hernet CRC equals t o:
MACLEN + 4( if VLE set ) + 8 ( FC CRC + EOF)
Not e: For FCoE packet s, t he maximum segment size defines t he FC payload size in all packet s but
t he last one, which can be smaller.
The cont ext descript or requires valid dat a only in t he fields used by t he specific offload opt ions. The
following t able list s t he required valid fields according t o t he different offload opt ions.
Not e: All fields t hat are not used in t he cont ext descript or must be set t o zero.
Tabl e 7.35. Val i d Fi el ds by Of f l oad Opt i on
Cont ex t
Fi el ds - >
F
C
o
E
F
C
o
E
F
V
L
A
N
M
A
C
L
E
N
I
P
L
E
N
/
H
E
A
D
L
E
N
L
4
L
E
N
S
N
A
P
I
P
V
4
L
4
T
E
n
c
r
y
p
t
i
o
n
I
P
S
E
C
T
Y
P
E
S
A
I
D
X
E
S
P
_
L
E
N
M
S
S
B
C
N
T
L
E
N
C
C

(
d
a
t
a

d
e
s
c
r
i
p
t
o
r
)
R
e
q
u
i
r
e
d

O
f
f
l
o
a
d
VLAN
i nser t i on
yes yes
I Pv 4 XSUM n/ a n/ a yes yes 1 yes 0
L4 XSUM n/ a n/ a yes yes yes yes 0
TCP/ UDP Seg n/ a n/ a yes yes yes yes yes yes yes yes 0
FCoE CRC yes yes yes yes n/ a n/ a n/ a n/ a n/ a n/ a n/ a n/ a yes 1
FCoE Seg yes yes yes yes n/ a n/ a n/ a n/ a n/ a n/ a n/ a n/ a yes yes 1
I PSec ESP n/ a n/ a yes yes yes yes yes yes yes yes 1
I PSec AH n/ a n/ a yes yes yes yes yes yes n/ a yes 1
Tx sw i t ch n/ a n/ a yes yes yes yes yes n/ a n/ a n/ a n/ a yes 1

289
7.2.3.2.4 Adv anced Tr ansmi t Dat a Descr i pt or
General Rule for all Fields
When a packet spreads over mult iple descript ors, all of t he descript or fields are valid only on t he first
descript or of t he packet , except for RS and EOP bit s, which are set on t he last descript or of t he packet .
Address ( 64)
This field holds t he physical address of a dat a buffer in host memory, which cont ains a port ion of a
t ransmit packet . This field is meaningful in all descript ors.
DTALEN ( 16)
This field holds t he lengt h in byt es of dat a buffer at t he address point ed t o by t his specific descript or.
This field is meaningful in all descript ors. The maximum lengt h is 15. 5 KB wit h no limit at ions on t he
minimum size. Refer t o t he comment on descript ors wit h zero lengt h described in t he sect ions t hat
follow.
RSV( 2)
Reserved
MAC ( 2) see t he following. This field is meaningful on t he first descript or of t he packet ( s) .
I LSec ( bit 0) Apply LinkSec on packet . When set , hardware includes t he LinkSec header
( SecTAG) and LinkSec header digest ( signat ure) . The LinkSec processing is defined by t he Enable
Tx LinkSec field in t he LSECTXCTRL regist er. The I LSec bit in t he packet descript or should not be set
if LinkSec processing is not enabled by t he Enable Tx LinkSec field. I f t he I LSec bit is set
erroneously while t he Enable Tx LinkSec field is set t o 00b, t hen t he packet is dropped.
1588 ( bit 1) I EEE1588 t ime st amp packet .
DTYP ( 4)
0011b for advanced dat a descript or. DTYP should be valid in all descript ors of t he packet ( s) .
DCMD ( 8) see t he following:
TSE ( bit 7) Transmit Segment at ion Enable - This bit indicat es a TCP or FCoE segment at ion
request . When TSE is set in t he first descript or of a TCP or FCoE packet , hardware must use t he
corresponding cont ext descript or in order t o perform segment at ion.
Tabl e 7. 36. Adv anced Tr ansmi t Dat a Descr i pt or Read For mat
0 Address[ 63: 0]
8 PAYLEN POPTS CC I DX STA DCMD DTYP MAC RSV DTALEN
63 46 45 40 39 38 36 35 32
31
24
23 20 19 18 17 16 15 0
Tabl e 7. 37. Adv anced Tr ansmi t Dat a Descr i pt or Wr i t e- back For mat
0 RSV
8 RSV STA RSV
63 36 35 32 31 0
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290
Not e: I t is recommended t hat HLREG0. TXPADEN be enabled when TSE is used since t he last frame
can be short er t han 60 byt es result ing in a bad frame.
VLE ( bit 6) VLAN Packet Enable - This bit indicat es t hat t he packet is a VLAN packet ( hardware
must add t he VLAN Et hert ype and an 802. 1q VLAN t ag t o t he packet ) .
DEXT ( bit 5) Descript or Ext ension - This bit must be one t o indicat e advanced descript or format
( as opposed t o legacy) .
Rsv ( bit 4) Reserved
RS ( bit 3) Report St at us: See t he descript ion in t he legacy t ransmit descript or in
Sect ion 7. 2. 3. 2.2.
Rsv ( bit 2) Reserved
I FCS ( bit 1) I nsert FCS - When t his bit is set , t he hardware appends t he MAC FCS at t he end of
t he packet . When cleared, soft ware should calculat e t he FCS for proper CRC check. There are
several cases in which soft ware must set I FCS as follows:
Transmit t ing a short packet while padding is enabled by t he HLREG0. TXPADEN bit .
Checksum offload is enabled by t he eit her I C, TXSM or I XSM bit s in t he TDESC. DCMD.
VLAN header insert ion enabled by t he VLE bit in t he TDESC. DCMD.
FC CRC ( FCoE) offload is enabled by t he FCoE bit in t he t ransmit cont ext descript or.
TCP or FCoE segment at ion offload enabled by t he TSE bit in t he TDESC. DCMD.
EOP ( bit 0) End of Packet - A packet might be composed of mult iple buffers ( each of t hem is
indicat ed by it s own descript or) . When EOP is set , it indicat es t he last descript or making up t he
packet . I n t ransmit segment at ion ( explained lat er on in t his sect ion) t he EOP flag indicat es t he last
descript or of t he last packet of t he segment ed t ransmission.
Not e: TSE, VLE and I FCS fields should be set in t he first descript or of t he packet ( s) . The RS bit can
be set only on t he last descript or of t he packet . The EOP bit is valid in all descript ors. The
DEXT bit must be set t o 1b for all descript ors.
Descript ors wit h zero lengt h, t ransfer no dat a. I f t he RS bit in t he command byt e is set , t hen
t he DD field in t he st at us word is not writ t en when hardware processes t hem.
STA ( 4)
Rsv ( bit 3: 1) Reserved
DD ( bit 0) Descript or Done: The DD bit provides a st at us indicat ion t hat t he DMA of t he buffer
has complet ed. Soft ware might reuse descript ors wit h t he DD bit set , and any ot her descript ors
processed by hardware before t his one. I n TSO, t he buffers t hat include t he TSO header are used
mult iple t imes during t ransmission and special considerat ions should be made as described in
Sect ion 7. 2. 4. 2.2.
I DX ( 3)
This field holds t he index int o t he hardware cont ext t able t o indicat e which of t he t wo per- queue
cont ext s should be used for t his request . I f no offload is required and t he CC bit is cleared, t his field is
not relevant and no cont ext needs t o be init iat ed before t he packet is sent . See Table 7. 35 for det ails of
which packet s requires a cont ext reference. This field is relevant only on t he first descript or of t he
packet ( s) .
CC ( 1)
Check Cont ext bit When set , a Tx cont ext descript or indicat ed by I DX index should be used for t his
packet ( s) . The CC bit should be set in t he following cases:
1. Non- zero BCNTLEN field is required ( defined in t he cont ext descript or) .
2. Any FCoE offload is required.

291
3. Tx swit ching is enabled in I OV mode.
POPTS ( 6)
This field is relevant only on t he first descript or of t he packet ( s) .
Rsv ( bit s 5: 3) Reserved
I PSEC ( bit 2) I psec offload request .
TXSM ( bit 1) I nsert TCP/ UDP Checksum: When set t o 1b, t he L4 checksum must be insert ed. I n
t his case, TUCMD. LP4 indicat es whet her t he checksum is TCP or UDP or SCTP. When DCMD. TSE is
set , TXSM must be set t o as well. I f t his bit is set , t he packet should at least cont ain an L4 header.
I XSM ( bit 0) I nsert I P Checksum: This field indicat es t hat I P checksum must be insert ed. I n I Pv6
mode, it must be reset t o 0b. I f DCMD. TSE and TUCMD.I PV4 are set , I XSM must be set as well. I f
t his bit is set , t he packet should at least cont ain an I P header.
PAYLEN ( 18)
PAYLEN indicat es t he size ( in byt e unit s) of t he dat a buffer( s) in host memory for t ransmission. I n a
single- send packet , PAYLEN defines t he ent ire packet size fet ched from host memory. I t does not
include t he fields t hat hardware adds such as: opt ional VLAN t agging, Et hernet CRC or Et hernet
padding. When LinkSec offload is enabled, t he PAYLEN field does not include t he LinkSec encapsulat ion.
When I Psec offload is enabled, t he PAYLEN field does not include t he ESP t railer added by hardware. I n
TSO ( regardless if it is t ransmit t ed on a single or mult iple packet s) , t he PAYLEN defines t he prot ocol
payload size fet ched from host memory. I n TCP or UDP segment at ion offload, PAYLEN defines t he TCP/
UDP payload size. I n FCoE offload ( single send and segment at ion) , t he PAYLEN field defines t he FC
payload size. I t includes t he FC opt ion headers ( if present ) and t he FC dat a payload but excludes t he
FCoE t railer cont aining t he FC CRC and EOF.
This field is relevant only on t he first descript or of t he packet ( s) . The minimum t ransmit t ed packet size
excluding VLAN padding and CRC byt es is 17 and t he PAYLEN size should meet t his limit at ion. On a
single- packet send, t he maximum size of t he PAYLEN is dict at ed by t he maximum allowed packet size
which is 15. 5 KB. On TSO, t he maximum PAYLEN can be up t o 2
18
- 1.
7.2.3.3 Tr ansmi t Descr i pt or Ri ng
The t ransmit descript or ring st ruct ure ( shown in Figure 7.20) uses a cont iguous memory space. A set of
four regist ers ( described lat er in t his sect ion) maint ain t he t ransmit descript or ring in t he host memory.
Hardware maint ains int ernal circular queues of 40 descript ors per queue t o hold t he descript ors t hat
were fet ched from t he soft ware ring.
Descript ors handled t o hardware should not be manipulat ed by soft ware unt il hardware complet es it s
processing. I t is indicat ed by advancing t he head point er beyond t hese descript ors.
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292
The t ransmit descript or ring is defined by t he following regist ers:
Transmit Descript or Base Address regist er ( TDBA 0- 127) This regist er indicat es t he st art address
of t he descript or ring buffer in t he host memory; t his 64- bit address is aligned on a 16- byt e
boundary and is st ored in t wo consecut ive 32- bit regist ers. Hardware ignores t he lower four bit s.
Transmit Descript or Lengt h regist er ( TDLEN 0- 127) This regist er det ermines t he number of byt es
allocat ed t o t he circular buffer. This value must be 0 modulo 128.
Transmit Descript or Head regist er ( TDH 0- 127) This regist er holds a value t hat is an offset from
t he base and indicat es t he in- progress descript or. There can be up t o 64 K minus 8 descript ors in
t he circular buffer. The t ransmit queue consist s of t he descript ors bet ween t he head and t ail
point ers. Transmission st art s wit h t he descript or point er by t he head regist ers. When t he DMA
engine processes a descript or, it might opt ionally writ e back t he complet ed descript or and t hen
advance t he head point er. I t t hen processes t he next descript or up t o t he point t hat t he head
point er reaches t he t ail. Head equals t ail means t hat t he t ransmit queue in host memory is empt y.
Reading t his regist er indicat es t he hardware progress t o t he soft ware. All descript ors behind t he
head point er and in front of t ail regist er are owned by t he soft ware. The ot her descript ors are
owned by t he hardware and should not be modified by t he soft ware.
Transmit Descript or Tail regist er ( TDT 0- 127) This regist er holds a value, which is an offset from
t he base, and indicat es t he locat ion beyond t he last descript or hardware can process. Soft ware
adds new descript ors t o t he ring by writ ing descript ors in t he circular buffer point ed by t he t ail
point er. The new descript or( s) are indicat ed t o hardware by updat ing t he t ail point er one descript or
above t he last added descript or. Not e t hat a single packet or TSO might be composed of mult iple
descript ors. The t ransmit t ail point er should never point t o t he middle of a packet or TSO, which
might cause undesired soft ware/ hardware races.
For t est abilit y purpose only: I f t he t ail point er is larger t hen t he ring lengt h, t hen t he 82599
reads t he descript or ring in an endless loop unt il t he queue is disabled. Prior t o set t ing such a
t ail point er value, it is required t o init ialize all t he descript ors of t he ring.
Fi gur e 7.20. Tr ansmi t Descr i pt or Ri ng St r uct ur e
Base
Base + Length
Head
Tail
Descriptors
Owned by HW
Last descriptor
added by SW
descriptor currently
processed by HW
Descriptors
Owned by SW
Transmit
Queue
Descriptors
Owned by SW

293
Soft ware might det ect which packet s have already been processed by hardware using t he following:
Read t he TDH head regist er t o det ermine which packet s ( t hose logically before t he head) have been
t ransferred t o t he on- chip FI FO or t ransmit t ed. This met hod is not recommended as races bet ween
t he int ernal updat e of t he head regist er and t he act ual writ e back of descript ors can occur.
When head writ e back is enabled ( TDWBAL[ n] . Head_WB_En = 1b) soft ware might read t he image
of t he head point er in host memory at t he address defined by TDWBAH[ n] / TDWBAL[ n] pair.
Hardware updat es t he head image in host memory by complet ed descript ors as described in
Sect ion 7. 2. 3. 5. 2.
When head writ e back is not enabled ( TDWBAL[ n] . Head_WB_En = 0b) , soft ware might t rack t he
DD bit s in t he descript or ring. Descript or writ e back is cont rolled by t he RS bit and t he WTHRESH
set t ing as well as int errupt assert ion.
I ssue an int errupt . An int errupt condit ion is generat ed each t ime a packet was t ransmit t ed or
received and a descript or was writ e back or t ransmit queue goes empt y ( EI CR. RTxQ[ 0- 19] ) . This
int errupt can eit her be enabled or masked.
All of t he regist ers cont rolling t he descript or rings behavior should be set before t ransmit is enabled.
7. 2. 3. 4 Tr ansmi t Descr i pt or Fet chi ng
The 82599 fet ches new descript ors as required for packet t ransmission depending on it s on- die
descript or buffer st at e:
Fet ch The on- chip descript or buffer is empt y or cont ains less descript ors t han a complet e packet .
A fet ch st art s as soon as any descript ors are made available ( host writ es t o t he t ail point er) .
A request is issued for any available descript ors up t o t he size of t he on- die buffer.
Once t he sum of on- die descript ors and request ed descript ors is more t han required for a single
packet , t he buffer t ransit ions t o t he prefet ch st at e.
I f several on- chip descript or queues are empt y simult aneously, queues are served in round robin
arbit rat ion except t he queues indicat ed as st rict priorit y which are served first .
Pr e- Fet ch The on- chip descript or buffer becomes almost empt y while t here are enough descript ors
in t he host memory.
The on- chip descript or buffer is defined as almost empt y if it cont ains less descript ors t hen t he
t hreshold defined by TXDCTL[ n] . PTHRESH
The t ransmit descript or cont ains enough descript ors if it includes more ready descript ors t han t he
t hreshold defined by TXDCTL[ n] . HTHRESH
I n prefet ch mode descript ors are fet ched only aft er t here are no ot her DMA act ivit y of great er
priorit y as: t ransmit descript or fet ch; st at us writ e- backs or packet dat a t ransfers)
A request is issued for any available descript ors up t o t he capacit y of t he on- die buffer.
I f several on- chip descript or queues are in t his sit uat ion simult aneously, queues are served in round
robin arbit rat ion except t he queues indicat ed as st rict priorit y which are served first .
I dl e Request s are not issued. This is t he st at e reached when none of t he previous st at es apply.
Not e: Soft ware must updat e t he Tail regist er on packet boundaries. That is, t he last valid descript or
might not be a cont ext descript or and must have t he EOP bit set .
7. 2.3. 4.1 Tr ansmi t Descr i pt or Fet ch and Wr i t e- back Set t i ngs
This sect ion describes t he set t ings of t ransmit descript or t hresholds. I t relat es t o fet ch t hresholds
described above as well as t he writ e- back t hreshold ( WTHRESH) when operat ing in descript or writ e-
back mode which is described in Sect ion 7. 2. 3.5.1.
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294
Transmit descript or fet ch set t ing is programmed in t he TXDCTL[ n] regist er per queue. The default
set t ings of PTHRESH, HTHRESH and WTHRESH are zeros.
I n order t o reduce t ransmission lat ency, it is recommended t o set t he PTHRESH value as high as
possible while t he HTHRESH and WTHRESH as low as possible ( down t o zero) .
I n order t o minimize PCI e overhead t he PTHRESH should be set as low as possible while HTHRESH
and WTHRESH should be set as high as possible.
The sum of PTHRESH plus WTHRESH must not be great er t han t he on- chip descript or buffer size
Some pract ical rules
CPU cache line opt imizat ion: Assume N equals t he CPU cache line divided by 16 ( descript or
size) . Then, in order t o align descript ors prefet ch t o CPU cache line ( in most cases) , it is
advised t o set PTHRESH t o t he on- chip descript or buffer size minus N and HTHRESH t o N. I n
order t o align descript or writ e back t o t he CPU cache line it is advised t o set WTHRESH t o eit her
' N' or even 2 t imes ' N' . Not e t hat part ial cache line writ es might significant ly degrade
performance. Therefore, it is highly recommended t o follow t his advice.
Minimizing PCI e overhead: As an example, set t ing PTHRESH t o t he on- chip descript or buffer
size minus 16 and HTHRESH t o 16 minimizes t he PCI e request and header overhead t o ~ 20%
of t he bandwidt h required for t he descript or fet ch.
Minimizing t ransmission lat ency from t ail updat e: Set t ing PTHRESH t o t he on- chip descript or
buffer size minus N ( N previously defined) while HTHRESH and WTHRESH t o zero.
Threshold set t ings in DCB mode: Not e t hat only values of PTHRESH equals on- chip descript or
buffer size minus 8 and HTHRESH equals 4 were t horoughly t est ed.
Not e: As previously described, device set t ing is a t rade off bet ween overhead ( t ranslat ed t o
performance) and lat encies. I t is expect ed t hat some level of opt imizat ion is done at soft ware
driver development phase. Cust omers who want bet t er performance might need t o adj ust t he
t hreshold values according t o t he previous guidelines while opt imizing t o specific plat form
and t arget s.
7. 2.3. 5 Tr ansmi t Wr i t e Back
The 82599 periodically updat es soft ware on it s progress in processing t ransmit buffers. Two met hods
are described for doing so:
Updat ing by writ ing back int o t he Tx descript or
Updat e by writ ing t o t he head point er in syst em memory
7.2.3. 5.1 Tx Descr i pt or Wr i t e Back
When t he TXDCTL[ n] . WTHRESH equals zero, descript ors are writ t en back for t hose descript ors wit h t he
RS bit set . When t he TXDCTL[ n] . WTHRESH value is great er t han zero, descript ors are accumulat ed unt il
t he number of accumulat ed descript ors equals t he TXDCTL[ n] .WTHRESH value, t hen t hese descript ors
are writ t en back. Accumulat ed descript or writ e back enables bet t er use of t he PCI e bus and memory
bandwidt h.
Any descript or writ e back includes t he full 16 byt es of t he descript or.
Descript ors are writ t en back in one of t hree cases:
TXDCTL[ n] . WTHRESH = 0 and a descript or t hat has RS set is ready t o be writ t en back.
TXDCTL[ n] . WTHRESH > 0 and TXDCTL[ n] .WTHRESH descript ors have accumulat ed.
TXDCTL[ n] . WTHRESH > 0 and t he corresponding EI TR count er has reached zero. The t imer
expirat ion flushes any accumulat ed descript ors and set s an int errupt event ( TXDW) .

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An addit ional mode in which t ransmit descript ors are not writ t en back at all and t he head point er of t he
descript or ring is writ t en inst ead is described in t he following sect ion.
7.2.3.5.2 Tx Head Poi nt er Wr i t e Back
I n legacy hardware, t ransmit request s are complet ed by writ ing t he DD bit t o t he t ransmit descript or
ring. This causes cache t hrash since bot h t he driver and hardware are writ ing t o t he descript or ring in
host memory. I nst ead of writ ing t he DD bit s t o signal t hat a t ransmit request is complet e, hardware can
writ e t he cont ent s of t he descript or queue head t o host memory. The driver reads t hat memory locat ion
t o det ermine which t ransmit request s are complet e. I n order t o improve t he performance of t his
feat ure, t he driver needs t o program DCA regist ers t o configure which CPU will be processing each TX
queue.
The head point er is reflect ed in a memory locat ion t hat is allocat ed by soft ware for each queue.
Rules for head point er writ e back:
Head writ e back occurs if TDWBAL[ n] . Head_WB_En is set for t his queue, and t he RS bit is set in t he
Tx descript or, following it s corresponding dat a upload int o packet buffer.
I f t he head writ e- back feat ure is enabled, soft ware must set WTHRESH t o 0x0 while only
descript ors wit h t he RS bit set , generat e header writ e back.
Not e t hat t he head point er writ e back does not hold t ransmission. I nst ead, if packet s wit h t he
RS bit are t ransmit t ed fast enough, it might happen t hat t he header point er writ e back is not
updat ed for each and every packet . I n addit ion, it might happen t hat t he head point er writ e
back might be updat ed up t o descript ors t hat do not have t he RS bit set . I n such cases,
hardware might report a complet ion of a descript or t hat might not be t he last descript or in a
TSO or even t he last descript or in a single packet .
The driver has cont rol of t his feat ure per queue t hrough t he TDWBAL and TDWBAH regist ers.
The low regist er' s LSB hold t he cont rol bit s.
The Head_WB_EN bit enables act ivat ion of t ail writ e back. I n t his case, no descript or writ e back is
execut ed.
The 30 upper bit s of t his regist er hold t he lowest 32 bit s of t he head writ e- back address, assuming
t hat t he t wo last bit s are zero.
The high regist er holds t he high part of t he 64- bit address.
Not e: Hardware writ es a full Dword when writ ing t his value, so soft ware should reserve enough
space for each head value and make sure t he TDBAL value is Dword- aligned.
7.2.4 TCP and UDP Segment at i on
Hardware TCP segment at ion is one of t he offloading opt ions support ed by t he Windows* and Linux*
TCP/ I P st ack. This is oft en referred t o as Large Send offloading or TSO. This feat ure enables t he TCP/ I P
st ack t o pass t o t he net work device driver a message t o be t ransmit t ed t hat is bigger t han t he
Maximum Transmission Unit ( MTU) of t he medium. I t is t hen t he responsibilit y of t he device driver and
hardware t o divide t he TCP message int o MTU size frames t hat have appropriat e layer 2 ( Et hernet ) , 3
( I P) , and 4 ( TCP) headers. These headers must include sequence number, checksum fields, opt ions and
flag values as required. Not e t hat some of t hese values ( such as t he checksum values) are unique for
each packet of t he TCP message, and ot her fields such as t he source I P address is const ant for all
packet s associat ed wit h t he TCP message.
Similar t o TCP segment at ion, t he 82599 also provides a capabilit y t o offload UDP segment at ion. Not e
t hat current UDP segment at ion offload is not support ed by any st andard OS.
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Not e: CRC appending ( HLREG0. TXCRCEN) must be enabled in TCP / UDP segment at ion mode
because CRC is insert ed by hardware.
Padding ( HLREG0.TXPADEN) must be enabled in TCP / UDP segment at ion mode, since t he
last frame might be short er t han 60 byt es result ing in a bad frame if TXPADEN is disabled.
The offloading of t hese mechanisms t o t he device driver and t he 82599 saves significant CPU cycles.
The device driver shares t he addit ional t asks t o support t hese opt ions wit h t he 82599.
7. 2. 4. 1 Assumpt i ons and Rest r i ct i ons
The following assumpt ions apply t o t he TCP / UDP segment at ion implement at ion in t he 82599:
To limit t he int ernal cache dimensions, soft ware is required t o spread t he header ont o a maximum
four descript ors, while st ill allowed t o mix header and dat a in t he last header buffer. This limit at ion
st ands for up t o Layer 4 header included, and for I Pv4 or I Pv6 independent ly.
The maximum size of a single TSO can be as large as defined by t he PAYLEN field in t he Tx dat a
descript or ( such as up t o 256 KB) .
The RS bit operat ion is not changed. I nt errupt s are set aft er dat a in t he buffers point ed t o by
individual descript ors is t ransferred ( DMA' ed) t o hardware.
SNAP packet s are support ed for segment at ion wit h t he following rest rict ion. The locat ion of t he
802. 3 lengt h field in 802. 3+ SNAP packet s is at MACLEN minus eight byt es ( MACLEN is indicat ed in
t he cont ext descript or) .
I P t unneled packet s are not support ed for offloading under TSO operat ion.
Soft ware must enable t he Et hernet CRC offload in t he HLREG0. TXCRCEN regist er since CRC must
be insert ed by hardware aft er t he checksum has been calculat ed.
Soft ware must init ialize t he appropriat e checksum fields in t he packet s header.
7. 2.4. 2 Tr ansmi ssi on Pr ocess
The t ransmission process involves t he following:
The prot ocol st ack receives from an applicat ion a block of dat a t hat is t o be t ransmit t ed.
The prot ocol st ack calculat es t he number of packet s required t o t ransmit t his block based on t he
MTU size of t he media and required packet headers.
The st ack int erfaces wit h t he device driver and passes t he block down wit h t he appropriat e header
informat ion: Et hernet , I P, opt ional I PSec and TCP / UDP headers.
The st ack int erfaces wit h t he device driver and commands t he driver t o send t he individual packet .
The device driver set s up t he int erface t o t he hardware ( via descript ors) for t he TCP / UDP
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The hardware t ransfers ( DMA' s) t he packet dat a and performs t he Et hernet packet segment at ion
and t ransmission based on offset and payload lengt h paramet ers in t he TCP/ I P or UDP/ I P cont ext
descript or including:
Packet encapsulat ion
Header generat ion and field updat es including I Pv4/ I Pv6 and TCP/ UDP checksum generat ion.
The driver ret urns ownership of t he block of dat a t o t he NOS when t he hardware has complet ed t he
DMA t ransfer of t he ent ire dat a block.
7. 2.4. 2.1 TCP and UDP Segment at i on Dat a Fet ch Cont r ol
To perform TCP / UDP segment at ion in t he 82599, t he DMA must be able t o fit at least one packet of t he
segment ed payload int o available space in t he on- chip packet buffer. The DMA does various
comparisons bet ween t he remaining payload and t he packet buffer available space, fet ching addit ional
payload and sending addit ional packet s as space permit s.
The 82599 enables int erleaving bet ween different TSO request s at an Et hernet packet level. I n ot her
words, t he 82599 might fet ch part of a TSO from a queue, equivalent t o one or more Et hernet packet s,
t hen t ransit ion t o anot her queue and fet ch t he equivalent of one or more packet s ( TSO or not ) , t hen
move t o anot her queue ( or t he first queue) , et c. The 82599 decides on t he order of dat a fet ched based
on it s QoS requirement s ( such as bandwidt h allocat ion and priorit y) .
I n order t o enable int erleaving bet ween descript or queues at t he Et hernet frame resolut ion inside TSO
request s, t he frame header point ed by t he so called header descript ors are re- read from syst em
memory for every TSO segment ( once per packet ) , st oring in an int ernal cache only t he header s
descript ors inst ead of t he header s cont ent .
Since t he header buffers are read mult iple t imes, it is guarant eed on most plat forms t hat by t he
second read, t he dat a does not reside in t he CPU caches any more. I n t hat case, it is possible t o
avoid snooping t he CPU cache during subsequent accesses t o t he same buffer.
7.2.4.2.2 TCP and UDP Segment at i on Wr i t e- back Modes
TCP / UDP segment at ion mode uses t he buffers t hat cont ain t he header of t he packet mult iple t imes
( once for each t ransmit t ed segment ) . Soft ware should guarant ee t hat t he header buffers are available
t hroughout t he ent ire TSO t ransmission. Therefore, soft ware should not reuse any descript ors of t he
TSO header during t he TSO t ransmission.
7.2.4.3 TCP and UDP Segment at i on Per f or mance
Performance improvement s for a hardware implement at ion of TCP / UDP segment at ion offload include:
The st ack does not need t o part it ion t he block t o fit t he MTU size, saving CPU cycles.
The st ack only comput es one Et hernet , I P, and TCP / UDP header per segment , saving CPU cycles.
The st ack int erfaces wit h t he device driver only once per block t ransfer, inst ead of once per frame.
Larger PCI burst s are used, which improves bus efficiency ( such as lowering t ransact ion overhead) .
I nt errupt s are easily reduced t o one per TCP / UDP message inst ead of one per packet .
Fewer I / O accesses are required t o command t he hardware.
7.2.4.4 Pack et For mat
Typical TCP/ I P t ransmit window size is 8760 byt es ( about six full size frames) . Today t he average size
on corporat e I nt ranet s is 12- 14 KB, and normally t he maximum window size allowed is 64 KB ( unless
Windows Scaling RFC 1323 is specified) . A TCP / UDP message can be as large as 256 KB and is
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generally fragment ed across mult iple pages in host memory. The 82599 part it ions t he dat a packet int o
st andard Et hernet frames prior t o t ransmission. The 82599 support s calculat ing t he Et hernet , I P, TCP,
and even UDP headers, include checksum, on a frame- by- frame basis.
Frame format s support ed by t he 82599 include:
Et hernet 802. 3
I EEE 802. 1Q VLAN ( Et hernet 802. 3ac)
Et hernet Type 2
Et hernet SNAP
I Pv4 headers wit h opt ions
I Pv4 headers wit hout opt ions wit h one AH/ ESP I Psec header
I Pv6 headers wit h ext ensions
TCP wit h opt ions
UDP wit h opt ions
VLAN t ag insert ion is handled by hardware.
Not e: UDP ( unlike TCP) is not a reliable prot ocol and fragment at ion is not support ed at t he UDP
level. UDP messages t hat are larger t han t he MTU size of t he given net work medium are
normally fragment ed at t he I P layer. This is different from TCP, where large TCP messages
can be fragment ed at eit her t he I P or TCP layers depending on t he soft ware implement at ion.
The 82599 has t he abilit y t o segment UDP t raffic ( in addit ion t o TCP t raffic) ; however,
because UDP packet s are generally fragment ed at t he I P layer, t he 82599' s segment at ion
capabilit y might not be used in pract ice for UDP.
7. 2.4. 5 TCP and UDP Segment at i on I ndi cat i on
Soft ware indicat es a TCP / UDP segment at ion t ransmission cont ext t o t he hardware by set t ing up a
TCP/ I P or UDP/ I P cont ext t ransmit descript or ( see Sect ion 7. 2. 3) . The purpose of t his descript or is t o
provide informat ion t o t he hardware t o be used during t he TCP / UDP segment at ion offload process.
Set t ing t he TSE bit in t he DCMD field t o one ( in t he dat a descript or) indicat es t hat t his descript or refers
t o t he segment at ion cont ext ( as opposed t o t he normal checksum offloading cont ext ) . This causes t he
checksum offloading, packet lengt h, header lengt h, and maximum segment size paramet ers t o be
loaded from t he descript or int o t he device.
The TCP / UDP segment at ion prot ot ype header is t aken from t he packet dat a it self. Soft ware must
ident it y t he t ype of packet t hat is being sent ( I Pv4/ I Pv6, TCP/ UDP, ot her) , calculat e appropriat e
checksum off loading values for t he desired checksums, and t hen calculat e t he lengt h of t he header
t hat is prepended. The header can be up t o 240 byt es in lengt h.
Tabl e 7.38. TCP/ I P and UDP/ I P Pack et For mat Sent by Host
Pseudo Header Dat a
Et hernet I Pv4/ I Pv6 TCP/ UDP DATA ( full TCP message)
Tabl e 7.39. Pack et s For mat Sent by Devi ce
Pseudo Header
( updat ed)
Dat a ( first
MSS)
FCS . . .
Pseudo Header
( updat ed)
Dat a ( Next
MSS)
FCS . . .

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Once t he TCP / UDP segment at ion cont ext has been set , t he next descript or provides t he init ial dat a t o
t ransfer. This first descript or( s) must point t o a packet of t he t ype indicat ed. Furt hermore, t he dat a it
point s t o might need t o be modified by soft ware as it serves as t he prot ot ype header for all packet s
wit hin t he TCP / UDP segment at ion cont ext . The following sect ions describe t he support ed packet t ypes
and t he various updat es t hat are performed by hardware. This should be used as a guide t o det ermine
what must be modified in t he original packet header t o make it a suit able prot ot ype header.
The following summarizes t he fields considered by t he driver for modificat ion in const ruct ing t he
prot ot ype header.
I P Header
For I Pv4 headers:
I dent ificat ion field should be set as appropriat e for first packet of send ( if not already) .
Header checksum should be zeroed out unless some adj ust ment is needed by t he driver.
TCP Header
Sequence number should be set as appropriat e for first packet of send ( if not already) .
PSH, and FI N flags should be set as appropriat e for LAST packet of send.
TCP checksum should be set t o t he part ial pseudo- header checksum as follows ( t here is a more
det ailed discussion of t his in Sect ion 7. 2. 4.6:
UDP Header
Checksum should be set as in TCP header, as previously explained.
The following sect ions describe t he updat ing process performed by t he hardware for each frame sent
using t he TCP segment at ion capabilit y.
7.2. 4.6 Tr ansmi t Check sum Of f l oadi ng w i t h TCP and UDP Segment at i on
The 82599 support s checksum offloading as a component of t he TCP / UDP segment at ion offload
feat ure and as st and- alone capabilit y. Sect ion 7. 2. 5 describes t he int erface for cont rolling t he checksum
offloading feat ure. This sect ion describes t he feat ure as it relat es t o TCP / UDP segment at ion.
The 82599 support s I P and TCP header opt ions in t he checksum comput at ion for packet s t hat are
derived from t he TCP segment at ion feat ure.
Tabl e 7. 40. TCP Par t i al Pseudo- header Check sum f or I Pv4
I P Source Address
I P Dest inat ion Address
Zero Layer 4 Prot ocol I D Zero
Tabl e 7. 41. TCP Par t i al Pseudo- header Check sum f or I Pv6
I Pv6 Source Address
I Pv6 Final Dest inat ion Address
Zero
Zero Next Header
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Two specific t ypes of checksum are support ed by t he hardware in t he cont ext of t he TCP / UDP
segment at ion offload feat ure:
I Pv4 checksum
TCP / UDP checksum
Each packet t hat is sent via t he TCP / UDP segment at ion offload feat ure opt ionally includes t he I Pv4
checksum and/ or t he TCP / UDP checksum.
All checksum calculat ions use a 16- bit wide one' s complement checksum. The checksum word is
calculat ed on t he out going dat a.
7. 2. 4. 7 I P/ TCP / UDP Header Updat i ng
I P/ TCP and I P/ UDP header is updat ed for each out going frame based on t he header prot ot ype t hat
hardware DMA' s from t he first descript or( s) . The checksum fields and ot her header informat ion are
lat er updat ed on a frame- by- frame basis. The updat ing process is performed concurrent ly wit h t he
packet dat a fet ch.
The following sect ions define what fields are modified by hardware during t he TCP / UDP segment at ion
process by t he 82599.
7.2.4. 7.1 TCP/ I P/ UDP Header f or t he Fi r st Fr ame
The hardware makes t he following changes t o t he headers of t he first packet t hat is derived from each
TCP segment at ion cont ext .
MAC Header ( for SNAP)
Type/ Len field = MSS + MACLEN + I PLEN + L4LEN 14
I Pv4 Header
I P Tot al Lengt h = MSS + L4LEN + I PLEN
Calculat es t he I P Checksum
I Pv6 Header
Payload Lengt h = MSS + L4LEN + I PV6_HDR_ext ension
1
Tabl e 7.42. Suppor t ed Tr ansmi t Check sum Capabi l i t i es
Pack et Ty pe HW I P Check sum Cal cul at i on HW TCP / UDP Check sum Cal cul at i on
I Pv4 packet s Yes Yes
I Pv6 packet s
( no I P checksum in I Ppv6)
NA Yes
Packet has 802. 3ac t ag Yes Yes
Packet has I P opt ions
( I P header is longer t han 20 byt es)
Yes Yes
Packet has TCP opt ions Yes Yes
I P header s prot ocol field cont ains a prot ocol #
ot her t han TCP or UDP
Yes No
1. I PV6_HDR_ext ension is calculat ed as I PLEN 40 byt es.

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TCP Header
Sequence Number: The value is t he sequence number of t he first TCP byt e in t his frame.
The flag values of t he first frame are set by logic AND funct ion bet ween t he flag word in t he pseudo
header and t he DTXTCPFLGL. TCP_flg_first _seg. The default values of t he
DTXTCPFLGL. TCP_flg_first _seg are set . The flags in a TSO t hat ends up as a single segment are
t aken from t he in t he pseudo header in t he Tx dat a buffers as is.
Calculat es t he TCP checksum.
UDP Header
Calculat es t he UDP checksum.
7.2.4.7.2 TCP/ I P Header f or t he Subsequent Fr ames
The hardware makes t he following changes t o t he headers for subsequent packet s t hat are derived as
part of a TCP segment at ion cont ext :
Number of byt es left for t ransmission = PAYLEN ( N * MSS) . Where N is t he number of frames t hat
have been t ransmit t ed.
MAC Header ( for SNAP packet s)
Type/ Len field = MSS + MACLEN + I PLEN + L4LEN 14
I Pv4 Header
I P I dent ificat ion: increment ed from last value ( wrap around)
I P Tot al Lengt h = MSS + L4LEN + I PLEN
Calculat e t he I P Checksum
I Pv6 Header
Payload Lengt h = MSS + L4LEN + I PV6_HDR_ext ension
1
TCP Header
Sequence Number updat e: Add previous TCP payload size t o t he previous sequence number value.
This is equivalent t o adding t he MSS t o t he previous sequence number.
The flag values of t he subsequent frames are set by logic AND funct ion bet ween t he flag word in t he
pseudo header wit h t he DTXTCPFLGL. TCP_Flg_mid_seg. The default values of t he
DTXTCPFLGL. TCP_Flg_mid_seg are set .
Calculat e t he TCP checksum
UDP Header
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7.2.4. 7.3 TCP/ I P Header f or t he Last Fr ame
Hardware makes t he following changes t o t he headers for t he last frame of a TCP segment at ion
cont ext :
Last frame payload byt es = PAYLEN ( N * MSS) .
MAC Header ( for SNAP packet s)
Type/ Len field = Last frame payload byt es + MACLEN + I PLEN + L4LEN 14
I Pv4 Header
I P Tot al lengt h = last frame payload byt es + L4LEN + I PLEN
I P ident ificat ion: increment ed from last value ( wrap around based on 16- bit widt h)
Calculat e t he I P checksum
I Pv6 Header
Payload lengt h = last frame payload byt es + L4LEN + I PV6_HDR_ext ension
1
TCP Header
Sequence number updat e: Add previous TCP payload size t o t he previous sequence number value.
This is equivalent t o adding t he MSS t o t he previous sequence number.
The flag values of t he last frames are set by logic AND funct ion bet ween t he flag word in t he pseudo
header and t he DTXTCPFLGH. TCP_Flg_lst _seg. The default values of t he
DTXTCPFLGH. TCP_Flg_lst _seg are set . The flags in a TSO t hat ends up as a single segment are
t aken from t he in t he pseudo header in t he Tx dat a buffers as is.
Calculat e t he TCP checksum
UDP Header
7. 2. 5 Tr ansmi t Check sum Of f l oadi ng i n Non- segment at i on Mode
The previous sect ion on TCP / UDP segment at ion offload describes t he I P/ TCP/ UDP checksum offloading
mechanism used in conj unct ion wit h segment at ion. The same underlying mechanism can also be
applied as a st and- alone checksum offloading. The main difference in a single packet send is t hat only
t he checksum fields in t he I P/ TCP/ UDP headers are calculat ed and updat ed by hardware.
Before t aking advant age of t he 82599' s enhanced checksum offload capabilit y, a checksum cont ext
must be init ialized. For a single packet send, DCMD. TSE should be set t o zero ( in t he dat a descript or) .
For addit ional det ails on cont ext s, refer t o Sect ion 7.2. 3. 3.
Enabling checksum offload, soft ware must also enable Et hernet CRC offload by t he HLREG0.TXCRCEN
since CRC must be insert ed by hardware aft er t he checksum has been calculat ed.
As ment ioned in Sect ion 7. 2. 3, t ransmit descript ors, it is not necessary t o set a new cont ext for each
new packet . I n many cases, t he same checksum cont ext can be used for a maj orit y of t he packet
st ream. I n t his case, some performance can be gained by only changing t he cont ext on an as needed
basis or elect ing t o use t he offload feat ure only for a part icular t raffic t ype, t hereby avoiding all cont ext
descript ors except for t he init ial one.
Each checksum operat es independent ly. I nsert ion of t he I P and TCP / UDP checksum for each packet
are enabled t hrough t he t ransmit dat a descript or POPTS. TXSM and POPTS.I XSM fields, respect ively.

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7.2.5.1 I P Check sum
Three fields in t he t ransmit cont ext descript or set t he cont ext of t he I P checksum offloading feat ure:
TUCMD.I PV4
I PLEN
MACLEN
TUCMD.I PV4= 1 specifies t hat t he packet t ype for t his cont ext is I Pv4, and t hat t he I P header checksum
should be insert ed. TUCMD.I PV4= 0 indicat es t hat t he packet t ype is I Pv6 ( or some ot her prot ocol) and
t hat t he I P header checksum should not be insert ed.
MACLEN specifies t he byt e offset from t he st art of t he DMA' ed dat a t o t he first byt e t o be included in
t he checksum, t he st art of t he I P header. The minimal allowed value for t his field is 14. Not e t hat t he
maximum value for t his field is 127. This is adequat e for t ypical applicat ions.
Not e: The MACLEN+ I PLEN value must be less t han t he t ot al DMA lengt h for a packet . I f t his is not
t he case, t he result s are unpredict able.
I PLEN specifies t he I P header lengt h. Maximum allowed value for t his field is 511 byt es.
MACLEN+ I PLEN specify where t he I P checksum should st op. The sum of MACLEN+ I PLEN must be
smaller equals t o t he first 638 ( 127+ 511) byt es of t he packet and obviously must be smaller or equal t o
t he t ot al lengt h of a given packet . I f t his is not t he case, t he result is unpredict able.
Not e: For I Psec packet s offloaded by hardware in Tx, it is assumed t hat I PLEN provided by soft ware
in t he Tx cont ext descript or is t he sum of t he I P header lengt h and t he I Psec header lengt h.
Thus, for t he I Pv4 header checksum offload, hardware could no longer rely on t he I PLEN field
provided by soft ware in t he Tx cont ext descript or, but should rely on t he fact t hat no I Pv4
opt ions is present in t he packet . Consequent ly, for I Psec offload packet s, hardware comput es
I P header checksum over a fixed amount of 20 byt es.
For I P t unnel packet s ( I Pv4- I Pv6) , I PLEN must be defined as t he lengt h of t he t wo I P headers.
Hardware is able t o offload t he L4 checksum calculat ion while soft ware should provide t he I Pv4
checksum.
The 16- bit I Pv4 header checksum is placed at t he t wo byt es st art ing at MACLEN+ 10.
As ment ioned in Sect ion 7.2. 3. 2.3, t ransmit cont ext s, it is not necessary t o set a new cont ext for each
new packet . I n many cases, t he same checksum cont ext can be used for a maj orit y of t he packet
st ream. I n t his case, some performance can be gained by only changing t he cont ext on an as needed
basis or elect ing t o use t he offload feat ure only for a part icular t raffic t ype, t hereby avoiding all cont ext
descript ors except for t he init ial one.
7.2.5.2 TCP and UDP Check sum
Three fields in t he t ransmit cont ext descript or set t he cont ext of t he TCP / UDP checksum offloading
feat ure:
MACLEN
I PLEN
TUCMD.L4T
TUCMD.L4T= 01b specifies t hat t he packet t ype is TCP, and t hat t he 16- bit TCP header checksum should
be insert ed at byt e offset MACLEN+ I PLEN+ 16. TUCMD. L4T= 00b indicat es t hat t he packet is UDP and
t hat t he 16- bit checksum should be insert ed st art ing at byt e offset MACLEN+ I PLEN+ 6.
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MACLEN+ I PLEN specifies t he byt e offset from t he st art of t he DMA' ed dat a t o t he first byt e t o be
included in t he checksum, t he st art of t he UDP/ TCP header. See MACLEN t able in Sect ion 7. 2. 3. 2. 3 for
it s relevant values.
Not e: The MACLEN+ I PLEN+ L4LEN value must be less t han t he t ot al DMA lengt h for a packet . I f t his
is not t he case, t he result s are unpredict able.
The TCP/ UDP checksum always cont inues t o t he last byt e of t he DMA dat a.
Not e: For non-TSO, soft ware st ill needs t o calculat e a full checksum for t he TCP/ UDP pseudo-
header. This checksum of t he pseudo- header should be placed in t he packet dat a buffer at t he
appropriat e offset for t he checksum calculat ion.
7. 2.5. 3 SCTP Tr ansmi t Of f l oad
For SCTP packet s, a CRC32 checksum offload is provided.
Three fields in t he t ransmit cont ext descript or set t he cont ext of t he STCP checksum offloading feat ure:
MACLEN
I PLEN
TUCMD. L4T
TUCMD. L4T= 10b specifies t hat t he packet t ype is SCTP, and t hat t he 32- bit STCP CRC should be
insert ed at byt e offset MACLEN+ I PLEN+ 8.
I PLEN+ MACLEN specifies t he byt e offset from t he st art of t he DMA' ed dat a t o t he first byt e t o be
included in t he checksum, t he st art of t he STCP header. The minimal allowed value for t his sum is 26.
The SCTP CRC calculat ion always cont inues t o t he last byt e of t he DMA dat a.
The SCTP t ot al L3 payload size ( PAYLEN - I PLEN - MACLEN) should be a mult iple of four byt es ( SCTP
padding not support ed) .
Not e: TSO is not available for SCTP packet s.
Soft ware must init ialize t he SCTP CRC field t o zero ( 0x00000000) .
7. 2.5. 4 Check sum Suppor t ed per Pack et Ty pes
The following t able list s which checksums are support ed per packet t ype.
Not e: TSO is not support ed for packet t ypes for which I P checksum and TCP / UDP checksum cannot
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Tabl e 7. 43. Check sums Suppor t ed by Pack et Ty pe
Pack et Type HW I P Check sum Cal cul at i on
HW TCP/ UDP/ SCTP Check sum
Cal cul at i on
I Pv4 packet s Yes Yes
I Pv6 packet s No ( n/ a) Yes
I Pv6 packet wit h next header opt ions:
Hop- by- hop opt ions
Dest inat ions opt ions
Rout ing ( wit h len 0)
Rout ing ( wit h len > 0)
Fragment
Home opt ion
Securit y opt ion ( AH/ ESP)
No ( n/ a)
No ( n/ a)
No ( n/ a)
No ( n/ a)
No ( n/ a)
No ( n/ a)
No ( n/ a)
Yes
Yes
Yes
No
No
No
Yes
I Pv4 t unnels:
I pv4 packet in an I Pv4 t unnel
I pv6 packet in an I Pv4 t unnel
No
No
No
Yes
I Pv6 t unnels:
I Pv4 packet in an I Pv6 t unnel
I Pv6 packet in an I Pv6 t unnel
No
No
No
No
Packet is an I Pv4 fragment Yes No
Packet has 802. 3ac t ag Yes Yes
I Pv4 packet has I P opt ions and no I PSec header ( I P
header is longer t han 20 byt es)
Yes Yes
I Pv4 packet has I PSec header wit hout I P opt ions Yes Yes
Packet has TCP or UDP opt ions Yes Yes
I P header s prot ocol field cont ains prot ocol # ot her
t han TCP or UDP
Yes No
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7.3 I nt er r upt s
The 82599 support s t he following int errupt modes. Mapping of int errupt s causes is different in each of
t hese modes as described in t his sect ion.
PCI legacy int errupt s or MSI or MSI -X and only a single vect or is allocat ed select ed when
GPI E. Mult iple_MSI X is set t o 0b.
MSI -X wit h mult iple MSI -X vect ors in non- I OV mode select ed when GPI E. Mult iple_MSI X is set t o
1b and GPI E.VT_Mode is set t o 00b.
MSI -X in I OV mode select ed when GPI E.Mult iple_MSI X is set ( as previously st at ed) and
GPI E. VT_Mode DOES NOT equal 00b.
The following sect ions describe t he int errupt regist er s and device funct ionalit y at all operat ion modes.
7. 3. 1 I nt er r upt Regi st er s
Physi cal Funct i on ( PF) Regi st er s
The PF int errupt logic consist s of t he regist ers list ed in t he Table 7.44 followed by t heir descript ion:
These regist ers are ext ended t o 64 bit s by an addit ional set of t wo regist ers. EI CR has an addit ional t wo
regist ers EI CR( 1) . . . EI CR( 2) and so on for t he EI CS, EI MS, EI MC, EI AM and EI TR regist ers. The EI AC
regist er is not ext ended t o 64 bit s as t his ext ended int errupt causes are always aut o cleared. Any
reference t o EI CR. . . EI AM regist ers as well as any global int errupt set t ings in t he GPI E regist er relat es
t o t heir ext ended size of 64 bit s.
The legacy EI CR[ 15: 0] mirror t he cont ent of EI CR( 1) [ 15: 0] . I n t he same manner t he lower 16 bit s of
EI CS, EI MS, EI MC, EI AC, EI AM mirror t he lower 16 bit s of EI CS( 1) , EI MS( 1) , EI MC( 1) , EI AM( 1) . For
more det ails on t he use of t hese regist ers in t he various int errupt modes ( Legacy, MSI , MSI -X) see
Sect ion 7. 3. 4.
Tabl e 7. 44. PF I nt er r upt Regi st er s
Acr ony m Compl et e Name
EI CR Ext ended I nt errupt Cause regist er
EI CS Ext ended I nt errupt Cause Set regist er ( enables soft ware t o init iat e int errupt s)
EI MS Ext ended I nt errupt Mask Set / Read regist er
EI MC Ext ended I nt errupt Mask Clear regist er
EI AC Ext ended I nt errupt Aut o Clear regist er ( following int errupt assert ion)
EI AM Ext ended I nt errupt Aut o Mask regist er ( aut o set / clear of t he EI MS)
EI TR Ext ended I nt errupt Throt t ling regist er [ t hrot t ling and Low Lat ency I nt errupt ( LLI ) set t ing]
I VAR I nt errupt Vect or Allocat ion Regist ers ( described in Sect ion 7. 3. 4)
I VAR_MI SC Miscellaneous I nt errupt Vect or Allocat ion Regist er ( described in Sect ion 7. 3. 4)
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Vi r t ual Funct i on ( VF) Regi st er s
The VF int errupt logic has t he same set of int errupt regist ers while each of t hem has t hree ent ries for
t hree int errupt causes. The names and funct ionalit y of t hese regist ers are t he same as t hose of t he PF
wit h a prefix of VT as follows: VFEI CR, VFEI CS, VFEI MS, VFEI MC, VFEI AM, VFEI TR. The VFEI AC
regist ers are not support ed since int errupt causes are always aut o cleared. Alt hough each VF can
generat e up t o t hree int errupt s, only t he first t wo regist ers are capable of int errupt t hrot t ling and are
associat ed t o VFEI TR regist ers ( see Sect ion 7. 3. 4. 3. 2 for it s proper usage) . Each VF also has t he
mapping regist ers VFI VAR and VFI VAR_MI SC. Not e t hat any global int errupt set t ing by t he GPI E
regist er affect bot h int errupt set t ings of t he PF as well as t he VFs.
7. 3.1. 1 Ex t ended I nt er r upt Cause ( EI CR) Regi st er s
This regist er records t he int errupt causes t o provide soft ware informat ion on t he int errupt source. Each
t ime an int errupt cause happens, t he corresponding int errupt bit is set in t he EI CR regist ers. An
int errupt is generat ed each t ime one of t he bit s in t hese regist ers is set , and t he corresponding
int errupt is enabled via t he EI MS regist ers. The possible int errupt causes are as follows:
Each RTxQ bit represent s t he following event s: Tx or Rx descript or writ e back; Rx queue full and Rx
descript or queue minimum t hreshold.
The RTxQ int errupt s can be t hrot t led by I TR or LLI as configured in t he EI TR regist er ( LLI does
not impact Tx) . Following int errupt assert ion, soft ware cannot dist inguish bet ween I TR or LLI
event s.
Mapping t he Tx and Rx queues t o EI CR is done by t he I VAR regist ers as described in
Sect ion 7. 3. 4. Each bit might represent an event on a single Tx or Rx queue or could represent
mult iple queues according t o t he I VAR set t ing. I n t he lat er case, soft ware might not be able t o
dist inguish bet ween t he int errupt causes ot her t han checking all associat ed Tx and Rx queues.
The Mult iple_MSI X = 1b set t ing is useful when mult iple MSI -X vect ors are assigned t o t he
device. When t he GPI E. Mult iple_MSI X bit is set , t he RTxQ bit s are associat ed wit h dedicat ed
MSI -X vect ors. Bit 0 is Tx / Rx int errupt associat ed wit h MSI -X vect or 0 and bit 15 is Tx / Rx
int errupt associat ed wit h MSI -X vect or 15.
Bit s 29: 16 in t he EI CR are named in t he EAS as t he ot her int errupt causes. Please refer t o t he
EI CR regist er definit ion for t he exact int errupt causes included in t his group. All t hese causes are
mapped t o t he same int errupt even in Mult iple_MSI X mode. I n Mult iple_MSI X mode t he ot her
int errupt causes are mapped t o a specific MSI -X vect or by t he I NT_Alloc[ 1] in t he I VAR_MI SC
regist er.
Bit 30 in t he EI CR regist er is t he TCP Timer int errupt usually used t o wake t he SW driver
periodically according t o t he TCPTI MER set t ing. I n Mult iple_MSI X mode t he TCP Timer int errupt is
mapped t o a specific MSI -X vect or by t he I NT_Alloc[ 0] in t he I VAR_MI SC regist er.
Writ ing a 1b t o any bit in t he regist er clears it . Writ ing a 0b t o any bit has no effect . The EI CR is also
cleared on read if GPI E.OCD bit is cleared. When t he GPI E. OCD bit is set , t hen only bit s 16. . . 29 are
cleared on read. The lat er set t ing is useful for MSI -X mode in which t he Tx and Rx and possibly t he
t imer int errupt s do not share t he same int errupt wit h t he ot her causes. Bit s in t he regist er can be aut o
cleared depending on t he EI AC regist er set t ing ( det ailed in Sect ion 7. 3. 1. 4) .
7. 3.1. 2 Ex t ended I nt er r upt Cause Set ( EI CS) Regi st er
This regist er enables soft ware t o init iat e a hardware int errupt . Set t ing any bit on t he EI CS set s it s
corresponding bit in t he EI CR regist er while bit s writ t en t o 0b have no impact . I t t hen causes an
int errupt assert ion if enabled by t he EI MS regist er. Set t ing any bit generat es eit her LLI or t hrot t led
int errupt depending on t he GPI E. EI MEN set t ing: When t he EI MEN bit is set , t hen set t ing t he EI CS
regist er causes an LLI int errupt ; When t he EI MEN bit is cleared, t hen set t ing t he EI CS regist er causes
an int errupt aft er t he corresponding int errupt t hrot t ling t imer expires.

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Not e: The EI MEN bit can be set high only when working in aut o- mask mode ( EI AM bit of t he
associat ed int errupt is set ) .
7.3.1.2.1 EI CS Af f ect on RSC Funct i onal i t y
Set t ing EI CS bit s causes int errupt assert ion ( if enabled) . EI CS set t ings have t he same impact on RSC
funct ionalit y as nominal operat ion:
I n I TR mode ( GPI E. EI MEN = 0b) , set t ing t he EI CS bit s impact t he RSC complet ion and int errupt
assert ion t he same as any Rx packet . The funct ionalit y depends on t he EI CS set t ing schedule
relat ive t o t he I TR int ervals as described in Sect ion 7.3. 2. 1.1.
I n LLI mode ( GPI E. EI MEN = 1b) , set t ing t he EI CS bit s impact t he RSC complet ion and int errupt
assert ion t he same as any LLI Rx packet . Device behavior is described in Sect ion 7. 3. 2. 2. 3 st art ing
wit h t he 2nd st ep.
7. 3. 1. 3 Ex t ended I nt er r upt Mask Set and Read ( EI MS) Regi st er , and Ex t ended
I nt er r upt Mask Cl ear ( EI MC) Regi st er
The Ext ended I nt errupt Mask Set and Read ( EI MS) regist er enables t he int errupt s in t he EI CR. When
set t o 1b, each bit in t he EI MS regist er, enables it s corresponding bit in t he EI CR. Soft ware might
enable each int errupt by set t ing bit s in t he EI MS regist er t o 1b. Reading EI MS ret urns it s value.
Soft ware might clear any bit in t he EI MS regist er by set t ing it s corresponding bit in t he Ext ended
I nt errupt Mask Clear ( EI MC) regist er. Reading t he EI MC regist er does not ret urn any meaningful dat a.
This independent mechanism of set t ing and clearing bit s in t he EI MS regist er saves t he need for read
modify writ e and also enables simple programming in mult i- t hread, mult i- CPU core syst ems.
Not e: The EI CR regist er st ores t he int errupt event s regardless of t he st at e of t he EI MS regist er.
7. 3. 1. 4 Ex t ended I nt er r upt Aut o Cl ear Enabl e ( EI AC) Regi st er
Each bit in t his regist er enables aut o clearing of it s corresponding bit in EI CR following int errupt
assert ion. I t is useful for Tx and Rx int errupt causes t hat have dedicat ed MSI -X vect ors. When t he Tx
and Rx int errupt causes share an int errupt wit h t he ot her or a t imer int errupt , t he relevant EI AC bit s
should not be set . Bit s in t he EI CR regist er t hat are not enabled by aut o clear, must be cleared by eit her
writ ing a 1b t o clear or a read t o clear.
Not e t hat t here are no EI AC( 1) . . . EI AC( 2) regist ers. The hardware set t ing for int errupt s 16. . . 63 is
always aut o clear.
Not e: Bit s 29: 16 should never be set t o aut o clear since t hey share t he same MSI -X vect or.
Writ ing t o t he EI AC regist er changes t he set t ing of t he ent ire regist er. I n I OV mode, some of
t he bit s in t his regist er might affect VF funct ionalit y ( VF- 56. . . VF- 63) . I t is recommended t hat
soft ware set t he regist er in PF before VFs are enabled. Ot herwise, a soft ware semaphore
might be required bet ween t he VF and t he PF t o avoid set t ing corrupt ion.
7. 3. 1. 5 Ex t ended I nt er r upt Aut o Mask Enabl e ( EI AM) Regi st er
Each bit in t his regist er enables aut o clearing and aut o set t ing of it s corresponding bit in t he EI MS
regist er as follows:
Following a writ e of 1b t o any bit in t he EI CS regist er ( int errupt cause set ) , it s corresponding bit in
t he EI MS regist er is aut o set as well enabling it s int errupt .
A writ e t o clear t he EI CR regist er clears it s corresponding bit s in t he EI MS regist er masking furt her
int errupt s.
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A read t o clear t he EI CR regist er, clears t he EI MS bit s ( enabled by t he EI AM) masking furt her
int errupt s. Not e t hat if t he GPI E. OCD bit is set , Tx and Rx int errupt causes are not cleared on read
( bit s 0: 15 in t he EI CR) . I n t his case, bit s 0: 15 in t he EI MS are not cleared as well.
I n MSI -X mode t he, aut o clear funct ionalit y can be driven by MSI -X vect or assert ion if GPI E. EI AME
is set .
Not e: Bit s 29: 16 should never be set t o aut o clear since t hey share t he same MSI -X vect or.
Writ ing t o t he EI AM regist er changes t he set t ing of t he ent ire regist er. I n I OV mode, some of
t he bit s in t his regist er might affect VF funct ionalit y. I t is recommended t hat soft ware set t he
regist er in PF before VFs are enabled. Ot herwise, a soft ware semaphore might be required
bet ween t he VF and t he PF t o avoid set t ing corrupt ion.
I f any of t he Aut o Mask enable bit s is set in t he EI AM regist ers, t he GPI E. EI AME bit must be
set as well.
7.3.2 I nt er r upt Moder at i on
I nt errupt rat es can be t uned by t he EI TR regist er for reduced CPU ut ilizat ion while minimizing CPU
lat ency. I n MSI or legacy int errupt modes, only EI TR regist er 0 can be used. I n MSI -X, non- I OV mode,
t he 82599 includes 64 EI TR regist ers 0. . . 63 t hat are mapped t o MSI -X vect ors 0.. .63, respect ively. I n
I OV mode, t here are an addit ional 65 EI TR regist ers t hat are mapped t o t he MSI -X vect ors of t he virt ual
funct ions. The mapping of MSI -X vect ors t o EI TR regist ers are described in Sect ion 7. 3. 1.1.
The EI TR regist ers include t wo t ypes of t hrot t ling mechanisms: I TR and LLI . Bot h are described in t he
sect ions t hat follow.
7. 3. 2. 1 Ti me- based I nt er r upt Thr ot t l i ng I TR
Time- based int errupt t hrot t ling is useful t o limit t he maximum int errupt rat e regardless of net work
t raffic condit ions. The I TR logic is t arget ed for Rx/ Tx int errupt s only. I t is assumed t hat t he t imer, ot her
and mail box ( I OV mode) int errupt s are not moderat ed. I n non- I OV mode, all 64 int errupt s can be
associat ed wit h I TR logic. I n I OV mode, t he I TR logic is shared bet ween t he PF and VFs as shown in
Figure 7. 21. The I TR mechanism is based on t he following paramet ers:
I TR I nt er v al field in t he EI TR regist ers The minimum int er- int errupt int erval is specified in 2 s
unit s ( at 1 Gb/ s or 10 Gb/ s link) . When t he I TR I nt erval equals zero, int errupt t hrot t ling is disabled
and any event causes an immediat e int errupt . The field is composed of nine bit s enabling a range of
2 s up t o 1024 s. These I TR int erval t imes correspond t o int errupt rat es in t he range of 500 K
I NT/ sec t o 980 I NT/ sec. When operat ing at 100 Mb/ s link, t he I TR int erval is specified in 20 s
unit s.
Due t o int ernal synchronizat ion issues, t he I TR int erval can be short ened by up t o 1 s at
10 Gb/ s or 1 Gb/ s link and up t o 10 s at 100 Mb/ s link when it is t riggered by packet writ e
back or int errupt enablement or t he last int errupt was LLI .
I TR Count er part ially exposed in t he EI TR regist ers Down count er t hat is loaded by t he I TR
int erval each t ime t he associat ed int errupt is assert ed.
The count er is decrement ed by one each 2 s ( at 1 Gb/ s or 10 Gb/ s link) and st ops
decrement ing at zero. At 100 Mb/ s link, t he speed of t he count er is decrement ed by one each
20 s.
I f an event happens before t he count er is zero, it set s t he EI CR. The int errupt can be assert ed
only when t he I TR t ime expires ( count er is zero) .
Else ( no event s during t he ent ire I TR int erval) , t he EI CR regist er is not set and t he int errupt is
not assert ed on I TR expirat ion. The next event set s t he EI CR bit and generat es an immediat e
int errupt . See Sect ion 7.3. 2. 1. 1 for int errupt assert ion when RSC is enabled.

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Once t he int errupt is assert ed, t he I TR count er is loaded by t he I TR int erval and t he ent ire cycle
rest art s. The next int errupt can be generat ed only aft er t he I TR count er expires once again.
7. 3.2. 1.1 I TR Af f ect on RSC Funct i onal i t y
I nt errupt assert ion is one of t he causes for RSC complet ion ( see Sect ion 7.11. 6) . When RSC is enabled
on specific Rx queues, t he associat ed I TR int erval wit h t hese queues must be enabled and must be
larger ( in t ime unit s) t han RSC delay. The I TR is divided t o t he t wo t ime int ervals t hat are defined by
t he I TR int erval and RSC delay. RSC complet ion is t riggered aft er t he first int erval complet es and t he
int errupt is assert ed when t he second int erval complet es.
The RSC Delay field is defined in t he GPI E regist ers. RSC Delay can have one of t he following eight
values: 4 s, 8 s, 12 s.. . 32 s.
The first I TR int erval equals I TR int erval minus RSC delay. The int ernal I TR count er st art s at I TR
int erval value and count s down unt il it reaches t he RSC delay value. Therefore, t he I TR int erval
must be set t o a larger value t han t he RSC delay.
The second I TR int erval equals RSC delay. The int ernal I TR count er cont inues t o count down unt il it
reaches zero.
RSC complet ion can t ake some t ime ( usually in t he range of a few micro seconds) . This t ime is
composed by complet ing t riggering lat ency and complet ing process lat ency. These delays should be
considered when t uning t he RSC delay. The clock frequency of t he RSC complet ion logic depends on
t he link speed. As a result , t he complet ion delay can as high as ~ 0. 8 s at 10 Gb/ s link and
~ 8 s at 1 Gb/ s link. The RSC complet ion logic might t ake addit ional ~ 50 ns at 10 Gb/ s link and
~ 0.5 s at 1 Gb/ s link per RSC. I n addit ion, t here is t he PCI e bus arbit rat ion lat ency as well as
syst em propagat ion lat encies from t he device up t o host memory.
Recommended RSC delay numbers are: 8 s at 10 Gb/ s link and 28 s at 1 Gb/ s link.
RSC is not recommended when operat ing at 100 Mb/ s link.
Following are cases of packet recept ion wit h respect t o t he I TR int ervals:
Packet s are received and post ed ( including t heir st at us) t o t he Rx queue in t he first I TR int erval. I n
t his case, RSC complet ion is t riggered at t he end of t he first I TR int erval and t he int errupt is
assert ed at t he second int erval expirat ion.
a packet ( and it s st at us) is received and post ed t o t he Rx queue only aft er t he first I TR int erval has
expired ( eit her on t he second int erval or aft er t he ent ire I TR int erval has expired) . I n t his case, RSC
complet ion is t riggered almost inst ant ly ( ot her t han int ernal logic lat encies) . The int errupt is
assert ed at RSC delay t ime aft er t he non- coalesced Rx st at us is queued t o be post ed t o t he host .
Due t o int ernal synchronizat ion issues, t he RSC delay can be short en by up t o 1 s when it is
t riggered by packet writ e back.
7.3.2.2 LLI
LLI provides low lat ency service for specific packet t ypes, bypassing t he I TR lat ency. LLI s are bound by
a credit - based t hrot t ling mechanism t hat limit s t he maximum rat e of low lat ency event s t hat require a
fast CPU response. Low lat ency event s are t riggered by t he writ e back of t he LLI packet s. I t t hen
generat es an immediat e int errupt if LLI credit s are not exhaust ed. See more det ails on t he credit
mechanism in t he Sect ion 7. 3. 2. 2.2. Not e also t hat in t he case of RSC, t he int errupt is not immediat e
as described in Sect ion 7. 3. 2. 2.3.
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7.3.2. 2.1 LLI Fi l t er s and Ot her Cases
Following is a list of all Rx packet s t hat are defined as low lat ency event s ( LLI packet s) :
LLI by 5- t upl e / TCP f l ags / f r ame si ze The 82599 support s a set of 128 filt ers t hat init iat e
LLI by a 5- t uple value and frame size. An LLI is issued if any of t he filt ers are set for LLI mat ches
against t he enabled fields of 5- t uple, TCP flags, and frame size. Configurat ion is done via t he FTQF,
SDPQF, L34TI MI R, DAQF, and SAQF regist ers as follows per filt er ( more det ails about t hese filt ers
can be found in Sect ion 7. 1. 2.5) . Not e t hat if a packet mat ches mult iple 5- t uple filt ers an LLI is
init iat ed if it is enabled by any of t he mat ched filt ers:
5- t uple fields ( prot ocol, I P address, port ) and mask opt ions for t hese fields
Pool and pool mask
SizeThresh A frame wit h a lengt h below t his t hreshold t riggers an int errupt . Unlike ot her fields,
t he SizeThresh field is shared by all filt ers ( like t here is a single copy of it ) . Mat ching t he frame
size is enabled by t he Size_BP bit .
Size_BP bit , when set t o 0b, equat es t o a mat ch t hat is performed against t he frame size.
LLI field When set , an LLI is issued for packet s t hat mat ch t he filt er.
LLI by Et her t ype The 82599 support s eight Et hert ype filt ers. Any filt er has an LLI act ion
defined by t he LLI field in t he ETQS regist ers.
LLI by VLAN pr i or i t y The 82599 support s VLAN priorit y filt ering as defined in t he I MI RVP
regist er. Packet s wit h VLAN header t hat have higher priorit y t agging t han t he one defined by
I MI RVP regist er generat es an LLI .
LLI by FCoE FCoE FCP_RSP packet s can t rigger LLI as defined in t he FCRXCTRL. RSCI NT bit . The
82599 ident ifies FCoE packet s by t he Et hert ype filt ers defined by t he ETQF regist ers. FCP_RSP
packet s recognit ion is explained in Sect ion 7. 13. 3. 3.10.
The 82599 might init iat e an LLI when t he receive descript or ring is almost empt y ( Rx descript ors below
a specific t hreshold) . The t hreshold is defined by SRRCTL[ n] . RDMTS per Rx queue. This mechanism can
prot ect against memory resources being used up during recept ion of a long burst of short packet s.
7.3.2. 2.2 LLI Par amet er s
LLI generat ion is based on t he following paramet ers:
LLI Moder at i on bit in t he EI TR regist ers When t he LLI Moderat ion bit is cleared, any low lat ency
event generat es an immediat e int errupt . When set , LLI moderat ion is based on t he LLI credit and
LLI int erval.
LLI Cr edi t field in t he EI TR regist er LLI packet s might generat e immediat e int errupt s as long as
t he LLI credit s count er is great er t han one ( posit ive credit ) .
The credit count er is increment ed by one on each LL int erval wit h a maximum ceiling of 31
credit s. I t t hen st ops increment ing.
I f an LLI packet is received and t he credit count er is great er t han zero, an immediat e int errupt
is t riggered int ernally. The int errupt is assert ed ext ernally when an int errupt is enabled ( EI MS
set t ing) and PCI credit s are available. Once t he int errupt is assert ed, t he credit count er is
decrement ed by one Not e t hat t he count er never goes below zero.
LLI assert ion might be delayed due t o: int errupt enablement , lack of LLI credit s or lack of PCI
credit s. Each t ime t he int errupt is assert ed, t he LLI credit is decrement ed by one regardless of
t he number of received LLI packet s and regardless if t he I TR t imer expires in t he mean t ime.
I f an LLI packet is received and t he credit count er is zero ( no credit s) , an int errupt can be
assert ed only on t he next LL int erval or when t he I TR t imer expires, whichever comes first .
The LLI credit count er is not affect ed by t he I TR t imer. Conversely, LLI assert ion init ializes t he
I TR t imer t o it s t imer int erval.
Not e t hat during nominal operat ion soft ware may not need t o access t he LL credit field.

313
LL i nt er v al is defined in unit s of 4 s ( at 1 Gb/ s or 10 Gb/ s link) in t he GPI E regist er. At 100 Mb/ s
link speed, t he LL int erval is defined in unit s of 40 s. This paramet er defines t he clock t hat
increment s t he LLI credit count er. The maximum rat e of t he LLI int errupt s per second is bound by
t he LL int erval, which equals t o 1/ LL I nt erval. When LLI moderat ion is enabled, t he I TR int erval of
t he same int errupt must be great er t han t he LL int erval.
7.3.2.2.3 LLI s Af f ect on RSC Funct i onal i t y
LLI packet recept ion requires inst ant CPU processing. Soft ware might be able t o access a specific
descript or only if all it s proceeding descript ors complet e. I f RSCs are enabled, some of t he preceding
descript ors might be incomplet e at t he t ime t hat t he LLI packet is received. Hardware overcomes t his
problem by:
Following LLI packet complet ion, all RSCs on t he same queue are complet ed as well.
Then, t he associat ed int errupt is assert ed.
Concurrent ly, hardware t riggers RSC complet ion in all Rx queues associat ed wit h t he same
int errupt .
Most likely t hese RSC( s) are complet ed t o host memory aft er t he int errupt is already assert ed. I n
t his case, it is guarant eed t hat an addit ional int errupt is assert ed when t he I TR expires.
7. 3. 3 TCP Ti mer I nt er r upt
7.3.3.1 I nt r oduct i on
I n order t o implement TCP t imers for I OAT, soft ware needs t o t ake act ion periodically ( every 10 ms) .
Today, t he driver must rely on soft ware- based t imers, whose granularit y can change from plat form t o
plat form. This soft ware t imer generat es a soft ware NI C int errupt , which t hen enables t he driver t o
perform t imer funct ions, avoiding cache t hrash and enabling parallelism. The t imer int erval is syst em-
specific.
I t would be more accurat e and more efficient for t his periodic t imer t o be implement ed in hardware.
The driver would program a t imeout value ( usual value of 10 ms) , and each t ime t he t imer expires,
hardware set s a specific bit in t he EI CR regist er. When an int errupt occurs ( due t o normal int errupt
moderat ion schemes) , soft ware reads t he EI CR regist er and discovers t hat it needs t o process t imer
event s.
The t imeout should be programmable by t he driver, and t he driver should be able t o disable t he t imer
int errupt if it is not needed.
7.3.3.2 Descr i pt i on
A st and- alone, down- count er is implement ed. An int errupt is issued each t ime t he value of t he count er
is zero.
Soft ware is responsible for set t ing an init ial value for t he t imer in t he Durat ion field. Kick- st art ing is
done by writ ing a 1b t o t he KickSt art bit .
Following kick st art ing, an int ernal count er is set t o t he value defined by t he Durat ion field. Then t he
count er is decreased by one each ms. When t he count er reaches zero, an int errupt is issued. The
count er rest art s count ing from it s init ial value if t he Loop field is set .
7. 3. 4 Mappi ng of I nt er r upt Causes
The following sect ions describe legacy, MSI and MSI -X int errupt modes.
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314
7. 3. 4. 1 Legacy and MSI I nt er r upt Modes
I n legacy and MSI modes, an int errupt cause is reflect ed by set t ing one of t he bit s in t he EI CR regist er,
where each bit reflect s one or more causes. All int errupt causes are mapped t o a single int errupt signal:
eit her legacy I NTA/ B or MSI . This sect ion describes t he mapping of int errupt causes ( t hat is a specific
Rx or Tx queue event or any ot her event ) t o bit s in t he EI CR.
The TCP t imer and all ot her int errupt causes are mapped direct ly t o EI CR[ 30: 16] . Not e t hat t he
I VAR_MI SC regist er is not used in legacy and MSI modes.
Mapping t he Tx and Rx queues t o int errupt bit s in t he EI CR regist er is programmed in t he I VAR
regist ers as shown in Figure 7. 21. Each ent ry in t he I VAR regist ers is composed of t wo fields t hat
ident ify t he associat ed bit in t he EI CR[ 15: 0] regist er. Soft ware might map mult iple Tx and Rx queues t o
t he same EI CR bit .
I NT_Al l oc - Defines one of t he bit s ( 0. .. 15) in t he EI CR regist er t hat reflect s t he int errupt st at us
indicat ion.
I NT_Al l oc_v al - Valid bit for t his int errupt cause.
Mapping bet ween t he Tx and Rx queue t o t he I VAR regist ers is hardwired as shown in t he Figure 7. 22
below:
7. 3. 4. 2 MSI - X Mode i n Non- I OV Mode
MSI -X defines a separat e opt ional ext ension t o basic MSI funct ionalit y. The number of request ed MSI -X
vect ors is loaded from t he MSI _X_N fields in t he EEPROM up t o maximum of 64 MSI -X vect ors.
Fi gur e 7.21. Cause Mappi ng i n Legacy and MSI Modes
Fi gur e 7.22. Rx and Tx Queue Mappi ng t o I VAR Regi st er s
I
V
A
R
R
e
g
i
s
t
e
r
s
Cause 0
Cause 255
E
I
C
R
(
r
e
f
l
e
c
t

c
a
u
s
e
s
)
INT(A/B)
/ MSI
Other
Interrupt
causes
TCP timer
0
15
16
30
Queue
Related
causes
Timer
and all
Other
Interrupt
causes
.
.
.
.
.
.
EITR 0
Rx 0
Tx 0
Rx 1
Tx 1
IVAR 0
Rx 2
Tx 2
Rx 3
Tx 3
IVAR 1
Rx 4
Tx 4
Rx 5
Tx 5
IVAR 2
Rx 124
Tx 124
Rx 125
Tx 125
IVAR 62
Rx 126
Tx 126
Rx 127
Tx 127
IVAR 63
. . .

315
Hardware indicat es t he number of request ed MSI -X vect ors in t he t able size in t he MSI -X capabilit y
st ruct ure in t he configurat ion space. This paramet er is loaded from t he MSI _X _N field in t he
EEPROM. The operat ing syst em might allocat e any number of MSI -X vect ors t o t he device from a
minimum of one up t o t he request ed number of MSI -X vect ors.
Enables int errupt s causes allocat ion t o t he assigned MSI -X vect ors. I nt errupt allocat ion is
programmed by t he I VAR regist ers and are described in t his sect ion.
Each vect or can use an independent address and dat a value as programmed direct ly by t he
operat ing syst em in t he MSI -X vect or t able.
Each MSI -X vect or is associat ed t o an EI TR regist er wit h t he same index ( MSI -X 0 t o EI TR[ 0] , MSI -
X 1 t o EI TR[ 1] , . . . ) .
For more informat ion on MSI -X, refer t o t he PCI Local Bus Specificat ion, Revision 3. 0.
MSI -X vect ors can be used for several purposes:
1. Dedicat ed MSI -X vect ors per int errupt cause ( avoids t he need t o read t he int errupt cause regist er) .
2. Load balancing by MSI -X vect ors assignment t o different CPUs.
3. Opt imized int errupt moderat ion schemes per MSI -X vect or using t he EI TR regist ers.
The MSI -X vect ors are used for Tx and Rx int errupt causes as well as t he ot her and t imer int errupt
causes. The remainder of t his sect ion describes t he mapping of int errupt causes ( such as a specific Rx
or Tx queue event or any ot her event ) t o t he int errupt s regist ers and t he MSI -X vect ors.
The TCP t imer and ot her event s are reflect ed in EI CR[ 30: 16] t he same as t he legacy and MSI mode. I t
is t hen mapped t o t he MSI -X vect ors by t he I VAR_MI SC regist er as shown in Figure 7. 23. The
I VAR_MI SC regist er includes t wo ent ries for t he t imer int errupt and an addit ional ent ry for all t he ot her
causes. The st ruct ure of each ent ry is as follows:
I NT_Al l oc - Defines t he MSI -X vect or ( 0. . . 63) assigned t o t his int errupt cause.
I NT_Al l oc_val - Valid bit for t he t his int errupt cause.
The Tx and Rx queues are associat ed t o t he I VAR0.. .I VAR63 t he same as legacy and MSI mode shown
in Figure 7. 22. The Tx and Rx queues are mapped by t he I VAR regist ers t o EI CR( 1) , . . . EI CR( 2) regist ers
and MSI -X vect ors 0.. . 63 illust rat ed in Figure 7. 23. The I VAR ent ries have t he same st ruct ure as t he
I VAR_MI SC regist er previously shown. Each bit in EI CR( 1. . . 2) regist ers is associat ed t o MSI -X vect or
0. . . 63 as follows:
EI CR( i) . bit _num is associat ed t o MSI -X vect or ( n x 32 + bit _num) .
The legacy EI CR[ 15: 0] mirror t he cont ent of EI CR( 1) [ 15: 0] . I n t he same manner t he lower 16 bit s
of EI CS, EI MS, EI MC, EI AC, EI AM mirror t he lower 16 bit s of EI CS( 1) , EI MS( 1) , EI MC( 1) , EI AC( 1) ,
EI AM( 1) . The use of t hese regist ers depends on t he number of assigned MSI -X int errupt s as
follows:
16 Tx and Rx I nt er r upt s - When using up t o 16 Tx and Rx int errupt s, soft ware might access t he
Tx and Rx int errupt bit s in t he legacy EI CR, EI CS, . . . regist ers.
Mor e t han 16 Tx and Rx I nt er r upt s - When using more t hen 16 Tx and Rx int errupt s, soft ware
must use EI CS( 1) . . . EI CS( 2) , EI MS( 1) . . . EI MS( 2) , . . . I n t he lat er case, soft ware should avoid
modifying t he lower 16 bit s in t he SEI C, EI CS. . . regist ers when it accesses t he higher bit s of t hese
regist ers as follows:
EI CR, EI CS, EI MS and EI MC When soft ware programs t he higher 16 bit s of t hese regist ers, it
should set t heir lower 16 bit s t o zeros keeping t he EI CR( 1) , EI CS( 1) , EI MS( 1) and EI MC( 1)
unaffect ed.
EI AM When soft ware programs t he higher 16 bit s, it should keep t he lower 16 bit s at t heir
previous set t ing so t he EI AM( 1) is unaffect ed.
EI AC When soft ware programs t he higher 16 bit s, it should set t he lower 16 bit s t o ones.
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316
Si ngl e MSI - X v ect or - I f t he operat ing syst em allocat es only a single MSI -X vect or, t he driver might
use t he non- MSI -X mapping met hod ( set t ing t he GPI E. Mult iple_MSI X t o 0b) . I n t his case, t he I NT_Alloc
field in t he I VAR regist ers might define one of t he lower 16 bit s in t he EI CR regist er while using MSI -X
vect or 0. The I VAR_MI SC should be programmed t o MSI -X vect or 0.
7. 3. 4. 3 MSI - X I nt er r upt s I n I OV Mode
I n I OV mode, int errupt s must be implement ed by MSI -X vect ors. The 82599 support s up t o 64 virt ual
funct ions VF( 0. . . 63) . Each VF can generat e up t o t hree MSI -X vect ors. The number of request ed MSI -X
vect ors per VF is loaded from t he MSI - X Table field in t he EEPROM. I t is reflect ed in t he Table Size field
in t he PCI e MSI -X capabilit y st ruct ure of t he VFs. I n addit ion, t he PF requires it s own int errupt s. The
number of request ed MSI -X vect ors for t he PF is loaded from t he MSI _X_N fields in t he EEPROM up t o
maximum of 64 MSI -X vect ors. I t is reflect ed in t he Table Size field in t he PCI e MSI -X capabilit y
st ruct ure.
7.3.4. 3.1 MSI - X Vect or s Used by Phy si cal Funct i on ( PF)
PF is responsible for t he t imer and ot her int errupt causes t hat include t he VM t o PF mailbox cause
( explained in t he virt ualizat ion sect ions) . These event s are reflect ed in EI CR[ 30: 16] and MSI -X vect ors
are t he same as t he non- I OV mode ( illust rat ed in Figure 7. 21) . When t here are less t han t he maximum
possible act ive VFs, some of t he Tx and Rx queues can be associat ed wit h t he PF. These queues can be
used for t he sake of addit ional VMs serviced by t he hypervisor ( t he same as VMDq mode) or some
Kernel applicat ions handled by t he hypervisor. Tx and Rx mapping t o t he I VAR regist ers is shown in
Figure 7. 22 and mapping t o t he EI CR, EI CR( 1) , . . . EI CR( 2) regist ers as well as t he MSI -X vect ors is
shown in Figure 7. 23. See Sect ion 7. 3. 4. 3.3 for MSI -X vect ors mapping of PF and VFs t o t he EI TR
regist ers.
Not e: Soft ware should not assign MSI -X vect ors in t he PF t o Tx and Rx queues t hat are assigned t o
ot her VFs. I n t he case t hat VFs become act ive aft er t he PF used t he relevant Tx and Rx
queues, it is t he responsibilit y of t he PF driver t o clear all pending int errupt s of t he associat ed
MSI -X vect ors.
Fi gur e 7.23. Cause Mappi ng i n MSI - X Mode ( non- I OV)
I
V
A
R
R
e
g
i
s
t
e
r
s
Cause 0
Cause 255
E
I
C
R
1

E
I
C
R
2
(
r
e
f
l
e
c
t

c
a
u
s
e
s
)
0
63
Queue
Related
causes:
Rx 0...127
Tx 0...127
Timer
and all
Other
Interrupt
causes
.
.
.
.
.
.
I
V
A
R
_
M
I
S
C
Other
Interrupt
causes
TCP timer
16
30
EICR
MSI-X
Vectors
0...63
EITR 0...63

317
7. 3.4. 3.2 MSI - X Vect or s Used by Vi r t ual Funct i ons ( VFs)
Each of t he VFs in I OV mode is allocat ed separat e I VAR( s) called VFI VAR regist ers, and a separat e
I VAR_MI SC called VFI VAR_MI SC regist er. The VFI VAR_MI SC maps t he mailbox int errupt of t he VF t o it s
VFEI CR and t he MSI -X vect or. The VFI VAR regist ers map t he Tx and Rx int errupt s of t he VF t o it s
VFEI CR and t he MSI -X vect or. The mapping is similar t o t he mapping in t he PF as shown in Figure 7. 24
wit h t he following comment s:
Each VF cannot have more t han t hree MSI -X vect ors. I t has only t hree act ive bit s in t he VFEI CR
regist er while VFEI CR. bit _num is associat ed wit h MSI -X vect or ( bit _num) .
The Tx and Rx int errupt can be mapped only t o MSI -X 0 and MSI -X 1 ( associat ed wit h VFEI CR. 0 and
VFEI CR. 1) .
The mailbox int errupt can be mapped t o any of t he t hree MSI -X vect ors. However, when all t hree of
t hem are allocat ed by t he operat ing syst em, soft ware should map t he mailbox t o MSI -X 2
( associat ed wit h VFEI CR.2) . This rule should be kept since only VFEI CR. 0 and VFEI CR. 1 have I TR
regist ers ( VFEI TR- 0 and VFEI TR- 1) .
Associat ion bet ween t he Tx and Rx queues and t he VFI VAR regist ers is shown in t he Figure 7. 24,
Figure 7.25 and Figure 7.26 for I OV- 64 ( 64 VFs) , I OV- 32 and I OV- 16. The colored boxes in t he
figures show t he mapping bet ween VF Rx and Tx queues t o VFI VAR regist ers while t he dashed
boxes show t he physical I VAR regist ers and t he associat ed physical Rx and Tx queues.
Fi gur e 7.24. VF I nt er r upt Cause Mappi ng ( MSI - X, I OV)
Fi gur e 7.25. VF Mappi ng of Rx and Tx Queue t o VFI VAR i n 64 VF s Mode
V
T
I
V
A
R
R
e
g
i
s
t
e
r
s
Cause 0
Cause 15
V
T
E
I
C
R
(
r
e
f
l
e
c
t

c
a
u
s
e
s
)
0
2
Queue
Related
causes:
Rx 0...7
Tx 0...7
Mail-Box
Interrupt
.
.
.
V
T
I
V
A
R
_
M
I
S
C
R
e
g
i
s
t
e
r
MSI-X 2
MSI-X 0
EITR 0
MSI-X 1
EITR 1
Rx 0
Tx 0
Rx 1
Tx 1
VFIVAR 0
HW Queeus VF Queues
VFIVAR 0
HW Queeus VF Queues
Rx 2
Tx 2
Rx 3
Tx 3
. . .
VFIVAR 0
HW Queeus VF Queues
Rx 126
Tx 126
Rx 127
Tx 127
Rx 0
Tx 0
Rx 1
Tx 1
Rx 0
Tx 0
Rx 1
Tx 1
Rx 0
Tx 0
Rx 1
Tx 1
VF 0 VF 1 VF 63
I nt el

318
HW Queeus VF Queues HW Queeus VF Queues
. . .
HW Queeus VF Queues
Rx 2
Tx 2
Rx 3
Tx 3
VFIVAR 1
HW Queeus VF Queues
VFIVAR 1
HW Queeus VF Queues
. . .
VFIVAR 1
HW Queeus VF Queues
Rx 0
Tx 0
Rx 1
Tx 1
Rx 2
Tx 2
Rx 3
Tx 3
Rx 0
Tx 0
Rx 1
Tx 1
Rx 4
Tx 4
Rx 5
Tx 5
Rx 124
Tx 124
Rx 125
Tx 125
Rx 126
Tx 126
Rx 127
Tx 127
Rx 6
Tx 6
Rx 7
Tx 7
VF 0 VF 1 VF 31
VFIVAR 0 VFIVAR 0 VFIVAR 0
Rx 0
Tx 0
Rx 1
Tx 1
Rx 2
Tx 2
Rx 3
Tx 3
Rx 0
Tx 0
Rx 1
Tx 1
Rx 2
Tx 2
Rx 3
Tx 3
. . .
VF Queues
Rx 2
Tx 2
Rx 3
Tx 3
VFIVAR 1
HW Queeus VF Queues
VFIVAR 1
HW Queeus VF Queues
. . .
VFIVAR 1
VF Queues
Rx 0
Tx 0
Rx 1
Tx 1
Rx 2
Tx 2
Rx 3
Tx 3
Rx 0
Tx 0
Rx 1
Tx 1
Rx 8
Tx 8
Rx 9
Tx 9
Rx 120
Tx 120
Rx 121
Tx 121
Rx 122
Tx 122
Rx 123
Tx 123
Rx 10
Tx 10
Rx 11
Tx 11
VF 0 VF 1 VF 15
. . .
VF Queues
Rx 6
Tx 6
Rx 7
Tx 7
VFIVAR 3
HW Queeus VF Queues
VFIVAR 3
HW Queeus VF Queues
. . .
VFIVAR 3
VF Queues
Rx 4
Tx 4
Rx 5
Tx 5
Rx 6
Tx 6
Rx 7
Tx 7
Rx 4
Tx 4
Rx 5
Tx 5
Rx 12
Tx 12
Rx 13
Tx 13
Rx 124
Tx 124
Rx 125
Tx 125
Rx 126
Tx 126
Rx 127
Tx 127
Rx 14
Tx 14
Rx 15
Tx 15
Rx 0
Tx 0
Rx 1
Tx 1
Rx 2
Tx 2
Rx 3
Tx 3
Rx 4
Tx 4
Rx 5
Tx 5
Rx 6
Tx 6
Rx 7
Tx 7
Rx 0
Tx 0
Rx 1
Tx 1
Rx 2
Tx 2
Rx 3
Tx 3
Rx 4
Tx 4
Rx 5
Tx 5
Rx 6
Tx 6
Rx 7
Tx 7

319
7. 3.4. 3.3 MSI - X Vect or s Mappi ng t o EI TR
EI TR regist ers are aimed for Tx and Rx int errupt t hrot t ling. I n I OV mode, t he Tx and Rx queues might
belong t o eit her t he PF or t o t he VFs. EI TR( 1. . .63) are mult iplexed bet ween t he PF and t he VFs as
configured by t he EI TRSEL regist er. Figure 7. 28 and Table 7. 45 show t he mult iplexing logic and
required soft ware set t ings. For any act ive VF ( st art ing from VF32 and above) , soft ware should program
t he mat ching bit in t he EI TRSEL t o 1b. For any EI TR t hat belongs t o a VF, soft ware should not map any
int errupt causes in t he PF t o an MSI -X vect or t hat is associat ed wit h t he same EI TR regist er.
Fi gur e 7. 28. PF / VF MSI - X Vect or s Mappi ng t o EI TR
Tabl e 7. 45. PF / VF MSI - X Vect or s Mappi ng Tabl e t o EI TR Regi st er s
VM Act i v e EI TRSEL. N Set t i ng MSI - X Rout i ng t o EI TR
Non- I OV or VF( 32. . . 63) inact ive EI TRSEL must be set t o 0x0000 MSI -X( 1. . . 63) - > EI TR( 1. . . 63)
VF( 32) act ive EI TRSEL[ 0] must be set t o 1b VF( 32) MSI -X( 0) - > EI TR( 63)
VF( 33) act ive EI TRSEL[ 1] must be set t o 1b
VF( 33) MSI -X( 1) - > EI TR( 62) VF( 33) MSI -X( 0)
- > EI TR( 61)
VF( 34) MSI -X( 1) - > EI TR( 60) VF( 34) MSI -X( 0)
- > EI TR( 59)
MSI-X 0
MSI-X 1
MSI-X 2
MSI-X 62
MSI-X 63
PF
Vectors
EITR 1
EITR 63
EITR 2
EITR 128
EITR 127
EITR 0
EITR 64
PF EITR
Registers
VF EITR
Registers
EITR 0
EITR 0
EITR 1
EITR 1
EITR 0
EITR 1
VF 0
VF 32
VF 63
Sel
EITRSEL
MSI-X 2 on each VF has no associated EITR register. It is useful
for the mailbox interrupts that do not require interrupt moderation.
EITR 66
EITR 65
EITR 1
EITR 0
VF 31
. . .
VF 0
MSI-X 0
MSI-X 1
MSI-X 2
VF 31
MSI-X 0
MSI-X 1
MSI-X 2
VF 32
MSI-X 0
MSI-X 1
MSI-X 2
. . .
VF 63
MSI-X 0
MSI-X 1
MSI-X 2
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320
7.4 802.1q VLAN Suppor t
The 82599 provides several specific mechanisms t o support 802. 1q VLANs:
Opt ional adding ( for t ransmit s) and st ripping ( for receives) of I EEE 802. 1q VLAN t ags.
Opt ional abilit y t o filt er packet s belonging t o cert ain 802. 1q VLANs.
7.4.1 802.1q VLAN Pack et For mat
The following t able compares an unt agged 802. 3 Et hernet packet wit h an 802. 1q VLAN t agged packet :
Not e: The CRC for t he 802. 1q t agged frame is re- comput ed, so t hat it covers t he ent ire t agged
frame including t he 802. 1q t ag header. Also, maximum frame size for an 802. 1q VLAN packet
is 1522 oct et s as opposed t o 1518 oct et s for a normal 802. 3z Et hernet packet .
7.4.2 802.1q Tagged Fr ames
For 802. 1q, t he Tag Header field consist s of four oct et s comprised of t he Tag Prot ocol I dent ifier ( TPI D)
and Tag Cont rol I nformat ion ( TCI ) ; each t aking t wo oct et s. The first 16 bit s of t he t ag header makes up
t he TPI D. I t cont ains t he prot ocol t ype t hat ident ifies t he packet as a valid 802. 1q t agged packet .
The t wo oct et s making up t he TCI cont ain t hree fields as follows:
User Priorit y ( UP)
Canonical Form I ndicat or ( CFI ) . Should be set t o 0b for t ransmit s. For receives, t he device has t he
capabilit y t o filt er out packet s t hat have t his bit set . See t he CFI EN and CFI bit s in t he VLNCTRL
VLAN I dent ifier ( VI D)
. . .
VF( 62) MSI -X( 1) - > EI TR( 4) VF( 62) MSI -X( 0) -
> EI TR( 3)
VF( 63) MSI -X( 1) - > EI TR( 2) VF( 63) MSI -X( 0) -
> EI TR( 1)
802. 3 Pack et # Oct et s
802. 1q VLAN
Pack et
# Oct et s
DA 6 DA 6
SA 6 SA 6
Type/ Lengt h 2 802. 1q Tag 4
Dat a 46- 1500 Type/ Lengt h 2
CRC 4 Dat a 46- 1500
CRC* 4
Oct et 1 Oct et 2
UP CFI VI D
Tabl e 7.45. PF / VF MSI - X Vect or s Mappi ng Tabl e t o EI TR Regi st er s

321
7.4.3 Tr ansmi t t i ng and Recei v i ng 802.1q Pack et s
Since t he 802. 1q t ag is only four byt es, adding and st ripping of t ags can be done complet ely in
soft ware. ( I n ot her words, for t ransmit s, soft ware insert s t he t ag int o packet dat a before it builds t he
t ransmit descript or list , and for receives, soft ware st rips t he 4- byt e t ag from t he packet dat a before
delivering t he packet t o upper layer soft ware) . However, because adding and st ripping of t ags in
soft ware adds overhead for t he host , t he 82599 has addit ional capabilit ies t o add and st rip t ags in
hardware. See Sect ion 7. 4. 3. 1 and Sect ion 7. 4. 3. 2.
7.4.3.1 Addi ng 802.1q Tags on Tr ansmi t s
Soft ware might inst ruct t he 82599 t o insert an 802. 1q VLAN t ag on a per- packet basis. I f t he VLE bit in
t he t ransmit descript or is set t o 1b, t hen t he 82599 insert s a VLAN t ag int o t he packet t hat it t ransmit s
over t he wire. The Tag Prot ocol I dent ifier TPI D ( VLAN Et her Type) field of t he 802. 1q t ag comes
from t he DMATXCTL. VT, and t he Tag Cont rol I nformat ion ( TCI ) of t he 802. 1q t ag comes from t he VLAN
field of t he legacy t ransmit descript or or t he VLAN Tag field of t he advanced dat a t ransmit descript or.
7.4.3.2 St r i ppi ng 802.1q Tags on Recei v es
Soft ware might inst ruct t he 82599 t o st rip 802. 1q VLAN t ags from received packet s. The policy whet her
t o st rip t he VLAN t ag is configurable per queue.
I f t he RXDCTL. VME bit for a given queue is set t o 1b, and t he incoming packet is an 802. 1q VLAN
packet ( t hat is, it s Et hernet Type field mat ched t he VLNCTRL.VET) , t hen t he 82599 st rips t he 4- byt e
VLAN t ag from t he packet , and st ores t he TCI in t he VLAN Tag field of t he receive descript or.
The 82599 also set s t he VP bit in t he receive descript or t o indicat e t hat t he packet had a VLAN t ag t hat
was st ripped. I f t he RXDCTL. VME bit is not set , t he 802. 1q packet s can st ill be received if t hey pass t he
receive filt er, but t he VLAN t ag is not st ripped and t he VP bit is not set .
7.4.4 802.1q VLAN Pack et Fi l t er i ng
VLAN filt ering is enabled by set t ing t he VLNCTRL. VFE bit t o 1b. I f enabled, hardware compares t he Type
field of t he incoming packet t o a 16- bit field in t he VLAN Et her Type ( VET) regist er. I f t he VLAN Type
field in t he incoming packet mat ches t he VET regist er, t he packet is t hen compared against t he VLAN
Filt er Table Array for accept ance.
The VLAN filt er regist er VTFA, is a vect or array composed of 4096 bit s. The VLAN I D ( VI D) is a 12- bit
field in t he VLAN t ag t hat is used as an index point er t o t his vect or. I f t he VI D in a received packet
point s t o an act ive bit ( set t o 1b) , t he packet mat ches t he VLAN filt er. The 4096- bit vect or is comprised
of 128 x 32 bit regist ers. The upper 7 bit s of t he VI D select s one of t he 128 regist ers while t he lower 5
bit s map t he bit wit hin t he select ed regist er.
Two ot her bit s in t he VLNCTRL regist er, CFI EN and CFI , are also used in conj unct ion wit h 802. 1q VLAN
filt ering operat ions. CFI EN enables t he comparison of t he value of t he CFI bit in t he 802. 1q packet t o
t he Receive Cont rol regist er CFI bit as accept ance crit eria for t he packet .
Not e: The VFE bit does not effect whet her t he VLAN t ag is st ripped. I t only effect s whet her t he
VLAN packet passes t he receive filt er.
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7.4.5 Doubl e VLAN and Si ngl e VLAN Suppor t
The 82599 support s a mode where all received and sent packet s have at least one VLAN t ag in addit ion
t o t he regular t agging t hat might opt ionally be added. I n t his document , when a packet carries t wo
VLAN headers, t he first header is referred t o as an out er VLAN and t he second header as an inner VLAN
header ( as list ed in t he t able t hat follows) . This mode is used for syst ems where t he near end swit ch
adds t he out er VLAN header cont aining swit ching informat ion. This mode is enabled by t he following
configurat ion:
This mode is act ivat ed by set t ing t he DMATXCTL. GDV and t he Ext ended VLAN bit in t he CTRL_EXT
regist er.
The Et hert ype of t he VLAN t ag used for t he addit ional VLAN is defined in t he VET EXT field in t he
EXVET regist er.
Cr oss f unct i onal i t y w i t h Manageabi l i t y
The 82599 does not provide any st ripping or adding VLAN header( s) t o manageabilit y packet s.
Therefore, packet s t hat are direct ed t o/ from t he manageabilit y cont roller should include t he VLAN
headers as part of t he Rx/ Tx dat a. The manageabilit y cont roller should know if t he 82599 is set t o
double VLAN mode as well as t he VLAN Et hert ype( s) . When operat ing in a double VLAN mode, cont rol
packet s sent by t he manageabilit y cont roller wit h no VLAN headers should not act ivat e any hardware
offload ot her t han LinkSec encapsulat ion.
Tr ansmi t f unct i onal i t y on t he out er VLAN header
A packet wit h a single VLAN header is assumed t o have only t he out er VLAN.
The out er VLAN header must be added by soft ware as part of t he Tx dat a buffers.
Hardware does not relat e t o t he out er VLAN header ot her t han t he capabilit y of skipping it for
parsing inner fields.
Hardware expect s t hat any t ransmit t ed packet ( see t he disclaimer t hat follows) has at least t he
out er VLAN added by soft ware. For any offload t hat hardware might provide in t he t ransmit dat a
pat h, hardware assumes t hat t he out er VLAN is present . For t hose packet s t hat an out er VLAN is
not present , any offload t hat relat es t o inner fields t o t he Et hert ype might not be provided.
Tr ansmi t f unct i onal i t y on t he i nner VLAN header
The inner VLAN header can be added by soft ware in one of t he following met hods:
The header is included in t he t ransmit dat a buffers.
The 16- bit port ion of t he header t hat includes t he priorit y t ag, CFI and VLAN I D are included in
t he t ransmit descript or. The VLAN Et hert ype is t aken from t he VT field in t he DMATXCTL
regist er.
I n I OV mode, t he priorit y t ag, CFI and VLAN I D can be t aken from t he PFVMVI R ( see det ails in
Sect ion 7. 10. 3. 9. 2)
Hardware ident ifies and skips t he VLAN header for parsing inner fields.
DCB The user priorit y of t he packet is t aken from t he inner VLAN. The t raffic class is dict at ed by
t he Tx queue.
Tabl e 7.46. Tr ansmi t Handl i ng of Pack et s w i t h VLAN Header ( s)
MAC
Addr ess
Out er
VLAN
I nner
VLAN
L2 Pay l oad
Et her net
CRC

323
Pool Filt ering Dest inat ion pool( s) and ant i- spoofing funct ionalit y is based on t he Et hernet MAC
address and inner VLAN ( if present ) as described in Sect ion 7.10.3.4 and Sect ion 7. 10. 3.9. 2.
7.4.5.1 Recei v e Handl i ng of Pack et s w i t h VLAN Header ( s)
Recei ve f unct i onal i t y on t he out er VLAN header
I f t he packet carries a single VLAN header, it is assumed as t he out er header and is t reat ed as such.
Hardware checks t he Et hert ype of t he out er VLAN header against t he programmed value in t he
EXVET regist er. VLAN header presence is indicat ed in t he St at us. VEXT bit in t he Rx descript or. I n
t he case of mismat ch, t he packet is handled as unknown packet t ype at which t ime hardware does
not provide any offloads ot her t han LinkSec processing. Also, hardware skips t he header for parsing
inner fields and provides any support ed offload funct ions.
The out er VLAN header is post ed as is t o t he receive dat a buffers.
Recei ve f unct i onal i t y on t he i nner VLAN header
Hardware checks t he Et hert ype of t he inner VLAN header against t he programmed value in t he
VLNCTRL. VET. VLAN header presence is indicat ed in t he St at us. VP bit in t he Rx descript or.
I f t he RXDCTL. VME is set , t he inner VLAN is st ripped by hardware while t he priorit y t ag, CFI and
VLAN I D are indicat ed in t he VLAN Tag field in t he Rx descript or.
Hardware ident ifies and skips t he VLAN header for parsing inner fields and provides any support ed
offload funct ions.
L2 packet filt ering is based on t he VLAN I D in t he inner VLAN header.
Pool Filt ering Dest inat ion pool( s) are defined by t he Et hernet MAC address and inner VLAN ( if
presence) as described in Sect ion 7. 10. 3. 3.
DCB The user priorit y of t he packet is t aken from t he inner VLAN. I n t he absence of inner VLAN,
t he packet is assumed as user priorit y 0 ( least priorit y) . See Sect ion 7.4. 5. 2 for t he absence of any
VLAN headers.
7.4.5.2 Pack et s w i t h no VLAN header s i n Doubl e VLAN Mode
There are some cases when packet s might not carry any VLAN headers, even when ext ended VLAN is
enabled. A few examples for packet s t hat might not carry any VLAN header are: flow cont rol and
priorit y flow cont rol, LACP, LLDP, GMRP, and opt ional 802. 1x packet s. When it is expect ed t o t ransmit
unt agged packet s by soft ware in double VLAN mode t he soft ware must not enable VLAN ant i- spoofing
and VLAN validat ion nor t ransmit t o receive swit ching.
Tr ansmi t t ed f unct i onal i t y
DCB The t raffic class in t he Tx dat a pat h is direct ed by t he Tx queue of t he t ransmit t ed packet .
Transmit offload funct ionalit y Soft ware should not enable any offload funct ions ot her t han LinkSec.
Recei ve f unct i onal i t y
DCB Assume user priorit y 0 ( lowest priorit y) .
Receive offload funct ionalit y pool and queue are select ed by t he Et hernet MAC address or ETQF/
ETQS regist ers. LinkSec offload is funct ional. Filt ering t o host and manageabilit y remains funct ional.
The Ext ended VLAN bit in t he CTRL_EXT regist er and DMATXCTL. GDV are not set . Hardware expect s
t hat Rx and Tx packet s might not carry a VLAN header or a single VLAN header. Hardware does not
relat e t o t he programming of t he VET EXT field in t he EXVET regist er. Tx and Rx handling of packet s
wit h double VLAN headers is unexpect ed.
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7. 4. 5. 3 Pack et Pr i or i t y i n Si ngl e and Doubl e VLAN Modes
This sect ion summarizes packet handling in bot h single and double VLAN modes. The user priorit y of a
packet is meaningful in DCB mode when mult iple t raffic classes are enabled as well as LLI s. The user
priorit y is ext ract ed from t he packet s as list ed in t he following t able.
7.5 Di r ect Cache Access ( DCA)
DCA is a met hod t o improve net work I / O performance by placing some post ed inbound writ es direct ly
wit hin CPU cache. DCA pot ent ially eliminat es cache misses due t o inbound writ es.
As Figure 7. 29 illust rat es, DCA provides a mechanism where t he post ed writ e dat a from an I / O device,
such as an Et hernet NI C, can be placed int o CPU cache wit h a hardware prefet ch. This mechanism is
init ialized upon a power good reset . A device driver for t he I / O device configures t he I / O device for DCA
and set s up t he appropriat e CPU I D and bus I D for t he device t o send dat a. The device t hen
encapsulat es t hat informat ion in PCI e TLP headers, in t he t ag field, t o t rigger a hardware prefet ch t o
t he CPU cache.
DCA implement at ion is cont rolled by separat e regist ers ( DCA_RXCTRL and DCA_TXCTRL) for each
t ransmit and receive queue. I n addit ion, a DCA disable bit can be found in t he DCA_CTRL regist er, and
a DCA_I D regist er can be found for each port , in order t o make t he funct ion, device, and bus numbers
visible t o t he driver.
Tabl e 7.47. Pack et Handl i ng i n Si ngl e and Doubl e VLAN Modes
Pack et t y pe Si ngl e VLAN Doubl e VLAN
Packet wit h no VLAN User priorit y = 0 User priorit y = 0
Packet wit h 1 VLAN
The user priorit y field in t he VLAN header in t he
packet
User priorit y = 0
Packet wit h 2 VLANs
Erroneous case: The user priorit y field in t he
out er VLAN header in t he packet
The user priorit y field in t he i nner VLAN
header in t he packet
Fi gur e 7.29. Di agr am of DCA I mpl ement at i on on FSB Syst em

CPU
Cache
Memory
NIC
MCH
D DM MA A W Wr ri it te e
B BI IL L- -D DC CA A
M Me em mo or ry y W Wr ri it te e
D DC CA A
t tr ri ig gg ge er re ed d
H HW W
P Pr re ef fe et tc ch h
C CP PU U d de em ma an nd d r re ea ad d

325
The DCA_RXCTRL and DCA_TXCTRL regist ers can be writ t en by soft ware on t he fly and can be changed
at any t ime. When soft ware changes t he regist er cont ent s, hardware applies changes only aft er all t he
previous packet s in progress for DCA have complet ed.
However, in order t o implement DCA, t he 82599 has t o be aware of t he I OAT version used. The
soft ware driver init ializes t he 82599 t o be aware of t he bus configurat ion. The DCA Mode field in t he
DCA_CTRL regist er defines t he syst em configurat ion:
1. Legacy DCA: The DCA t arget I D is derived from CPU I D.
2. DCA 1.0: The DCA t arget I D is derived from API C I D.
Bot h modes are described as follows.
7. 5. 1 PCI e TLP For mat f or DCA
Figure 7.30 shows t he format of t he PCI e TLP for DCA.
The DCA preferences field has t he following format s.
For legacy DCA syst ems:
Fi gur e 7. 30. PCI e Message For mat f or DCA
Bi t s Name Descr i pt i on
0 DCA indicat ion
0b = DCA disabled.
1b = DCA enabled.
4: 1 DCA t arget I D The DCA t arget I D specifies t he t arget cache for t he dat a.
TLP digest
Length specific data
Length specific data
Address [32:2] R
Address [63:32]
Requester ID DCA Preferences Last DW BE First DW BE
R
Fmt=
11
Type=00000b R TC Rsv
T
D
E
P
Attr R Length
+0
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
+1 +2 +3
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For DCA 1. 0 syst ems:
Not e: All funct ions wit hin a t he 82599 have t o adhere t o t he t ag encoding rules for DCA writ es. Even
if a given funct ion is not capable of DCA, but ot her funct ions are capable of DCA, memory
writ es from t he non- DCA funct ion must set t he t ag field t o 00000000b.
7.6 LEDs
The 82599 implement s four out put drivers int ended for driving ext ernal LED circuit s per port . Each of
t he four LED out put s can be individually configured t o select t he part icular event , st at e, or act ivit y,
which is indicat ed on t hat out put . I n addit ion, each LED can be individually configured for out put
polarit y as well as for blinking versus non- blinking ( st eady- st at e) indicat ion.
The configurat ion for LED out put s is specified via t he LEDCTL Regist er. Furt hermore, t he hardware-
default configurat ion for all LED out put s can be specified via EEPROM fields t hereby support ing LED
displays configurable t o a part icular OEM preference.
Each of t he four LED' s can be configured t o use one of a variet y of sources for out put indicat ion. For
more informat ion on t he MODE bit s see LEDCTL regist er ( see Sect ion 8. 2. 3.1.5) .
The I VRT bit s enable t he LED source t o be invert ed before being out put or observed by t he blink- cont rol
logic. LED out put s are assumed t o normally be connect ed t o t he negat ive side ( cat hode) of an ext ernal
LED.
The BLI NK bit s cont rol whet her t he LED should be blinked ( on for 200 ms, t hen off for 200 ms) while
t he LED source is assert ed. The blink cont rol can be especially useful for ensuring t hat cert ain event s,
such as ACTI VI TY indicat ion, cause LED t ransit ions, which are sufficient ly visible by a human eye.
Not e: The LI NK/ ACTI VI TY source funct ions slight ly different from t he ot hers when BLI NK is enabled.
The LED is:
Off if t here is no LI NK
On if t here is LI NK and no ACTI VI TY
Blinks if t here is LI NK and ACTI VI TY
Bi t s Name Descr i pt i on
7: 0 DCA t arget I D
0000. 0000b: DCA is disabled.
Ot her: Target core I D derived from API C I D. 25915

327
7. 7 Dat a Cent er Br i dgi ng ( DCB)
See Sect ion 4. 6. 11 for t he DCB configurat ion sequence and Sect ion 11. 5 for t he expect ed performance
of DCB funct ionalit y.
7.7.1 Ov er v i ew
DCB is a set of feat ures t hat improve t he capabilit y of Et hernet t o handle mult iple t raffic t ypes ( such as
LAN, st orage, I PC) by answering t he various needs of t hose t ypes. DCB enables mult iple t raffic t ypes
t hat have different requirement s of packet delivery, bandwidt h allocat ion and delay. Each t raffic t ype
can have one or several user priorit ies, or Traffic Classes ( TCs) . For example, I PC might have a high
priorit y class for synchronizat ion messages bet ween servers and lower priorit y t raffic class for bulk
t raffic exchange bet ween servers. Most of t he DCB funct ions impact t he t ransmit t raffic generat ed from
t he end node t o t he net work ( t raffic generat ion) . The receive dat a pat h needs be compliant wit h t he
requirement s of DCB and provide t he required funct ions as a t raffic t erminat ion point .
DCB syst em requirement s include:
1. Bandwidt h grouping For effect ive mult iplexing t hat simulat es a separat e link for t he separat e
t ypes of t raffic, DCB requires t hat t raffic t ypes be recognized as groups in t he bandwidt h and
priorit y handling by nodes in t he net work. Traffic t ypes are associat ed t o Bandwidt h Groups
( BWGs) . The syst em needs t o be able t o allocat e bandwidt h t o t he BWGs in a way t hat emulat es
t hat group being on it s own separat e link.
2. Bandwidt h fairness DCB mult iplexing funct ions ( t ransmit ) and de- mult iplexing funct ions
( receive) need t o guarant ee minimum allocat ion of bandwidt h t o t raffic t ypes and t raffic classes.
Fairness bet ween groups comes first , t hen fairness bet ween TCs. I f syst em resources ( such as PCI e
bandwidt h) limit t ot al t hroughput , t hen t he available bandwidt h should be dist ribut ed among
consumers proport ionally t o t heir allocat ions.
3. Lat ency of operat ion DCB mult iplexing and de- mult iplexing funct ions need t o allow minimum
lat ency for some TCs. Arbit rat ion mechanisms, packet buffers, descript or queues and flow cont rol
algorit hm need t o be defined and designed t o allow t his. The best example is t he cont rol/ sync
t raffic in I PC. The expect at ion for end- t o- end I PC cont rol is measured in t he low 10' s of s for t he
82599 and is expect ed t o drop t o a singe digit s lat er. Some element s in mult imedia t raffic also
bear similar requirement s. Alt hough some of t he end- t o- end delays can be quit e long, t he
individual cont ribut ion of t he arbit rat ion in each node must be kept t o a minimal. End- t o- end
budget s do not comprehend large delays wit hin t ransmission nodes.
4. No- drop behavior and net work congest ion management The end node must be able t o guarant ee
no- drop behavior for some TCs or some packet s wit hin TCs. As a t erminat ion point in receive, it is
t he end nodes responsibilit y t o properly cont rol t raffic coming from t he net work t o achieve t his
end. For t raffic generat ion in t ransmit , t he end st at ion must be able t o posit ively respond t o flow
cont rol from t he net work as t he must have t ool t o prevent packet drop. I t also needs t o part icipat e
in net work congest ion management .
5. Compat ibilit y wit h exist ing syst ems. The DCB implement at ion needs t o be usable by I T using
known configurat ions and paramet ers, unless new ones are made expressly available. For example,
DCB implement at ion cannot assume new knowledge regarding bandwidt h allocat ion of t raffic t ypes
t hat do not have known bandwidt h requirement s.
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The layer 2 feat ures of DCB implement ed in t he 82599 are:
1. Mult i- class priorit y arbit rat ion and scheduling The 82599 implement s an arbit rat ion mechanism
on it s t ransmit dat a pat h. The arbit rat ion mechanism allocat es bandwidt h bet ween TC in BWGs and
bet ween Virt ual Machines ( VMs) or Virt ual Funct ions ( VFs) in a virt ualizat ion environment . The
BWGs can be used t o cont rol bandwidt h and priorit y allocat ed t o t raffic t ypes. Typically BWGs
should be used t o represent t raffic t ypes. TC arbit rat ion allows cont rol of bandwidt h and priorit y
cont rol wit hin BWGs as well as wit hin t he ent ire link bandwidt h. The arbit rat ion is designed t o
respect t he bandwidt h allocat ions t o BWGs. The priorit y allocat ion allows minimizat ion of delay for
specific TCs. I n t he 82599, TCs and user priorit ies are processed on a packet - by- packet basis based
on t he 802. 1p ident ifier in t he 802. 1Q- t ag.
2. Class- based flow cont rol ( PFC Priorit y Flow Cont rol) Class- based flow cont rol funct ionalit y is
similar t o t he I EEE802. 3X link flow cont rol. I t is applied separat ely t o t he different TCs.
Transmit response t o class- based flow cont rol from t he ingress swit ch it is connect ed t o.
Receive class- based flow cont rol commands t o t he swit ch in response t o packet buffers filling
st at us.
3. DMA queuing per t raffic t ype I mplement at ion of t he DCB t ransmit , minimizat ion of soft ware
processing and delays require implement at ion of separat e DMA queues for t he different t raffic
t ypes. The 82599 implement s 128 descript or queue in t ransmit and 128 descript or queues in
receive.
4. Mult iple Buffers The 82599 implement s separat e t ransmit and receive packet buffers per TC.
5. Rat e- limit er per Tx queue limit ing t he t ransmit dat a rat e for each Tx queue.
Lat ency requirement s:
Quant it at ive lat ency requirement s are defined for a single 64- byt e packet at t he highest priorit y t raffic
class. Lat ency is defined separat ely for t ransmit and receive:
Transmit lat ency measured from a t ail updat e unt il t he packet is t ransmit t ed on t he wire. I t is
assumed t hat a single packet is submit t ed for t his TC and it s lat ency is t hen measured in t he
presence of t raffic belonging t o ot her TCs.
Receive lat ency measured from packet recept ion from t he wire and unt il t he descript or is
updat ed on PCI e.

329
Figure 7.31 shows t he lat ency requirement s as previously defined.
Not e: I n DCB mode, it is assumed all t raffic is t agged ( cont ains a VLAN header) except for Layer2
frames wit h special Et hernet MAC addresses t hat goes unt agged. GMRP frames ( special
Et hernet MAC addresses st art ing wit h 0x0180c20000) must , however, go t agged. Unt agged
packet s must be delivered t o t he host and are assumed t o belong t o User Priorit y 7.
Not e t hat any BCN signaling is t erminat ed at t he net work' s edge. At init ializat ion, every component
exchanges it s capabilit ies wit h it s peer via a Capabilit y Exchange ( DCX) prot ocol carried over dedicat ed
Link Layer Discovery Prot ocol ( LLDP) frames. Support for t hese prot ocols is t ransparent t o t he hardware
implement at ion, and as a result , is not described in t his document .
7. 7. 2 Tr ansmi t - si de Capabi l i t i es
Not e: When configured for DCB mode, t he t he 82599 driver should only use advanced t ransmit
descript ors. Refer t o Sect ion 7. 2. 3. 2.3. Using legacy t ransmit descript ors is not allowed.
Fi gur e 7. 31. Lat ency Requi r ement s
0
5
10
15
20
25
30
35
40
0 5000 10000 15000 20000 25000 30000 35000
Segment Size (Bytes)
L
a
t
e
n
c
y

(
u
s
e
c
)
Transmit
Receive
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7. 7. 2. 1 Tr ansmi t Rat e Schedul er ( RS)
7.7.2. 1.1 Basi c Rat e Cont r ol Oper at i on
Rat e cont rol is defined in t erms of maximum payload rat e, and not in t erms of maximum packet rat e.
This means t hat each t ime a rat e cont rolled packet is sent , t he next t ime a new packet can be sent out
of t he same rat e cont rolled queue is relat ive t o t he packet size of t he last packet sent . The minimum
spacing in t ime bet ween t wo st art s of packet s sent from t he same rat e cont rolled queue is recalculat ed
in hardware on every packet again, by using t he following formula:
MI FS = PL x RF
Where:
Packet Lengt h ( PL) , is t he Layer2 lengt h ( such as wit hout preamble and I PG) in byt es of t he
previous packet sent out of t hat rat e cont roller. I t is an int eger ranging from 64 t o 9 K ( at least 14-
bit s) .
RF = 10 Gb/ s / t arget rat e ( rat e fact or) is t he rat io bet ween t he nominal link rat e and t he t arget
maximum rat e t o achieve for t hat rat e- cont rolled queue. I t is dynamically updat ed eit her by
soft ware via t he RTTBCNRC regist er, or by hardware via t he rat e- drift mechanism, as described in
Sect ion 7. 7. 2. 1.2. I t is a decimal number ranging from 1 t o 1, 000 ( 10 Mb/ s minimum t arget rat e) .
For example, at least 10- bit s before t he hexadecimal point and 14- bit s aft er as required for t he
maximum packet lengt h by which it is mult iplied. For links at 1 Gb/ s, t he rat e fact or must be
configured relat ively t o t he link speed, replacing 10 Gb/ s by 1 Gb/ s in t he above formula.
Minimum I nt er Frame Space ( MI FS) is t he minimum delay in byt es unit s, bet ween t he st art ing of
t wo Et hernet frames issued from t he same rat e- cont rolled queue. I t is an int eger ranging from 76
t o 9,216, 012 ( at least 24- bit s) . I n spit e of t he 8- byt e resolut ion provided at t he int ernal dat a pat h,
t he byt e- level resolut ion is required here t o maint ain an accept able rat e resolut ion ( at 1% level) for
t he small packet s case and high rat es.
Not e: I t might be t hat a pipeline implement at ion causes t he MI FS calculat ed on a t ransmit t ed
packet t o be enforced only on t he subsequent t ransmit t ed packet .
Time St amps A rat e- scheduling t able cont ains t he accumulat ed int erval MI FS, for each rat e-
cont rolled descript or queue separat ely, and is st ored as an absolut e Time St amp ( TS) relat ive t o an
int ernal free running t imer. The TS value point s t o t he t ime in t he fut ure at which a next dat a read
request can be sent for t hat queue. Whenever updat ing a TimeSt amp:
Ti meSt amp( new) = TimeSt amp( ol d) + MI FS
When a descript or queue st art s t o be rat e cont rolled, t he first int erval MI FS value is equal t o 0 ( TS
equal t o t he current t imer value) wit hout t aking int o account t he last packet sent prior t o rat e
cont rol. When t he TS value st ored becomes equal t o or smaller t han t he current free running t imer
value, it means t hat t he swit ch is on and t hat t he queue st art s accumulat ing compensat ion t imes from
t he past ( referred as a negat ive TS) . When t he TS value st ored is st rict ly great er t han t he current free
running t imer value, it means t hat t he swit ch is off ( referred as a posit ive TS.
( Cur r ent Ti me) < Ti meSt amp < - - > swi t ch i s of f
( Cur r ent Ti me) > = Ti meSt amp< - - > swi t ch i s on
MMW The abilit y t o accumulat e negat ive compensat ion t imes t hat sat urat es t o a Max Memory
Window ( MMW) t ime backward. MMW size is configured per TC via t he MMW_SI ZE field of t he
RTTBCNMR regist er, and is expressed in 1 KB unit s of payload, ranging from 0 up t o 2 KB unit s ( at least

331
11- bit s) . The MMW_SI ZE configured in KB unit s of payload has t o be convert ed in t ime int erval
MMW_TI ME expressed in KB, before a new t ime st amp is checked for sat urat ion. I t is comput ed for
each queue according t o it s associat ed Rat e Fact or ( RF) using t he following formula:
MMW_TI ME = MMW_SI ZE x RF
Not e: MMW_TI ME is rounded by default t o a 1 KB precision level and must be at least 31 bit s long.
Hence, t he t ime st amp byt e- level values st ored must be at least 32- bit s long for properly
handling t he wrap- around case. 29- bit s are required for t he int ernal free running t imer
clocked once every 8 byt es.
Whenever updat ing a t ime st amp verify:
Ti meSt amp( ol d) + MI FS > = ( Cur r ent Ti me) MMW_TI ME
and t hen t he t ime st amp is updat ed according t o t he non- sat urat ed formula:
Ti meSt amp( new) = Ti meSt amp( ol d) + MI FS
Ot herwise, enforced sat urat ion by assigning:
Ti meSt amp( new) = ( Cur r ent Ti me) MMW_TI ME + MI FS
Not e: Non- null MMW int roduces some flexibilit y in t he way cont rolled rat es are enforced. I t is
required t o avoid overall t hroughput losses and unfairness caused by rat e- cont rolled packet s
over- delayed, consequent ly t o packet s insert ed in bet ween. Bet ween t wo rat e- limit ed packet s
spaced by at least t he MI FS int erval, non- rat e- limit ed packet s, or rat e- limit ed packet s from
ot her rat e- cont rolled queues, might be insert ed. I f a rat e cont rolled packet has been delayed
by more t ime t han it was required for rat e cont rol ( because of arbit rat ion bet ween VMs or
TCs) , t he next MI FS accumulat es from t he last t ime t he queue was swit ched on by t he rat e
scheduling t able and not from t he current t ime. Refer t o Figure 7. 32 for visualizing t he
effect of MMW.
MMW_SI ZE set t o 0 must be support ed as well.
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7.7.2. 1.2 Rat e Dr i f t
Periodically, at fixed int ervals in t ime, t he rat e fact ors of all rat e- cont rolled queues must be increased
int ernally by a small amount . The periodic int erval in t ime at which rat e drift mechanism is t riggered is
configured via t he DRI FT_I NT field in RTTBCNRD regist er. t he rat e- drift mechanism done in hardware is
enabled by set t ing t he DRI FT_ENA bit in RTTBCNRD regist er; ot herwise, it is assumed t hat it is handled
by soft ware.
The rat e- drift mechanism is essent ial for fairness and rat e recovery of rat e- cont rolled flows reduced t o
very low rat es.
Not e: For providing accurat e rat e- drift int ervals, t he rat e- drift mechanism must be st art ed
immediat ely once t he int erval in t ime has elapsed wit hout wait ing for t he next t ime st amp
t able scan cycle t o st art .
Fi gur e 7.32. Mi ni mum I nt er - Fr ame Spaci ng f or Rat e- Cont r ol l ed Fr ames ( i n Or ange)
P1
MIFS1
P2
MIFS2
P3
MIFS3
P4
MMW_TIME from P4
MIFS4
PL3 PL2 PL1 PL4 time
MIFS accumulation cannot result in a time
point older than MMW_TIME backward
MMW_TIME from P3
MMW_TIME from P2
P1
MIFS1
P2
MIFS2
P3
MIFS3
P4
MIFS4
C - Non-null Max Memory Window (MMW):
B - Unlimited Memory Window (or infinite Memory Window):
P1
MIFS1
P2
MIFS2
P3
MIFS3
P4
MIFS4
Time from which
P2 can be sent
Packet from other DQs inserted
because DQ or DCB arbitration
Time from which
P3 can be sent
Time from which
P4 can be sent
Time from which
P5 can be sent
A - No Memory Window:
MIFS4

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Rat es are increased in a mult iplicat ive manner, by mult iplying t he rat es wit h a fixed value slight ly
great er t han unit y. I t is t hus similar t o mult iplying t he rat e fact ors by a fixed value slight ly smaller t han
unit y, which is referred t o as t he drift fact or. I t is configured via t he DRI FT_FAC field in RTTBCNRD
regist er. The rat e- drift mechanism sat urat es if t he full line rat e has been recovered ( when t he rat e
fact or has been decreased down t o unit y) :
Rat e- Fact or ( new) = max( 1, Rat e- Fact or ( ol d) x Dr i f t - Fact or )
For example, if a periodic rat e increase of 3% is desired, t hen a drift fact or of 1/ 1. 03= 0. 97087. . . must
be configured.
Not e: One disadvant age of t he mult iplicat ive rat e increase met hod result s in smaller increases for
low- rat ed flows and larger increases for high- rat ed flows. An addit ive met hod has been
envisaged inst ead, increasing t he rat e fact ors by small addit ive st eps on each int erval, but it
has been dropped off because it had poor chances of being st andardized by I EEE 802. 1au.
A queue t hat has recovered t he full line rat e via t he rat e- drift mechanism ( rat e fact or
decreased down t o one) is not considered as a rat e- cont rolled queue, it s corresponding
RS_ENA bit in t he RTTBCNRC regist er must be int ernally self- cleared, and it should st op
t agging it s frames wit h t he RLT opt ion. Refer t o Sect ion 7. 7. 2. 1 for furt her det ails on CM-
t agging.
7.7.2.2 User Pr i or i t y t o Tr af f i c Cl ass Mappi ng
DCB- enabled soft ware is responsible for classifying any Tx packet int o one of t he eight 802. 1p user
priorit ies, and t o assure it is t agged accordingly by eit her soft ware or hardware. The driver dispat ches
classified Tx t raffic int o t he Tx queues at t ached t o t he proper TC, according t o a UP- t o-TC Tx mapping
policy decided by t he I T manager.
Not e: When configured for DCB mode or when using t he Tx rat e- limit ing funct ionalit y, t he 82599
soft ware driver should only use advanced t ransmit descript ors. Refer t o Sect ion 7. 2. 3.2. 3. DO
NOT use legacy t ransmit descript ors.
Caut i on: When t ranslat ing XON/ XOFF priorit y flow cont rol commands defined per UP int o commands t o
t he Tx packet buffers, t he 82599 is required t o use t he same UP- t o-TC Tx mapping t able t hat
soft ware is using. The RTTUP2TC regist er must be configured by soft ware accordingly. Refer
t o Sect ion 3. 7. 7. 1.3 for det ails on priorit y flow cont rol.
7.7. 2.3 VM- Wei ght ed Round- Robi n Ar bi t er s
The 82599 implement s VM- weight ed arbit er( s) for virt ualized environment s and according t o t he
following case:
I f DCB is enabled, t here is one such arbit er per TC, arbit rat ing bet ween t he descript or queues
at t ached t o t he TC ( one queue per VF) . Bandwidt h allocat ion t o VMs is enforced at t he descript or
plane, per each TC separat ely. The VM arbit er inst ant iat ed for each TC is aimed t o elect t he next
queue for which a dat a read request is sent in case t he TC is elect ed for t ransmission by t he next
level arbit er. For example, t he TC weight ed st rict priorit y descript or plane arbit er.
I f DCB is disabled, t here is one single VM weight ed arbit er, arbit rat ing bet ween pools of descript or
queues, where a pool is formed by t he queues at t ached t o t he same VF. Bandwidt h allocat ion t o
VMs is enforced at t he descript or plane, bet ween t he pools, where queues wit hin a pool are served
on a frame- by- frame round- robin manner.
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Refer t o t he different arbit rat ion schemes where virt ualizat ion is enabled, as shown in Figure 7. 17.
Not e: I n t his sect ion, VM is considered a generic t erm used t o refer t o t he arbit rat ed ent it y, whet her
it is a Tx descript or queue wit hin t he TC or whet her it is a pool of Tx descript or queues. I n t he
lat er case, pool paramet ers are allocat ed only t o t he lowest indexed queue wit hin t he pool,
t aken as t he represent at ion of t he ent ire pool.
7.7.2. 3.1 Def i ni t i on and Descr i pt i on of Par amet er s
Cr edi t s: Credit s regulat e t he bandwidt h allocat ed t o VMs. As part of t he Weight ed Round Robin ( WRR)
algorit hm, each VM has pre- allocat ed credit s. They are decrement ed upon each t ransmission and
replenished cyclically. The rat io bet ween t he credit s of t he VMs represent s t he relat ive bandwidt h
percent age allocat ed t o each VM ( wit hin t he TC for t he DCB enabled case) . The 82599 effect ively
maint ains one t able t hat represent s t hese rat ios. Not e t hat credit s can get negat ive values down t o t he
maximum sized frame allowed on t he TC/ pool.
Not e: The absolut e value of t he credit s has no direct bearing on t he allocat ion of bandwidt h. The
rat io bet ween t he credit s does. However, since credit s can accumulat e only up t o t wice t he
credit refills, t he refills should be allocat ed as low as possible but must be set great er t han
t he maximum sized frame allowed on t he TC or on t he pool.
WRR: The algorit hm implement ed in t he 82599 for VM arbit rat ion.
Table 7. 48 ( T1) defines t he VMs and t heir bandwidt h allocat ion. The following element s are defined in
t his t able:
VM: Configurat ion The unique Tx descript or queue at t ached t o a VF wit hin a TC, or t he pool of Tx
descript or queues at t ached t o t he same VF.
VM Cr edi t Ref i l l : Configurat ion The 82599' s WRR algorit hm implement credit refill as t he t echnique
for percent age allocat ion t o VMs. The credit s refill are added t o each VM credit count on each
complet ion of t he full round of t he algorit hm ( aft er all t he VMs had t heir chance t o send what t hey had
in st ore or at least one frame) .
The 82599' s driver needs t o calculat e t he VM credit refill t o mat ch t he percent allocat ed t hrough
management ( such as in t he MI B) . Since t he WRR arbit rat ion is self t imed, t he rat io bet ween t he credit s
refill is t he only defining paramet er for t he VMs. However, t he refills must be great er or equal t o t he
maximum sized frame allowed on t he TC or on t he pool in order t o guarant y t ransmission of at least
one frame on each recycling round. The 82599 allows a value of 1. 5 KB t o 1,024 KB for a dynamic
range of x1000.
Tabl e 7.48. Bandw i dt h Al l ocat i on t o VMs
T1: VM Bandw i dt h Al l ocat i on
VM
N
VM Ref i l l VM Max Cr edi t s VM Mi n Cr edi t s
0 MSS: 1, 024 KB 2xMSS: 2, 048 KB - MSS
1 MSS: 1, 024 KB 2xMSS: 2, 048 KB - MSS
2 MSS: 1, 024 KB 2xMSS: 2, 048 KB - MSS
3 MSS: 1, 024 KB 2xMSS: 2, 048 KB - MSS
. . .
15 MSS: 1, 024 KB 2xMSS: 2, 048 KB - MSS
Due t o a pipelined implement at ion, t he VM credit s range is enlarged by one MSS, beyond negat ive limit s.
All values are implement ed wit h 64- byt e granularit y ( a value of one corresponds t o 64 byt es of credit ) .

335
VM Max i mum Accumul at ed Cr edi t s: Deduct ed from Refill Configurat ion I n order t o prevent t he
use of st ale credit s, t he number of credit s each VM can accumulat e upon refill is limit ed. The credit s for
each VM can only reach t wice t heir refill. The maximum range for t he credit s is t hus - 9. 5 KB t o
2, 048 KB, assuming negat ive credit s can accumulat e up t o a maximum sized frame ( 9. 5 KB [ 9728
byt es] if j umbo frames are allowed) , and where posit ive credit s can accumulat e up t o t wice t he
maximum credit refill.
VM Cr edi t s: Run t ime paramet er VM credit s is a running count er for each VM. I t holds t he number
of available credit s in 64- byt e unit s. The algorit hm runs sequent ially bet ween t he VMs and enables
t ransmission for t hose VMs t hat have enough pending credit s ( t heir credit number is great er t han zero) .
7.7.2.3.2 WRR Ar bi t er Al gor i t hm
Low Lat ency TC Condi t i on - When a TC is dedicat ed t o low- lat ency t raffic, t here is a drive t o always
keep spare TC bandwidt h for t he VMs t hat are quiet , for serving t hem wit h minimum lat ency when t hey
resume offering a workload. This avoids overloaded VMs t o overt ake t he abilit y t o serve t he TC wit h low
lat ency. This feat ure is enabled per TC by set t ing t he corresponding bit in t he RTTDCS. LLTC bit map.
When enabled on a TC, t he associat ed VM arbit er does not replenish unless t here is at least half t he
MaxCredit s in t he TCs credit s account ( if t he TC is not LSP) :
T2 [ TC] . Cr edi t s > = ( T2 [ TC] . Max Cr edi t s / 2 ) , i f ! T2[ TC] . LSP
Refer t o next sect ion for t he det ails on TCs credit s account s.
Not e: This feat ure should be combined wit h configuring at least t wice t he sum of T1[ VM] . Refills
over a TC t o it s corresponding T2. [ TC] MaxCredit s. See Sect ion 4. 6. 11.5. 1 for det ails.
Tabl e 7. 49. Regi st er s Al l ocat i on f or Tx VM Ar bi t er s
At t r i but e Tx VM Ar bi t er
VM Cont rol regist ers RTTDT1C
VMC St at us regist ers RTTDT1S
VM credit refill CRQ
VM credit s CCC
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Round Robi n The round- robin aspect of t he VM WRR arbit er resides in t he fact t hat once a VM has
been grant ed for a dat a read request , t he next VMs are checked in a cyclic round- robin order, even if
t he grant ed VM st ill has credit s for anot her dat a read request .
7. 7. 2. 4 Tx TC Wei ght ed St r i ct Pr i or i t y Ar bi t er s
I n DCB, mult iple t raffic t ypes are essent ially mult iplexed over t he Et hernet 10 Gb/ s net work. There is a
need t o allow different behavior t o different t raffic flows as t hey pass t hrough mult iple Et hernet
swit ches and links. For example, for LAN, SAN and I PC connect ions are consolidat ed on a single
Et hernet link. Each t raffic t ype ( BWG) is guarant eed t he bandwidt h it has been allocat ed and is
prevent ed from usurping bandwidt h from ot her t ypes. However, if a BWG does not use it s bandwidt h,
t hat bandwidt h is made available t o t he ot her BWGs. The same holds for TCs wit hin a BWG. I f allocat ed
some bandwidt h, TCs are guarant eed t o have it , and if unused, t hat bandwidt h can be used by t he
ot her TCs wit hin t he BWG. I nformat ion regarding bandwidt h allocat ion for some TCs might not be
available. I n t he case of LAN, t he ent ire allocat ion of bandwidt h wit hin t he LAN link is t ypically
undefined in t oday' s net works. The arbit rat ion scheme includes Group St rict Priorit ies ( GSP) t o cover
for t hat . TCs for which t he GSP bit is set are limit ed by t he t ot al t hroughput allocat ed t o t heir BWG
rat her t han t o TC allocat ion.
Link bandwidt h is divided among t he BWGs for guarant eed minimum behavior. For example: LAN:
4 Gb/ s, SAN: 4 Gb/ s, I PC: 2 Gb/ s. The 82599 support s t wo t ypes of bandwidt h allocat ion wit hin BWGs.
TCs can be eit her allocat ed bandwidt h or be used as in st rict priorit y. I f a TC does not use all of it s
allocat ed bandwidt h, t hat bandwidt h is recycled t o ot her TCs in t he BWG.
The 82599 implement s t wo replicat ions of t he weight ed TC arbit er:
One in t he descript or plane, arbit rat ing bet ween t he different descript or queues, deciding which
queue is serviced next . I t is aimed t o enforce t he TC bandwidt h allocat ion and priorit izat ion scheme
for a case when PCI e bandwidt h is smaller t han t he link bandwidt h.
A second in t he packet plane, at t he out put of t he packet buffers, deciding which packet t o t ransmit
next . I t is aimed t o enforce t he TC bandwidt h allocat ion and priorit izat ion scheme for a case when
PCI e bandwidt h is great er t han t he link bandwidt h.
The condit ion for ent ry int o t he bandwidt h allocat ion algorit hm sequence differs for t he descript or and
dat a arbit ers:
Fi gur e 7.33. Tx VM WRR Ar bi t er s Oper at i on
WRR Arbiters
All VMs in that TC
are either empty, switched-off by BCN,
or have no credits?
N
Y
Select VM for next
data read request
Decrement T1[VM].Credits
VM := first VM in the TC;
Y
N
Start
VM is empty or
switched-off by BCN?
T1[VM].Credits > 0?
Y
Next data read request
was sent (from this VM)?
Y
N
Cyclic VM ++
N
Saturated to twice T1[VM].Refill
For all the VMs:
T1[VM].Credits :=
Min( (T1[VM].Credits + T1[VM].Refill), 2 x T1[VM].Refill)
Replenish all VMs credits

337
The descript or arbit er queries whet her t here is at least one queue at t ached t o a TC t hat is not
empt y, not swit ched off by t he rat e scheduler, wit h posit ive VM weight ed arbit er credit s ( when
relevant ) , and for which t he dest ined packet buffer has room for t he worst case maximum sized
frame. This last condit ion is cont rolled by RTTDCS. BPBFSM.
The packet arbit er queries whet her t he packet buffer has a packet t o send and whet her it is not
st alled by priorit y flow cont rol.
7.7.2.4.1 Def i ni t i on and Descr i pt i on of Par amet er s
User Pr i or i t y ( UP) : There are eight t raffic priorit ies, det ermined by 802. 1p t ag bit s on an Et hernet
link. The Q- Tag field holds UP' s. Per 802. 1p, Priorit y # 7 is t he highest priorit y. User priorit ies are
assigned by t he applicat ion or t he syst em t o cert ain usage classes, such as manageabilit y, I PC cont rol
channel, VoI P. And addit ional bit from t he S-Tag format defines whet her t he packet has a no drop
requirement . This bit is not being used by DCB mechanisms.
User Bandw i dt h Gr oup ( UBWG) : a user bandwidt h group is a management paramet er t hat is a
binding of user priorit ies int o bandwidt h groups for provisioning purposes. The hardware
implement at ion does not recognize t he UBWG ent it y.
Tr af f i c Cl ass ( TC) : incoming packet s are placed in t raffic classes. Per t he DCB funct ional specificat ion,
t here might be a 1: 1 mapping bet ween UP and TC, or more t han one priorit y can be grouped int o a
single class. Such grouping does not cross boundaries of t raffic BWGs. t he 82599 implement s eight or
four TCs and maps t hem t o UP' s according t o a programmable regist er. This provides t he best flexibilit y
for t he I T manager. However, when more t han one UP is mapped t o t he same TC, t hey must have t he
same no- drop policy net work wide.
Pack et Buf f er ( PB) : TCs are mapped t o packet buffers in a st raight forward 1: 1 mapping. Packet s are
also placed in packet buffers based on t heir class assignment s.
Tr af f i c Bandw i dt h Gr oup ( BWG) : For bandwidt h allocat ion and grouping, one or more TC can be
grouped int o a Traffic Bandwidt h Group ( BWG) . A BWG is a logical associat ion at a node, and has no
markings inside a packet header. End st at ions and swit ches are independent in t heir definit ion and
allocat ion of grouping of different TCs. Consist ency of behavior t hroughout t he net work is handled by
t he UBWG provisioning mechanism.
One or more TCs can be grouped in a BWG. BWGs are allocat ed a percent age of bandwidt h of available
Et hernet link. The allocat ed bandwidt h for BWG can be furt her divided among t he TCs t hat are inside
t he BWG.
Cr edi t s: Credit s regulat e t he bandwidt h allocat ed t o BWGs and TCs. As part of t he WSP algorit hm,
each BWG and TC has pre- allocat ed credit s. Those are decrement ed upon each t ransmission and
replenished cyclically. The rat io bet ween t he credit s of t he BWGs represent s t he relat ive bandwidt h
percent age allocat ed t o each BWG. The rat io bet ween t he credit s of t he TCs represent s t he relat ive
bandwidt h percent age allocat ed t o each TC wit hin a BWG. The 82599 effect ively maint ains one t able
t hat represent s bot h rat ios at once. Not e t hat credit s can get negat ive values down t o t he maximum
sized frame allowed on t he TC.
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Max i mum Cr edi t Val ue: The maximum credit value est ablishes a limit for t he running sum of credit s
allot t ed t o a class or group. This value prevent s st acking up st ale credit s t hat can be added up over a
relat ively long period of t ime and t hen used by TCs all at once, alt ering fairness and lat ency.
Not e: The absolut e value of t he credit s has no direct bearing on t he allocat ion of bandwidt h. The
rat io bet ween t he credit s does. However, t he absolut e value might have subst ant ial impact on
t he algorit hm behavior. Larger absolut e values can impact t he lat ency of high priorit y queues
and t heir abilit y t o serve burst s wit h minimum lat ency, whereas t oo small credit values might
impact t he correct funct ionalit y in presence of j umbo frames. The speed of t he algorit hm
implement at ion should also be t aken int o account . The value of t he maximum credit limit are
also in principle not part of t he main WSP algorit hm. However, t hey impact t he fairness of
bandwidt h reallocat ion bet ween queues in case some queues do not t ransmit t he full amount
t hey have been permit t ed t o. Also, small values prevent correct funct ionalit y of j umbo
frames. From high- level simulat ions it appears t hat credit s should be allocat ed as low as
possible based on t he speed of t he algorit hm. Maximum credit values for TCs should be 1. 5x
t o 2x t he size of t he maximum ent it y expect ed in t hat TC.
Wei ght ed St r i ct Pr i or i t y ( WSP) : The algorit hm implement ed in t he 82599 for TC arbit rat ion.
Gr oup St r i ct Pr i or i t y ( GSP) : Refer t o t he sect ions t hat follow for det ails.
Li nk St r i ct Pr i or i t y ( LSP) : Refer t o t he sect ions t hat follow for det ails.
Table 7. 50 ( T2) defines t he TCs, t heir associat ion t o BWGs and t heir bandwidt h allocat ion. The following
element s are defined in t his t able:
Due t o a pipelined implement at ion, t he TC credit s range is enlarged by one MSS in bot h direct ions, beyond it s posit ive and
negat ive limit s.
TC: Configurat ion The t raffic t ype associat ed t o t he packet buffer where incoming packet s are kept
before t ransmission ( or discard not implement ed in t ransmit in t he 82599) . TC7 is t he highest
priorit y TC.
BWG: Configurat ion Traffic BWG t hat a TC belongs t o.
TC Cr edi t Ref i l l : Configurat ion The 82599' s WSP algorit hm implement s credit refill as t he t echnique
for t raffic class percent age allocat ion. The credit s refill are added t o each TC credit count on each
complet ion of t he full round of t he algorit hm ( aft er all TCs had t heir chance t o send what t hey had in
st ore and if t hey had credit s for it ) .
Tabl e 7.50. Bandw i dt h Al l ocat i on t o TCs and BWGs
T2:
Tr af f i c Cl ass Bandw i dt h Al l ocat i on Wi t hi n a BWG
TC
N
BWG TC Ref i l l TC Max Cr edi t s LSP GSP
TC Mi n Cr edi t s ( accor di ng t o
GSP 0/ 1)
0 1 64 byt es t o 32 KB 64 byt es t o 256 KB 0/ 1 0/ 1 - MSS / - 2, 048 KB

339
The 82599' s driver needs t o calculat e t he TC Credit refill t o mat ch t he percent age allocat ed t hrough
management ( in t he MI B) . The TC credit refill t able includes, in one t able bot h t he TC and t he BWG.
Since t he WSP arbit rat ion is self t imed, t he rat io bet ween t he credit s refill is t he only defining
paramet er for t he TC and BWG. The absolut e values of t he refill have significance as t o t he rat e of
dist ribut ion bet ween t he queues and can have impact on lat ency and on t he moment ary st abilit y of t he
bandwidt h fairness. Result s from simulat ions indicat e t hat t he quant um for t he refill should be small t o
prevent large swings. I t should not be t oo small as t o creat e overhead in t he mechanism due t o t he
execut ion t ime; however. The 82599 allows a value of 64 byt es t o 32 KB, A dynamic range of x500. The
usage model is likely t o call for a smallest refill value of 256 byt es t o 512 byt es. This leaves a dynamic
range of 80x- 200x. For example, if a queue is assigned 1% and t his is t ranslat ed int o a 256- byt e
increment , anot her assigned wit h 99% would have a refill value of 25344 byt es.
TC Max Cr edi t : Configurat ion I n order t o prevent use of st ale credit s, t he number of credit s each TC
can accumulat e upon refill is limit ed. The TC credit can only reach MaxCredit , beyond t hat it s value get s
recycled t o ot her queues. Refer t o t he recycling mode for more det ails. The maximum range for t he
MaxCredit is 256 KB. This high range value was inherit ed from t he 82598 t hat had t o deal wit h ent ire
LSOs, but is not really necessary for t he 82599.
Not e: Full t est ing of many values for maximum value is unnecessary. Hierarchical t est ing should be
applied. For t he random t est , four t o six values should be sufficient . I t is import ant t hat t he
t est ing includes values t hat are relevant t o t he int erest ing zone of maximum value. For
example, in t he 0. 8x t o 2x t he relevant largest ent it y in t he class. Alt hough class wit h an
expect ed short er packet could use a smaller MaxCredit , it is recommended t hat t est ing fully
covers t he cases where all t he classes have similar values of MaxCredit , as it is a possible
variant use of t he algorit hm.
Li nk St r i ct Pr i or i t y ( LSP) : Configurat ion I f set , t his bit specifies t hat t his TC can t ransmit wit hout
any rest rict ion of credit s. This effect ively means t hat t his TC can t ake up t he ent ire link bandwidt h,
unless preempt ed by higher priorit y t raffic. I f t his bit is set , t hen TC. Credit Refill must be set t o 0b t o
ensure fair bandwidt h allocat ion. Preferably, t he algorit hm implement at ion should disregard non- zero
values in all it s calculat ions.
Gr oup St r i ct Pr i or i t y ( GSP) : Configurat ion This bit defines whet her st rict priorit y is enabled or
disabled for t his TC wit hin it s BWG. I f TC. GSP is set t o 1b, t he TC is scheduled for t ransmission using
st rict priorit y. I t does not check for availabilit y of TC. Credit s. I t does check whet her t he BWG of t his TC
has credit s ( such as t he amount of t raffic generat ed from t his TC is st ill limit ed by t he BWG allocat ed for
t he BWG ( T3. BWGP) . I f t his bit is set , t hen TC. Credit Refill values can be set t o 0b, if a non- zero value
is configured, TC credit s are reduced first from t he GSP TC and if reached t o zero from ot her TCs in t he
group, if t he refill credit s are configured t o zero t he TC credit s are reduced from t he ot her TCs in t he
BWG.
Not e: Since t he TC. GSP paramet er relat es t o individual TCs, some BWGs might have bot h TC' s wit h
bandwidt h allocat ion and TC' s wit h GSP. This is a hybrid usage mode t hat is complex t o
validat e and is possibly secondary in import ance.
Usage Not e I t is possible t hat a TC using LSP dominat es t he link bandwidt h if t here are no packet s
wait ing and eligible in higher priorit y TC' s. To guarant ee correct bandwidt h allocat ion, all TC' s wit h t he
unlimit ed bit set should be in t he same t raffic BWG ( high priorit y group) . Not e t hat t his is different t han
a t ypical DCB deployment considered where BWG is creat ed wit h funct ional grouping, like LAN, SAN,
and I PC et c. TC' s wit h t he LSP bit set should be t he first t o be considered by t he scheduler ( t he first
TC' s) . For example, from queue 7 t o queue 5 wit h t he ot her five TC' s for groups wit h bandwidt h
allocat ion. These are not st rict requirement s, if t hese rules are not followed, undesirable behavior could
occur in some cases. A group cont aining only TC' s wit h t he unlimit ed bit set effect ively has zero BWG
credit s since TC' s wit h t he LSP unlimit ed bit set should have TC credit s set t o zero. Use of LSP / TC. GSP
should be rest rict ed t o UP/ TC' s t hat service t rust ed applicat ions.
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340
TC Cr edi t s: Run- t ime paramet er TC credit s is a running algebraic count er for each TC. I t holds t he
number of available credit s in 64- byt e unit s. The algorit hm runs sequent ially bet ween t he TC' s and
enables t ransmission for t hose TCs t hat have posit ive pending credit s. Not e t hat credit s can get
negat ive values down t o t he maximum sized frame allowed on t he TC.
Table 7. 51 ( T3) defines t he hierarchy of BWG similarly t o T2 defining t he hierarchy wit hin t he BWG' s. T3
implement at ion should include eight rows.
Due t o a pipelined implement at ion, t he BWG credit s range is enlarged by one MSS in bot h direct ions, beyond it s posit ive and
negat ive limit s.
BWG: Configurat ion This is t he number of t he t raffic BWG t hat is t hree bit s wide. This field
corresponds t o t he TC. BWG field in Table 7.50.
BWG Ref i l l Cr edi t s: A virt ual number The credit s provisioned for t his BWG. The credit s rat io
bet ween t he BWG' s should reflect t he rat io of bandwidt h bet ween t he BWG' s. I n t he act ual
implement at ion, t his number is t he sum of t he credit Refills of t he TC' s associat ed wit h t his BWG.
BWG Max Cr edi t : A virt ual number The maximum credit s for a BWG. Credit s in t he BWG. Credit
count er are limit ed t o t his value. Credit s t hat should have been refilled above t his value are lost . I n
effect , due t o t he self- t imed cyclic nat ure of t he WSP algorit hm, t hose credit s are dist ribut ed bet ween
all BWG' s. I n t he act ual implement at ion, t his number is t he sum of t he MaxCredit of t he TC' s associat ed
wit h t his BWG.
BWG.Cr edi t : Run- t ime paramet er A running algebraic count er t hat is decrement ed for each
t ransmission. At t he end of each cycle, t his count er is synchronized wit h t he sum of t he TC. Credit
count er associat ed wit h t his BWG. The synchronizat ion algorit hm depends on t he recycling mode. refer
t o t he sect ions t hat follow for det ails about arbit rat ion configurat ions. Not e t hat credit s can get negat ive
values down t o t he maximum sized frame allowed on t he BWG.
7.7.2. 4.2 Ar bi t er s Convent i ons
The WSP scheme previously described is writ t en wit h t he dat a plane arbit er in mind. However, t he same
scheme is used by t he t ransmit descript or plane arbit er and a subset of it is used by t he receive dat a
arbit er. To dist inguish bet ween t he t wo arbit ers, at t ribut es of t he each arbit er are prefixed as depict ed
in Table 7.52.
Tabl e 7.51. Li ne Bandw i dt h Al l ocat i ons t o Bandw i dt h Gr oups ( BWG) ( w i t h ex ampl e)
T3:
Li ne bandw i dt h al l ocat i on t o Tr af f i c Bandw i dt h Gr oups ( BWG)
BWG BWG Refill Credit s BWG MaxCredit BWG Credit Descript ion
0 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048 KB I PC
1 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048 KB SAN
2 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048 KB LAN
3 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048 KB Manageabilit y
-
-
-
7

341
Table 7.53 list s t he regist er fields t hat cont ain t he relevant at t ribut es from Table 7.52.
7.7.2.4.3 Tx TC WSP Ar bi t r at i on Conf i gur at i ons
RR / WSP: Global Configurat ion bit s When t his bit is set , t he arbit rat ion is in WSP mode. When
reset , t he arbit rat ion is in flat frame- based round robin mode. I n RR mode, one frame is t ransmit t ed
from each packet buffer in it s t urn. BWG and TC paramet ers do not apply.
Recycl e Mode: Global Configurat ion bit s.
Ar chi t ect ur e Over vi ew of Recy cl e As a result of GSP t ransmit s and TCs t hat reach t heir maximum
credit limit , t he credit count of a BWG might not mat ch t he t ot al credit count of it s TCs ( refer t o t he
sect ions t hat follow for more det ails) . I t is not merely an arit hmet ic issue. The WSP algorit hm, dual
hierarchy behaves as a maximum allocat ion algorit hm wit hin t he BWG' s and minimum allocat ion
algorit hm bet ween t he BWG' s. Since t he recycle is self t imed, when a BWG does not t ransmit all of it s
allocat ed bandwidt h wit hin a cycle, at t he end of t he cycle it s bandwidt h is in effect reallocat ed t o all
BWG' s. This result s in a minimum allocat ion behavior. I nside t he BWG' s; however, t his not ion of self
t iming does not exist . Some explicit mechanism is required t o recycle bandwidt h wit hin a BWG rat her
t han t o all t he BWG' s The requirement t o have a minimum allocat ion behavior.
A BWG credit count might not mat ch t he t ot al credit count of it s TCs in t he following cases:
A TC is defined as GSP when a GSP is select ed, t he BWG credit s are decrement ed but no TC
is deduct ed. Therefore, t he BWG credit count would be lower t hat t he credit count of it s TCs.
Tabl e 7. 52. At t r i but es of Tx Ar bi t er s
At t r i but e Tx Pack et Ar bi t er Tx Descr i pt or Ar bi t er
TC P-TC D-TC
BWG P- BWG D- BWG
TC Credit Refill P-TC Credit Refill D-TC Credit Refill
TC MaxCredit P-TC MaxCredit D-TC MaxCredit
LSP P- LSP D- LSP
GSP P- GSP D- GSP
TC Credit s P-TC Credit s D-TC Credit s
BWG Refill Credit s P- BWG Refill Credit s D- BWG Refill Credit s
BWG MaxCredit s P- BWG MaxCredit s D- BWG MaxCredit s
BWG Credit s P- BWG Credit s D- BWG Credit s
Tabl e 7. 53. Regi st er s Al l ocat i on f or Tx TC Ar bi t er s
At t r i but e Tx Pack et Ar bi t er Tx Descr i pt or Ar bi t er
TC Cont rol regist ers RTTPT2C Reserved
TC St at us regist ers RTTPT2S RTTDT2S
BWG BWG BWG
TC credit refill CRQ CRQ
TC MaxCredit MCL MCL
LSP LSP LSP
GSP GSP GSP
TC credit s CCC CCC
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342
Max credit s during refill I f a TC reaches it s max credit s value during refill, t hen some credit s
are lost for t hat TC. However, t he BWG for t hat TC is provided wit h t he full refill count .
Therefore, t he BWG credit count would be higher t hat t he credit count of it s TCs.
One bit per TC arbit er governs t he recycle mode of t he WSP algorit hm:
0: No Recycl i ng At t he end of each full arbit rat ion cycle all TC' s are refilled wit h t heir
TC. Refill up t o t heir TC. MaxCredit s values. All BWG. Credit are loaded by t he sum of t he BWG
TC.Credit .
1: Recycl e TC credit s for TC' s t hat have reached t heir maximum are recycled t o ot her TC' s
of t he BWG. The operat ion is calculat ed based on t he BWG. Credit and t he TC. Credit s aft er t heir
refill. The difference bet ween t hem is t he BWG. Recycle value.
Posit ive BWG. Recycle - The recycle algorit hm adds credit s from t he BWG. Recycle t o t he
TC. Credit s st art ing from t he highest priorit y TC in t he BWG down, considering t he
TC. MaxCredit , unt il BWG. Recycle is zero.
Negat ive BWG. Recycle - The recycle algorit hm subt ract s credit s from t he BWG. Recycle t o t he
TC. Credit s st art ing from t he lowest priorit y TC in t he BWG up, unt il BWG. Recycle is zero.
A separat e set of configurat ion paramet ers exist s for each of t he t hree TC arbit ers as list ed in
Table 7. 54.
7.7.2. 4.4 Tx TC WSP Ar bi t er Al gor i t hm
The Transmit Packet Plane Arbit rat ion Cont rol ( TPPAC) bit in t he RTTPCS regist ers det ermines t he
scheduler t ype ( RR or WSP) .
St r i ct Pr i or i t y The st rict - priorit y aspect of t he TC WSP arbit er resides in t he fact t hat once a TC has
been grant ed for a dat a read request or for t ransmission, t he highest priorit y TCs are checked ( again)
in a st rict - priorit y order, st art ing from TC7, even if t he grant ed TC st ill has credit s for anot her dat a read
request or t ransmission.
Not e: The descript or plane arbit er can' t issue a dat a read request unless t here is an unused request
for dat a. Therefore t he arbit er st alls in it s current st at e each t ime t here are no dat a read
request s available. The next arbit rat ion decision is only done once t here is at least one free
dat a read request .
Tabl e 7.54. Conf i gur at i on Par amet er s f or t he Tx and Rx TC Ar bi t er s
Par amet er Tx Pack et Ar bi t er Tx Descr i pt or Ar bi t er Rx Pack et Ar bi t er
RTTPCS RTTDCS RTRPCS
RR / WSP mode TPPAC TDPAC RAC
Recycle mode TPRM TDRM RRM

343
Fi gur e 7.34. Tx TC WSP Ar bi t er s Oper at i on
7. 7. 3 Recei v e- Si de Capabi l i t i es
7.7.3.1 User Pr i or i t y t o Tr af f i c Cl ass Mappi ng
To enable different TC support for incoming packet s and proper behavior per TC, t he 82599s receive
packet buffer is segment ed int o several packet buffers. The 82599 support s t he following configurat ions
of packet buffer segment at ion:
DCB disabled Single buffer of 512 KB
DCB enabled wit h 4 TCs 4 buffers, 128 KB each
DCB enabled wit h 8 TCs 8 buffers, 64 KB each
DCB enabled wit h 8 TCs 8 buffers, buffers 3: 0 are 80 KB and buffers 7: 4 are 48 KB
I ncoming packet s are t ransferred from t he packet buffers int o dat a buffers in syst em memory. Dat a
buffers are arranged around descript or rings described in Sect ion 7. 1. 9. Each descript or queue is
assigned dynamically t o a given TC ( and t herefore t o a packet buffer) as described in Sect ion 7. 1. 2.
Tx WSP Arbiter
TC < 0?
N
N
N
Y
Y
Tx Packet
Decrement Credits
If (!T2[TC]LSP) then {
Decrement T2[TC].Credits
DecrementT3[BWG].Credits
}
TC - -
Y
TC := 7;
Y
N
N
N
Start
Are stall conditions
in place *?
BWG = T2[TC].BWG
T2[TC].LSP?
T2[TC].Credits > 0?
Update BWG Credits to Max
All BWG
T3[BWG].Credits :=
Min ((T3[BWG].Credits + T3[BWG].Refill),
T3[BWG].MaxCredit)
Update TC Credits to Max
All TC:
T2[TC].Credits :=
Min( (T2[TC].Credits + T2[TC].Refill), T2[TC].MaxCredit)
Recycle unused BW & Sync TCs to BWG:
for each BWG:
T3[BWG].Recycle :=T3[BWG].Credits - (T2[TC].Credits)
if T3[BWG].Recycle > 0 then
for ((TC = 7 to 0) & TC BWG)
T2Recycle:= Min( T3[BWG].Recycle,
(T2[TC].MaxCredit -T2[TC].Credits))
T2[TC].Credits += T2Recycle
T3[BWG].Recycle -= T2Recycle
end
Descriptor Plane Arbiter
All descriptor queues attached to that TC are either empty,
and/or switched-off by the transmit rate scheduler, and/or no
place in PB[TC] (for example, it is filled with more KB than
TXPBSIZE.THRESH.

Data Plane Arbiter
PB[TC] is either empty, and/or paused by Priority Flow Control
Y
Y
T3[BWG].Credits > 0
or no GSP in the BWG?
T2[TC].GSP?
Replenish All BWG & Traffic Class Credits
Saturated to a Max Value with Recycle to Group
// Some TC(s) have saturated
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344
Configurat ion regist ers:
The size of each buffer is defined by t he RXPBSI ZE[ 0- 7] regist ers. Not e t hat it is possible t o
configure t he buffers at 1 KB granularit y
A received packet is assigned by t he 82599 t o a TC, and is t hus rout ed t o t he corresponding Rx
packet buffer according t o it s User Priorit y field in t he 802. 1Q t ag and according t o a UP t o TC
mapping t able loaded int o t he RTRUP2TC regist er.
Caut i on: Different UP t o TC mappings can be loaded in each direct ion Tx and Rx, as per RTTUP2TC and
RTRUP2TC regist ers, respect ively. But in such a case, when a packet is looped back by t he
int ernal VM t o VM swit ch, it is rout ed t o t he Rx packet buffer t hat corresponds t o t he TC t hat
was used in Tx.
7. 7. 3. 2 Rx PB Wei ght ed St r i ct Pr i or i t y Ar bi t er
The 82599' s Rx arbit er det ermines t he order in which packet s are writ t en from t he different packet
buffers int o syst em memory. Not e t hat each packet buffer by it self is drained in t he order packet s
arrived, as long as it deals wit h packet s dest ined t o t he same Rx queue.
The arbit rat ion algorit hm bet ween t he receive packet buffers is WSP, similar t o t he TC scheme on t he
t ransmit side. Mot ivat ion for t his scheme is as follows:
1. The maj or considerat ion is t o prevent any delay in delivery of high- priorit y t raffic.
2. Allocat ion of credit s cont rols t he bandwidt h allocat ed t o t he different packet buffers.
3. A secondary mean of bandwidt h allocat ion is t he priorit y flow cont rol. By alt ering t he flow cont rol
high wat ermark, t he 82599 can effect ively ( if coarsely) regulat e bandwidt h allocat ion t o t ypes of
t raffic.
Table 7. 55 ( T4) defines t he TCs and t heir bandwidt h allocat ion. The following element s are defined in
t his t able:
Due t o a pipelined implement at ion, t he PB credit s range is enlarged by one MSS in bot h direct ions, beyond it s posit ive and
negat ive limit s.
Table 7. 56 ( T5) defines t he hierarchy of BWG similarly t o T4 defining t he hierarchy wit hin t he BWG' s. T4
implement at ion should include eight rows.
Tabl e 7.55. Bandw i dt h Al l ocat i on t o Tr af f i c Cl asses and Bandw i dt h Gr oups
T4:
Pack et Buf f er Bandw i dt h Al l ocat i on Wi t hi n a BWG
PB BWG PB Ref i l l PB Max Cr edi t s LSP GSP
PB Mi n Cr edi t s ( accor di ng t o
GSP 0/ 1)

345
The at t ribut es of t he Rx packet arbit er are described in Sect ion 7. 7. 2. 4. 2.
7.7.3.2.1 Rx TC Ar bi t r at i on Conf i gur at i ons
Table 7.57 list s t he regist er fields t hat cont rol t he Rx arbit er.
Configurat ion paramet ers for t he Rx packet arbit er are defined and list ed in Sect ion 7.7. 2. 4. 1.
7.7.3.2.2 Rx TC WSP Ar bi t er Al gor i t hm
The Rx packet arbit er operat es in RR or WSP mode, configured t hrough t he RAC bit in t he RTRPCS
regist er. The WSP arbit er operat ion is described as follows.
Tabl e 7. 56. Pack et Buf f er Al l ocat i ons t o BWGs ( w i t h Ex ampl e)
T5:
Li ne Bandw i dt h Al l ocat i on t o Tr af f i c BWGs
BWG BWG Credit Refill BWG MaxCredit BWG Credit Descript ion
0 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048KB I PC
1 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048KB SAN
2 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048KB LAN
3 = E[TC] Credit Refill = E[TC]. MaxCredit - / + 2, 048KB MGMT.
-
-
-
7
Tabl e 7. 57. Regi st er s Al l ocat i on f or DCB Rx Ar bi t er s
At t r i but e Rx Pack et Ar bi t er
PB Cont rol regist ers RTRPT4C
PB St at us regist ers RTRPT4S
BWG BWG
PB credit refill CRQ
PB MaxCredit MCL
LSP LSP
GSP GSP
PB credit s CCC
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Fi gur e 7.35. Rx Pack et WSP Ar bi t er Oper at i on
Rx WSP Arbiter
PB < 0?
N
N
N
Y
Y
Tx Packet
Decrement Credits
If (!T4[PB]LSP) then {
Decrement T4[PB].Credits
DecrementT5[BWG].Credits
}
PB - -
Y
PB := 7;
Y
N
N
N
Start
BWG = T4[PB].BWG
T4[PB].LSP?
T4[PB].Credits > 0?
Update BWG Credits to Max
All BWG
T5[BWG].Credits :=
Min ((T5[BWG].Credits + T5[BWG].Refill),
T5[BWG].MaxCredit)
Update PB Credits to Max
All PB:
T4[PB].Credits :=
Min( (T4[PB].Credits + T4[PB].Refill), T4[PB].MaxCredit)
Recycle unused BW & Sync PB s to BWG :
for each BWG:
T5[BWG].Recycle :=T5[BWG].Credits - E (T4[PB].Credits)
if T5[BWG].Recycle > 0 then
for ((PB = 7 to 0) & PB e BWG)
T4Recycle:= Min( T5[BWG].Recycle,
(T4[PB].MaxCredit - T4[PB].Credits))
T4[PB].Credits += T4Recycle
T5[BWG].Recycle - = T4Recycle
end
Y
Y
T5[BWG].Credits > 0?
or no GSP in the BWG?
T4[TC].GSP?
Replenish all BWG & Traffic Class credits
Saturated to a Max value w/ Recycle to Group
// Some TC(s) have saturated
PB is empty or
no Rx descriptors in the ring?

347
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348
7.8 Li nk Sec
LinkSec ( or MACsec, 802. 1AE) is a MAC- level encrypt ion/ aut hent icat ion scheme defined in I EEE
802. 1AE t hat uses symmet ric crypt ography. The 802. 1AE defines AES- GCM 128- bit key as a mandat ory
cipher suit e t hat can be processed by t he 82599. The LinkSec implement at ion, enabled as det ailed in
Sect ion 4. 6. 12, support s t he following:
GCM AES 128- bit offload engine in t he Tx and Rx dat a pat h t hat support 10 Gb/ s wire speed.
Bot h host and manageabilit y cont roller t raffic can be processed by t he GCM AES engines.
Support a single, secure Connect ivit y Associat ion ( CA) :
Single Secure Connect ion ( SC) on t ransmit dat a pat h.
Single SC on receive dat a pat h.
Each SC support s t wo Securit y Associat ions ( SAs) for seamless re- keying.
At any given t ime, eit her t he manageabilit y cont roller or t he host can act as key agreement ent it y
( KaY in 802. 1AE spec t erminology) . For example, cont rol and access t he offloading engine ( SecY
in 802. 1AE specificat ion t erminology) .
Arbit rat ion semaphores indicat e whet her t he manageabilit y cont roller or t he host act s as t he
KaY.
Tamper resist ance When t he manageabilit y cont roller act s as KaY it can disable accesses
from t he host t o SecYs address space. When t he host act s as t he KaY no prot ect ion is provided.
Provide st at ist ic count ers as list ed in t he Sect ion 8. 3. 5. 6.
Support replay prot ect ion wit h replay window equal t o zero. Packet s t hat fail replay validat ion are
post ed wit h a replay error in t he Rx descript or. The packet s are post ed t o t he host regardless of
st rict versus check mode described lat er on in t his sect ion.
Receive memory st ruct ure:
New LinkSec offload receive st at us indicat ion in t he receive descript ors. LinkSec offload must
not be used wit h t he legacy receive format but rat her use t he ext ended receive descript or
format .
LinkSec header/ t ag can be post ed t o t he KaY for debug.
Support VLAN header locat ion according t o I EEE 802. 1AE ( first header inner t o t he LinkSec t ag) .
When LinkSec offload is enabled, Et hernet CRC must be enabled as well by set t ing bot h TXCRCEN
and RXCRCSTRP bit s in t he HLREG0 regist er.
7.8.1 Pack et For mat
LinkSec defines frame encapsulat ion format as follows.
Tabl e 7.58. Legacy Fr ame For mat
MAC DA, SA VLAN ( opt ional) Legacy Type / Len
LLC dat a ( may include
I P/ TCP and higher level
payload)
CRC
- - - - - - - - - - User Dat a - - - - -
- - - - -
Tabl e 7.59. Li nk Sec Encapsul at i on
MAC DA, SA LinkSec header ( SecTag) User dat a ( opt ional encrypt ed) LinkSec I CV ( t ag) CRC

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7.8.2 Li nk Sec Header ( SecTag) For mat
7.8.2.1 Li nk Sec Et her t y pe
The MACsec Et hert ype comprises oct et 1 and oct et 2 of t he SecTAG. I t is included t o allow:
a. Coexist ence of MACsec capable syst ems in t he same environment as ot her syst ems.
b. I ncrement al deployment of MACsec capable syst ems.
c. Peer SecYs t o communicat e using t he same media as ot her communicat ing ent it ies.
d. Concurrent operat ion of key agreement prot ocols t hat are independent of t he MACsec prot ocol
and t he current cipher suit e.
e. Operat ion of ot her prot ocols and ent it ies t hat make use of t he service provided by t he SecYs
uncont rolled port t o communicat e independent ly of t he Key agreement st at e.
7.8.2.2 TCI and AN
Not e: The combinat ion of t he E bit equals 1b and t he C bit equals 0b is reserved for KaY packet s.
The LinkSec logic ignores t hese packet s on t he receive pat h and t ransfers t hem t o KaY as is
( no LinkSec processing and no LinkSec header st rip) . t he 82599s implement at ion never
issues a packet in which t he E bit is cleared and t he C bit is set , alt hough can t olerat e such
packet s on receive.
Tabl e 7. 60. Sect ag For mat
LinkSec Et hert ype TCI and AN SL PN SCI ( opt ional)
2 byt es 1 byt e 1 byt e 4 byt es 8 byt es
Tabl e 7. 61. Li nk Sec Et her t ype
Tag Ty pe Name Val ue
802. 1AE securit y TAG LinkSec Et hert ype 88- E5
Tabl e 7. 62. TCI and AN Descr i pt i on
Bi t ( s) Descr i pt i on
7
Ver si on Number ( V) . t he 82599 support s only version 0. Packet s wit h ot her version value are discarded by t he
82599.
6
End St at i on ( ES) . When set , indicat es t hat t he sender is an end st at ion. As a result , SCI is redundant and causes t he
SC bit t o be cleared. Current ly, should be always 0b.
5
Secur e Channel ( SC) . Equals 1b when t he SCI field is act ive. I f t he ES bit is set t he SC must be cleared. Since only
ES equals zero is support ed, t he SCI field must be act ive by set t ing t he LSECTXCTRL. AI SCI .
4 Si ngl e Copy Br oadcast ( SCB) . Cleared t o 0b unless SC support s EPON. Should always be 0b.
3 Encr y pt i on ( E) . Set t o 1b when user dat a is encrypt ed. ( see t he not e t hat follows) .
2
Changed Tex t ( C) . Set t o 1b if t he dat a port ion is modified by t he int egrit y algorit hm. For example, if non- default
int egrit y algorit hm is used or if packet is encrypt ed. ( see t he not e t hat follows) .
1: 0 Associ at i on Number ( AN) . 2- bit value defined by cont rol channel t o uniquely ident ify SA ( Keys, et c. ) .
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7.8.2. 2.1 Shor t Lengt h
7.8.2. 2.2 Pack et Number ( PN)
The LinkSec engine increment s it for each packet on t he t ransmit side. The PN is used t o generat e t he
init ial value ( I V) for t he crypt o engines. When KaY is est ablishing a new SA, it should set t he init ial
value of PN t o 1b. See more det ails on PN exhaust ing in Sect ion 7. 8. 5.1.
7. 8. 2. 3 Secur e Channel I dent i f i er ( SCI )
The SCI is composed of t he Et hernet MAC address and port number as list ed in t he following t able. I f
t he SC bit in TCI is not set , t he SCI is not encoded in t he SecTag.
7. 8. 2. 4 I ni t i al Val ue ( I V) Cal cul at i on
The I V is t he init ial value used by t he Tx and Rx aut hent icat ion engines. The I V is generat ed from t he
PN and SCI as described in t he 802. 1AE specificat ion.
7.8.3 Li nk Sec Management KaY ( Key Agr eement Ent i t y )
Kay management is done by t he host or t he manageabilit y cont roller. The ownership of LinkSec
management is as follows:
1. I nit ializat ion at power up or aft er wake on LAN.
I n most cases t he manageabilit y cont roller wakes before t he host , so:
I f t he manageabilit y cont roller can be a KaY, it est ablishes an SC ( aut hent icat ion and key
exchange) .
I f t he manageabilit y cont roller cannot be a KaY t he only way for it t o communicat e is t hrough a
dedicat ed Et hernet MAC address or VLAN. This means t hat t he swit ch must support set t ings
t hat enable specific Et hernet MAC Address or VLAN t o bypass LinkSec.
When t he host is awake:
I f t he manageabilit y cont roller act ed as KaY, t he host should aut hent icat e it self and t ransfer it s
abilit y t o aut hent icat e t o t he manageabilit y cont roller in order for t he manageabilit y cont roller
t o t ransfer ownership over t he LinkSec hardware. At t his st age, t he syst em operat es in proxy
mode where t he host manages t he secured channel while t he manageabilit y cont roller
piggybacks on it .
I f t he manageabilit y cont roller wasn' t KaY, t he host t akes ownership over t he LinkSec hardware
and est ablishes an SC ( aut hent icat ion and key exchange) . The manageabilit y cont roller mode
of operat ion does not change and it cont inues t o communicat e t hrough a dedicat ed Et hernet
MAC address or VLAN.
Tabl e 7.63. SL Fi el d Descr i pt i on
Bi t ( s) Descr i pt i on
7: 6 Reserved, set t o 0b.
5: 0
Shor t Lengt h ( SL) . Number of oct et s in t he secure dat a field from t he end of SecTag t o t he beginning of I CV if it is
less t hen 48 oct et s, else SL value is 0b.
Tabl e 7.64. SCI Fi el d Descr i pt i on
Byt e 0 By t e 1 By t e 2 By t e 3 Byt e 4 By t e 5 By t e 6 By t e 7
Source Et hernet MAC Address Port Number

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2. Host in Sx st at e manageabilit y cont roller act ive:
I f t he manageabilit y cont roller is not Kay capable, t hen t he SC should be reset by link reset or
by sending a logoff packet ( 1af ) and t hen t he manageabilit y cont roller can ret urn t o VLAN
solut ion ( or remain in such) .
I f t he manageabilit y cont roller is KaY capable, t he host should not ify t he manageabilit y
cont roller t hat it ret ires KaY ownership and t he manageabilit y cont roller should ret ake it .
7.8.4 Recei v e Fl ow
The 82599 might concurrent ly receive packet s t hat cont ain LinkSec encapsulat ion as well as packet s
t hat do not include LinkSec encapsulat ion. This sect ion describes t he incoming packet classificat ion.
Examine t he user dat a for a SecTAG:
I f no SecTag, post t he packet wit h a cleared LinkSec bit in t he Packet Type field of t he receive
descript or.
Validat e frames wit h a SecTAG:
The MPDU comprises at least 18 oct et s
Oct et s 1 and 2 compose t he MACsec Et hert ype ( 88E5)
The V bit in t he TCI is cleared
I f t he ES or t he SCB bit in t he TCI is set , t hen t he SC bit is cleared
Bit s 7 and 8 of oct et 4 of t he SecTAG are cleared SL < = 0x3F
I f t he C and SC bit s in t he TCI are cleared, t he MPDU comprises 24 oct et s plus t he number of
oct et s indicat ed by t he SL field if t hat is non- zero and at least 72 oct et s ot herwise
I f t he C bit is cleared and t he SC bit set , t hen t he MPDU comprises 32 oct et s plus t he number of
oct et s indicat ed by t he SL field if t hat is non- zero and at least 80 oct et s ot herwise
I f t he C bit is set and t he SC bit cleared, t hen t he MPDU comprises 8 oct et s plus t he minimum
lengt h of t he I CV as det ermined by t he cipher suit e in use at t he receiving SecY, plus t he
number of oct et s indicat ed by t he SL field if t hat is non- zero and at least 48 addit ional oct et s
ot herwise
I f t he C and SC bit s are bot h set , t he frame comprises at least 16 oct et s plus t he minimum
lengt h of t he I CV as det ermined by t he cipher suit e in use at t he receiving SecY, plus t he
number of oct et s indicat ed by t he SL field if t hat is non- zero and at least 48 addit ional oct et s
ot herwise
Ext ract and decode t he SecTAG as specified in Sect ion 7. 8. 2.
Ext ract t he user dat a and I CV as specified sect ion Sect ion 7. 8. 1.
Assign t he frame t o an SA:
I f a valid SCI , use it t o ident ify t he SC
Select SA according t o AN value
I f no valid SC or no valid SA found, drop t he packet
I f SCI is omit t ed, use default SC
Select SA according t o AN value
I f no valid SC ( or more t hen SC act ive) or no valid SA found drop packet
Perform a preliminary replay check against t he last validat ed PN
Provide t he validat ion funct ion wit h:
The SA Key ( SAK)
The SCI for t he SC used by t he SecY t o t ransmit
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The PN
The SecTAG
The sequence of oct et s t hat compose t he secure dat a
The I CV
Receive t he following paramet ers from t he cipher suit e validat ion operat ion
A valid indicat ion, if t he int egrit y check was valid and t he user dat a could be recovered
The sequence of oct et s t hat compose t he user dat a
Updat e t he replay check
I ssue an indicat ion t o t he cont rolled port wit h t he DA, SA, and priorit y of t he frame as received
from t he receive de- mult iplexer, and t he user dat a provided by t he validat ion operat ion
Not e: All t he references t o clauses are t o t he I EEE P802.1AE/ D5.1 document from January 19,
2006.
7. 8.4. 1 Recei v e Modes
There are four modes of operat ion defined for LinkSec Rx as defined by t he LSECRXCTRL. LSRXEN field:
1. Bypass ( LSRXEN = 00b) in t his mode, LinkSec is not offloaded. There is no aut hent icat ion or
decrypt ing of t he incoming t raffic. The LinkSec header and t railer are not removed and t hese
packet s are forwarded t o t he host or t he manageabilit y cont roller according t o t he regular L2 MAC
filt ering. The packet is considered as unt agged ( no VLAN filt ering) . No furt her offloads are done on
LinkSec packet s.
2. Check ( LSRXEN = 01b) in t his mode, incoming packet s wit h mat ching key are decrypt ed and
aut hent icat ed according t o t he LinkSec t ag. I n t his mode bot h good and erroneous packet s are
forwarded t o host ( wit h t he relevant error indicat ion) . The only cases where packet s are dropped
are: erroneous encrypt ed packet s ( wit h t he C bit in t he SecTag header is set ) or erroneous packet s
wit h replay error if replay prot ect ion is enabled in t he LSECRXCTRL regist ers. The Check mode is
expect ed t o be used mainly for debug purposes. I n t his mode, it may be useful t o set also t he Post
LinkSec header bit in t he LSECRXCTRL regist er which cont rols bot h SecTag and I CV t o be post ed t o
host memory. Not e t hat t he header is not removed from KaY packet s.
3. St rict ( LSRXEN = 10b) in t his mode, incoming packet s wit h mat ching key are decrypt ed and
aut hent icat ed according t o t he LinkSec t ag. The LinkSec header and t railer might be removed from
t hese packet s and t he packet s are forwarded t o t he host only if t he decrypt ing or aut hent icat ion
was successful. Addit ional offloads are possible on LinkSec packet s. The header is not removed
from KaY packet s.
4. Drop ( LSRXEN = 11b) in t his mode, LinkSec is not offloaded and LinkSec packet s are dropped.
There is no aut hent icat ion or decrypt ing of t he incoming t raffic.
7. 8.4. 2 Recei v e SA Ex haust i ng Re- Key i ng
The seamless re- keying mechanism is explained in t he following example.
KaY est ablishes SC0 SC and set s SA0 as t he act ive SA by writ ing t he key in regist er LinkSec RX Key,
writ ing t he AN in LSECRXSA[ 0] , and set t ing t he SA Valid bit in t he same regist er. This clears t he Frame
Received bit . On t he first packet t hat arrived t o SA0, t he frame received aut omat ically set s t he Frame
Received bit . Only at t his t ime t he KaY can and should init iat e SA1 in t he same manner as for SA0.
When a frame of SA1 arrives, SA0 ret ires and can be used for t he next SA.
Not e: The same mechanism should be used for all RX SCs.

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7. 8. 4. 3 Recei v e SA Cont ex t and I dent i f i cat i on
Upon arrival of a secured frame t he cont ext of t he SecTag is verified. This cont ext of t he SecTag is
described in Sect ion 7.8. 2. I n order t o process t he secured frame it should be associat ed wit h one of
t he SA keys. The ident ificat ion is done by comparing t he SCI dat a wit h LinkSec RX SC regist ers and t he
appropriat e SC is select ed. To ensure t hat t he SC bit in t he TCI of t he frame is not set and more t han
one SC is valid belongs t o t he frame considered as erroneous and t ransferred t o error handling if only
one SC is valid, t his SC is select ed in t his case SC. The incoming frame AN field is compared t o t he AN
field of t he Link RX SA regist er of t he select ed SC in order t o select an SA. The select ed SA PN ( regist er
LinkSec RX SA PN) field is compared t o t he incoming PN which should be equal or great er t han t he
LinkSec RX SA PN value, ot herwise t his frame is dropped. On a mat ch, t he select ed SA key is used for
t he secured frame processing.
7.8.4.4 Recei v e St at i st i c Count er s
A det ailed list and descript ion of t he LinkSec RX st at ist ics count ers can found in Sect ion 8. 3. 5. 6.
7. 8. 5 Tr ansmi t Dat a Pat h
The 82599 might concurrent ly t ransmit packet s t hat cont ain LinkSec encapsulat ion as well as packet s
t hat do not include LinkSec encapsulat ion. This sect ion describes t he t ransmit packet classificat ion,
t ransmit descript ors and st at ist ic count ers.
Not e: Since flow cont rol ( PAUSE) packet s are part of t he MAC service t hey should not go t hrough
t he LinkSec logic.
1. Assign t he frame t o an SA by adding t he AN according t o SA select bit in t he LSECTXSA regist er.
2. Assign t he next PN variable for t hat SA t o be used as t he value of t he PN in t he SecTAG based on
t he value in t he appropriat e ( according t o SA) LSECTXPN regist er.
3. Encode t he oct et s of t he SecTAG according t o t he set t ing in LSECTXCTRL regist er.
4. Provide t he prot ect ion funct ion of t he current cipher suit e wit h:
a. The SA Key ( SAK) .
b. The SCI for t he SC used by t he SecY t o t ransmit .
c. The PN.
d. The SecTAG.
e. The sequence of oct et s t hat compose t he user dat a.
5. Receive t he following paramet ers from t he cipher suit e prot ect ion operat ion:
a. The sequence of oct et s t hat compose t he secure dat a.
b. The I CV.
6. I ssue a request t o t he t ransmit mult iplexer wit h t he dest inat ion and source Et hernet MAC
addresses, and priorit y of t he frame as received from t he cont rolled port , and an MPDU comprising
t he oct et s of t he SecTAG, secure dat a, and t he I CV concat enat ed in t hat order.
7. 8. 5. 1 Tr ansmi t SA Ex haust i ng Re- Key i ng
t he 82599 support s a single SC on t he t ransmit dat a pat h wit h a seamless re- keying mechanism. The
SC might act wit h one of t wo opt ional SAs. The SA is select ed st at ically by t he Act ive SA field in t he
LSECTXSA regist er. Once t he KaY ent it y ( could be eit her soft ware or hardware as defined by t he
LinkSec Ownership field in t he LSWFW regist er) changes t he set t ing of t he SA Select field in t he
LSEXTXSA regist er t he Act ive SA field is get t ing t he same value on a packet boundary. The next packet
t hat is processed by t he t ransmit LinkSec engine uses t he updat ed SA.
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354
The KaY should swit ch bet ween t he t wo SAs before t he PN is exhaust ed. I n order t o prot ect against
such event , hardware generat es a LinkSec packet number int errupt t o KaY when t he PN reaches t he
exhaust ion t hreshold as defined in t he LSECTXCTRL regist er. The exhaust ion t hreshold should be set t o
a level t hat enables t he KaY t o swit ch bet ween SAs fast er t hen t he PN might be exhaust ed. I f t he KaY
is slower t han it should be, t hen t he PN might be increment above planned. Hardware guarant ees t hat
t he PN never repeat s it self, even if t he KaY is slow. Once t he PN reaches a value of 0xFFF0, hardware
clears t he Enable Tx LinkSec field in t he LSECTXCTRL regist er t o 00b. Clearing t he Enable Tx LinkSec
field, hardware disables LinkSec offload before t he PN could wrap around and t hen might repeat it self.
Not e: Pot ent ial race condit ions are possible as follows. t he 82599 might fet ch a t ransmit packet
( indicat ed as TxPacket N) from t he host memory ( host or manageabilit y cont roller packet ) .
KaY can change t he set t ing of t he Tx SA I ndex. The TxPacket N can use t he new TX SA I ndex
if t he TX SA index was updat ed before t he TxPacket N propagat ed t o t he t ransmit LinkSec
engine. This race is not crit ical since t he receiving node should be able t o process t he
previous SA as well as t he new SA in t he re- keying t ransit ion period.
7. 8.5. 2 Tr ansmi t SA Cont ex t
Upon t ransmission of a secured frame, t he SA associat ed dat a is insert ed int o t he SecTag field of t he
frame. The SecTag dat a is composed from t he LinkSec Tx regist ers. The SCI value is t aken from LinkSec
TX SCI Low and High regist ers unless inst ruct ed t o omit SCI . The AN value is t aken from t he act ive
LinkSec TX SA and t he PN from t he appropriat e LinkSec TX SA PN.
7. 8. 5. 3 Tr ansmi t St at i st i c Count er s
A det ailed list and descript ion of t he LinkSec TX st at ist ics count ers can found in Sect ion 8.2. 3. 13.
7.8.6 Li nk Sec and Manageabi l i t y
See Sect ion 10. 4.
7.8.7 Key and Tamper Pr ot ect i on
LinkSec provides t he net work administ rat or prot ect ion t o t he net work infrast ruct ure from host ile or
unaut horized devices. Since t he local host operat ing syst em can it self be compromised, hardware
prot ect s vit al LinkSec cont ext from soft ware access. There are t wo levels of prot ect ion:
Disable host read access t o t he LinkSec Keys ( keys are writ e- only)
Disable host access t o LinkSec logic while t he firmware manages t he LinkSec SC.
7. 8.7. 1 Key Pr ot ect i on
The LinkSec keys are prot ect ed against read accesses at all t imes. Bot h soft ware and firmware are not
able t o read back t he keys t hat hardware uses for t ransmit and receive act ivit y. I nst ead, hardware
enables t he soft ware and firmware reading a signat ure enabling t o verify proper programming of t he
device. The signat ure is a byt e XOR operat ion of t he Tx and Rx keys readable in t he LSECTXSUM and
LSECRXSUM fields in t he LSECCAP regist er.

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7.8.7.2 Tamper Pr ot ect i on
I n a scenario where t he host failed aut hent icat ion and as a result cannot act as t he KaY, t he
manageabilit y cont roller disables t he host access t o net work and manages t he LinkSec channel while
t he host operat ing syst em is already up and running. I n such cases, hardware provides t he required
hooks t o prot ect LinkSec connect ivit y against host ile soft ware. The manageabilit y cont roller firmware
can disable writ e accesses generat ed by t he host CPU ( on t he PCI int erface) by set t ing t he Lock LinkSec
Logic ( bit 12) bit in t he LSWFW regist er. Set t ing t his bit can generat e an int errupt t o t he host in case it
is enabled by t he host in t he I MS regist er.
7. 8. 8 Li nk Sec St at i st i cs
7.8.8.1 Rx St at i st i cs
Aft er receiving a packet , one and only one of t he st at ist ics in Table 7. 65 applies. The precedence order
of t he st at ist ics is also defined in Table 7.65.
Tabl e 7. 65. Rx St at i st i cs
Regi st er Name 802. 1ae Name Pr i or i t y Not es
LSECRXBAD I nPkt sBadTag 2
Packet is dropped in st rict mode or in check mode when t he C bit is
one.
LSECRXUNSCI I nPkt sUnknownSCI 3
Used only in check mode. Packet is forwarded t o t he host if t he C bit is
zero.
LSECRXNOSCI I nPkt sNoSCI 3
one.
LSECRXUNSA I nPkt sUnusedSA 4
one. Not e: This st at ist ic reflect s t he sum of I nPkt sUnusedSA for all SAs.
LSECRXNUSA I nPkt sNot UsingSA 4
zero. Not e: This st at ist ic reflect s t he sum of I nPkt sUnusedSA for all
SAs.
LSECRXLATE I nPkt sLat e 5
n/ a I nPkt sOverrun n/ a
The 82599 support s wire- speed decrypt ion and t hus t his st at ist ic is not
needed.
LSECRXNV[ SA# ] I nPkt sNot Valid 6
one.
LSECRXI NV[ SA# ] I nPkt sI nvalid 6
zero.
LSECRXDELAY I nPkt sDelayed 7
GPRC I nPkt sUnchecked n/ a
This st at ist ic is relevant only in bypass mode. I n t his case, t his st at ist ic
is reflect ed in t he regular GPRC st at ist ic.
LSECRXOK[ SA# ] I nPkt sOK 8
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7.9 Ti me SYNC ( I EEE1588 and 802.1AS)
7.9.1 Ov er v i ew
Measurement and cont rol applicat ions are increasingly using dist ribut ed syst em t echnologies such as
net work communicat ion, local comput ing, and dist ribut ed obj ect s. Many of t hese applicat ions are
enhanced by having an accurat e syst em- wide sense of t ime achieved by having local clocks in each
sensor, act uat or, or ot her syst em device. Wit hout a st andardized prot ocol for synchronizing t hese
clocks, it is unlikely t hat t he benefit s are realized in t he mult i- vendor syst em component market .
Exist ing prot ocols for clock synchronizat ion are not opt imum for t hese applicat ions. For example,
Net work Time Prot ocol ( NTP) t arget s large dist ribut ed comput ing syst ems wit h Millisecond ( ms)
synchronizat ion requirement s. The 1588 st andard specifically addresses t he needs of measurement and
cont rol syst ems:
Spat ially localized
Microsecond ( s) t o sub- s accuracy
Administ rat ion free
Accessible for bot h high- end devices and low- cost , low- end devices
Not e: The t ime sync mechanism act ivat ion is possible in full- duplex mode only. There are no
limit at ions on t he wire speed alt hough t he wire speed might affect t he accuracy.
7.9.2 Fl ow and Har dw ar e/ Sof t w ar e Responsi bi l i t i es
The operat ion of a Precision Time Prot ocol ( PTP) enabled net work is divided int o t wo st ages:
init ializat ion and t ime synchronizat ion.
At t he init ializat ion st age, every mast er- enabled node st art s by sending sync packet s t hat include t he
clock paramet ers of it s clock. Upon receipt of a sync packet , a node compares t he received clock
paramet ers t o it s own and if t he received paramet ers are bet t er, t hen t his node moves t o a slave st at e
and st ops sending sync packet s. While in slave st at e, t he node cont inuously compares t he incoming
packet t o it s current ly chosen mast er and if t he new clock paramet ers are bet t er, t han t he mast er
select ion is t ransferred t o t his mast er clock. Event ually t he best mast er clock is chosen. Every node has
a defined t imeout int erval t hat if no sync packet was received from it s chosen mast er clock it moves
back t o a mast er st at e and st art s sending sync packet s unt il a new best mast er clock ( PTP) is chosen.
The t ime synchronizat ion st age is different t o mast er and slave nodes. I f a node is in a mast er st at e it
should periodically send a sync packet t hat is t ime st amped by hardware on t he TX pat h ( as close as
possible t o t he PHY) . Aft er t he sync packet , a Follow_Up packet is sent t hat includes t he value of t he
t ime st amp kept from t he sync packet . I n addit ion, t he mast er should t ime st amp Delay_Req packet s
on it s Rx pat h and ret urn t o t he slave t hat sent t he t ime st amp value using a Delay_Response packet . A
node in a slave st at e should t ime st amp every incoming sync packet and if it came from it s select ed
mast er, soft ware uses t his value for t ime offset calculat ion. I n addit ion, it should periodically send
Delay_Req packet s in order t o calculat e t he pat h delay from it s mast er. Every sent Delay_Req packet
sent by t he slave is t ime st amped and kept . Wit h t he value received from t he mast er wit h
Delay_Response packet , t he slave can now calculat e t he pat h delay from t he mast er t o t he slave. The
synchronizat ion prot ocol flow and t he offset calculat ion are shown in Figure 7. 36.

357
Hardware responsibilit ies are:
1. I dent ify t he packet s t hat require t ime st amping.
2. Time st amp t he packet s on bot h Rx and Tx pat hs.
3. St ore t he t ime st amp value for soft ware.
4. Keep t he syst em t ime in hardware and give a t ime adj ust ment service t o soft ware.
5. Maint ain auxiliary feat ures relat ed t o t he syst em t ime.
Soft ware responsibilit ies are:
1. Manageabilit y cont roller prot ocol execut ion, which means defining t he node st at e ( mast er or slave)
and select ion of t he mast er clock if in slave st at e.
2. Generat e PTP packet s, consume PTP packet s.
3. Calculat e t he t ime offset and adj ust t he syst em t ime using a hardware mechanism for t hat .
4. Enable configurat ion and usage of t he auxiliary feat ures.
Fi gur e 7.36. Sync Fl ow and Of f set Cal cul at i on
Act i on Responsi bi l i t y Node Rol e
Generat e a sync packet wit h t ime st amp not if icat ion in t he descript or. Soft ware Mast er
Time st amp t he packet and st ore t he value in regist ers ( T1) . Hardware Mast er
Time st amp incoming sync packet , st ore t he value in regist er and st ore t he sourceI D and
sequenceI D in regist ers ( T2) .
Hardware Slave
Read t he t ime st amp from regist er put in a Follow_Up packet and send. Soft ware Mast er
Once received, t he Follow_Up st ore T2 from regist ers and T1 from Follow_up packet . Soft ware Slave
Generat e a Delay_Req packet wit h t ime st amp not ificat ion in t he descript or. Soft ware Slave
Time st amp t he packet and st ore t he value in regist ers ( T3) . Hardware Slave
Sync
Follow_Up(T1)
Delay_Response(T4)
Dely_Req
Mast er Slave
T1
T2
T3
T4
Calculat ed delt a T = [ (T2-T1)-(T4-T3)] / 2 ; assuming symmet ric t ransmission delays
Toffset = - delt a T ; offset at t he Slave
T0 + delt a T T0
Mast er t o Slave
Transmission delay
Follow_Up(T3)
Slave t o Mast er
Transmission delay
T1, T2, T3 and T4
are sampled by t he HW
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358
7. 9. 2. 1 Ti meSy nc I ndi cat i ons i n Rx and Tx Pack et Descr i pt or s
Some indicat ions need t o be t ransferred bet ween soft ware and hardware regarding PTP packet s. On t he
Tx pat h, soft ware should set t he 1588 bit in t he Tx packet descript or ( bit 9) . On t he Rx pat h, hardware
has t wo indicat ions t o t ransfer t o soft ware, one is t o indicat e t hat t his packet is a PTP packet ( whet her
t ime st amp is t aken or not ) . This is also for ot her t ypes of PTP packet s needed for management of t he
prot ocol and t his bit is set only for t he L2 t ype of packet s ( t he PTP packet is ident ified according t o it s
Et hert ype) . PTP packet s have t he L2Type bit in t he packet t ype field set ( bit 9) and t he Et hert ype
mat ches t he filt er number set by soft ware t o filt er PTP packet s. The UDP t ype of PTP packet s dont need
such indicat ion since t he port number ( 319 for event and 320 all t he rest PTP packet s) direct s t he
packet s t oward t he t ime sync applicat ion. The second indicat ion is TS ( bit 14) t o indicat e t o soft ware
t hat t ime st amp was t aken for t his packet . Soft ware needs t o access t he t ime st amp regist ers t o get t he
t ime st amp values.
7.9.3 Har dw ar e Ti me Sy nc El ement s
All t ime sync hardware element s are reset t o t heir init ial values ( as defined in Sect ion 8. 0) upon MAC
reset . The clock driving t he t ime sync element s is t he DMA clock which frequency depends on t he link
speed. Upon change in link speed some of t he t ime sync paramet ers should be changed accordingly. For
det ails please see Table 7.66.
7. 9. 3. 1 Sy st em Ti me St r uct ur e and Mode of Oper at i on
The t ime sync logic cont ains an up count er t o maint ain t he syst em t ime value. This is a 64- bit count er
t hat is built from t he SYSTI ML and SYSTI MH regist ers. When operat ing as a mast er, t he SYSTI MH and
SYSTI ML regist ers should be set once by soft ware according t o t he general syst em. When operat ing as
a slave, soft ware should updat e t he syst em t ime on every sync event as described in Sect ion 7. 9. 3. 3.
Set t ing t he syst em t ime is done by a direct writ e t o t he SYSTI MH regist er and a fine t une set t ing of t he
SYSTI ML regist er using t he adj ust ment mechanism described in Sect ion 7. 9.3.3.
Read access t o t he SYSTI MH and SYSTI ML regist ers should execut e in t he following manner:
1. Soft ware reads regist er SYSTI ML, at t his st age hardware should lat ch t he value of SYSTI MH.
2. Soft ware reads regist er SYSTI MH, t he lat ched ( from last read from SYSTI ML) value should be
ret urned by hardware.
Upon an increment event , t he syst em t ime value should increment it s value by t he value st ored in
TI MI NCA.incvalue. An increment event happens every TI MI NCA.incperiod cycle if it s one t hen an
increment event should occur on every clock cycle. The incvalue defines t he granularit y in which t he
t ime is represent ed by t he SYSTMH/ L regist ers. For example, if t he cycle t ime is 16 ns and t he incperiod
is one t hen and t he incvalue is 16 t hen t he t ime is represent ed in nanoseconds if t he incvalue is 160
t hen t he t ime is represent ed in 0.1 ns unit s and so on. The incperiod helps t o avoid inaccuracy in cases
where T value cannot be represent ed as a simple int eger and should be mult iplied t o get t o an int eger
represent at ion. The incperiod value should be as small as possible t o achieve best accuracy possible.
Time st amp incoming Delay_Req packet , st ore t he value in regist er and st ore t he sourceI D
and sequenceI D in regist ers ( T4) .
Hardware Mast er
Read t he t ime st amp from regist er and send back t o slave using a Delay_Response packet . Soft ware Mast er
Once received, t he Delay_Response packet calculat e offset using T1, T2, T3 and T4 values. Soft ware Slave
Act i on Responsi bi l i t y Node Rol e

359
Not e: Best accuracy is achieved at lowest permit t ed I ncperiod equals t wo and as high as possible
I ncvalue.
7. 9. 3. 2 Ti me St ampi ng Mechani sm
The t ime st amping logic is locat ed as close as possible t o t he PHY. Figure 7.37 shows t he exact point in
t ime where t he t ime value is capt ured by t he hardware relat ive t o t he packet cont ent . This is t o reduce
delay uncert aint ies originat ed from implement at ion differences. While t he t ime st amp is sampled at a
very lat e phase in t he dat a pat h, t he 82599 does not insert it t o t he t ransferred packet . I nst ead, t he
82599 support s t he t wo- st ep operat ion as follows for Tx and Rx.
Tx t i me st ampi ng
The t ime st amp logic is act ivat ed if enabled by t he TSYNCTXCTL.EN bit and t he t ime st amp bit in t he
packet descript or is set . I n t his case, hardware capt ures t he packet ' s t ransmission t ime in t he TXSTMPL
and TXSTMPH regist ers. Soft ware is responsible t o read t he t ransmission t ime and append it in t he
Folow_Up packet as shown in Figure 7.36.
Rx t i me st ampi ng
On t he Rx, t his logic parses t he t raversing frame. I f it is mat ching t he message t ype defined in RXMTRL
regist er, t he following packet ' s paramet ers are lat ched: The recept ion t ime st amp is st ored in t he
RXSTMPL and RXSTMPH regist ers. The SourceuuI D and SequenceI D are st ored in t he RXSATRL and
RXSATRH regist ers. I n addit ion, t wo st at us bit s are report ed in t he Rx descript or: PTP packet indicat ion
( t his bit is set only for L2 packet s since on t he UDP packet s t he port number direct t he packet t o t he
applicat ion) and t he TS bit t o ident ify t hat a t ime st amp was t aken for t his packet ( st ored in t he
RXSTMPL and RXSTMPH regist ers) .
Not e: The t ime st amp values are locked in t he RXSTMPL and RXSTMPH regist ers unt il soft ware
accesses t hem. As long as soft ware does not read t hese regist ers, hardware does not capt ure
t he t ime st amp of furt her Rx packet s. I n order t o avoid pot ent ial deadlocks, it is
recommended t hat soft ware read t he Rx t ime st amp regist ers at some t ime aft er sync or
Delay_Req packet s are expect ed. I t would overcome erroneous cases on which t he hardware
lat ches a packet recept ion t ime while t he packet ' s cont ent was not posed properly t o t he
soft ware.
Recept ion consecut ive packet s t hat are able t o lat ch it s recept ion t ime st amp are not
support ed by t he 82599. The RXSATRL and RXSATRH regist ers may not cont ain sufficient
informat ion t o ident ify uniquely a specific client . Therefore, Mast er soft ware must not init iat e
consecut ive sync request s before t he previous response is received.
Tabl e 7. 66. Recommended Val ues f or i ncval ue and i ncper i od and t he out come SYSTI ME
Li nk Speed Cl ock Fr equency
Recommended
I ncv al ue
Recommended
I ncper i od
SYSTI ML / SYSTI MH
Ti me Uni t s
SYSTI ML / SYSTI MH
Gr anul ar i t y
10 Gb/ s 156. 25 MHz
16000000
( 0xF42400)
2 0. 8 x 10
- 15
12. 8 ns
1 Gb/ s 15. 625 MHz 16000000 2 8 x 10
- 15
128 ns
100 Mb/ s 1. 5625 MHz 16000000 2 80 x 10
- 15
1. 28 s
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7. 9. 3. 3 Ti me Adj ust ment Mode of Oper at i on
A node in a t ime sync net work can be in one of t wo st at es: mast er or slave. When a t ime sync ent it y is
in a mast er st at e, it should synchronize ot her ent it ies t o it s syst em clock. I n t his case, no t ime
adj ust ment s are needed. When t he ent it y is in slave st at e, it should adj ust it s syst em clock by using t he
dat a arrived wit h t he Follow_Up and Delay_Response packet s and t o t he t ime st amp values of Sync and
Delay_Req packet s. When having all t he values soft ware on t he slave ent it y can calculat e it s offset in
t he following manner.
Aft er an offset calculat ion, t he syst em t ime regist er should be updat ed. This is done by writ ing t he
calculat ed offset t o TI MADJL and TI MADJH regist ers. The order should be as follows:
1. Writ e t he lower port ion of t he offset t o TI MADJL.
2. Writ e t he high port ion of t he offset t o TI MADJH t o t he lower 31 bit s and t he sign t o t he most
significant bit .
Aft er t he writ e cycle t o TI MADJH t he value of TI MADJH and TI MADJL should be added t o t he syst em
t ime.
7.9.4 Ti me Sy nc Rel at ed Aux i l i ar y El ement s
The t ime sync logic implement s t hree t ypes of auxiliary element using t he precise syst em t imer and
SDPs. The t ime sync block implement s t wo of each feat ures while t he possible opt ions of connect ing
t hem t o SDPs are:
Select ing t he SDP funct ionalit y is done by programming t he TimeSync Auxiliary cont rol regist er and t he
Ext ended SDP Cont rol regist er.
7. 9.4. 1 Tar get Ti me
The t arget t ime regist er is used t o get a t ime t riggered event t o hardware using an SDP pin. Each t arget
t ime regist er is st ruct ured t he same as t he syst em t ime regist er. I f t he value of t he syst em t ime is
equal t o t he value writ t en t o one of t he t arget t ime regist ers, a change in level occurs on one t he
select ed SDP out put s. The accuracy of t he comparison is defined by t he value of Mask field in t he
TSAUXC regist er. The t arget t ime regist er also can be used for adj ust ment of t he configurable clock out .
Fi gur e 7.37. Ti me St amp Poi nt
SDP2 Time St amp 0 Time St amp 0 Target Time 1 Time St amp 0 Time St amp 0 Time St amp 0
SDP3 Time St amp 1 Target Time 0 Target Time 0 Time St amp 1 Time St amp 1 Target Time 0
SDP6 CLK0 CLK0 CLK0 Target Time 1 Target Time 1 Target Time 1
SDP7 CLK1 CLK1 CLK1 CLK1 Target Time 0 CLK1

361
Each t arget t ime regist er has an enable bit locat ed in t he Auxiliary Cont rol regist er. Aft er receiving a
t arget t ime event , t he enable bit is cleared and needs t o be set again by soft ware t o get anot her t arget
t ime event .
7.9.4.2 Ti me St amp Ev ent s
Aft er a change in level of an input from one of t he SDP pins, a t ime st amp of t he syst em t ime is
capt ured int o one of t he t wo auxiliary t ime st amp regist ers.
7. 9. 5 PTP Pack et St r uct ur e
The t ime sync implement at ion support s bot h t he 1588 V1 and V2 PTP frame format s. The V1 st ruct ure
can come only as UDP payload over I Pv4 while t he V2 can come over L2 wit h it s Et hert ype or as a UDP
payload over I Pv4 or I Pv6. The 802.1AS uses only t he layer 2 V2 format . Not e t hat PTP frame st ruct ure
over UDP is not support ed in t he 82599 for I P t unneling packet s.
Of f set i n By t es V1 Fi el ds V2 Fi el ds
Bit s 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0
v er si onPTP
t ransport Specific
1
messageI d
1 Reserved v er si onPTP
2
versionNet work messageLengt h
3
4
Subdomain
SubdomainNumber
5 Reserved
6
flags
7
8
Correct ion Field
9
10
11
12
13
14
15
16
reserved
17
18
19
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Not e: Only t he fields wit h t he bold it alic format colored red are of int erest t o hardware.
When a PTP packet is recognized ( by Et hert ype or UDP port address) on t he Rx side t he version should
be checked if it is V1 t hen t he cont rol field at offset 32 should be compared t o message field in regist er
described in Sect ion 8. 2. 3.26. 6, ot herwise t he byt e at offset 0 should be used for comparison t o t he
rest of t he needed field are at t he same locat ion and size for bot h V1 and V2.
20 messageType
Sour ce Por t I D
( only part of t he field is capt ured in t he RXSATRL and
RXSATRH regist ers)
21 Source communicat ion t echnology
22
Sour ceuui d
23
24
25
26
27
28
sourceport id
29
30
sequenceI d sequenceI d
31
32 cont r ol cont rol
33 reserved logMessagePeriod
34
falgs n/ a
35
1. Should all be zero.
Et hernet ( L2) VLAN ( Opt ional) PTP Et hert ype PTP message
Et hernet ( L2) I P ( L3) UDP PTP message
Enumer at i on Val ue
PTP_SYNC_MESSAGE 0
PTP_DELAY_REQ_MESSAGE 1
PTP_FOLLOWUP_MESSAGE 2
PTP_DELAY_RESP_MESSAGE 3
PTP_MANAGEMENT_MESSAGE 4
reserved 5255
MessageI d Message Ty pe Val ue ( hex )
PTP_SYNC_MESSAGE Event 0
PTP_DELAY_REQ_MESSAGE Event 1
PTP_PATH_DELAY_REQ_MESSAGE Event 2
Of f set i n By t es V1 Fi el ds V2 Fi el ds
Bit s 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

363
I f V2 mode is configured in Sect ion 8. 2.3.26.15,t hen t ime st amp should be t aken on
PTP_PATH_DELAY_REQ_MESSAGE and PTP_PATH_DELAY_RESP_MESSAGE for any value in t he
message field in t he regist er described at Sect ion 8.2. 3. 26. 6.
PTP_PATH_DELAY_RESP_MESSAGE Event 3
Unused 4- 7
PTP_FOLLOWUP_MESSAGE General 8
PTP_DELAY_RESP_MESSAGE General 9
PTP_PATH_DELAY_FOLLOWUP_MESSAGE General A
PTP_ANNOUNCE_MESSAGE General B
PTP_SI GNALLI NG_MESSAGE General C
PTP_MANAGEMENT_MESSAGE General D
Unused E- F
MessageI d Message Ty pe Val ue ( hex )
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7.10 Vi r t ual i zat i on
7.10. 1 Over vi ew
I / O virt ualizat ion is a mechanism t hat can be used t o share I / O resources among several consumers.
For example, in a virt ual syst em, mult iple operat ing syst ems are loaded and each operat es as t hough
t he ent ire syst em' s resources were at it s disposal. However, for t he limit ed number of I / O devices, t his
present s a problem because each operat ing syst em might be in a separat e memory domain and all t he
dat a movement and device management has t o be done by a Virt ual Machine Monit or ( VMM) . VMM
access adds lat ency and delay t o I / O accesses and degrades I / O performance. Virt ualized devices are
designed t o reduce t he burden of t he VMM by making cert ain funct ions of an I / O device shared among
mult iple guest operat ing syst ems or a Virt ual Machine ( VM) , t hereby allowing each VM direct access t o
t he I / O device.
The 82599 support s t wo modes of operat ions of virt ualized environment s:
1. Direct assignment of part of t he port resources t o different guest operat ing syst ems using t he PCI
SI G SR I OV st andard. Also known as nat ive mode or pass t hrough mode. This mode is referenced
as I OV mode t hroughout t his sect ion.
2. Cent ral management of t he net working resources by an I OVM or by t he VMM. Also known as
soft ware swit ch accelerat ion mode. This mode is referred t o as Next Generat ion VMDq mode in t his
sect ion.
The virt ualizat ion offloads capabilit ies provided by t he 82599 apart from t he replicat ion of funct ions
defined in t he PCI SI G I OV specificat ion are part of Next Generat ion VMDq.
A hybrid model, where part of t he VMs are assigned a dedicat ed share of t he port and t he rest are
serviced by an I OVM is also support ed. However, in t his case t he offloads provided t o t he soft ware
swit ch might be more limit ed. This model can be used when part s of t he VMs run operat ing syst ems for
which VF drivers are available and t hus can benefit from an I OV and ot hers t hat run older operat ing
syst ems for which VF drivers are not available and are serviced by an I OVM. I n t his case, t he I OVM is
assigned one VF and receives all t he packet s wit h Et hernet MAC addresses of t he VMs behind it .
The following sect ion describes t he support t he 82599 provides for t hese modes.
This sect ion assumes a single- root implement at ion of I OV and no support for mult i- root .
7. 10. 1. 1 Di r ect Assi gnment Model
The direct assignment support in t he 82599 is built according t o t he following model of t he soft ware
environment .
I t is assumed t hat one of t he soft ware drivers sharing t he port hardware behaves as a mast er driver
( Physical Funct ion or PF driver) . This driver is responsible for t he init ializat ion and t he handling of t he
common resources of t he port . All t he ot her drivers ( Virt ual Funct ion drivers or VF drivers) might read
part of t he st at us of t he common part s but cannot change t hem. The PF driver might run eit her in t he
VMM or in some service operat ing syst em. I t might be part of an I OVM or part of a dedicat ed service
operat ing syst em.
I n addit ion, part of t he non t ime- crit ical t asks are also handled by t he PF driver. For example, access t o
CSR t hrough t he I / O space or access t o t he configurat ion space are available only t hrough t he mast er
int erface. Time- crit ical CSR space like cont rol of t he Tx and Rx queue or int errupt handling is replicat ed
per VF, and direct ly accessible by t he VF driver.

365
Not e: I n some syst ems wit h a t hick hypervisor, t he service operat ing syst em might be an int egral
part of t he VMM. For t hese syst ems, each reference t o t he service operat ing syst em in t he
sect ions t hat follow refer t o t he VMM.
7.10.1.1.1 Rat i onal e
The direct assignment model enables each of t he VMs t o receive and t ransmit packet s wit h minimum of
overhead. Non t ime- crit ical operat ions such as init ializat ion and error handling can be done via t he PF
driver. I n addit ion, it is import ant t hat t he VMs can operat e independent ly wit h minimal dist urbance. I t
is also preferable t hat t he VM int erface t o hardware should be as close as possible t o t he nat ive
int erface in non-virt ualized syst ems in order t o minimize t he soft ware development effort .
The main t ime crit ical operat ions t hat require direct handling by t he VM are:
Maint enance of t he dat a buffers and descript or rings in host memory. I n order t o support t his, t he
DMA accesses of t he queues associat ed t o a VM should be ident ified as such on t he PCI e using a
different request er I D.
Handling of t he hardware ring ( t ail bump and head updat es)
I nt errupt s handling
The capabilit ies needed t o provide independence bet ween VMs are:
Per VM reset and enable capabilit ies
Tx rat e cont rol
Allocat ing separat e CSR space per VM. This CSR space is organized as close as possible t o t he
regular CSR space t o enable sharing of t he base driver code.
Not e: The rat e cont rol and VF enable capabilit ies are cont rolled by t he PF.
7.10. 1. 2 Sy st em Ov er v i ew
The following drawings show t he various element s involved in t he I / O process in a virt ualized syst em.
Figure 7.38 shows t he flow in soft ware Next Generat ion VMDq mode and Figure 7. 39 shows t he flow in
I OV mode.
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366
This sect ion assumes t hat in I OV mode, t he driver on t he guest operat ing syst em is aware t hat it
operat es in a virt ual syst em ( para-virt ualized) and t here is a channel bet ween each of t he VM drivers
and t he PF driver allowing message passing such as configurat ion request or int errupt messages. This
channel can use t he mailbox syst em implement ed in t he 82599 or any ot her means provided by t he
VMM vendor.
Fi gur e 7.38. Syst em Conf i gur at i on f or Nex t Gener at i on VMDq Mode
VMM
CPUs
Init +
control
IOVM
Guest
OS 1
IOH (VT-d)
Host
memory
LAN controller
Shared
part
VM-1 VM-n
Guest
OS n
SW
HW
Translated
Mem
Accesses
(VT-x)
Translated DMA
Accesses (VT-d)
IOVI
Physical
Address
Physical address
IOVI
Physical
Address
Control
VMDq queuing
Data
DMA packet
Buffers
Packet switch
Translated
Mem
Accesses
(VT-x)

367
7. 10. 2 PCI - SI G SR- I OV Suppor t
7.10. 2. 1 SR- I OV Concept s
SR- I OV defines t he following ent it ies in relat ion t o I / O virt ualizat ion:
Virt ual I mage ( VI ) : Part of t he I / O resources are assigned t o a A VM.
I / O Virt ual I nt ermediary ( I OVI ) or I / O Virt ual Machine ( I OVM) : A special VM t hat owns t he physical
device and is responsible for t he configurat ion of t he physical device.
Fi gur e 7. 39. Syst em Conf i gur at i on f or I OV Mode
Real time
Control
VMM
CPU
Init
Real time
Control
IOVM
Guest
OS 1
Host
memory
LAN Controller
Shared
part
VM-1 VM-n
Guest
OS n
SW
HW
Translated
Mem
Accesses
(VT-x)
Control
VMDq queuing
VM 1 PB
IOVM PB
VM n PB
Translated
Mem
Accesses
(VT-x)
PF
Real time
Control
IOH (VT-d)
Translated DMA
Accesses (VT-d)
Physical addresses
Guest 1
Physical
Address
Guest n
Physical
Address
Guest 1
Physical
Address
IOVM
Physical
Address
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Physical funct ion ( PF) : A funct ion represent ing a physical inst ance One port for t he 82599. The
PF driver is responsible for t he configurat ion and management of t he shared resources in t he
funct ion.
Virt ual Funct ion ( VF) : A part of a PF assigned t o a VI .
7. 10. 2. 2 Conf i gur at i on Space Repl i cat i on
The SR- I OV specificat ion defines a reduced configurat ion space for t he virt ual funct ions. Most of t he
PCI e configurat ion of t he VFs comes from t he PF.
This sect ion describes t he expect ed handling of t he different part s of t he configurat ion space for virt ual
funct ions. I t deals only wit h t he part s relevant t o t he 82599.
Det ails of t he configurat ion space for virt ual funct ions can be found in Sect ion 9.5.
7.10.2.2.1 Legacy PCI Conf i gur at i on Space
The legacy configurat ion space is allocat ed t o t he PF only and emulat ed for t he VFs. A separat e set of
BARs and one bus mast er enable bit is allocat ed in t he SR- I OV capabilit y st ruct ure in t he PF and is used
t o define t he address space used by t he ent ire set of VFs.
All t he legacy error report ing bit s are emulat ed for t he VF. See Sect ion 7. 10. 2. 4 for det ails.
7.10.2.2.2 Memor y BARs Assi gnment
The SR- I OV specificat ion defines a fixed st ride for all t he VF BARs, so t hat each VF can be allocat ed part
of t he memory BARs at a fixed st ride from t he a basic set of BARs. I n t his met hod, only t wo decoders
per replicat ed BAR per PF are required and t he BARs reflect ed t o t he VF are emulat ed by t he VMM.
The only BARs t hat are useful for t he VFs are BAR0 and BAR3, so only t hose are replicat ed. The
following t able list s t he exist ing BARs and t he st ride used for t he VFs:
BAR0 of t he VFs are a sparse version of t he original PF BAR and include only t he regist er relevant t o t he
VF. For more det ails see Sect ion 7. 10. 2.7.
Tabl e 7.67. BARs i n t he 82599 ( 64- bi t BARs)
BAR Type Usage Request ed Si ze per VF ( = St r i de)
0, 1 Mem CSR space
Maximum ( 16 KB, page size) . For page size see Sect ion 9. 4. 4. 8 for
more det ails.
2 n/ a Not used n/ a
3, 4 Mem MSI -X Maximum ( 16 KB, page size) .
5 n/ a Not used n/ a

369
The following figure shows t he different BARs in an I OV- enabled syst em:
7.10.2.2.3 PCI e Capabi l i t y St r uct ur e
The PCI e capabilit y st ruct ure is shared bet ween t he PF and t he VFs. The only relevant bit s t hat are
replicat ed are:
1. Transact ion pending
2. Funct ion Level Reset ( FLR) . See Sect ion 7.10.2.3 for det ails.
7.10.2.2.4 MSI and MSI - X Capabi l i t i es
Bot h MSI and MSI -X are implement ed in t he 82599. MSI -X vect ors can be assigned per VF. MSI is not
support ed for t he VFs.
See Sect ion 9. 3. 8. 1 for more det ails of t he MSI -X and PBA t ables implement at ion.
7.10.2.2.5 VPD Capabi l i t y
VPD is implement ed only once and is accessible only from t he PF.
7.10.2.2.6 Pow er Management Capabi l i t y
The 82599 does not support power management per VF. The power management regist ers exist for
each VF, but only t he D0 power st at e is support ed.
Fi gur e 7.40. BARs i n an I OV- enabl ed Sy st em
PF configuration space
32 bytes I/O Space
MSI-X Space
Max (16K, Page Size)
VF0 CSR Space
BAR0, BAR 1
VF BAR2 (Null)
VF BAR0, BAR1
. . .
BAR4, BAR 5
BAR3 (Null)
BAR2
VF BAR3, BAR4
VF BAR5 (Null)
. . .
128K CSR + FLASH
Space
VF63 CSR Space
. . .
VF1 CSR Space
VF0 MSI-X Space
VF63 MSI-X Space
. . .
VF1 MSI-X Space
6
4

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7.10.2.2.7 Ser i al I D
The same serial I D is report ed t o all VFs in t he 82599.
7.10.2.2.8 Er r or Repor t i ng Capabi l i t i es ( Advanced and Legacy )
All t he bit s in t his capabilit y st ruct ure are implement ed only for t he PF. Not e t hat t he VMs see an
emulat ed version of t his capabilit y st ruct ure. See Sect ion 7. 10. 2. 4 for det ails.
7. 10. 2. 3 FLR Capabi l i t y
The FLR bit is required per VF. Set t ing of t his bit reset s only a part of t he logic dedicat ed t o t he specific
VF and does not influence t he shared part of t he port . This reset should disable t he queues, disable
int errupt s and t he st op receive and t ransmit process per VF.
Set t ing t he PF FLR bit reset s t he ent ire funct ion.
7. 10. 2. 4 Er r or Repor t i ng
Error report ing includes legacy error report ing and Advanced Error Report ing ( AER) or role- based
capabilit y.
The legacy error management includes t he following funct ions:
1. Error capabilit ies enablement . These are set by t he PF for all t he VFs. Narrower error report ing for a
given VM can be achieved by filt ering of t he errors by t he VMM. This includes:
a. SERR# Enable
b. Parit y Error Response
c. Correct able Report ing Enable
d. Non- Fat al Report ing Enable
e. Fat al Report ing Enable
f. UR Report ing Enable
2. Error st at us in t he configurat ion space. These should be set separat ely for each VF. This includes:
a. Mast er Dat a Parit y Error
b. Signaled Target Abort
c. Received Target Abort
d. Mast er Abort
e. SERR# Assert ed
f. Det ect ed Parit y Error
g. Correct able Error Det ect ed
h. Non- Fat al Error Det ect ed
i. Unsupport ed Request Det ect ed
AER capabilit y includes t he following funct ions:
1. Error capabilit ies enablement . The Error Mask, and Severit y bit s are set by t he PF for all t he VFs.
Narrower error report ing for a given VM can be achieved by filt ering of t he errors by t he VMM.
These includes:
a. Uncorrect able Error Mask Regist er
b. Uncorrect able Error Severit y Regist er

371
c. Correct able Error Mask Regist er
d. ECRC Generat ion Enable
e. ECRC Check Enable
2. Non- Funct ion Specific Errors St at us in t he configurat ion space.
a. Non- Funct ion Specific Errors are logged in t he PF
b. Error logged in one regist er only
c. VI avoids t ouching all VFs t o clear device level errors
d. The following errors are not funct ion specific
All Physical Layer errors
All Link Layer errors
ECRC Fail
UR, when caused by no funct ion claiming a TLP
Receiver Overflow
Flow Cont rol Prot ocol Error
Malformed TLP
Unexpect ed Complet ion
3. Funct ion Specific Errors St at us in t he configurat ion space.
a. Allows Per VF error det ect ion and logging
b. Help wit h fault isolat ion
c. The following errors are funct ion specific
Poisoned TLP received
Complet ion Timeout
Complet er Abort
UR, when caused by a funct ion t hat claims a TLP
ACS Violat ion
4. Error logging. Each VF has it s own header log.
5. Error messages. I n order t o ease t he det ect ion of t he source of t he error, t he error messages
should be emit t ed using t he request er I D of t he VF in which t he error occurred.
7. 10. 2. 5 Al t er nat i v e Rout i ng I D ( ARI ) and I OV Capabi l i t y St r uct ur es
I n order t o allow more t han eight funct ions per end point wit hout request ing an int ernal swit ch, as
usually needed in virt ualizat ion scenarios, t he PCI - SI G defines t he ARI capabilit y st ruct ure. This is a
new capabilit y t hat enables an int erpret at ion of t he Device and Funct ion fields as a single ident ificat ion
of a funct ion wit hin t he bus. I n addit ion, a new st ruct ure used t o support t he I OV capabilit ies report ing
and cont rol is defined. Bot h st ruct ures are described in sect ions Sect ion 9. 4. 3 and Sect ion 9.4.4. Refer
t o t he following sect ion for det ails on t he Request er I D ( RI D) allocat ion t o VFs.
7.10. 2. 6 RI D Al l ocat i on
RI D allocat ion of t he VF is done using t he Offset field in t he I OV st ruct ure. This field should be
replicat ed per VF and is used t o do t he enumerat ion of t he VFs.
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372
Each PF includes an offset t o t he first associat ed VF. This point er is a relat ive offset t o t he Bus/ Device/
Funct ion ( BDF) of t he first VF. The Offset field is added t o PFs request er I D t o det ermine t he request er
I D of t he next VF. An addit ional field in t he I OV capabilit y st ruct ure describes t he dist ance bet ween t wo
consecut ive VFs request er I Ds.
7.10.2.6.1 BDF Lay out
7.10.2.6.1.1 ARI Mode
ARI allows int erpret at ion of t he device I D part of t he RI D as part of t he funct ion I D inside a device.
Thus, a single device can span up t o 256 funct ions. I n order t o ease t he decoding, t he least significant
bit of t he funct ion number point s t o t he physical port number. The Next bit s indicat e t he VF number.
The following t able list s t he VF RI Ds.
The layout of RI Ds used by t he 82599 is report ed t o t he operat ing syst em via t he PCI e I OV capabilit y
st ruct ure. See Sect ion 9. 4. 4.6.

7.10.2.6.1.2 Non- ARI Mode
When ARI is disabled, non-zero devices in t he first bus cannot be used, t hus a second bus is needed t o
provide enough RI Ds. I n t his mode, t he RI D layout is as follows:
Tabl e 7.68. RI D per VF ARI Mode
Por t VF# B, D, F Bi nar y Not es
0 PF B, 0, 0 B, 00000, 000 PF
1 PF B, 0, 1 B, 00000, 001 PF
0 0 B, 16, 0 B, 10000, 000
Offset t o first VF
from PF is 128.
1 0 B, 16, 1 B, 10000, 001
0 1 B, 16, 2 B, 10000, 010
1 1 B, 16, 3 B, 10000, 011
0 2 B, 16, 4 B, 10000, 100
1 2 B, 16, 5 B, 10000, 101
. . .
0 63 B, 31, 6 B, 11111, 110
1 63 B, 31, 7 B, 11111, 111 Last
Tabl e 7.69. RI D per VF Non- ARI Mode
0 PF B, 0, 0 B, 00000, 000 PF
1 PF B, 0, 1 B, 00000, 001 PF
0 0 B+ 1, 16, 0 B+ 1, 10000, 000
Offset t o first VF
from PF is 384.
1 0 B+ 1, 16, 1 B+ 1, 10000, 001
0 1 B+ 1, 16, 2 B+ 1, 10000, 010
1 1 B+ 1, 16, 3 B+ 1, 10000, 011
0 2 B+ 1, 16, 4 B+ 1, 10000, 100
1 2 B+ 1, 16, 5 B+ 1, 10000, 101

373
Not e: When t he device I D of a physical funct ion changes ( because of LAN disable or LAN funct ion
select set t ings) , t he VF device I Ds changes accordingly.
7. 10. 2. 7 Har dw ar e Resour ces Assi gnment
The main resources t o allocat e per VM are queues and int errupt s. The assignment is st at ic. I f a VM
requires more resources, it might be allocat ed t o more t han one VF. I n t his case, each VF get s a specific
Et hernet MAC address/ VLAN t ag in order t o enable forwarding of incoming t raffic. The t wo VFs are t hen
t eamed in soft ware.
7.10.2.7.1 PF Resour ces
A possible use of t he PF is for a configurat ion set t ing wit hout t ransmit and receive capabilit ies. I n t his
case, it is not allocat ed t o any queues but is allocat ed t o one MSI -X vect or.
The PF has access t o all t he resources of all VMs, but it is not expect ed t o make use of resources
allocat ed t o act ive VFs.
7.10.2.7.2 Assi gnment of Queues t o VF
See Sect ion 7. 2. 1. 2.1 for allocat ing Tx queues.
See Sect ion 7. 1. 2. 2 for allocat ing Rx queues.
The following t able list s t he Tx and Rx queues t o VF allocat ion.
7.10.2.7.3 Assi gnment of MSI - X Vect or t o VF
See Sect ion 7. 3. 4. 3 for allocat ing MSI -X vect ors in I OV mode.
. . .
0 63 B+ 1, 31, 6 B+ 1, 11111, 110
1 63 B+ 1, 31, 7 B+ 1, 11111, 111 Last
Tabl e 7. 70. Queue t o VF Al l ocat i on
VF Queues i n 16 VMs Mode Queues i n 32 VMs Mode Queues i n 64 VMs Mode
0 0- 7 0- 3 0- 1
1 8- 15 4- 7 2- 3
. . . . . . . . . . . .
15 120- 127 . . . . . .
. . . . . . . . .
31 124- 127 . . .
. . . . . .
63 126- 127
Tabl e 7. 69. RI D per VF Non- ARI Mode
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7. 10. 2. 8 CSR Or gani zat i on
CSRs can be divided int o t hree t ypes:
Global Configurat ion regist ers t hat should be accessible only t o t he PF. For example, link cont rol and
LED cont rol. These t ypes of regist ers also include all of t he debug feat ures such as t he mapping of
t he packet buffers and is responsible for most of t he CSR area request ed by t he 82599. This
includes per VF configurat ion paramet ers t hat can be set by t he PF wit hout performance impact .
Per-VF paramet ers For example, per VF reset , int errupt enable, et c. Mult iple inst ances of t hese
paramet ers are used only in an I OV syst em and only one inst ance is needed for non I OV syst ems.
Per- queue paramet ers t hat should be replicat ed per queue For example, head, t ail, Rx buffer
size, DCA t ag, et c. These paramet ers are used by bot h a VF in an I OV syst em and by t he PF in a
non- I OV mode.
I n order t o support I OV wit hout dist ribut ing t he current drivers operat ion in legacy mode, t he following
met hod is used:
The PF inst ance of BAR0 cont inues t o cont ain t he legacy and cont rol regist ers. I t is accessible only
t o t he PF. The BAR enables access t o all t he resources including t he VF queues and ot her VF
paramet ers. However, it is expect ed t hat t he PF driver does not access t hese queues in I OV mode.
The VF inst ances of BAR0 provide cont rol on t he VF specific regist ers. These BARs have t he same
mapping as t he original BAR0 wit h t he following except ions:
a. Fields relat ed t o t he shared resources are reserved.
b. The queues assigned t o a VF are mapped at t he same locat ion as t he first same number of
queues of t he PF.
Assuming some backward compat ibilit y is needed for I OV drivers, The PF/ VF paramet ers block
should cont ain a part ial regist er set as described in Sect ion 8.3.
7. 10. 2. 9 SR I OV Cont r ol
I n order t o cont rol t he I OV operat ion, t he physical driver is provided wit h a set of regist ers. These
include:
The mailbox mechanism described in t he next sect ion.
The swit ch and filt ering cont rol regist ers described in Sect ion 7.10.3.10.
PFVFLRE regist er indicat ing t hat a VFLR reset occurred in one of t he VFs ( bit map) .
7.10.2.9.1 VF- t o- PF Mai l box
The VF drivers and t he PF driver require some means of communicat ion bet ween t hem. This channel
can be used for t he PF driver t o send st at us updat es t o t he VFs ( such as link change, memory parit y
error, et c. ) or for t he VF t o send request s t o t he PF ( add t o VLAN) .
Such a channel can be implement ed in soft ware, but requires enablement by t he VMM vendors. I n
order t o avoid t he need for such an enablement , t he 82599 provides such a channel t hat enables direct
communicat ion bet ween t he t wo drivers.
The channel consist s of a mailbox. Each driver can t hen receive an indicat ion ( eit her poll or int errupt )
when t he ot her side wrot e a message.
Assuming a maximum message size of 64 byt es ( one cache line) , a memory of 64 byt es x 64 VMs =
4 KB. 512 byt es is provided per port . The RAM is organized as follows:

375
I n addit ion for each VF, t he VFMailbox and PFMailbox regist ers are defined in order t o coordinat e t he
t ransmission of t he messages. These regist ers cont ain a semaphore mechanism t o enable coordinat ion
of t he mailbox usage.
The PF driver can decide which VFs are allowed t o int errupt t he PF t o indicat e a mailbox message using
t he PFMBI MR mask regist er.
The following flows describe t he usage of t he mailbox:
Tabl e 7. 71. Mai l box Memor y
RAM Addr ess Funct i on PF BAR 0 Mappi ng
1
1. Relat ive t o mailbox offset .
VF BAR 0 Mappi ng
2
2. MBO = mailbox offset in VF CSR space.
0 63 VF0 < - > PF 0 63 VF0 + MBO
64 127 VF1 < - > PF 64 127 VF1 + MBO
. . . .
( 4 KB- 64) ( 4 KB- 1) VF63< - > PF ( 4 KB- 64) ( 4 KB- 1) VF63 + MBO
Tabl e 7. 72. PF- t o- VF Messagi ng Fl ow
St ep PF Dr i v er Har dw ar e VF # n dr i v er
1 Set PFMailbox[ n] . PFU
2
Set PFU bit if PFMailbox[ n] . VFU is
cleared
3
Read PFMailbox [ n] and check t hat PFU bit
was set . Ot herwise wait and go t o st ep 1.
4
Writ e message t o relevant locat ion in
VMFBMEM.
5
Set t he PFMailbox[ n] . STS bit and wait for
ACK
1
.
1. The PF might implement a t imeout mechanism t o det ect non- responsive VFs.
6 I ndicat e an int errupt t o VF # n.
7
Read t he message from
VFMBMEM.
8 Set t he VFMailbox. ACK bit .
9 I ndicat e an int errupt t o PF.
10 Clear PFMailbox[ n] . PFU
Tabl e 7. 73. VF- t o- PF Messagi ng Fl ow
St ep PF Dr i ver Har dw ar e VF # n Dr i v er
1 Set VFMailbox. VFU.
2
Set VFU bit if VFMailbox[ n] . PFU
is cleared.
3
Read VFMailbox [ n] and check t hat VFU bit
was set . Ot herwise wait and go t o st ep 1.
4
Writ e message t o relevant locat ion in
VFMBMEM.
5 Set t he VFMailbox. REQ bit .
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The cont ent of t he message is hardware independent and is det ermined by soft ware.
The messages current ly assumed by t his specificat ion are:
Regist rat ion t o VLAN/ mult icast packet / broadcast packet s A VF can request t o be part of a given
VLAN or t o get some mult icast / broadcast t raffic.
Recept ion of large packet Each VF should not ify t he PF driver what is t he largest packet size
allowed in receive.
Get global st at ist ics A VF can request informat ion from t he PF driver on t he global st at ist ics.
Filt er allocat ion request A VF can request allocat ion of a filt er for queuing/ immediat e int errupt
support .
Global int errupt indicat ion.
I ndicat ion of errors.
7. 10. 2. 10 DMA
7.10.2.10.1 RI D
Each VF is allocat ed a RI D. Each DMA request should use t he RI D of t he VM t hat request ed it . See
Sect ion 7. 10. 2. 6 for det ails.
7.10.2.10.2 Shar i ng of t he DMA Resour ces
The out st anding request s and complet ion credit s are shared bet ween all t he VFs. The t ags at t ached t o
read request s are assigned t he same way as in a non-virt ualized set t ing, alt hough in VF syst ems t ags
can be re- used for different RI Ds. See Sect ion 3.1.3. 1.
7.10.2.10.3 DCA
The DCA enable is common t o all t he devices ( all PFs and VFs) . Given a DCA enabled device, each VM
might decide for each queue, on which t ype of t raffic ( dat a, headers, Tx descript ors, Rx descript ors) t he
DCA should be assert ed and what is t he CPU I D assigned t o t his queue.
Not e: There are no plans t o virt ualize DCA in t he I OH. Thus, t he physical CPU I D should be used in
t he programming of t he CPUI D field.
6 I ndicat e an int errupt t o PF.
7
Read PFMBI CR t o det ect which
VF caused t he int errupt .
8
Read t he adequat e message
from VFMBMEM.
9 Set t he PFMailbox. ACK bit .
10 I ndicat e an int errupt t o VF # n.
11 Clear VFMailbox. VFU.
Tabl e 7.73. VF- t o- PF Messagi ng Fl ow
St ep PF Dr i v er Har dw ar e VF # n Dr i ver

377
7.10. 2. 11 Ti mer s and Wat chdog
7.10.2.11.1 TCP Ti mer
The TCP t imer is available only t o t he Physical Funct ion ( PF) . I t might indicat e an int errupt t o t he VFs
via t he mailbox mechanism.
7. 10. 2. 11.2 I EEE 1588
I EEE 1588 is a per- link funct ion and t hus is cont rolled by t he PF driver. The VMs have access t o t he real
t ime clock regist er.
7.10.2.11.3 Wat chdog
The wat chdog was originally developed for pass- t hrough NI Cs where virt ualizat ion is not a viable. Thus,
t his funct ionalit y is used only by t he PF.
7.10.2.11.4 Fr ee Runni ng Ti mer
The free running t imer is a PF driver resource t he VMs can access. This regist er is read only t o all VFs
and is reset only by t he PCI reset .
7.10. 2. 12 Pow er Management and Wak e Up
Power management is a PF resource and is not support ed per VF.
7.10. 2. 13 Li nk Cont r ol
The link is a shared resource and as such is cont rollable only by t he PF. This includes int erface set t ings,
speed and duplex set t ings, flow cont rol set t ings, et c. The flow cont rol packet s are sent wit h t he st at ion
Et hernet MAC address st ored in t he EEPROM. The wat ermarks of t he flow cont rol process and t he t ime-
out value are also cont rollable by t he PF only. I n a DCB environment , t he paramet ers of t he per TC flow
cont rol are also part of t he PF responsibilit ies.
Linksec is a per- link funct ion and is cont rolled by t he PF driver.
Double VLAN is a net work set t ing and as such should be common t o all VFs.
7.10.2.13.1 Speci al Fi l t er i ng Opt i ons
Pass bad packet s is a debug feat ure. As such, pass bad packet s is available only t o t he PF. Bad packet s
are passed according t o t he same filt ering rules of t he regular packet s.
Not e: Pass bad packet s might cause guest operat ing syst ems t o get unexpect ed packet s. As a
result , it should be used only for debug purposes of t he ent ire syst em.
Receiving long packet s is enabled separat ely per Rx queue in t he RXDCTL regist ers. As t his impact s t he
flow cont rol t hresholds, t he PF should be made aware of t he decision of all t he VMs. Because of t his, t he
set up of TSO packet s is cent ralized by t he PF and each VF might request t his set t ing.
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7.10. 3 Pack et Sw i t chi ng
7. 10. 3. 1 Assumpt i ons
The following assumpt ions are made:
The required bandwidt h for t he VM- t o-VM loopback t raffic is low. That is, t he PCI e bandwidt h is not
congest ed by t he combinat ion of t he VM- t o-VM and t he regular incoming t raffic. This case is
handled but not opt imized for. Unless specified ot herwise, Tx and Rx packet s should not be dropped
or lost due t o congest ion caused by loopback t raffic.
I f t he buffer allocat ed for t he VM- t o-VM loopback t raffic is full, it is accept able t o back pressure t he
t ransmit t raffic of t he same TC. This means t hat t he out going t raffic might be blocked if t he
loopback t raffic is congest ed.
The decision on local t raffic is done only according t o t he Et hernet DA address and t he VLAN t ag.
There is no filt ering according t o ot her paramet ers ( I P, L4, et c.) . The swit ch has no learning
capabilit ies. I n case of double VLAN mode, t he inner VLAN is used for t he swit ching funct ionalit y.
The forwarding decisions are based on t he receive filt ering programming.
No packet swit ching bet ween TCs.
Coexist ence wit h I PSEC offload: Any loopback VM- t o-VM t raffic should not use t he I PSEC offload
( t he I PSEC bit must be cleared in t he advanced Tx dat a descript or) . I Psec processing of Tx packet s
dest ined t o a local VM must be handled by soft ware.
Coexist ence wit h TimeSync: t ime st amp is not sampled for any VM- t o-VM loopback t raffic.
Coexist ence wit h Double VLAN: When double VLAN is enabled by DMATXCTL.GDV and it is expect ed
t o t ransmit unt agged packet s by soft ware, t ransmit - t o- receive packet swit ching should not be
enabled.
7. 10. 3. 2 Pool Sel ect i on
Pool select ion is described in t he following sect ions. A packet might be forwarded t o a single pool or
replicat ed t o mult iple pools. Mult icast and broadcast packet s are cases of replicat ion, as is mirroring.
The following capabilit ies det ermine t he dest inat ion pools of each packet :
128 Et hernet MAC address filt ers ( RAH/ RAL regist ers) for bot h unicast and mult icast filt ering. These
are shared wit h L2 filt ering. For example, t he same Et hernet MAC addresses are used t o det ermine
if a packet is received by t he swit ch and t o det ermine t he forwarding dest inat ion.
64 shared VLAN filt ers ( PFVLVF and PFVLVFB regist ers) each VM can be made a member of each
VLAN.
Hash filt ering of unicast and mult icast addresses ( if t he direct filt ers previously ment ioned are not
sufficient )
Forwarding of broadcast packet s t o mult iple pools
Forwarding by Et hert ype
Mirroring by pool, VLAN, or link
7. 10. 3. 3 Rx Pack et s Sw i t chi ng
Rx packet swit ching is t he second of t hree st ages t hat det ermine t he dest inat ion of a received packet .
The t hree st ages are defined in Sect ion 7. 1.2.
As far as swit ching is concerned, it doesnt mat t er whet her t he 82599s virt ual environment operat es in
I OV mode or in Next Generat ion VMDq mode.

379
When operat ing in replicat ion mode, broadcast and mult icast packet s can be forwarded t o more t han
one pool, and is replicat ed t o more t han one Rx queue. Replicat ion is enabled by t he Rpl_En bit in t he
PFVTCTL regist er.
7.10.3.3.1 Repl i cat i on Mode Enabl ed
When replicat ion mode is enabled, each broadcast / mult icast packet can go t o more t han one pool.
Finding t he pool list of any packet is provided in t he following st eps:
1. Ex act uni cast or mul t i cast mat ch I f t here is a mat ch in one of t he exact filt ers ( RAL/ RAH) , for
unicast or mult icast packet s, use t he MAC Pool Select Array ( MPSAR[ n] ) bit s as a candidat e for t he
pool list .
2. Br oadcast I f t he packet is a broadcast packet , add pools for which t heir PFVML2FLT.BAM bit
( Broadcast Accept Mode) is set .
3. Uni cast hash I f t he packet is a unicast packet , and t he prior st eps yielded no pools, check it
against t he Unicast Hash Table ( PFUTA) . I f t here is a mat ch, add pools for which t heir
PFVML2FLT. ROPE bit ( Accept Unicast Hash) is set .
4. Mul t i cast hash I f t he packet is a mult icast packet and t he prior st eps yielded no pools, check it
against t he Mult icast Hash Table ( MTA) . I f t here is a mat ch, add pools for which t heir
PFVML2FLT. ROMPE bit ( Receive Mult icast Packet Enable) is set .
5. Mul t i cast pr omi scuous I f t he packet is a mult icast packet , t ake t he candidat e list from prior
st eps and add pools for which t heir PFVML2FLT.MPE bit ( Mult icast Promiscuous Enable) is set .
6. VLAN gr oups This st ep is relevant only when VLAN filt ering is enabled by t he VLNCTRL. VFE bit .
Tagged packet s: enable only pools in t he packet s VLAN group as defined by t he VLAN filt ers
PFVLVF[ n] and t heir pool list PFVLVFB[ n] . Unt agged packet s: enable only pools wit h t heir
PFVML2FLT.AUPE bit set . I f t here is no mat ch, t he pool list should be empt y.
Not e: I n a VLAN net work, unt agged packet s are not expect ed. Such packet s received by t he swit ch
should be dropped, unless t heir dest inat ion is a virt ual port set t o receive t hese packet s. The
set t ing is done t hrough t he PFVML2FLT. AUPE bit . I t is assumed t hat VMs for which t his bit is
set are members of a default VLAN and t hus only MAC queuing is done on t hese packet s.
7. Def aul t pool I f t he pool list is empt y at t his st age and t he PFVTCTL.Dis_Def_Pool bit is cleared,
t hen set t he default pool bit in t he t arget pool list ( from PFVTCTL.DEF_PL) .
8. Et her t ype f i l t er s I f one of t he Et hert ype filt ers ( ETQF) is mat ched by t he packet and queuing
act ion is request ed and t he Pool Enable bit in t he ETQF is set , t he pool list is set t o t he pool point ed
t o by t he filt er.
9. PFVFRE I f any bit in t he PFVFRE regist er is cleared, clear t he respect ive bit in t he pool list . The
PFVFRE regist er blocks recept ion by a VF while t he PF configures it s regist ers.
10. Mi r r or i ng Each of t he four mirroring rules adds it s dest inat ion pool ( PFMRCTL. MP) t o t he pool
list if t he following applies:
a. Pool mi r r or i ng PFMRCTL.VPME is set and one of t he bit s in t he pool list mat ches one of t he
bit s in t he PFMRVM regist er.
b. VLAN por t mi r r or i ng PFMRCTL.VLME is set and t he index of t he VLAN of t he packet in t he
PFVLVF t able mat ches one of t he bit s in t he VMVLAN regist er.
c. Upl i nk por t mi r r or i ng PFMRCTL.UPME is set , t he pool list is not empt y.
d. PFVFRE I f any bit in t he PFVFRE regist er is cleared, clear t he respect ive bit in t he pool list .
The PFVFRE regist er blocks recept ion by a VF while t he PF configures it s regist ers. Not e t hat t his
st age appears t wice in order t o handle mirroring cases.
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7.10.3.3.2 Repl i cat i on Mode Di sabl ed
When replicat ion mode is disabled, soft ware should t ake care of mult icast and broadcast packet s and
check which of t he VMs should get t hem. I n t his mode, t he pool list of any packet always cont ains one
pool only according t o t he following st eps:
1. Ex act uni cast or mul t i cast mat ch I f t he packet DA mat ches one of t he exact filt ers ( RAL/
RAH) , use t he MAC Pool Select Array ( MPSAR[ n] ) bit s as a candidat e for t he pool list .
2. Uni cast hash I f t he packet is a unicast packet , and t he prior st ep yielded no pools, check it
against t he Unicast Hash Table ( PFUTA) . I f t here is a mat ch, add t he pool for which t heir
PFVML2FLT.ROPE ( Accept Unicast Hash) bit is set . Refer t o t he soft ware limit at ions described aft er
st ep 7.
4. Def aul t pool I f t he pool list is empt y at t his st age and t he PFVTCTL.Dis_Def_Pool bit is cleared,
t hen set t he default pool bit in t he t arget pool list ( from PFVTCTL.DEF_PL) .
5. Mul t i cast or br oadcast I f t he packet is a mult icast or broadcast packet and was not forwarded
in st ep 1 and 2, set t he default pool bit in t he pool list ( from PFVTCTL.DEF_PL) .
6. Et her t y pe f i l t er s I f one of t he Et hert ype filt ers ( ETQF) is mat ched by t he packet and queuing
act ion is request ed and t he Pool Enable bit in t he ETQF is set , t he pool list is set t o t he pool point ed
by t he filt er.
7. PFVFRE I f any bit in t he PFVFRE regist er is cleared, clear t he respect ive bit in t he pool list . The
PFVFRE regist er blocks recept ion by a VF while t he PF configures it s regist ers.
The following soft ware limit at ions apply when replicat ion is disabled:
Soft ware must not set more t han one bit in t he bit maps of t he exact filt ers. Not e t hat mult iple bit s
can be set in an RAH regist er as long as it s guarant eed t hat t he packet is sent t o only one queue by
ot her means ( such as VLAN) .
Soft ware must not set per-VM promiscuous bit s ( mult icast or broadcast ) .
Soft ware must not set t he ROPE bit in more t han one PFVML2FLT regist er.
Soft ware should not act ivat e mirroring.
7. 10. 3. 4 Tx Pack et s Sw i t chi ng
Tx swit ching is used only in a virt ualized environment t o serve VM- t o-VM t raffic. Packet s t hat are
dest ined t o one or more local VMs are direct ed back ( loopback) t o t he Rx packet buffers. Enabling Tx
swit ching is done by set t ing t he PFDTXGSWC. LBE bit . Tx t o Rx swit ching always avoids packet drop as
if flow cont rol is enabled. Therefore, t he soft ware must set t he FCRTH[ n] .RTH fields regardless if flow
cont rol is act ivat ed on t he 82599.
Tx swit ching rules are very similar t o Rx swit ching in a virt ualized environment , wit h t he following
except ions:
I f a t arget pool is not found, t he default pool is used only for broadcast and mult icast packet s.
A unicast packet t hat mat ches an exact filt er is not sent t o t he LAN.
Broadcast and mult icast packet s are always sent t o t he ext ernal LAN.
A packet might not be sent back t o t he originat ing pool ( even if t he dest inat ion address is equal t o
t he source address) unless loopback is enabled for t hat pool by t he PFVMTXSW[ n] regist er.

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The det ailed flow for pool select ion as well as t he rules t hat apply t o loopback t raffic is as follows:
Loopback is disabled when t he net work link is disconnect ed. I t is expect ed ( but not required) t hat
syst em soft ware ( including VMs) does not post packet s for t ransmission when t he link is
disconnect ed. Not e t hat packet s post ed by syst em soft ware for t ransmission when t he link is down
are buffered.
Loopback is disabled when t he RXEN ( Receive Enable) bit is cleared.
Loopback packet s are ident ified by t he LB bit in t he receive descript or.
Not e: When Tx swit ching is enabled, t he host must avoid sending packet s longer t han 9.5 KB as t his
hangs t he Tx pat h.
7.10.3.4.1 Repl i cat i on Mode Enabl ed
When replicat ion mode is enabled, t he pool list for any packet is det ermined according t o t he following
st eps:
1. Ex act uni cast or mul t i cast mat ch I f t here is a mat ch in one of t he exact filt ers ( RAL/ RAH) , for
unicast or mult icast packet s, t ake t he MPSAR[ n] bit s as a candidat e for t he pool list .
2. Br oadcast I f t he packet is a broadcast packet , add pools for which t heir PFVML2FLT.BAM bit
( Broadcast Accept Mode) is set .
against t he Unicast Hash Table ( PFUTA) . I f t here is a mat ch, add pools for which t heir
PFVML2FLT. ROPE bit ( Accept Unicast Hash) is set .
4. Mul t i cast hash I f t he packet is a mult icast packet and t he prior st eps yielded no pools, check it
against t he Mult icast Hash Table ( MTA) . I f t here is a mat ch, add pools for which t heir
PFVML2FLT. ROMPE bit ( Receive Mult icast Packet Enable) is set .
5. Mul t i cast pr omi scuous I f t he packet is a mult icast packet , t ake t he candidat e list from prior
st eps and add pools for which t heir PFVML2FLT.MPE bit ( Mult icast Promiscuous Enable) is set .
6. Fi l t er sour ce pool The pool from which t he packet was sent is removed from t he pool list unless
t he PFVMTXSW.LLE bit is set .
8. For w ar di ng t o t he net w or k Packet s are forwarded t o t he net work in t he following cases:
a. All broadcast and mult icast packet s.
b. Unicast packet s t hat do not mat ch any exact filt er.
9. PFVFRE I f any bit in t he PFVFRE regist er is cleared, clear t he respect ive bit in t he pool list ( pre
mirroring st ep) . Refer t o t he not es aft er st ep 11.
10. Mi r r or i ng Each of t he following t hree mirroring rules adds it s dest inat ion pool ( PFMRCTL.MP) t o
t he pool list if t he following applies:
a. Pool mi r r or i ng PFMRCTL.VPME is set and one of t he bit s in t he pool list mat ches one of t he
bit s in t he PFMRVM regist er.
b. VLAN por t mi r r or i ng PFMRCTL.VLME is set and t he index of t he VLAN of t he packet in t he
PFVLVF t able mat ches one of t he bit s in t he VMVLAN regist er.
c. Dow nl i nk por t mi r r or i ng PFMRCTL.DPME is set and t he packet is sent t o t he net work.
11. PFVFRE I f any bit in t he PFVFRE regist er is cleared, clear t he respect ive bit in t he pool list ( post
mirroring st ep) . Refer t o t he following not es.
Not e: The PFVFRE filt ering is applied only aft er t he decision t o forward t he packet t o net work and/ or
local pool ( based on MAC address and VLAN) . I f a packet t hat mat ches an exact MAC address
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is set t o be forwarded t o a local pool, it is not sent t o t he net work regardless of t he PFVFRE
set t ing. Therefore, when a pool is disabled, soft ware should also clear it s exact MAC address
filt ers before clearing t he PFVFRE.
7.10.3.4.2 Repl i cat i on Mode Di sabl ed
When replicat ion mode is disabled, soft ware should t ake care of mult icast and broadcast packet s and
check which of t he VMs should get t hem. I n t his mode t he pool list for any packet always cont ains one
pool only according t o t he following st eps:
1. Ex act uni cast or mul t i cast mat ch I f t he packet DA mat ches one of t he exact filt ers ( RAL/
RAH) , t ake t he MPSAR[ n] bit s as a candidat e for t he pool list .
against t he Unicast Hash Table ( PFUTA) . I f t here is a mat ch, add t he pool for which t heir
PFVML2FLT.ROPE bit ( Accept Unicast Hash) is set . Refer t o t he soft ware limit at ions t hat follow.
4. Mul t i cast or br oadcast I f t he packet is a mult icast or broadcast packet and was not forwarded
in st ep 1 and 2, set t he default pool bit in t he pool list ( from PFVTCTL.DEF_PL) .
5. Fi l t er sour ce pool The pool from which t he packet was sent is removed from t he pool list unless
t he PFVMTXSW.LLE bit is set .
6. For w ar di ng t o t he net w or k Packet s are forwarded t o t he net work in t he following cases:
a. All broadcast and mult icast packet s.
b. Unicast packet s t hat do not mat ch any exact filt er.

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7. PFVFRE I f any bit in t he PFVFRE regist er is cleared, clear t he respect ive bit in t he pool list .
Not e: The PFVFRE filt ering is applied only aft er t he decision t o forward t he packet t o net work and/ or
local pool ( based on MAC address and VLAN) . I f a packet t hat mat ches an exact MAC address
is set t o be forwarded t o a local pool, it is not sent t o t he net work regardless of t he PFVFRE
set t ing. Therefore, when a pool is disabled, soft ware should also clear it s exact MAC address
filt ers before clearing t he PFVFRE.
The following soft ware limit at ions apply when replicat ion is disabled:
1. I t is soft wares responsibilit y not t o set more t han one bit in t he bit maps of t he exact filt ers. Not e
t hat mult iple bit s can be set in an RAH regist er as long as it is guarant eed t hat t he packet is sent t o
only one queue by ot her means ( such as VLAN)
2. Soft ware must not set per-VM promiscuous bit s ( mult icast or broadcast ) .
3. Soft ware must not set t he ROPE bit in more t han one PFVML2FLT regist er.
4. Soft ware should not act ivat e mirroring.
7. 10. 3. 5 Mi r r or i ng Suppor t
The 82599 support s four separat e mirroring rules, each associat ed wit h a dest inat ion pool ( mirroring
can be done int o up t o four pools) . Each rule is programmed wit h one of t he four mirroring t ypes:
1. Pool mirroring reflect all t he packet s received t o a pool from t he net work.
2. Uplink port mirroring reflect all t he t raffic received from t he net work.
3. Downlink port mirroring reflect all t he t raffic t ransmit t ed t o t he net work.
4. VLAN mirroring reflect all t he t raffic received from t he net work in a set of given VLANs ( eit her
from t he net work or from local VMs) .
Not e: Reflect ing all t he t raffic received by any of t he pools ( eit her from t he net work or from local
VMs) is support ed by enabling mirroring of all pools.
Not e: Mirroring and replicat ion on FCoE t raffic is not support ed on receive if t he ETQF filt ers define
FCoE packet s and on t ransmit if t he packet s are indicat ed as FCoE ( by set t ing t he FCoE bit in
t he TUCMD field in t he Transmit Cont ext Descript or) .
Mirroring modes are cont rolled by a set of rule cont rol regist ers:
PFMRCTL cont rols t he rules t o be applied and t he dest inat ion port .
PFMRCTL cont rols t he VLAN port s as list ed in t he PFVLVF t able t aking part in t he VLAN mirror
rule.
PFMRVM cont rols t he pools t aking part in t he pool mirror rule.
7.10.3.6 Of f l oads
The general rule is t hat offloads are execut ed as configured for t he pool and queue associat ed wit h t he
receive packet . Some special cases:
I f a packet is direct ed t o a single pool, t hen offloads are det ermined by t he pool and queue for t hat
packet .
I f a packet is replicat ed t o more t han one pool, t hen each copy of t he packet is offloaded according
t o t he configurat ion of it s pool and queue.
I f replicat ion is disabled, offloads are det ermined by t he unique dest inat ion of t he packet .
The following subsect ions describe except ions t o t he previously described special cases.
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7.10.3.6.1 Local Tr af f i c Of f l oad
The following capabilit ies are not support ed on t he loopback pat h:
The Et hert ype filt ers do not apply.
Padding t o a legal packet size is not support ed.
The following offload capabilit ies are only support ed if XSUM offload is provided on t he Tx pat h for
t he packet : RSS, 5- t uple filt ers, VLAN st rip. The reason is t hat when XSUM is not offloaded,
soft ware does not provide t he necessary offload offset s wit h t he Tx packet .
Header split / replicat ion is not support ed for NFS.
Receive Side Coalescing ( RSC) is not support ed.
FCoE offloads are not support ed.
I PSec offload is not support ed.
7.10.3.6.2 Rx Tr af f i c Of f l oad
Securit y offloads ( LinkSec, I Psec) are managed globally and not per pool.
CRC offload is a global policy. CRC st rip is enabled or disabled for all received packet s.
7. 10. 3. 7 Congest i on Cont r ol
Tx packet s going t hrough t he local swit ch are st ored in t he Rx packet buffer, similar t o packet s
received from t he net work. Tx t o Rx swit ching always avoids packet drop as if flow cont rol is
enabled. Therefore, t he soft ware must set t he FCRTH[ n] .RTH fields regardless if flow cont rol is
act ivat ed on t he 82599.
The 82599 guarant ees t hat one TC flow is not affect ed by congest ion in anot her TC.
Receive and local t raffic are provided wit h t he same priorit y and performance expect at ions. Packet s
from t he t wo sources are merged in t he Rx packet buffers, which can in general support bot h st reams
at full bandwidt h. Any congest ion furt her in t he pipeline ( such as lack of PCI e bandwidt h) evenly affect s
Rx and local t raffic.
7. 10. 3. 8 Tx Queue Ar bi t r at i on and Rat e Cont r ol
I n order t o guarant ee each pool wit h adequat e bandwidt h, a per- pool bandwidt h cont rol mechanism is
added t o t he 82599. Each Tx pool get s a percent age of t he t ransmit bandwidt h and is guarant eed it can
t ransmit wit hin it s allocat ion. This arbit rat ion is combined wit h t he TC arbit rat ion. See addit ional det ails
on DCB Tx capabilit ies in Sect ion 7.7. 2. 2.
7. 10. 3. 9 Secur i t y Feat ur es
The 82599 allows some securit y checks on t he inbound and out bound t raffic of t he swit ch.
7.10.3.9.1 I nbound Secur i t y
Each incoming packet ( eit her from t he LAN or from a local VM) is filt ered according t o t he VLAN t ag so
t hat packet s from one VLAN cannot be received by pools t hat are not members of t hat VLAN.

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7.10.3.9.2 Out bound Secur i t y
MAC ant i - spoof i ng
Each pool is associat ed wit h one or more Et hernet MAC addresses on t he receive pat h. The associat ion
is det ermined t hrough t he MPSAR regist ers. The MAC ant i- spoofing capabilit y insures t hat a VM always
uses a source Et hernet MAC address on t he t ransmit pat h t hat is part of t he set of Et hernet MAC
addresses defined on t he Rx pat h. A packet wit h a non- mat ching SA is dropped, prevent ing spoofing of
t he Et hernet MAC address. This feat ure is enabled in t he PFVFSPOOF.MACAS field, and can be enabled
per Tx pool.
Not e: Ant i- spoofing is not available for VMs t hat hide behind ot her VMs whose Et hernet MAC
addresses are not part of t he RAH/ RAL Et hernet MAC Address regist ers. I n t his case, ant i-
spoofing should be done by soft ware swit ching, handling t hese VMs.
VLAN ant i - spoof i ng
Each pool is associat ed wit h one or more VLAN t ags on t he receive pat h. The associat ion is det ermined
t hrough t he PFVLVF and PFVLVFB regist ers. The VLAN ant i- spoofing capabilit y insures t hat a VM always
uses a VLAN t ag on t he t ransmit pat h t hat is part of t he set of VLAN t ags defined on t he Rx pat h. A
packet wit h a non- mat ching VLAN t ag is dropped, prevent ing spoofing of t he VLAN t ag. This feat ure is
enabled in t he PFVFSPOOF. VLANAS field, and can be enabled per Tx pool.
Not e: I f VLAN ant i- spoofing is enabled, t hen MAC ant i- spoofing must be enabled as well.
Not e: When double VLAN is enabled by DMATXCTL.GDV and it is expect ed t o t ransmit unt agged
packet s by soft ware, VLAN ant i- spoofing should not be enabled.
VLAN t ag val i dat i on
I n PCI - SI G I OV scenarios t he driver might be malicious, and t hus may fake a VLAN t ag. The 82599
provides t he abilit y t o override t he VLAN t ag insert ed by a VM. The possible behaviors are cont rolled by
t he PFVMVI R[ n] regist ers as follows:
Use descript or value t o be used in case of a t rust ed VM t hat can decide which VLAN t o send. This
opt ion should also be used in case one VM is member of mult iple VLANs.
Always insert default VLAN t his mode should be used for non- t rust ed or non-VLAN aware VMs. I n
t his case, any VLAN insert ion command from t he VM is ignored. I f a packet is received wit h a VLAN,
t he packet should be dropped.
Never insert VLAN This mode should be used in a non-VLAN net work. I n t his case, any VLAN
insert ion command from t he VM is ignored. I f a packet is received wit h a VLAN, t he packet should
be dropped.
Not e: The VLAN insert ion set t ings should be done before any of t he queues of t he VM are enabled.
Not e: When double VLAN is enabled by DMATXCTL.GDV and it is expect ed t o t ransmit unt agged
packet s by soft ware, VLAN validat ion should not be enabled.
7.10. 3. 10 Sw i t ch Cont r ol
The PF driver has some cont rol of t he swit ch logic. The following regist ers are available t o t he PF for t his
purpose:
PFVTCTL: - VT Cont rol regist er cont ains t he following fields:
Replicat ion Enable ( Rpl_En) enables replicat ion of mult icast and broadcast packet s bot h in
incoming and local t raffic. I f t his bit is cleared, Tx mult icast and broadcast packet s are sent only t o
t he net work and Rx mult icast and broadcast packet s are sent t o t he default pool.
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Default Pool ( DEF_PL) defines t he t arget pool for packet s t hat passed L2 filt ering but didnt pass
any of t he pool filt ers. This field is invalid when t he Dis_Def_Pool bit is set .
Disable Default Pool ( Dis_Def_Pool) disables accept ance of packet s t hat failed all pool filt ers.
PFVFRE Enables/ disables recept ion of packet s from t he link t o a specific VF. Used during
init ializat ion of t he VF. See Sect ion 4.2. 2. 2 for more det ails.
PFDTXGSWC ( LBE) VMDQ loopback enables swit ching of Tx t raffic t o t he Rx pat h for VM- t o-VM
communicat ion.
PFVFSPOOF MAC Ant i- spoof Enable ( MACAS) enables filt ering of Tx packet for ant i- spoof.
Local Loopback Enable ( LLE) defines whet her or not t o allow loopback of a packet from a cert ain
pool int o it self.
Queue Drop Enable ( PFQDE) regist er A regist er defining global policy for drop enable
funct ionalit y when no descript ors are available. I t let s t he PF override t he per- queue SRRCTL[ n]
Drop_En set t ing. PFQDE should be used in SR- I OV mode as described in Sect ion 4. 6. 11. 3. 1.
PFVML2FLT Receive Overflow Mult icast Packet s ( ROMPE) accept mult icast hash Defines
whet her or not a pool accept s packet s t hat mat ch t he mult icast MTA t able.
Receive MAC Filt ers Overflow ( ROPE) accept unicast hash Defines whet her or not a pool
accept s packet s t hat mat ch t he unicast PFUTA t able.
Broadcast Accept ( BAM) Defines whet her or not a pool accept s broadcast packet s.
Mult icast Promiscuous ( MPE) Defines whet her or not a pool accept s all mult icast packet s.
Accept Unt agged Packet s Enable ( AUPE) Defines whet her or not a pool accept s unt agged VLAN
packet s.
Mirror Cont rol See Sect ion 7.10.3. 5.
PFVFTE Enables/ disables t ransmission of packet s t o t he link t o a specific VF. Used during
init ializat ion of t he VF. See Sect ion 4.2. 2. 2 for more det ails.
PFVLVF/ PFVLVFB VLAN queuing t able A set of 64 VLAN ent ries wit h an associat ed bit map, one
bit per pool. Bit s are set for each pool t hat part icipat es in t his VLAN.
Unicast Table Array ( PFUTA) a 4 Kb array t hat covers all combinat ions of 12 bit s from t he MAC
dest inat ion address. A received unicast packet t hat misses t he MAC filt ers is compared against t he
PFUTA. I f t he relevant bit in t he PFUTA is set , t he packet is rout ed t o all pools for which t he ROPE bit
is set .
Mult icast Table Array ( MTA) a 4 Kb array t hat covers all combinat ions of 12 bit s from t he MAC
dest inat ion address. A received mult icast packet t hat misses t he MAC filt ers is compared against
t he MTA. I f t he relevant bit in t he MTA is set , t he packet is rout ed t o all pools for which t he ROMPE
bit is set .
I n addit ion, t he rat e- cont rol mechanism is programmed as described in Sect ion 7. 7. 2.2.
7.10. 4 Vi r t ual i zat i on of Har dw ar e
This sect ion describes addit ional feat ures used in bot h I OV and Next Generat ion VMDq modes.
7. 10. 4. 1 Per - pool St at i st i cs
Part of t he st at ist ics are by definit ion shared and cannot be allocat ed t o a specific VM. For example, CRC
error count cannot be allocat ed t o a specific VM, as t he dest inat ion of such a packet is not known if t he
CRC is wrong.
All t he non- specific st at ist ics are handled by t he PF driver in t he same way it is done in non-virt ualized
syst ems. A VM might request a st at ist ic from t he PF driver but might not access it direct ly.

387
The concept ual model used t o gat her st at ist ics in a virt ualizat ion cont ext is t hat each queue pool is
considered as a virt ual link and t he Et hernet link is considered as t he uplink of t he swit ch. Thus, any
packet sent by a pool is count ed in t he Tx st at ist ics, even if it was forwarded t o anot her pool int ernally
or was dropped by t he MAC for some reason. I n t he same way, a replicat ed packet is count ed in each of
t he pools receiving it .
The following st at ist ics are provided per pool:
Good packet received count
Good packet t ransmit t ed count
Good oct et s received count
Good oct et s t ransmit t ed count
Mult icast packet s received count
Not e: All t he per VF st at ist ics are read only and wrap around aft er reaching t heir maximum value.
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7.11 Recei ve Si de Coal esci ng ( RSC)
The 82599 can merge mult iple received frames from t he same TCP/ I P connect ion ( referred t o as flow in
t his sect ion) int o a single st ruct ure. The 82599 does t his by coalescing t he incoming frames int o a
single or mult iple buffers ( descript ors) t hat share a single accumulat ed header. This feat ure is called
RSC. Not e t hat t he t erm Large Receive is used t o describe a packet const ruct generat ed by RSC.
The 82599 digest s received packet s and cat egorizes t hem by t heir TCP/ I P connect ions ( flows) . For each
flow, hardware coalesces t he packet s as shown in Figure 7. 41 and Figure 7.42 ( t he colored paramet ers
are explained in t he RSC cont ext t able and receive descript or sect ions) . The 82599 can handle up t o 32
concurrent flows per LAN port at any given t ime. Each flow handled by RSC offload has an associat ed
cont ext . The 82599 opens and closes t he RSC cont ext s aut onomously wit h no need for any soft ware
int ervent ion. Soft ware needs only t o enable RSC in t he select ed receive queues.
Figure 7. 41 shows a t op level flow diagram t hat is used for RSC funct ionalit y. The following sect ions
provide a det ailed explanat ion of t his flow as well as t he memory st ruct ures and device set t ings t hat
support t he RSC funct ionalit y.

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Not e: Soft ware might abort recept ion t o any queue at any t ime. For example: VFLR or queue
disable. Following t hese set t ings, hardware abort s furt her DMA( s) and descript or
complet ions. Specifically, act ive RSC( s) in t he specific queue( s) are not complet ed. I n such
cases t here could be complet ed packet s and RSC( s) hidden from soft ware by prior incomplet e
RSC( s) .
Fi gur e 7. 41. RSC Funct i onal i t y ( No Header Spl i t )
Fi gur e 7. 42. RSC Funct i onal i t y ( No Header Spl i t )
Header Payload-1 CRC Header Payload-2 CRC Header Payload-3 CRC Header Payload-4 CRC
Rx
Packets
First packet in the RSC
Header
Large Rx
Packet
Payload-1 Payload-2 Payload-3 Payload-4
Large Rx
Buffers
Large Rx
Descriptors
NEXTP
Data Length =
whole buffer size
NEXTP
Data Length =
whole buffer size
Last packet in the RSC
Header Payload-1 Payload-2 Payload-3
Large Receive example
while using Advanced
receive descriptors
(SRRCTL.DESCTYPE = 1)
Payload-4
EOP
Data Length =
partial buffer size
EOP=1, RSCCNT=1
EOP=0, RSCCNT=3, NEXTP=5
EOP=0, RSCCNT=3, NEXTP=3
Descriptor Ring
(SRRCTL.DESCTYPE = 1)
DATDESC = 5
Data Buffers
Descriptor
Index
0
N
7
6
5
4
3
2
1
. . .
1st Packet Data
Packet 2 Data
Packet 3 Data
HPTR
DATOFF
Descriptor setting if
packet 4 is the last
one in the RSC
Coalesced Header
Packet 4 Data
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7.11. 1 Pack et Vi abi l i t y f or RSC Funct i onal i t y
I ncoming packet s can be good candidat es for RSC offload when t he following condit ions are met . I f any
of t he t hese condit ions are not met , t he received packet is processed in t he legacy ( non- coalescing)
scheme.
RSC is not disabled globally by t he RFCTL.RSC_DI S bit . Not e t hat in SR- I OV mode t he RSC must be
disabled globally by set t ing t he RFCTL. RSC_DI S bit .
RSC is enabled in t he dest inat ion receive queue by t he RSCCTL.RSCEN. I n t his case, soft ware must
set t he SRRCTL.DESCTYPE field in t he relevant queues t o advanced descript or modes.
The SRRCTL[ n] .BSI ZEHEADER ( header buffer size) must be larger t han t he packet header ( even if
header split is not enabled) . A minimum size of 128 byt es for t he header buffer addresses t his
requirement .
The SRRCTL[ n] .BSI ZEPACKET ( packet buffer size) must be 2 KB at minimum.
The received packet has no MAC errors and no TCP/ I P checksum errors. MAC errors are: CRC error
or undersize frame received or oversize frame received or error cont rol byt e received in mid- packet
or illegal code byt e received in mid- packet .
I f t he Lengt h field in t he I P header does not cover t he ent ire packet ( as t he case for padding byt es)
t hen t he received packet is not a candidat e for RSC.
I f t he packet carries LinkSec encapsulat ion, t he LinkSec offload is act ivat ed on t he packet wit h no
errors.
The packet t ype is TCP/ I Pv4 ( non- SNAP) wit h opt ional VLAN header.
I P header does not carry any opt ion headers.
NFS packet s can be coalesced only if NFS filt ering is disabled by set t ing bot h RFCTL.NFSW_DI S and
RFCTL. NFSR_DI S bit s t o 1b. Furt hermore, t he PSR_t ype1 bit ( header split on NFS) must be t urned
off in all PSRTYPE[ n] regist ers.
Fi gur e 7.43. RSC Event Fl ow
Processing New RSC Processing active RSC
Check
New / Old
Flow
Packet
viable for
RSC
viable for
old RSC
Yes
New Old
No
Yes
Create new
RSC context
Close Existing
Large Receive
Yes
Coalesce and
Send packet to
DMA Engine
Update RSC
context and
packet header
No
New packet
Close large
Receive
Yes No
No
free RSC
context
No Coalescing
Flow
End End
Close Large
Receive
ITR or
Immediate Packet
(on the relevant
receive queue)
Close oldest
Large Receive
(RSC context
is evicted)

391
I f NFS coalescing is not required, soft ware should set bot h RFCTL.NFSW_DI S and RFCTL.NFSR_DI S
bit s t o 0b.
The packet does not carry I Psec encapsulat ion ( regardless if I Psec offload is enabled) .
The TCP segment is not fragment ed.
The following TCP flags are inact ive: FI N, SYN, RST, PSH, URG, ECE, CWR, NS and t he ot her t hree
reserved TCP flags ( see TCP Flags mapping in Table 7. 74) .
The ECT and CE bit s in t he TOS field in t he I P header are not equal t o 11b ( see t he flags in
Table 7.75) .
The packet does not carry any TCP opt ion headers.
Virt ualizat ion rule 1: RSC is not support ed for swit ched packet t ransmit t ed from a local VM.
Virt ualizat ion rule 2: When a Rx packet is replicat ed or mirrored, it might be coalesced only on t he
Rx queue t hat belongs t o t he source VM.
Not e t hat t here are no limit at ions on t he maximum packet lengt h including j umbo packet s.
I f t here is already an act ive RSC for t he mat ched flow, t hen a few addit ional condit ions should be
met as list ed in Sect ion 7. 11. 4.
The support ed packet format is as follows:
Size Packet fields
6 Byt e Dest inat ion Et hernet MAC address
6 Byt e Source Et hernet MAC address
[ 8 / 16 Byt e]
Opt ional LinkSec header ( support ed by RSC only if LinkSec offload is enabled and t he hardware ext ract s
t his header)
[ 4 Byt e] Opt ional VLAN
[ 4 Byt e] Opt ional 2nd VLAN ( double VLAN)
2 Byt e Et hernet t ype field equals 0x0800 ( MS byt e first on t he wire)
20 Byt e I Pv4 header wit h no opt ions
20 Byt e Basic TCP header ( no opt ions refer t o t he rows t hat follow)
[ 10 Byt e]
Opt ional TCP t ime st amp header:
1 Byt e Kind 0x08
1 Byt e Lengt h 0x0A
4 Byt e TS value variable
4 Byt e TS echo reply variable
[ 1 Byt e]
Opt ional TCP no operat ion header
1 Byt e Kind 0x01
[ 1 Byt e]
Opt ional TCP end of opt ion header list
1 Byt e Kind 0x00
Variable lengt h TCP payload ( RSC candidat e must have payload size great er t han zero)
[ 8 / 18 Byt e]
Opt ional LinkSec I nt egrit y Checksum Value I CV ( support ed by RSC only if LinkSec offload is enabled
and t he hardware ext ract s t his field)
Tabl e 7. 74. Pack et For mat Suppor t ed by RSC
11 10 9 8 7 6 5 4 3 2 1 0
Reserved NS CWR ECE URG ACK PSH RST SYN FI N
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7. 11. 2 Fl ow I dent i f i cat i on and RSC Cont ex t Mat chi ng
TCP/ I P packet s flow is ident ified by it s four t uples: Source / Dest inat ion I P addresses and Source /
Dest inat ion TCP port numbers. These t uples are compared against t he Flow I dent ificat ion fields st ored
in t he act ive RSC cont ext s ( list ed in Table 7.77) . Comparison is done in t wo phases:
Hash Compare Hardware comput es a hash value of t he four t uples for each flow. The hash value
is st ored in t he RSC cont ext t able. I t is used for silicon opt imizat ion of t he compare logic. The hash
value of t he incoming packet is compared against t he hash values of all RSC cont ext s. No mat ch
bet ween t he t wo hash values means t hat t here is no valid cont ext of t he same flow.
Perfect Mat ch Hardware checks t he four t uples of t he RSC cont ext t hat passed t he first st ep wit h
t he received frame.
A mat ch bet ween t he t wo means t hat an act ive RSC cont ext is found.
Mismat ch bet ween t he t wo indicat es a hash collision, which causes a complet ion of t he collided
RSC.
I n any case of cont ext mismat ch, a new cont ext might be opened as described in Chapt er 7. 11. 3.
I f t he packet s flow mat ches an act ive RSC cont ext t hen t he packet might be appended t o t he
exist ing RSC as described in Chapt er 7. 11. 4.
Tabl e 7.75. I P TOS Fi el d Bi t Map
7 6 5 4 3 2 1 0
TOS ( DS) ECT CE
Tabl e 7.76. TCP Ti me- St amp Opt i on Header ( RFC 1323)
1 by t e: Fi r st on t he w i r e 1 by t e 4 by t e 4 by t es: Last on t he w i r e
Kind = 0x8 Lengt h = 10 TS Value ( TSval) TS Echo Reply ( TSecr)
Tabl e 7.77. RSC Cont ex t
Si ze Name Descr i pt i on
Fl ow I dent i f i cat i on
1
1 bit CVALI D
Cont ext valid indicat ion. Set t o 1b by hardware when a new cont ext is defined. Cleared t o zero when
RSC complet es.
1 byt es CHASH Cont ext hash value ( logic XOR of all byt es of t he four t uples) .
16 byt es I PDADDR I P dest inat ion address ( set t o zero for inact ive cont ext ) .
16 byt es I PSADDR I P source address ( set t o zero for inact ive cont ext ) .
1 bit I P4TYPE Defines I P version t ype ( set t o 1 for I Pv4) .
2 byt es TCPDPORT TCP dest inat ion port .
2 byt es TCPSPORT TCP source port .
37 byt es Tot al.
RSC Header
2
2 byt es RSCI PLEN
Tot al Lengt h field in t he I P header defines t he size of t he I P dat agram ( I P header and I P payload) in
byt es. Dynamic paramet er updat ed by each received packet .
5 bit s I POFF The word offset of t he I P header wit hin t he packet t hat is t ransferred t o t he DMA unit .

393
7.11.3 Pr ocessi ng New RSC
Defining t he RSC cont ext paramet ers act ivat es a new large receive. I f a received packet does not mat ch
any act ive RSC cont ext , t he packet st art s ( opens) a new one. I f t here is no free cont ext , t he oldest
act ive large receive is closed and it s evict ed cont ext is used for t he new large receive.
7. 11. 3. 1 RSC Cont ex t Set t i ng
The 82599 ext ract s t he flow ident ificat ion and RSC header paramet ers from t he packet t hat opens t he
cont ext ( t he first packet in a large receive t hat act ivat es an RSC cont ext ) . The cont ext paramet ers can
be divided int o cat egories: flow ident ificat ion; RSC header and DMA paramet ers.
7.11.4 Pr ocessi ng Act i v e RSC
Received packet s t hat belong t o an act ive RSC can be added t o t he large receive if all t he following
condit ions are met :
The L2 header size equals t he size of previous packet s in t he RSC as recorded in t he int ernal I POFF
paramet er in t he RSC cont ext t able.
The packet header lengt h as report ed in t he HDR_LEN field is assumed t o be t he same as t he first
packet in t he RSC ( not checked by hardware) .
The ACK bit in t he TCP header is 1b or equals t o t he RSCACK bit in t he RSC cont ext ( an act ive
RSCACK cont ext and inact ive received ACK bit is defined as no mat ch) .
1 bit RSCTS TCP t ime st amp header presence indicat ion.
1 bit RSCACK ACK bit in t he TCP header is a dynamic paramet er t aken from t he last coalesced packet .
1 bit RSCACKTYPE ACK packet t ype indicat ion ( ACK bit is set while packet does not has TCP payload) .
2 bit s CE, ECT ECN bit s in t he I P. TOS header: CE and ECT.
4 byt es RSCSEQ
Non- RSCACKTYPE case: Expect ed sequence number in t he TCP header of t he next packet .
RSCACKTYPE case: The ACK sequence number in t he last good packet .
Dynamic paramet er updat ed by each received packet .
8 byt es Tot al.
DMA Par amet er s
7 bit s RXQUEUE
Receive queue index. This paramet er is set by t he first packet in t he RSC and expect ed t o be t he
same for all packet s in t he RSC.
4 bit s RSCDESC
Remaining descript ors of t his cont ext . The device init ialized RSCDESC by t he MAXDESC field in t he
RSCCTL regist er of t he associat ed receive queue.
4 bit s RSCCNT
Count t he number of packet s t hat are st art ed in t he current descript or. The count er st art s at 0x1 for
each new descript or. RSCCNT st ops increment ing when it reaches 0xF.
8 byt es HPTR
Header buffer point er defines t he address in host memory of t he large receive header ( see
Sect ion 7. 11. 5. 3) .
2 byt es DATDESC
Dat a descript or is t he act ive descript or index. I nit ialized by t he first packet in t he RSC t o t he first
descript or. I t is updat ed t o t he act ive descript or at a packet DMA complet ion.
2 byt es DATOFF
Offset wit hin t he dat a buffer. The dat a of t he first packet in a large receive is t he same as t he legacy
( non- coalescing) definit ion. Following a DMA complet ion, it point s t o t he beginning of t he dat a
port ion of t he next packet .
13 byt es Tot al.
1. These paramet ers are ext ract ed from t he first packet t hat opens ( act ivat e) t he cont ext .
2. All paramet ers are set by t he first packet t hat opens t he cont ext while some are dynamic.
Tabl e 7. 77. RSC Cont ex t ( Cont i nued)
I nt el

394
The packet t ype remains t he same as indicat ed by t he RSCACKTYPE bit in t he RSC cont ext . Packet
t ype can be eit her ACK packet ( wit h no TCP payload) or ot her.
For non- RSCACKTYPE ( packet wit h TCP payload) : The sequence number in t he TCP header mat ches
t he expect ed value in t he RSC cont ext ( RSCSEQ) .
For RSCACKTYPE: The ACK sequence number in t he TCP header is great er t han t he RSCSEQ
number in t he RSC cont ext . Not e t hat t he 82598 does not coalesce duplicat ed ACK nor ACK packet s
t hat only updat es t he TCP window.
ECN handling: The value of t he CE and ECT bit s in t he I P.TOS field remains t he same as t he RSC
cont ext and different t han 11b.
The t arget receive queue mat ches t he RXQUEUE in t he RSC cont ext .
The packet does not include a TCP t ime st amp header unless it was included on t he first packet t hat
st art ed t he large receive ( indicat ed by t he RSCTS) . Not e t hat if t he packet includes ot her opt ion
headers t han t ime st amp, NOP or End of opt ion header, t he packet is not processed by RSC flow at
all.
The packet fit s wit hin t he RSC buffer( s) .
I f t he received packet does not meet any of t he above condit ions, t he mat ched act ive large receive
is closed. Then hardware opens a new large receive by t hat packet . Not e t hat since t he 82599
closes t he old large receive it is guarant eed t hat t here is at least one free cont ext .
I f t he received packet meet s all t he above condit ions, t he 82599 appends t his packet t o t he act ive large
receive and updat es t he cont ext as follows. The packet is t hen DMAed t o t he RSC buffers ( as described
in Sect ion 7. 11. 5) .
Updat e t he TCP ACK: The RSCACK in t he large receive cont ext get s t he value of t he ACK bit in t he
TCP header in t he received packet .
Updat e t he expect ed sequence number for non- RSCACKTYPE: The RSCSEQ in t he large receive
cont ext is increment ed by t he value of t he TCP payload size of t he received packet .
Updat e t he expect ed sequence number for RSCACKTYPE: The RSCSEQ in t he large receive cont ext
is updat ed t o t he value of t he ACK sequence number field in t he received packet .
Updat e t he t ot al lengt h: The RSCI PLEN in t he large receive cont ext is increment ed by t he value of
t he TCP payload size of t he received packet . The value of t he Tot al Lengt h field in t he I P header in
t he received packet get s t he updat ed RSCI PLEN. Not e t hat in RSCACKTYPE packet s t he received
payload size is zero.
Not e t hat LinkSec encapsulat ion ( if it exist s) is st ripped first by hardware. I n t his case, hardware
also st rips t he Et hernet padding ( if it exist s) .
I P header checksum is modified t o reflect t he changes in t he Tot al Lengt h field as follows ( not e t hat
t here is no special process for RSCACKTYPE packet s) :
1s { ( RSCI PLEN Packet t ot al lengt h) + 1s ( Packet I P header checksum) } while...
Packet t ot al lengt h is t he t ot al lengt h value in t he received packet .
Packet I P header checksum st ands for t he I P header checksum field in t he received packet .
1s operat ion defines a ones complement .
Plus ( + ) operat ion is a cyclic plus while t he carry out is fed as a carry in.
TCP header checksum is left as is in t he first packet in t he RSC and is set t o zero on any succeeding
packet s.

395
Updat e t he DMA paramet ers.
The RSCCNT is init ialized t o 0x1 on each new descript or. I t is t hen increment ed by one on each
packet t hat st art s on t he same descript or as long as it does not exceed a value of 0xF. When
t he RSCCNT is set t o 0xF ( 14 packet s) t he RSC complet es.
Decrement by one t he Remaining Descript ors ( RSCDESC) for each new descript or.
Updat e t he receive descript or index ( DATDESC) for each new descript or.
Updat e t he offset wit hin t he dat a buffer ( DATOFF) at t he end of t he DMA t o it s valid value for
t he next packet .
All ot her fields are kept as defined by t he first packet in t he large receive.
7. 11. 5 Pack et DMA and Descr i pt or Wr i t e Back
The Figure 7.44 shows a t op view of t he RSC buffers using advanced receive descript ors and header
split descript ors.
7. 11. 5. 1 RSC Descr i pt or I ndi cat i on ( Wr i t e Back )
Following recept ion of each packet , t he 82599 post s t he packet dat a t o t he dat a buffers and updat es
t he coalesced header in it s buffer. Any complet ed descript or is indicat ed ( writ e back) by set t ing t he
fields list ed in t he following t able. A descript or is defined as t he last one when an RSC complet es.
Sect ion 7.11.5.1 summarizes all t he causes for RSC complet ion. Any ot her descript or in t he middle of
t he RSC is indicat ed ( writ e back) when t he hardware requires t he next descript or so it can report t he
NEXTP field explained as follows.
Fi gur e 7. 44. RSC Header and Dat a Buf f er s
Advanced (DESCTYPE = 1)
Data Buffers
. . .
1st Packet
Data
Packet 2
Data
DATOFF
Coalesced
Header
. . .
DATDESC
Descriptor 2
Descriptor 1
Header Split (DESCTYPE = 2 or 5)
Header Buffer 1
. . .
HPTR
DATOFF
Coalesced
Header
. . .
DATDESC
Header Buffer 2
D
a
t
a

B
u
f
f
e
r

2
1st Packet
Data
Packet 2
Data (start)
Packet 2
Data (end)
Descriptor 2
Descriptor 1
HPTR
D
a
t
a

B
u
f
f
e
r

1
(Empty)
I nt el

396
7. 11. 5. 2 Recei v ed Dat a DMA
On t he first packet of a large receive, t he ent ire packet is post ed t o it s buffers in host memory. On any
ot her packet , t he packet ' s header and dat a are post ed t o host memory as det ailed in Sect ion 7.11.5.3
and Sect ion 7. 11. 5. 4.
7. 11. 5. 3 RSC Header
The RSC header is st ored at t he beginning of t he first buffer when using advanced receive descript ors,
or at t he header buffer of t he first descript or when using header split descript ors. ( I t is defined by t he
int ernal HPTR paramet er in t he RSC cont ext - see Figure 7.44) .
The packet s header is post ed t o host memory aft er it is updat ed by t he RSC cont ext as follow:
Pack et s w i t h payl oad coal esci ng ( RSCACKTYPE= 0) - The TCP sequence number is t aken from t he
TCP cont ext ( it is t aken from t he first packet ) . The Tot al Lengt h field in t he I P header is t aken from t he
RSC cont ext ( it represent t he lengt h of all coalesced packet s) . The I P checksum is recalculat ed. The
TCP checksum is set t o zero.
ACK no pay l oad coal esci ng ( RSCACKTYPE= 0) - The received packet header is post ed as is t o host
memory. Not e t hat if t he received packet includes padding byt es, t hese byt es are discarded.
7. 11. 5. 4 Lar ge Recei v e Dat a
The dat a of a coalesced packet is post ed t o it s buffer by t he DMA engine as follows.
Et hernet CRC.
When RSC is enabled on any queue, t he global CRC st rip must be set ( HLREG0.RXCRCSTRP = 1b) .
Packet dat a spans on a single buffer.
The dat a of t he received packet spans on a single buffer if buffer has t he required space.
The DMA engine post s t he packet dat a t o it s buffer point ed t o by DATDESC descript or at an offset
indicat ed by t he DATOFF.
Packet dat a spans on mult iple buffers.
The dat a of t he received packet spans across mult iple buffers when it is larger t han a single buffer
or larger t han t he residual size of t he current buffer.
When a new buffer is required ( new descript or) t he DMA engine writ es back t o t he complet ed
descript or linking it t o t he new one ( Sect ion 7. 11. 5.1 det ails t he indicat ed descript or fields) .
Decrement t he RSCDESC paramet er by one and updat e t he DATDESC for each new opened
descript or.
Fi el ds on t he Last Descr i pt or s of Lar ge Recei v e Fi el ds on Al l Descr i pt or s Ex cept f or t he Last One
EOP: End of packet , and all ot her fields t hat are report ed
t oget her wit h t he EOP.
NEXTP: Point s t o t he next descript or of t he same large receive.
DD: indicat es t hat t his descript or is complet ed by t he hardware and can be processed by t he soft ware.
RSCCNT: indicat es t he number of coalesced packet s in t his descript or.

397
DMA complet ion.
Following DMA complet ion, set t he DATOFF t o t he byt e offset of t he next packet .
Not enough descript ors in t he receive ring buffer.
I f t he SRRCTL[ n] .Drop_En bit on t he relevant queue is set , The large receive complet es and t he
new packet is discarded.
Ot herwise ( t he Drop_En bit is cleared) , t he packet wait s inside t he int ernal packet buffer unt il new
descript ors are added ( indicat ed by t he relevant Tail regist er) .
Not enough descript ors due t o RSCDESC exhaust .
I f t he received packet requires more descript ors t han indicat ed by t he int ernal RSCDESC
paramet er, t hen t he 82599 complet es t he current large receive while t he new packet st art s a new
large receive.
7.11.6 RSC Compl et i on and Agi ng
This sect ion summarizes all causes of large receive complet ion ( t he first t hree cases repeat previous
sect ions) .
A packet of a new flow is received while t here are no free RSC cont ext s. t he 82599 complet es
( closes) t he oldest large receive ( opened first ) . The new packet st art s a new large receive using t he
evict ed cont ext .
The received packet cannot be added t o t he act ive large receive due t o one of t he following cases
( indicat ed also in Sect ion 7.11.4) . I n t hese cases t he exist ing RSC complet es and t he received
packet opens a new large receive.
The sequence number does not meet expect ed value.
The receive packet includes a t ime st amp TCP opt ion header while t here was no t ime st amp TCP
opt ion header in t he first packet in t he RSC.
There is not enough space in t he RSC buffer( s) for t he packet dat a. Meaning, t he received
packet requires a new buffer while t he RSC already exhaust ed all permit t ed buffers defined by
t he RSCCTL[ n] . MAXDESC.
The received packet requires a new buffer while it s descript or wraps around t he descript or ring.
When a packet s is received while t here are no more descript ors in t he receive queue and t he
SRRCTL.Drop_En bit is set , t he large receive complet es and t he new packet is discarded.
EI TR expirat ion while int errupt is enabled RSC complet ion is synchronized wit h int errupt
assert ion t o t he host . I t enables soft ware t o process t he received frames since t he last int errupt .
See more det ails and EI TR set t ing in Sect ion 7. 3. 2.1.1.
EI TR expirat ion while int errupt is disabled The I TR count er cont inues t o count even when it s
int errupt is disabled. Every t ime t he t imer expires it t riggers RSC complet ion on t he associat ed Rx
queues.
LLI packet recept ion All act ive RSCs on t he same Rx queue complet e and t hen t he int errupt is
assert ed. Hardware t hen t riggers RSC complet ion on all ot her queues associat ed wit h t his int errupt .
Low number of available descript ors Whenever crossing t he number of free Rx descript ors, t he
receive descript or minimum t hreshold size defined in t he SRRCTL[ n] regist ers an LLI event is
generat ed t hat affect s RSC complet ion as well.
I nt errupt assert ion by set t ing t he EI CS regist er has t he same impact on packet recept ion as
described in Sect ion 7.3. 1. 2. 1.
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398
Aut o RSC Disable When t he int errupt logic t riggers RSC complet ion it might also aut o- disable
furt her coalescing by clearing t he RSCI NT.RSCEN bit . Aut o RSC disablement is cont rolled by t he
RSCI NT.AUTORSC bit . I n t his mode, hardware also re- enables RSC ( by set t ing t he RSCI NT.RSCEN
bit back t o 1b) when t he int errupt is re- enabled by t he EI MS ( eit her by soft ware or hardware as
described in Sect ion 7. 3. 1.3 and Sect ion 7.3.1.5) .
Not e: I n some cases packet s t hat do not meet coalescing condit ions might have act ive RSC of t he
same flow. As an example: received packet s wit h ECE or CWR TCP flags. Such packet s bypass
complet ely t he RSC logic ( post ed as single packet s) , and do not cause a complet ion of t he
act ive RSC. The act ive RSC would event ually be closed by eit her recept ion of a legit imat e
packet t hat is processed by t he RSC logic but would not have t he expect ed TCP sequence
number. Or, an int errupt event closes all RSCs in it s Rx queue. When soft ware processes t he
packet s, it get s t hem in order even t hough t he RSC complet es aft er t he previous packet ( s)
t hat bypassed t he RSC logic.
Any int errupt closes all RSCs on t he associat ed receive queues. Therefore, when I TR is not
enabled any receive packet causes an immediat e int errupt and receive coalescing should not
be enabled on t he associat ed Rx queues.

399
7.12 I Psec Suppor t
7. 12. 1 Ov er v i ew
This sect ion defines t he hardware requirement s for t he I Psec offload abilit y included in t he 82599. I Psec
offload is t he abilit y t o handle ( in hardware) a cert ain amount of t he t ot al number of I Psec flows, while
t he remaining are st ill handled by t he operat ing syst em. I t is t he operat ing syst ems responsibilit y t o
submit t o hardware t he most loaded flows, in order t o t ake maximum benefit s of t he I Psec offload in
t erms of CPU ut ilizat ion savings. Est ablishing I Psec Securit y Associat ions bet ween peers is out side t he
scope of t his document , since it is handled by t he operat ing syst em. I n general, t he requirement s on
t he driver or on t he operat ing syst em for enabling I Psec offload are not det ailed here.
When an I Psec flow is handled in soft ware, since t he packet might be encrypt ed and t he int egrit y check
field already valid, and as I Pv4 opt ions might be present in t he packet t oget her wit h I Psec headers, t he
82599 processes it like it does for any ot her unsupport ed Layer4 prot ocol, and wit hout performing on it
any layer4 offload.
Refer t o sect ion Sect ion 4.6.12 for securit y offload enablement .
7.12.2 Har dw ar e Feat ur es Li st
7.12.2.1 Mai n Feat ur es
Offload I Psec for up t o 1024 Securit y Associat ions ( SA) for each of Tx and Rx.
On- chip st orage for bot h Tx and Rx SA t ables
Tx SA index is conveyed t o hardware via Tx cont ext descript or
Det erminist ic Rx SA lookup according t o a search key made of SPI , dest inat ion I P address, and
I P version t ype ( I Pv6 or I Pv4)
I Psec prot ocols:
I P Aut hent icat ion Header ( AH) prot ocol for aut hent icat ion
I P Encapsulat ing Securit y Payload ( ESP) for aut hent icat ion only
I P ESP for bot h aut hent icat ion and encrypt ion, only if using t he same key for bot h
Crypt o engines:
For AH or ESP aut hent icat ion only: AES- 128- GMAC ( 128- bit key)
For ESP encrypt ion and aut hent icat ion: AES- 128- GCM ( 128- bit key)
I Psec encapsulat ion mode: t ransport mode, wit h t unnel mode only in receive
I n Tx, packet s are provided by soft ware already encapsulat ed wit h a valid I Psec header, and
for AH wit h blank I CV inside
for ESP single send, wit h a valid ESP t railer and ESP I CV ( blank I CV)
for ESP large send, wit hout ESP t railer and wit hout ESP I CV
I n Rx, packet s are provided t o soft ware encapsulat ed wit h t heir I Psec header and for ESP wit h
t he ESP t railer and ESP I CV,
where up t o 255 byt es of incoming ESP padding is support ed, for peers t hat
prefer hiding t he packet lengt h
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I P versions:
I Pv4 packet s t hat do not include any I P opt ion
I Pv6 packet s t hat do not include any ext ension header ( ot her t han AH/ ESP ext ension header)
Rx st at us report ed t o soft ware via Rx descript or:
Packet t ype: AH/ ESP ( in t he SECSTAT field)
I Psec offload done ( SA mat ch) , in t he I PSSA field
One Rx error report ed t o soft ware via Rx descript or in t he following precedence order: no error,
invalid I Psec prot ocol, packet lengt h error, aut hent icat ion failed ( SECERR field)
7. 12. 2. 2 Cr oss Feat ur es
When I PSec offload is enabled, Et hernet CRC must be enabled as well by set t ing bot h TXCRCEN and
RXCRCSTRP bit s in t he HLREG0 regist er
Segment at ion: full coexist ence ( TCP/ UDP packet s only)
increment I Psec Sequence Number ( SN) and I nit ializat ion Vect or ( I V) on each addit ional
segment
Checksum offload: full coexist ence ( Tx and Rx)
I P header checksum
TCP/ UDP checksum
I P fragment at ion: no I Psec offload done on I P fragment s
RSS: full coexist ence, hash on t he same fields used wit hout I Psec ( eit her 4- t uples or 2- t uples)
LinkSec offload:
A device int erface is operat ed in eit her LinkSec offload or I Psec offload mode, but not bot h of
t hem alt oget her
I f bot h I Psec and LinkSec encapsulat ions are required on t he same packet s, t he 82599s
int erface is operat ed in LinkSec offload mode, while I Psec is performed by t he operat ing syst em
Virt ualizat ion:
Full coexist ence in VMDq mode
in I OV mode, all I Psec regist ers are owned by t he VMM/ PF. For example, I Psec can be used for
VMot ion t raffic.
No coexist ence wit h VM- t o-VM swit ch, I Psec packet s handled in hardware are not looped back
by t he 82599 t o anot her VM. Tx I Psec packet s dest ined t o a local VM must be handled in
soft ware and looped back via t he soft ware swit ch. However, an ant i- spoofing check is
performed on any I Psec packet .
DCB: full coexist ence
Priorit y flow cont rol, wit h special care t o respect t iming considerat ions
Bandwidt h allocat ion scheme enforced on I Psec packet s since 802. 1p field is always sent in
clear t ext
CM- t agging t akes place at Layer2 and t hen does not int erfere wit h I Psec
FCoE: no int eract ion as FCoE packet s are not I P packet s
RSC: no coexist ence
Jumbo frames: When t he SECTXCTRL. STORE_FORWARD bit is set ( as required for I PSec offload) ,
t he maximum support ed j umbo packet size is 9.5 KB ( 9728 byt es) . This limit at ion is valid for all
packet s regardless if t hey are offloaded by hardware or carry I PSec encapsulat ion alt oget her.
802.1x: no int eract ion

401
Teaming: no int eract ion
TimeSync:
TimeSync I EEE 1588v1 UDP packet s must not be encapsulat ed as I Psec packet s
No int eract ion wit h TimeSync 1588v2 Layer2 packet s
Layer2 encapsulat ion modes:
I Psec offload is not support ed for flows wit h SNAP header
I Psec offload coexist s wit h double VLAN encapsulat ions
Tunneled I Psec packet s in receive: I Psec offload support ed, but no ot her Layer4 offload performed
NFS and any ot her Layer5 Rx filt er: NFS or Layer5 packet s encapsulat ed over ESP ( whet her I Psec is
offloaded in hardware or not ) and over a Layer4 prot ocol ot her t han TCP are not parsed, nor
recognized
SCTP Rx offload: part ial coexist ence wit h SCTP CRC32 offload for I PSec-AH packet s only.
SCTP Tx offload: full coexist ence wit h SCTP CRC32 offload for bot h I PSec-AH and I PSec- ESP
packet s.
Manageabilit y t raffic: I Psec offload abilit y is cont rolled exclusively by t he host , and t hus
manageabilit y t raffic could use I Psec offload only if it is coordinat ed/ configured wit h/ by t he host .
For I Psec flows handled by soft ware:
I f manageabilit y and host ent it ies share some I P address( es) , t hen manageabilit y should
coordinat e any use of I Psec prot ocol wit h t he host . Not e it should be t rue for previous devices
t hat do not offer I Psec offload.
I f manageabilit y and host ent it ies have t ot ally separat e I P addresses, t hen manageabilit y can
use I Psec prot ocol ( as long as it is handled by t he manageabilit y cont roller soft ware)
Header split :
Support ed for SAs handled in hardware, I P boundary split includes t he I Psec header
For SAs handled in soft ware, no header split done
7.12.3 Sof t w ar e/ Har dw ar e Demar cat i on
The followings it ems are not support ed by hardware but might be support ed by operat ing syst em/
driver:
Mult icast SAs
I Psec prot ocols:
Bot h AH and ESP prot ocols on t he same SA or packet
ESP for encrypt ion only
ESP for bot h aut hent icat ion and encrypt ion using different keys and/ or different crypt o engines
Crypt o engines:
AES- 256, SHA- 1, AES- 128- CBC, or any ot her crypt o algorit hm
Tx I Psec packet s encapsulat ed in t unnel mode
Ext ended Sequence Number ( ESN)
I P versions:
I Pv4 packet s t hat include I P opt ion
I Pv6 packet s t hat include ext ension headers ot her t han t he AH/ ESP ext ension headers
Ant i- replay check and discard of incoming replayed packet s
Discard of incoming dummy ESP packet s ( packet s wit h prot ocol value 59)
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I Psec packet s t hat are I P fragment s
ESP padding cont ent check
I Psec st at ist ics
I Psec for flows wit h SNAP header
Not e: For SCTP and ot her Layer4 header t ypes, or for t unneled packet s, hardware does not care
what is t here when doing Rx I Psec processing. Everyt hing aft er t he I P/ I Psec headers can be
opaque t o hardware ( consider as I P payload) . I Psec processing can be done on any packet
t hat has a mat ching SA and appropriat e I P opt ions/ ext ension headers. There is no
expect at ion t hat hardware det ermines what is in t he packet beyond t he I P/ I Psec headers
before decrypt ing/ aut hent icat ing t he packet . The most import ant point is t hat hardware
should not corrupt or drop incoming I Psec packet s in any sit uat ion. When hardware
decides and st art s performing I Psec offload on a packet , it should pursue t he offload unt il t he
packet ' s end at t he price of event ually not doing ot her Layer3/ 4 offloads on it . I t is always
accept able for hardware not t o st art doing t he I Psec offload on a mat ched SA, if it knows it is
an unsupport ed encapsulat ion. For example, one of t he t hree cases: I Pv4 opt ion, I Pv6
ext ensions, or SNAP.
7. 12. 4 I Psec For mat s Ex changed Bet w een Har dw ar e and Sof t w ar e
This sect ion describes t he I Psec packet encapsulat ion format s used bet ween soft ware and hardware by
an I Psec packet concerned wit h t he offload in eit her Tx or Rx direct ion.
I n Rx direct ion, t he I Psec packet s are delivered by hardware t o soft ware encapsulat ed as t hey were
received from t he line, whet her I Psec offload was done or not , and when it was done, whet her
aut hent icat ion/ decrypt ing has succeeded or failed. Refer t o t he format s described in Sect ion 18. 3.
7. 12. 4. 1 Si ngl e Send
I n Tx direct ion, single- send I Psec packet s are delivered by soft ware t o hardware already encapsulat ed
and format t ed wit h t heir valid I Psec header and t railer cont ent s, as t hey should be run over t he wire
except for t he I CV field t hat is filled wit h zeros, and t he ESP payload dest ined t o be encrypt ed t hat is
provided in clear t ext before I Psec encrypt ion.
7. 12. 4. 2 Si ngl e Send w i t h TCP/ UDP Check sum Of f l oad
For single- send ESP packet s wit h TCP/ UDP checksum offload, t he checksum comput ing includes t he
TCP/ UDP header and payload before hardware encrypt ion occurred and wit hout t he ESP t railer and ESP
I CV provided by soft ware. Soft ware provides t he lengt h of t he ESP t railer plus ESP I CV in a dedicat ed
field of t he Tx cont ext descript or ( I PS_ESP_LEN field) t o signal hardware when t o st op TCP/ UDP
checksum comput ing.
Soft ware calculat es a full checksum for t he I P pseudo- header as in t he usual case. The prot ocol value
used in t he I P pseudo- header must be t he TCP/ UDP prot ocol value and not t he AH/ ESP prot ocol value
t hat appears in t he I P header. This full checksum of t he pseudo- header is placed in t he packet dat a
buffer at t he appropriat e offset for t he checksum calculat ion.

403
The byt e offset from t he st art of t he DMA' ed dat a t o t he first byt e t o be included in t he TCP/ UDP
checksum ( t he st art of t he TCP header) is comput ed as in t he usual case: MACLEN+ I PLEN. I t assumes
t hat I PLEN provided by soft ware in t he Tx cont ext descript or is t he sum of t he I P header lengt h wit h t he
I Psec header lengt h.
Not e: For t he I Pv4 header checksum offload, hardware cannot rely on t he I PLEN field provided by
soft ware in t he Tx cont ext descript or, but should rely on t he fact t hat no I Pv4 opt ions are
present in t he packet . Consequent ly, for I Psec offload packet s, hardware always comput es I P
header checksum over a fixed amount of 20 byt es.
7.12. 4. 3 TSO TCP/ UDP
I n Tx direct ion, TSO I Psec packet s are delivered by soft ware t o t he 82599 already encapsulat ed and
format t ed wit h only t heir valid I Psec header cont ent s except for t he I CV field included in AH packet s
headers t hat is filled wit h zeros, and t o t he ESP payload dest ined t o be encrypt ed t hat is provided in
clear t ext before any encrypt ion. No ESP t railer or ESP I CV are appended t o TSO by soft ware. I t means
t hat hardware has t o append t he ESP t railer and ESP I CV on each segment by it self, and t o updat e I P
t ot al lengt h / I P payload lengt h accordingly.
The next header of t he ESP t railer t o be appended by hardware is t aken from TUCMD.L4T field of t he Tx
cont ext descript or.
By definit ion TSO requires on each segment t hat t he I P t ot al lengt h / I P payload lengt h be updat ed, and
t he I P header checksum and TCP/ UDP checksum be re- comput ed. But for t he TSO of I Psec packet s, t he
SN and t he I V fields must be increased by one in hardware on each new segment ( aft er t he first one) as
well.
Soft ware calculat es a part ial checksum for t he I P pseudo- header as in t he usual case. The prot ocol
value used in t he I P pseudo- header must be t he TCP/ UDP prot ocol value and not t he AH/ ESP prot ocol
value t hat appears in t he I P header. This part ial checksum of t he pseudo header is placed in t he packet
dat a buffer at t he appropriat e offset for t he checksum calculat ion.
The byt e offset from t he st art of t he DMA' ed dat a t o t he first byt e t o be included in t he TCP checksum
( t he st art of t he TCP/ UDP header) is comput ed as in t he usual case: MACLEN+ I PLEN. I t assumes t hat
I PLEN provided by soft ware in t he Tx cont ext descript or is t he sum of t he I P header lengt h wit h t he
I Psec header lengt h.
For TSO ESP packet s, t he TCP/ UDP checksum comput ing includes t he TCP/ UDP header and payload
before hardware encrypt ion occurred and wit hout t he ESP t railer and ESP I CV appended by hardware.
The 82599 t hus st ops TCP/ UDP checksum comput ing aft er t he amount of byt es given by L4LEN + MSS.
I t is assumed t hat t he MSS value placed by soft ware in t he Tx cont ext descript or specifies t he
maximum TCP/ UDP payload segment sent per frame, not including any I Psec header or t railer and
not including t he TCP/ UDP header.
Not e: For I Pv4 header checksum comput ing, refer t o t he not e in sect ion Sect ion 7. 12. 4.2.
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404
Shaded fields in t he t ables t hat follow correspond t o fields t hat need t o be updat ed per each segment .
Tabl e 7.78. I Pv4 TSO ESP Pack et Pr ov i ded by Sof t w ar e
0 3 4 7 8 15 16 19 23 24 31
1 Ver Hlen TOS I P Tot al Lengt h
2 I dent ificat ion Flags Fragment Offset
3 TTL Prot ocol = ESP Header Checksum
4 Source I Pv4 Address
5 Dest inat ion I Pv4 Address
1 Securit y Paramet er I ndex ( SPI )
2 Sequence Number ( SN)
3
I nit ializat ion Vect or ( I V)
4
1
TCP/ UDP Header
TCP/ UDP Payload
Tabl e 7.79. I Pv6 TSO ESP Pack et Pr ov i ded by Sof t w ar e
0 3 4 7 8 15 16 23 24 31
1 Ver Priorit y Flow Label
2 I P Payload Lengt h Next Header = ESP Hop Limit
3
Source I Pv6 Address
4
5
6
7
Dest inat ion I Pv6 Address
8
9
10

405
7.12.5 TX SA Tabl e
I Psec offload is support ed only via advanced t ransmit descript ors. See Sect ion 7.2.3. 2. 4 for det ails.
7.12. 5. 1 Tx SA Tabl e St r uct ur e
The Tx SA t able cont ains addit ional informat ion required by t he AES- 128 crypt o engine t o aut hent icat e
and encrypt dat a. This informat ion is not run over t he wire t oget her wit h t he I Psec packet s, but is
exchanged bet ween t he I Psec peers operat ing syst em during t he SA est ablishment process. When t he
I KE soft ware does a key comput at ion it comput es four ext ra byt es using a pseudo- random funct ion ( it
generat es 20 byt es inst ead of 16 byt es t hat it needs t o use as a key) and t he last four byt es are used
as a salt value.
The SA t able in Tx is a 1024 x 20- byt e t able loaded by soft ware. Each line in t he t able cont ains t he
following fields:
Refer t o Sect ion 7. 12.7 for a descript ion of t he way t hese fields are used by t he AES- 128 crypt o engine.
Each t ime an unrecoverable memory error occurs when accessing t he Tx SA t ables, an int errupt is
generat ed and t he t ransmit pat h is st opped unt il t he host reset s t he 82599. Packet s t hat have already
st art ed t o be t ransmit t ed on t he wire are sent wit h a wrong CRC.
Upon reset , t he 82599 clears t he cont ent s of t he Tx SA t able. Not e t hat access t o Tx SA t able is not
guarant eed for 10 s aft er t he reset command.
1 Securit y Paramet er I ndex ( SPI )
2 Sequence Number ( SN)
3
I nit ializat ion Vect or ( I V)
4
1
TCP/ UDP Header
TCP/ UDP Payload
Tabl e 7. 80. TX SA Tabl e
AES- 128 KEY AES- 128 SALT
16 byt es 4 byt es
Tabl e 7.79. I Pv6 TSO ESP Pack et Pr ovi ded by Sof t w ar e ( Cont i nued)
0 3 4 7 8 15 16 23 24 31
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7. 12. 5. 2 Access t o Tx SA Tabl e
7.12.5.2.1 Wr i t e Access
1. Soft ware writ es t he I PSTXKEY 0.. .3 and/ or I PSTXSALT regist er( s) .
2. Soft ware writ es t he I PSTXI DX regist er wit h t he SA_I DX field carrying t he index of t he SA ent ry t o
be writ t en, and wit h t he Writ e bit set ( Read bit cleared) .
3. Hardware issues a Writ e command int o t he SA t able, copying t he I PSTXKEY ( 16 byt es) and t he
I PSTXSALT ( 4 byt es) regist ers int o t he t able ent ry point ed by t he SA_I DX field configured in
I PSTXI DX regist er. I t t hen clears t he Writ e bit in I PSTXI DX regist er.
4. Soft ware st art s/ resumes sending I Psec offload packet s wit h t he I Psec SA I DX field in t he Tx cont ext
descript or point ing t o valid/ invalid SA ent ries. A valid SA ent ry cont ains updat ed key and salt fields
current ly in use by t he I Psec peers.
7.12.5.2.2 Read Access
1. Soft ware writ es t he I PSTXI DX regist er wit h t he index of t he SA ent ry t o be read, and wit h t he Read
bit set ( Writ e bit cleared) .
2. Hardware issues a Read command from t he SA t able, copying int o t he regist ers t he I PSTXKEY ( 16
byt es) and t he I PSTXSALT ( 4 byt es) values from t he t able ent ry point ed by t he SA_I DX field
configured in t he I PSTXI DX regist er. I t t hen clears t he Read bit in I PSTXI DX regist er.
3. Soft ware reads t he I PSTXKEY 0...3 and/ or I PSTXSALT regist er( s) .
7.12. 6 TX Har dw ar e Fl ow
7. 12. 6. 1 Si ngl e Send w i t hout TCP/ UDP Check sum Of f l oad
1. Ext ract I Psec offload request from t he I PSEC bit of t he POPTS field in t he advanced Tx t ransmit dat a
descript or.
2. I f I Psec offload is required for t he packet ( I PSEC bit was set ) , t hen ext ract t he SA_I DX, Encrypt ion,
and I PSEC_TYPE fields from t he Tx cont ext descript or associat ed t o t hat flow.
3. Fet ch t he AES- 128 KEY and Salt from t he Tx SA ent ry indexed by SA_I DX and according t o t he
Encrypt ion and I PSEC_TYPE bit s t o det ermine which I Psec offload t o perform.
4. For AH, zero t he mut able fields.
5. Comput e I CV and encrypt ion dat a ( if required for ESP) over t he appropriat e fields as specified in
Sect ion 18.3, according t o t he operat ing rules described in Sect ion 7.12.7, and making use of t he
AES- 128 KEY and Salt fields fet ched in st ep 3.
6. I nsert I CV at it s appropriat e locat ion and replace t he plaint ext wit h t he ciphert ext ( if required for
ESP) , as specified in Sect ion 18.3.
7. 12. 6. 2 Si ngl e Send w i t h TCP/ UDP Check sum Of f l oad
1. Ext ract t he I Psec offload command from t he I PSEC bit of t he POPTS field in t he advanced Tx
t ransmit dat a descript or.
I PSEC_TYPE, and I PS_ESP_LEN fields from t he Tx cont ext descript or associat ed t o t hat flow.
3. Fet ch t he AES- 128 KEY and Salt from t he Tx SA ent ry indexed by SA_I DX, and according t o t he
4. Comput e t he byt e offset from t he st art of t he DMA' ed dat a t o t he first byt e t o be included in t he
checksum ( t he st art of t he TCP header) as specified in Sect ion 7. 12. 4.2.

407
5. Comput e TCP/ UDP checksum unt il eit her t he last byt e of t he DMA dat a or for ESP packet s, up t o
I PS_ESP_LEN byt es before it . As in t he usual case, implicit ly pad out t he dat a by one zeroed byt e if
it s lengt h is an odd number.
6. Sum t he full checksum of t he I P pseudo header placed by soft ware at it s appropriat e locat ion wit h
t he TCP/ UDP checksum comput ed in st ep 5. Overwrit e t he checksum locat ion wit h t he 1s
complement of t he sum.
8. Comput e I CV and encrypt dat a ( if required for ESP) over t he appropriat e fields as specified in
Sect ion 18. 3, according t o t he operat ing rules described in Sect ion 7. 12. 7, and making use of t he
AES- 128 KEY and Salt fields fet ched in st ep 3.
7.12. 6. 3 TSO TCP/ UDP
1. Ext ract t he I Psec offload command from t he I PSEC bit of t he POPTS field in t he advanced Tx
t ransmit dat a descript or.
and I PSEC_TYPE fields from t he Tx cont ext descript or associat ed t o t hat flow.
3. Fet ch t he AES- 128 KEY and Salt from t he Tx SA ent ry indexed by SA_I DX, and according t o t he
4. Fet ch t he packet header from syst em memory, up t o I PLEN+ L4LEN byt es from t he st art of t he
DMA' ed dat a.
5. Overwrit e t he TCP SN wit h t he st ored accumulat ed TCP SN ( if it is not t he first segment ) .
6. Fet ch ( next ) MSS byt es ( or t he remaining byt es up t o PAYLEN for t he last segment ) from syst em
memory and from t he segment formed by packet header and dat a byt es, while st oring t he
accumulat ed TCP SN.
7. Comput e t he byt e offset from t he st art of t he DMA'ed dat a t o t he first byt e t o be included in t he
checksum ( t he st art of t he TCP header) as specified in Sect ion 7. 12. 4. 3.
8. Comput e TCP/ UDP checksum unt il t he last byt e of t he DMA dat a. As in t he usual case, implicit ly pad
out t he dat a by one zeroed byt e if it s lengt h is an odd number.
9. For bot h I Pv4 and I Pv6, hardware needs t o fact or in t he TCP/ UDP lengt h ( t ypically L4LEN+ MSS) t o
t he soft ware- supplied pseudo header part ial checksum. I t t hen sums t o obt ain a full checksum of
t he I P pseudo header wit h t he TCP/ UDP checksum comput ed in st ep 7. Overwrit e t he TCP/ UDP
checksum locat ion wit h t he 1s complement of t he sum.
10. I ncrement by one t he AH/ ESP SN and I V fields on every segment ( except ed t o t he first segment ) ,
and st ore t he updat ed SN and I V fields wit h ot her t emporary st at uses st ored for t hat TSO ( one
TSO set of st at uses per Tx queue) .
11. For ESP, append t he ESP t railer: 0- 3 padding byt es, padding lengt h, and next header = TCP/ UDP
prot ocol value, in a way t o get t he 4- byt e alignment as described in Sect ion 7.12.4.3.
12. Comput e t he I P t ot al lengt h / I P payload lengt h and comput e I Pv4 header checksum as described in
t he not e of Sect ion 7.12.4.1. Place t he result s in t heir appropriat e locat ion.
14. Comput e I CV and encrypt ion dat a ( if required for ESP) over t he appropriat e fields as specified in
Sect ion 18. 3, according t o t he operat ing rules described in Sect ion 7. 12. 7, and making use of t he
AES- 128 KEY and Salt field fet ched in st ep 3.
16. Go back t o st ep 4 t o process t he next segment ( if necessary) .
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7.12. 7 AES- 128 Oper at i on i n Tx
The AES- 128- GCM crypt o engine used for I Psec is t he same AES- 128- GCM crypt o engine used for
LinkSec. I t is referred t hroughout t he document as an AES- 128 black box, wit h 4- bit st ring input s and
2- bit st ring out put s, as shown in Figure 7. 45. Refer t o t he GCM specificat ion for t he int ernal det ails of
t he engine. The difference bet ween I Psec and LinkSec, and bet ween t he different I Psec modes reside in
t he set of input s present ed t o t he box.
Key 128- bit s AES- 128 KEY field ( secret key) st ored for t hat I Psec flow in t he Tx SA t able:
Key = AES- 128 KEY
Nonce 96- bit s init ializat ion vect or used by t he AES- 128 engine, which is dist inct for each
invocat ion of t he encrypt ion operat ion for a fixed key. I t is formed by t he AES- 128 Salt field st ored
for t hat I Psec flow in t he Tx SA t able, appended wit h t he I nit ializat ion Vect or ( I V) field included in
t he I Psec packet :
Nonce = [ AES- 128 SALT, I V]
The nonce, also confusingly referred as I V in t he GCM specificat ion, is broken int o t wo pieces a
fixed random part salt and increasing count er part I V, so t he salt value goes wit h t he packet as t he
fixed part . The purpose behind using t he salt value is t o prevent offline dict ionary- t ype at t acks in
hashing case, t o prevent predict able pat t erns in t he hash.
AAD Addit ional Aut hent icat ion Dat a input , which is aut hent icat ed dat a t hat must be left un-
encrypt ed.
Pl ai nt ex t Dat a t o be bot h aut hent icat ed and encrypt ed.
Ci pher t ex t Encrypt ed dat a, whose lengt h is exact ly t hat of t he plaint ext .
I CV 128- bit I nt egrit y Check Value ( referred also as aut hent icat ion t ag) .
H is int ernally derived from t he key.
Not e: The square bracket s in t he formulas is used as a not at ion for concat enat ed fields.
Fi gur e 7.45. AES- 128 Cr y pt o Engi ne Box
Key
Nonce
AAD
Plaintext
ICV
Ciphertext
Pipeline engine
for AES counter
mode
Finite Field
Multiplier
H

409
7.12. 7. 1 AES- 128- GCM f or ESP Bot h Aut hent i cat e and Encr y pt i on
AAD = [ SPI , SN]
Pl ai nt ext = [ TCP/ UDP header, TCP/ UDP payl oad, ESP t rai l er ]
Not e: Unlike ot her I Psec modes, in t his mode, t he I V field is used only in t he nonce, and it is not
included in eit her t he plaint ext or t he AAD input s.
ESP t railer does not include t he I CV field. Refer t o Sect ion 18. 3. 2.
7.12. 7. 2 AES- 128- GMAC f or ESP Aut hent i cat e Onl y
AAD = [ SPI , SN, I V, TCP/ UDP header, TCP/ UDP payl oad, ESP t rai l er ]
Pl ai nt ext = [ ] = empt y st r i ng, no pl ai nt ext i nput i n t hi s mode
Not e: ESP t railer does not include t he I CV field. Refer t o Sect ion 18. 3. 2.
7.12. 7. 3 AES- 128- GMAC f or AH Aut hent i cat e Onl y
AAD = [ I P header, AH header, TCP/ UDP header, TCP/ UDP payl oad]
Pl ai nt ext = [ ] = empt y st r i ng, no pl ai nt ext i nput i n t hi s mode
Not e: Bot h I P header and AH header cont ain mut able fields t hat must be zeroed prior t o be ent ered
int o t he engine. Refer t o Sect ion 18. 3. 1. Among ot her fields, t he AH header includes SPI , SN,
and I V fields.
7.12.8 RX Descr i pt or s
I Psec offload is support ed only via advanced receive descript ors. See Sect ion 7. 1.6 for det ails.
7.12.9 Rx SA Tabl es
7.12. 9. 1 Rx SA Tabl es St r uct ur e
The Rx SA t ables cont ain addit ional informat ion required by t he AES- 128 crypt o engine t o aut hent icat e
and decrypt t he dat a. This informat ion is not run over t he wire t oget her wit h t he I Psec packet s, but is
exchanged bet ween t he I Psec peers operat ing syst em during t he SA est ablishment process. When t he
I KE soft ware does a key comput at ion it comput es four ext ra byt es using a pseudo- random funct ion ( it
generat es 20 byt es inst ead of 16 byt es t hat it needs t o use as a key) and t he last four byt es are used
as a salt value.
SPI is allocat ed by t he receiving operat ing syst em in a unique manner. However, in a virt ualized
cont ext , guest operat ing syst ems can allocat e SPI values t hat collide wit h t he SPI values allocat ed by
t he VMM/ PF. Consequent ly, t he SPI search must be complet ed by comparing t he dest inat ion I P address
wit h t he I P addresses of t he VMM/ PF, which are st ored in a separat e t able. Guest operat ing syst ems
could t hus use t he proposed I Psec offload as long as t heir SAs are configured via t he VMM/ PF. I t is
assumed t hat refreshing t he SAs would be done once every several minut es, and would t hus not
overload t he VMM/ PF.
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410
There are t hree Rx SA t ables in t he 82599:
I P address t able 128 ent ries
SPI t able 1K ent ries
KEY t able 1K ent ries
They are loaded by soft ware via indirect ly addressed CSRs, as described in Sect ion 7. 12. 9.2.
The I Psec Mode field cont ains t he following bit s:
VALI D
I Pv6
PROTO
DECRYPT
I t is assumed t hat t he SPI and I P address t ables are implement ed int ernally in CAM cells, while t he KEY
t able uses RAM cells. When an incoming I Psec packet ( which does not includes opt ion in I Pv4 or
anot her ext ension header in I Pv6) is det ect ed, hardware first looks up for t he dest inat ion I P address t o
mat ch one of t he I P addresses st ored in t he I P address t able. I f t here is a mat ch, t he index of t hat I P
Addr. mat ch is used t oget her wit h t he SPI field ext ract ed from t he packet for a second lookup int o t he
SPI t able. I f t here is again a mat ch, t hen t he index of t hat SPI + I P I ndex mat ch is used t o ret rieve t he
SA paramet ers from t he KEY t able. The packet is finally considered t o get an SA mat ch only aft er
inspect ing t he corresponding ent ry in t he KEY t able, as long as all t he following condit ions are met :
Valid bit is set
I Pv6 bit mat ch wit h t he I P version ( I Pv6/ I Pv4) of t he incoming I Psec packet
Prot o bit mat ch wit h t he AH/ ESP t ype of t he incoming I Psec packet
Each t ime an unrecoverable memory ECC error occurs when accessing one of t he Rx SA t ables, an
int errupt is generat ed and t he receive pat h is st opped unt il t he host reset s t he 82599.
Upon reset , t he 82599 clears t he cont ent s of t he Rx KEY t able and soft ware is required t o invalidat e t he
ent ire I P address and SPI CAM t ables by clearing t heir cont ent s. Access t o Rx SA t ables is not
guarant eed for 10 s aft er t he Reset command.
Tabl e 7.81. I P Addr ess Tabl e
I P Address
16 byt es
Tabl e 7.82. SPI Tabl e
SPI
I P I ndex
( point s t o I P address t able)
4 byt es 1 byt es
Tabl e 7.83. KEY Tabl e
I Psec Mode AES- 128 KEY AES- 128 SALT
1 byt e 16 byt es 4 byt es

411
7.12. 9. 2 Access t o Rx SA Tabl es
7.12.9.2.1 Wr i t e Access
1. Soft ware writ es t he I P address t able via t he I PSRXI PADDR 0. .. 3 regist ers
2. Soft ware writ es t he I PSRXI DX regist er wit h t he following:
a. Table bit s combinat ion corresponding t o t he Rx SA t able t o be writ t en ( such as 01b for I P address
t able)
b. TB_I DX field point ing t o t he index t o be writ t en wit hin t he t able
c. Writ e bit set ( Read bit cleared)
3. Hardware issues a Writ e command int o t he Rx SA t able point ed by t he Table bit s combinat ion,
copying t he concerned regist er( s) int o t he ent ry point ed by t he TB_I DX field configured in t he
I PSRXI DX regist er. I t t hen clears t he Writ e bit in I PSRXI DX regist er.
4. Soft ware performs st eps 1 t o 3 t wice, first for writ ing t he SPI t able via I PSRXSPI , I PSRXI PI DX
regist ers, and second for writ ing t he KEY t able via I PSRXKEY 0...3, I PSRXSALT, and I PSRXMOD
regist ers.
Each t ime an ent ry in t he I P address or SPI t able is not valid/ in- use anymore, soft ware is required t o
invalidat e it s cont ent by clearing it . For t he I P t able, an ent ry must be invalidat ed by soft ware each t ime
t here is no more SPI ent ry t hat point s t o it ; while for t he SPI t able, soft ware must invalidat e any ent ry
as soon as it is not valid/ not used anymore.
7.12.9.2.2 Read Access
1. Soft ware writ es t he I PSRXI DX regist er wit h t he Table and TB_I DX fields corresponding t o t he Rx SA
t able and ent ry t o be read, and wit h t he Read bit set ( Writ e bit cleared) .
2. Hardware issues a Read command from t he Rx SA t able and ent ry point ed by Table bit s
combinat ion and TB_I DX field, copying each field int o it s corresponding regist er. I t t hen clears t he
Read bit in I PSRXI DX regist er.
3. Soft ware reads t he corresponding regist er( s) .
Caut i on: There is an int ernal limit at ion in t hat only one single Rx SA t able can be read accessed by
soft ware at a t ime. Hence, it is recommended t hat t he ent ire read process, from st eps 1 t o 3,
be repeat ed successively for each Rx SA t able separat ely.
7.12.10 RX Har dw ar e Fl ow w i t hout TCP/ UDP Check sum Of f l oad
1. Det ect an I Psec header not encapsulat ed over a SNAP header is present wit hout any I Pv4 opt ion or
ot her I Pv6 ext ension header encapsulat ed before it , and det ermine it s t ype AH/ ESP.
2. I f such an I Psec header is present ( as announced by t he I P prot ocol field for I Pv4 or by t he next
header for I Pv6) , t hen ext ract t he SPI , dest inat ion I P address, and I P version ( I Pv4 or I Pv6) , and
use t hese fields for t he lookups int o t he Rx SA t ables as described in Sect ion 7.12. 9.1. Also report
t he I Psec prot ocol found in t he Securit y bit s of t he Ext ended St at us field in t he advanced Rx
descript or.
3. I f t here is a SA mat ch for t hat packet , fet ch t he I Psec Rx mode from t he SA ent ry, and according t o
t he Prot o and Decrypt bit s det ermine which I Psec offload t o perform. Also, set t he I PSSA bit of t he
Ext ended St at us field in t he advanced Rx descript or. I f t here was no SA mat ch, t hen clear t he
I PSSA bit , report no error in Securit y error bit s of t he Ext ended Errors field in t he advanced Rx
descript or, and st op processing t he packet for I Psec.
4. I f t he Prot o field recorded in t he Rx SA t able does not mat ch t he I P Prot ocol field ( next header for
I Pv6) seen in t he packet , t hen report it via t he Securit y error bit s of t he Ext ended Errors field in t he
advanced Rx descript or, and st op processing t he packet for I Psec.
5. Fet ch t he AES- 128 KEY and Salt from t he mat ched Rx SA ent ry.
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412
7. Make sure t he AH/ ESP header is not t runcat ed, and for ESP make sure whet her or not t he packet is
4- byt es aligned. I f not , report it via t he Securit y error bit s of t he Ext ended Errors field in t he
advanced Rx descript or, but processing of t he packet for I Psec might be complet ed ( if it has already
st art ed) . A t runcat ed I Psec packet is a valid Et hernet frame ( at least 64 byt es) short er t han:
a. ESP at least 40 byt es following t he I P header ( 16 [ ESP header] + 4 [ min. padding, pad_len,
NH] + 16 [ I CV] + 4 [ CRC] )
b. AH over I Pv4 at least 40 byt es following t he I P header ( 20 [ AH header] + 16 [ I CV] + 4 [ CRC] )
c. AH over I Pv6 at least 44 byt es following t he I P header ( 20 [ AH header] + 4 [ I CV padding] +
16 [ I CV] + 4 [ CRC] )
8. Comput e I CV and decrypt dat a ( if required for ESP) over t he appropriat e fields as specified in
Sect ion 18.3, according t o t he operat ing rules described in Sect ion 7. 12. 12, and making use of t he
AES- 128 KEY and SALT fields fet ched in st ep 5.
9. Compare t he comput ed I CV wit h t he I CV field included in t he packet at it s appropriat e locat ion as
specified in Sect ion 18.3, and report t he comparison st at us mat ch/ fail via t he Securit y error bit s of
t he Ext ended Errors field in t he advanced Rx descript or.
7.12. 11 RX Har dw ar e Fl ow w i t h TCP/ UDP Check sum Of f l oad
Perform t he RX hardware flow described in Sect ion 7.12.10 and add t he following st eps:
10. St art comput ing t he checksum from t he TCP/ UDP header s beginning found according t o t he Rx
parser logic updat ed for I Psec format s described in Sect ion 18. 3. Do not perform Layer4 offloads if
unsupport ed I Psec encapsulat ion is det ect ed. For example, t unneled I Psec, I Pv4 opt ions or I Pv6
ext ensions aft er t he I Psec header.
11. For ESP, st op checksum comput ing before t he beginning of t he ESP t railer found from t he end of
packet according t o t he padding lengt h field cont ent , and t o t he format s described in
Sect ion 18.3. 2. As in t he usual case, implicit ly pad out t he dat a by one zeroed byt e if it s lengt h is
an odd number.
12. St ore t he next header ext ract ed from t he AH header/ ESP t railer int o t he Packet Type field of t he
advanced Rx descript or, but use t he TCP/ UDP prot ocol value in t he I P pseudo header used for t he
TCP/ UDP checksum. Also comput e t he TCP/ UDP packet lengt h t o be insert ed in t he I P pseudo
header ( excluding any I Psec header or t railer) .
13. Compare t he comput ed checksum value wit h t he TCP/ UDP checksum included in t he packet . Report
t he comparison st at us in t he Ext ended Errors field of t he advanced Rx descript or.
7.12. 12 AES- 128 Oper at i on i n Rx
The AES- 128 operat ion in Rx is similar t o t he operat ion in Tx, while for decrypt ion, t he encrypt ed
payload is fed int o t he plaint ext input , and t he result ed ciphert ext st ands for t he decrypt ed payload.
Refer t o Sect ion 7.12.7 for t he proper input s t o use in every I Psec mode.

413
7. 12. 12. 1 Handl i ng I Psec Pack et s i n Rx
The following t able list s how I Psec packet s are handled according t o some of t heir charact erist ics.
Tabl e 7. 84. Summar y of I Psec Pack et s Handl i ng i n Rx
I P
Fr agment
I Pv4 Opt i on
or I Pv6
Ex t ensi ons
or SNAP
I P
Ver si on
SA Mat ch
I Psec
Of f l oad i n
Har dw ar e
Lay er 4/ 3
Of f l oad i n
Har dw ar e
Header Spl i t
AH/ ESP
Repor t ed
i n Rx
Desc.
Yes Yes v4 Dont care No I P checksum only
Up t o I Psec header
included
Yes
Yes Yes v6 Dont care No No
Up t o I P fragment
ext ension included
No
Yes No v4 Dont care No I P checksum only
Up t o I Psec header
included
Yes
No Yes v4 Dont care No I P checksum only No Yes
No Yes v6 Dont care No No
Up t o first unknown or
I Psec ext ension header,
excluded
No
1
1. Except ion t o SNAP I Psec packet s t hat are report ed as AH/ ESP in Rx descript or.
No No v4 Yes Yes Yes
2
2. No Layer4 offload done on packet s wit h I PSec error.
Yes
3
3. According t o definit ion made in PSRTYPE[ n] regist ers.
Yes
No No v4 No No I P checksum only No Yes
No No v6 Yes Yes Yes
4
4. No Layer4 offload done on packet s wit h I PSec error.
Yes
3
Yes
No No v6 No No No No Yes
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7.13 Fi br e Channel ov er Et her net ( FCoE)
7.13. 1 I nt r oduct i on
Fibre Channel ( FC) is t he predominant prot ocol used in St orage Area Net works ( SAN) . Fibre Channel
over Et hernet ( FCoE) is used t o connect an Et hernet st orage init iat or and legacy FC st orage t arget s.
The FC prot ocol is based on high reliabilit y of t he communicat ion link bet ween t he init iat or and t he
st orage t arget . I t assumes an ext remely low error rat e of 10
- 12
and no packet drop. DCB ext ends
Et hernet t hrough class- based flow cont rol in such a way t hat FC- like no- drop is guarant eed as required
by FC. Doing so, FC prot ocol can be t ransposed t o an Et hernet link by Layer 2 encapsulat ion t hat is
defined by t he FCoE prot ocol. Figure 7. 46 shows a connect ion bet ween an FCoE init iat or and legacy FC
t arget s.
Exist ing FC HBAs used t o connect bet ween an FC init iat or and FC t arget s provide full offload of t he FC
prot ocol t o t he init iat or t o maximize st orage performance. I n order t o compet e wit h t his market , t he
82599 offloads t he main dat a pat h of I / O Read and Writ e commands t o t he st orage t arget .
7. 13. 1. 1 FC Ter mi nol ogy
Useful background on FC framing and it s Et hernet encapsulat ion can be found in Sect ion 18.5. More
comprehensive mat erial can be found in t he FI BRE CHANNEL FRAMI NG AND SI GNALI NG- 2 ( FC- FS- 2)
specificat ion. Following are some of t he most common t erms used ext ensively in t he sect ions t hat
describe t he FCoE funct ionalit y.
FC Ex change - Complet e FC read or FC writ e flow. I t st art s wit h a read or writ e request by t he init iat or
( t he host syst em) unt il it receives a complet ion indicat ion from t he t arget ( t he remot e disk) .
FC Sequence - An FC exchange is composed of mult iple FC sequences. An FC sequence can be single
or mult iple frames t hat are sent by t he init iat or or t he t arget . Also, each FC sequence has a unique
sequence I D.
FC Fr ame - FC frames are t he smallest unit s sent bet ween t he init iat or and t he t arget . The FC- FS- 2
specificat ion defines t he maximum frame size as 2112 byt es. Each FC frame includes an FC header and
opt ional FC payload. I t also may include ext ended headers and FC opt ional headers. Ext ended headers
ot her t han Virt ual Fabric Tagging ( VFT) are not expect ed in an FCoE net work and FC opt ional headers
are not used in most cases as well.
Fi gur e 7.46. Connect i ng an FCoE I ni t i at or t o FC Tar get s
Legacy FC Target
Legacy FC Target
DCB
Ethernet
FCoE Initiator
FC
FC
FCoE gateway
LAN
Network
Ethernet

415
Dat a Fr ame - FC frames t hat carry read or writ e dat a.
FCP_RSP Fr ame - FC cont rol frames are sent from t he t arget t o t he init iat or, which defines t he
complet ion of an FC read or writ e exchange.
7. 13. 2 FCoE Tr ansmi t Oper at i on
Transmit FCoE offload is enabled by set t ing t he TUCMD. FCoE bit in t he t ransmit cont ext descript or. The
82599 support s t he following offload capabilit ies: FC CRC calculat ion and insert ion, FC padding
insert ion and FC segment at ion. These capabilit ies are described in t he following sect ions.
7. 13. 2. 1 FCoE Tr ansmi t Cr oss Funct i onal i t y
Aft er set t ing t he TUCMD. FCoE bit , hardware digest s t he packet s cont ent before it is sent t o t he wire. I n
t his case, soft ware must enable hardware offload for addit ional t asks as follows:
7. 13. 2. 2 FC Paddi ng I nser t i on
FC frames always consist of a whole number of four byt es. I f user dat a is not composed of a whole
number of four byt es, t hen t he FC frames cont ain padding byt es wit h a zero value. The lengt h of t he
padding byt es can be any number bet ween zero t o t hree so t oget her wit h t he user dat a, t he lengt h of
t he FC frames has a whole number of four byt es. The lengt h of t he padding byt es is indicat ed by
soft ware in t he Fill Byt es field in t he FC header. This field is used by t he receiving end node ( t arget ) t o
ext ract t hese byt es. Hardware does not use t his field t o ident ify t he required lengt h of t he padding
byt es. I nst ead, it checks t he t ransmit buffer size indicat ed by t he PAYLEN field in t he t ransmit dat a
descript or. The lengt h of t he padding byt es added by hardware equals:
2s complement { t wo LS bit s of ( PAYLEN minus MACLEN) } . While PAYLEN is defined in t he Tx dat a
descript or and MACLEN is defined in t he Tx cont ext descript or.
The 82599 aut o- pads t he frame wit h t he required zero byt es when FCoE offload is enabled
( TUCMD.FCoE bit is set ) . I n TSO, padding byt es are added only on t he last frame since t he MSS must
be a whole number of four byt es.
Cr oss Funct i on Requi r ement s
Et hernet CRC insert ion
Soft ware must enable Et hernet CRC insert ion by set t ing t he I FCS bit in t he t ransmit dat a
descript or. The Et hernet CRC covers t he ent ire packet . Enabling FCoE offloading, hardware
modifies t he packet cont ent and must also adj ust t he Et hernet CRC.
LinkSec offload
LinkSec encapsulat ion covers t he ent ire Et hernet packet payload ( it includes bot h FCoE
cont ent and Et hernet padding) . When packet s carry LinkSec encapsulat ion on t he wire,
LinkSec offload by hardware should be act ivat ed.
VLAN header
I t is assumed t hat any FCoE has a VLAN header. I n t he case of double VLAN mode, t he
packet must have t he t wo VLAN headers.
SNAP packet The 82599 does not provide FCoE offload for FCoE frame over SNAP.
Traffic rat e cont rol
FC t raffic relies on a high qualit y link t hat guarant ees no packet loss. I t is expect ed t hat any
lost t raffic prot ocols support ed by t he net work are enabled by t he 82599 as well.
FC and PFC
Virt ualizat ion
I t is expect ed t hat t he VMM abst ract t he FCoE funct ionalit y t o t he VM( s) . FCoE set t ing and
FCoE t raffic is expect ed only by t he VMM accessing t he LAN via t he PF.
TCP/ I P and UDP/ I P offload
FCoE t raffic is L2 t raffic ( not over I P) . Any set t ing of TCP/ I P and UDP/ I P offload capabilit ies
are not applicable and do not impact FCoE offload funct ions.
Transmit descript ors
Soft ware must use t he advanced t ransmit descript or t o act ivat e eit her FC CRC offload or
TSO funct ionalit y.
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416
7. 13. 2. 3 SOF Pl acement
During a single send, t he SOF field is t aken as is from t he FCoE header in t he dat a buffer.
7. 13. 2. 4 EOF I nser t i on
The 82599 aut omat ically insert s t he End of Frame field when t he TUCMD.FCoE bit in t he t ransmit
cont ext descript or is set . The EOF codes t hat are insert ed int o t he t ransmit t ed packet s are st ored in t he
TEOFF regist er. The TEOFF regist er cont ains four EOF codes named EOF0...EOF3 t hat are support ed by
t he t ransmit FCoE offload. By default , t hese values are programmed int o t he following values: EOF0 =
EOFn; EOF1 = EOFt ; EOF2 = EOFni; EOF3 = EOFa. The EOF flag in t he FCoEF field in t he t ransmit
cont ext descript or define an index value as list ed in t he Table 7. 85.
7. 13. 2. 5 FC CRC I nser t i on
FC CRC calculat ion is one of t he most CPU int ensive t asks in large t ransact ions. The 82599 offloads t he
FC CRC calculat ion when t he FCoE bit is set in t he TUCMD field wit hin t he t ransmit cont ext descript or.
The 82599 calculat es and adds t he FC CRC before packet t ransmission but aft er t he required FC
padding byt es are already added.
The CRC polynomial used by t he FC prot ocol is t he same one as used in FDDI and Et hernet as shown in
t he following equat ion. While CRC byt es are t ransmit t ed in big endian byt e ordering ( MS byt e first on
t he wire) : X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+ X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X+ 1.
The size of FCoE payload on which FC CRC is calculat ed is indicat ed in t he cont ext and dat a descript ors
as follows. Figure 7.47 specifies t he FCoE frame and t he relevant paramet ers t o CRC calculat ion.
FC CRC Calculat ion Beginning
FC CRC calculat ion st art s aft er t he FCoE header. I t equals t o byt e offset of MACLEN + 4, while t he
MACLEN field in t he t ransmit cont ext descript or is t he byt e offset of t he last Dword in t he FCoE header
t hat cont ains t he SOF flag.
Tabl e 7.85. EOF Codes i n Si ngl e Send
EOF Bi t s i n t he Cont ex t Descr i pt or
( ORI E bit in t he Cont ext Descript or must be set t o 1b)
00 01 10 11
I nser t ed EOF Code EOF0 ( EOFn) EOF1 ( EOFt ) EOF2 ( EOFni) EOF3 ( EOFa)
Fi gur e 7.47. FCoE Fr ame and Rel ev ant Tr ansmi t Descr i pt or Par amet er s
MAC
Addresses
F
C
o
E
H
e
a
d
e
r
FC (basic)
Header
[opt.] FC Option Headers +
Data & FC Padding
E
-
E
O
F
V
L
A
N
F
C

C
R
C
E
-
C
R
C
==HEADLEN== ==FC Payload LEN==
==MACLEN== ==FC CRC Calculation==
[opt.] FC
Extended
Headers
E
-
S
O
F

417
FC CRC Calculat ion End
FC CRC calculat ion ends at t he end of t he FC Payload LEN shown in Figure 7. 47 ( eight byt es before t he
Et hernet CRC) .
7.13. 2. 6 Host Dat a Buf f er s Cont ent f or a Si ngl e Pack et Send
The Table 7. 86 list s t he dat a prepared by soft ware when t ransmit FCoE offload is enabled ( t he FCoE bit
in t he TUCMD field is set in t he t ransmit cont ext descript or) .
List ed below are fields in t he t ransmit t ed FCoE frame t hat are not included in t he dat a buffers ( in host
memory) as shown in Figure 7. 86.
VLAN Header The VLAN header could be part of t he dat a buffer or in t he t ransmit descript or
depending on VLE bit in t he CMD field in t he t ransmit descript or.
EOF The EOF is defined by t he EOF fields and ORI E bit in t he cont ext descript or ( more det ails in
Sect ion 7.2.3. 2. 3)
FC- CRC The 82599 calculat es and insert s t he FC CRC byt es.
FC- Paddi ng The 82599 calculat es t he padding lengt h and insert s t hese byt es as required ( all zeros) .
Et her net CRC I nsert ion should be enabled by t he I FCS bit in t ransmit dat a descript or.
Li nk Sec Header and Di gest When t he link is secured by LinkSec, t hen LinkSec offload must be
enabled and t he LinkSec encapsulat ion is added by hardware.
7.13. 2. 7 FCoE Tr ansmi t Segment at i on Of f l oad ( TSO)
FCoE segment at ion enables t he FCoE soft ware t o init iat e a t ransmission of mult iple FCoE packet s up t o
a complet e FC sequence wit h a single header in host memory ( single inst ruct ion) . I t is act ivat ed by
using t he advanced Tx cont ext descript or ( DTYP equals 0010b) and set t ing bot h t he TUCMD.FCoE in t he
cont ext descript or and set t ing t he DCMD.TSE bit in t he t ransmit dat a descript or. The 82599 split s t he
t ransmit t ed cont ent t o mult iple packet s as defined by t he MSS field in t he Tx cont ext descript or.
TSO Paramet ers
The frame header includes t he Et hernet MAC addresses, VLAN Tag, FCoE header and t he FC header.
The header size is defined in t he cont ext descript or by t he HEADLEN and MACLEN as illust rat ed.
The SOF and EOF fields are defined by t he SOF, ORI S, EOF and ORI E fields in t he cont ext descript or
as described in Sect ion 7. 13.2. 3 and Sect ion 7. 13. 2. 4.
MSS t he maximum segment size in t he cont ext descript or t hat define t he FC dat a ( payload) size
on each packet ot her t han t he last frame which can be smaller.
Tabl e 7. 86. Tr ansmi t FCoE Pack et Dat a Pr ovi ded by Sof t w ar e ( f or TUCMD.FCoE = 1)
Et hernet MAC
Addresses
VLAN
Header
FCoE
Header
FC Frame ( provided by soft ware)
FC Header FC Opt ion Header( s) Opt . Dat a
I nt el

418
7.13.2.7.1 Host Dat a Buf f er s Cont ent f or TSO Of f l oad
The Figure 7. 48 shows t he dat a in host memory when FCoE TSO is act ivat ed. The TSO header is
repeat ed on all frames of t he TSO. The header includes st at ic and dynamic fields t hat are modified by
hardware from packet - t o- packet . The payload size is reflect ed in all frames.
FCoE Header
The FCoE packet header must not span more t han t wo buffers. For best bus use it is recommended t hat
t he header be locat ed in a single buffer ( t he first one) .
Et hernet MAC addresses are t he source and dest inat ion Et hernet MAC addresses
VLAN t ag can be provided by t he driver as part of t he packet header or as part of t he dat a
descript or.
FCoE header ( shown in Figure 7. 48) includes t he FCoE Et hernet t ype, FCoE Version and SOF flag.
Soft ware should leave t he SOF fields as zero while hardware insert s it according t o t he SOF and
ORI S bit s in t he Tx cont ext descript or.
FC ( basic) header as shown in Sect ion 18. 5.2.3.
FCoE TSO Payload
FC opt ion headers as described in Sect ion 18. 5.2.5.
FC dat a t o be segment ed
The payload may or may not include t he opt ional FC padding byt es. Hardware adds any required
padding byt es not included in t he dat a buffers according t o t he PAYLEN field in t he dat a descript or.
Modified fields bet ween consecut ive frames wit hin TSO are described in t he following sect ions.
7.13.2.7.2 Dy nami c St ar t of Fr ame i n TSO
During TSO t he SOF field in t he dat a buffer is replaced by hardware according t o t he values of t he SOF
and ORI S bit s in t he t ransmit cont ext descript or. I n t his case t he value of t he SOF field in t he dat a
buffer is ignored ( for fut ure expansion soft ware should set it t o zero) . The SOF codes t hat are insert ed
t o t he t ransmit t ed packet s are st ored in t he TSOFF regist er. The TSOFF regist er cont ains four SOF codes
named as SOF0...SOF3 t hat are support ed by t he t ransmit FCoE offload. By default t hese values are
programmed t o t he following values: SOF0 = SOFi2; SOF1 = SOFi3; SOF2 = SOFn2; SOF3 = SOFn3.
The SOF flag and Orient at ion St art ( ORI S) bit in t he FCoEF field in t he t ransmit cont ext descript or
define an index value. This index is used t o ext ract t he SOF code t hat is insert ed t o t he packet as list ed
in t he Table 7.87. The ORI S bit defines if t he TSO st art s an FC sequence or if t he first frame on t he FC
sequence is already sent .
Fi gur e 7.48. FCoE TSO Pr ov i ded by t he FCoE Dr i ver
MAC Addresses ; VLAN ; FCoE Header ; FC (basic) Header
FC Option
Header(s)
FC Payload / Data (including optional padding)
. .MSS. . . .MSS. .
FC Option
Header(s)
FC Data (1) FC Data (2) FC Data (3)
. .Residual. .
TSO
header
TSO
header
TSO
header
TSO
header

419
7.13.2.7.3 Dynami c FC Header f i el ds i n TSO
F_CTL Table 7.88 list s t hose fields in t he F_CTL t hat are modified bet ween consecut ive frames of a
TSO ( see Sect ion 18.5.2. 3 for a complet e descript ion of t he F_CTL field) . I f a TSO is
t ransmit t ed by a single packet all F_CTL fields are t aken from t he dat a buffer ( as if it is t he
last frame in t he TSO) .
DF_CTL Table 7. 89 list s t hose fields in t he DF_CTL t hat can be modified bet ween consecut ive
frames of a TSO. Not e t hat t he ESP Header presence bit is not list ed in t his t able. When
ESP Header is present , soft ware must not use a TSO t hat spans across mult iple
packet s. I f a TSO is t ransmit t ed by a single packet all DF_CTL fields are t aken from t he
dat a buffer ( as if it is t he first frame in t he TSO) .
SEQ_CNT SEQ_CNT in t he first frame is t aken from t he SEQ_CNT field in t he FC header in t he
dat a buffers. On any ot her frame, t he value of SEQ_CNT is increment ed by one from it s
value in t he previous frame. The SEQ_CNT wrap- t o-zero aft er reaching a value of
65, 535.
PARAM The PARAM field in t he first frame is t aken from t he PARAM field in t he FC header in t he
dat a buffers. I f t he FCoEF. PARI NC bit is set in t he t ransmit cont ext descript or, t he value
of t he PARAM becomes dynamic. I n t hat case, t he PARAM is increment ed by hardware
by t he MSS value on each frame. Soft ware should set t he FCoEF. PARI NC bit when t he
PARAM field indicat es t he dat a offset ( Relat ive Offset Present bit in t he F_CTL field is
set ) .
Tabl e 7. 87. SOF Codes i n TSO
SOF Bi t i n t he Cont ex t
Descr i pt or
ORI S Bi t i n t he Cont ex t
Descr i pt or
SOF Code i n t he Fi r st
Fr ame
SOF Code i n Ot her
Fr ames
SOF Code w hi l e TSO
= Si ngl e Fr ame
0 ( Class 2) 0 ( not a sequence) SOF2 ( SOFn2) SOF2 ( SOFn2) SOF2 ( SOFn2)
Tabl e 7. 88. F_CTL Codes i n TSO
F_CTL Bit s last frame in TSO when t he ORI E bit in t he Tx cont ext descript or is set . Any ot her frame
Fill Byt es ( 1: 0)
Taken from t he F_CTL( 1: 0) in t he dat a buffer. I t defines t he lengt h of t he FC
padding required t o make t he FC dat a a complet e mult iply of four byt es.
00b
Cont inue Sequence
Condit ion ( 7: 6)
Taken from t he F_CTL( 7: 6) in t he dat a buffer. The cont inue sequence
condit ion is meaningful only if F_CTL( 19) is set and F_CTL( 16) is cleared.
00b
Sequence I nit iat ive
( 16)
Taken from t he F_CTL( 16) in t he dat a buffer. The sequence init iat ive is
meaningful only if F_CTL( 19) is also set .
0b
End Sequence ( 19)
Taken from t he F_CTL( 19) in t he dat a buffer. The end sequence should be set
t o 1b by soft ware only if t he frame is t he last one of a sequence.
0b
Tabl e 7. 89. DF_CTL Codes i n TSO
DF_CTL Fields
1st frame in TSO when ORI S bit in t he Tx cont ext
descript or is set .
Any ot her frame
Device Header I ndicat ion ( 1: 0) Taken from t he dat a buffer. 00b
Associat ion Header I ndicat ion ( 4) Taken from t he dat a buffer. 0b
Net work Header I ndicat ion ( 5) Taken from t he dat a buffer. 0b
I nt el

420
7.13.2.7.4 Dynami c End Of Fr ame Fi el ds
FC_CRC Calculat ed and insert ed on each frame as described in sect ion Sect ion 7. 13. 2. 5.
FC_Paddi ng Calculat ed t he number of required padding byt es and insert ed t hem on t he last frame
as described in sect ion Sect ion 7.13.2.2.
EOF As explained for a single send, t he EOF flag is appended t o t he t ransmit t ed packet s
while values are t aken from t he TEOFF regist er. The FCoE flag index t o t he TEOFF
regist er is defined by t he EOF flag and Orient at ion End ( ORI E) bit in t he FCoEF field in
t he t ransmit cont ext descript or as list ed in Table 7.90.
7. 13. 3 FCoE Recei v e Oper at i on
t he 82599 can offload t he following t asks from t he CPU while processing FCoE receive t raffic: FC CRC
check, receive coalescing and Direct Dat a placement ( DDP) . These offload opt ions are described in t he
sect ions t hat follow.
DDP funct ionalit y is not provided for cont rol packet s or dat a packet s t hat do not meet DDP crit eria
( described lat er in t he sect ions t hat follow) . I n t hose cases, hardware post s t he packet s t o t he legacy
Rx queues as is ( header and t railer are not st ripped including SOF, EOF, FC padding and FC CRC byt es) .
When DDP funct ionalit y is enabled, only t he FC payload is post ed t o t he user buffers. I f t he packet s
header should be indicat ed t o t he legacy Rx queues, all byt es st art ing at t he dest inat ion Et hernet MAC
address unt il t he FC header and opt ionally FC header( s) inclusive are post ed t o t he legacy buffer.
7. 13. 3. 1 FCoE Recei v e Cr oss Funct i onal i t y
FCoE receive offload capabilit ies coexist wit h ot her funct ions in t he 82599 are list ed as follows:
Tabl e 7.90. EOF Codes i n TSO
EOF Bi t s i n t he
Cont ex t
Descr i pt or
ORI E Bi t i n t he Cont ex t
Descr i pt or
Last Fr ame of t he
TSO
Ot her Fr ames of
t he TSO
TSO = Si ngl e
Fr ame
00 ( EOFn) 0 ( not a sequence end) EOF0 ( EOFn) EOF0 ( EOFn) EOF0 ( EOFn)
00 ( EOFn) 1 ( sequence end) EOF1 ( EOFt ) EOF0 ( EOFn) EOF1 ( EOFt )
01 ( EOFt ) 1 ( sequence end) n/ a n/ a EOF1 ( EOFt )
10 ( EOFni) 1 ( dont care) n/ a n/ a EOF2 ( EOFni)
11 ( EOFa) 1 ( dont care) n/ a n/ a EOF3 ( EOFa)
Tabl e 7.91. FCoE Recei ve Cr oss Funct i onal i t y
Et hernet CRC check
There is no enforcement on save bad frames policy. I n t he case of save bad frames, packet s
wit h bad Et hernet CRC are post ed t o t he legacy receive queue even if DDP is enabled. FC
payload of bad packet s are never post ed direct ly t o t he user buffers.
Et hernet padding ext ract ion
There is no enforcement on t he Et hernet padding ext ract ion. When DDP is enabled,
hardware post s t he FC payload t o t he user buffers. When DDP is not enabled t he ent ire
packet s are post ed t o t he legacy receive queues wit h or wit hout t he Et hernet padding
according t o t he device set t ing.
LinkSec offload
LinkSec encapsulat ion covers t he ent ire Et hernet packet payload. I f t he t raffic includes
LinkSec, hardware must process first t he LinkSec encapsulat ion uncovering t he FCoE plain
t ext t o t he FCoE offload logic. I f t he LinkSec processing is not enabled and t he packet s
include LinkSec encapsulat ion, t hen t he packet s are post ed t o t he mat ched legacy receive
queue. I f t he LinkSec processing is enabled but fails for any reason, t he packet can st ill be
post ed t o t he mat ched legacy queue according t o save bad frames policy.

421
7.13.3.2 FC Recei v e CRC Of f l oad
FC CRC calculat ion is one of t he most CPU int ensive t asks in TSO t ransact ions. The 82599 offloads t he
receive FC CRC int egrit y check while t rashing t he CRC byt es and FC padding byt es.
The 82599 recognizes FCoE frames in t he receive dat a pat h by t heir FCoE Et hernet t ype and t he FCoE
version in t he FCoE header. The Et hernet t ype t hat hardware associat es wit h FCoE is defined in t he
ETQF regist er by set t ing t he FCoE bit wit h a specific Et hernet t ype value. The support ed FCoE versions
by t he Rx offload logic are defined by FCRXCTRL.FCOEVER. FCoE packet s t hat do not mat ch t he
previously described Et hernet t ype and FCoE versions are ignored by t he Rx FCoE logic.
The 82599 reconst ruct s t he FC CRC while processing t he incoming byt es and compares it against t he
received FC CRC. The frame is considered a good FC packet if t he previous comparison mat ches and it
is considered as a bad FC packet ot herwise.
The FC CRC int egrit y check is meaningful only if all t he following condit ions are met :
The received frame cont ains a correct Et hernet CRC
I f t he received frame includes LinkSec encapsulat ion t hen LinkSec offload must be enabled and
LinkSec int egrit y is found OK.
The lengt h of t he FC padding byt es t hat hardware t rashes are defined in t he Fill Byt es field in t he FC
frame cont rol ( F_CTL) . The Fill Byt es field can have any value bet ween zero t o t hree t hat makes t he FC
frame a whole number of Dwords. I t is expect ed t hat t he Fill Byt es field would be zero except for last
dat a frames wit hin a sequence.
VLAN header
I t is assumed t hat any FCoE has a VLAN header. I n t he case of double VLAN mode, t he
packet must have t he t wo VLAN headers.
SNAP packet The 82599 does not provide FCoE offload for FCoE frame over SNAP.
FC and PFC
FC t raffic relies on a high- qualit y link t hat guarant ees no packet loss. I t is expect ed t hat any
lost t raffic prot ocols support ed by t he net work is enabled by t he 82599 as well.
Virt ualizat ion
I t is expect ed t hat VM( s) generat e FC writ e request s t o t he VMM. FCoE set t ing and FCoE
t raffic is expect ed only by t he VMM accessing t he physical funct ion.
TCP/ I P and UDP/ I P offload
FCoE t raffic is L2 t raffic ( not over I P) . Any set t ing of TCP/ I P and UDP/ I P offload capabilit ies
are not applicable and do not impact FCoE offload funct ions.
Jumbo frames
Maximum expect ed clear t ext FC frame size is 2140 byt es ( FC header + FC payload + FC
CRC) . Adding opt ional FC crypt o, plus FCoE encapsulat ion, plus opt ional LinkSec
encapsulat ion packet might exceed t he 2200 byt es. I n order t o enable FCoE t raffic, j umbo
packet recept ion should be enabled.
Receive descript ors in t he legacy Rx
queues
When FC CRC offload or DDP funct ionalit y are enabled, soft war e must use t he advanced
descript ors in t he associat ed legacy Rx queues ( SRRCTL. DESCTYPE = 001b) . The legacy Rx
buffers must be larger t han t he maximum expect ed packet size so any Rx packet s span on a
single buffer.
Tabl e 7. 91. FCoE Recei ve Cr oss Funct i onal i t y
I nt el

422
7.13.3.3 Lar ge FC Recei v e
Large FC receive includes t wo t ypes of offloads. The 82599 can save a dat a copy by post ing t he
received FC payload direct ly t o t he kernel st orage cache or t he user applicat ion space ( in t he remainder
of t he document t here is no difference bet ween t he t wo cases and it is named as user buffers) . When
t he packet s payload are post ed direct ly t o t he user buffers t heir headers can st ill be post ed t o t he
legacy receive queues. The 82599 saves CPU cycles by reducing t he dat a copy and also minimize CPU
processing by post ing only t he packet s headers t hat are required for soft ware.
Figure 7. 50 shows t he mapping of received FCoE frames t o t he legacy Rx queue and t he user buffers.
Figure 7. 51 shows a t op level overview of t he large FC receive flow. The remaining sect ions det ail t he
large FC receive funct ionalit y as follows:
Enabling large FC receive Sect ion 7. 13.3. 3. 1
FC read exchange flow Sect ion 7. 13. 3. 3.2
FC writ e exchange flow Sect ion 7. 13. 3. 3. 3
FCoE receive filt ering ( Frame t ypes and rules) Sect ion 7. 13. 3. 3.5, Sect ion 7.13.3. 3. 10 and
Sect ion 7. 13. 3. 3. 12
User descript ors Sect ion 7. 13. 3. 3.7
Header post ing t o t he legacy receive queues and FC except ions Sect ion 7. 13. 3. 3.13 and
Sect ion 7. 13. 3. 3. 14
I nt errupt s Sect ion 7. 13. 3.3.15
Fi gur e 7.49. Rel ev ant FCoE and FC Fi el ds f or CRC Recei ve Of f l oad
MAC
Addresses
FCoE
Header
FC Header(s) FC Data
VLAN
Tag
FC CRC
Opt. FC
Padding
FCoE Ethernet Type PLEN F_CTL.Fill Bytes
CRC polynomial: X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+ X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X + 1

423
Fi gur e 7.50. Lar ge FC Recept i on t o User Buf f er s and Legacy Rx Queue
Fi gur e 7. 51. FCoE Lar ge Recei ve Fl ow Di agr am
Address
Status
Rx Buff: FCoE Frame
Header of t he first
frame ( opt ional)
Rx Buffer
Addr ess
( 512) x User Descr i pt or s Li st s
and t hei r User Buf f er s
Buffer
0
Buffer
1
Buffer
2
( 16) x Legacy Rx Queues
used f or FCoE Tr af f i c
Buffer
N
FC Dat a
First Frame
FC Dat a
Frame N
FC Dat a
Frame N+1
FC Dat a
Last Frame
Rx Buffer: FCoE Frame
Header of t he last
frame in t he FC
Sequence
. . .
Example:
First FC
Read
Sequence
Example:
Proceeding
FC read
Sequences
. . .
. . .
. . .
Addr ess
Addr ess
Addr ess
. . .
Descript ors Dat a Buffers
Address
Status
Address
Status
Address
Status
Address
Status
Address
Status
Address
Status
. .DDP. .
DDP status
indication
Required headers are posted in the
legacy Rx queue. The OX_ID
indicates the associated FC Context
. . .
( 512) x FC Cont ex t s
New Frame is received
Check
Ethernet
CRC
Packet parsing: Identify FCoE
header and FC frame length
Check
FCoE
CRC
OK
Bad CRC
OK
Bad CRC
Fetch FC context
according to OX_ID value
Post FC data to user buffer at user
buffer Offset. If data exceeds the
buffer limits update the User
Descriptor PTR and fetch a new User
Descriptor.
Then update the User Buffer offset
Update SEQ_CNT and SEQ_ID
1
1
FCoE Header
Required (3)
No
Yes
Post FCoE frame header to legacy Rx
queue with DDP status indication. The
The OX_ID in the frames header
points to the User descriptor list
Initiate an Rx interrupt according to
FCoE interrupt policy
End Frame processing
Identify Legacy Rx Queue
Note (1) LinkSec offload must be
enabled if LinkSec encapsulation
is used and FCoE offload is
active. Proceed if LinkSec
integrity is found OK. Otherwise
handle it according to LinkSec
setting for bad frames.
Note (2) Check Legit frames for
large FCoE receive (FCoE
receive filtering): Allowed SOF
values; The Frame Contains FC
Data; no ESP option header;
Valid Context in the OX_ID entry
in the context table; Abort
Sequence Condition is inactive
and in order reception.
Note (3) Examples for required
headers of: Last packet in FC
sequence. First packet in FC
sequence that includes FC option
headers.
Check
LinkSec (1)
OK
Fail
FC filtering
(2)
OK
Fail
Indicate packet to legacy
Rx queues in case of Save
Bad Frame setting
Indicate the frame to
Legacy Rx queue
I nt el

424
7.13.3.3.1 Enabl i ng Lar ge FC Recei ve
Large FC receive offload is enabled per each out st anding read or writ e exchange by programming t he
FCoE cont ext t able wit h t he flow paramet ers. Set t ing t he FC cont ext for read or writ e exchange is done
at run t ime. I t is expect ed t hat a read cont ext is programmed before t he read request is init iat ed t o t he
remot e t arget and writ e cont ext is programmed before t he t arget sends t he ready indicat ion t o t he
init iat or. Unless t he FC cont ext is invalidat ed, soft ware must not modify it in t he middle of a t ransact ion
( see Sect ion 7.13.3.3. 5 for det ails on cont ext invalidat ion) . For more det ails on FCoE init ializat ion flow
see Sect ion 4.6.9.
7.13.3.3.2 FC Read Ex change Fl ow
Figure 7. 52 shows an example of an FC ( class 3) read request . This flow is det ailed in t his sect ion.
1. The soft ware checks if t he read request can use large FC receive offload depending on FC cont ext
resources and some crit eria as list ed in Sect ion 7. 13. 3. 3.5. Sect ion 7. 13. 3. 3. 12 describes a
proposed soft ware flow t o manage t he FC cont ext s.
2. I f t he previous condit ions are not met , soft ware can init iat e t he FC read request according t he flow
described in Figure 7. 52 while t he received frames are post ed t o t he legacy receive queues.
I f t he previous condit ions are met , soft ware locks t he relevant user buffers ( t he t arget buffers for
t he FC read request ) and program t he FC cont ext t able. I t t hen init iat es t he FC read request
according t he flow shown in Figure 7.52. The payload of t he received frames is post ed direct ly t o
t he user buffers. Some of t he packet s headers ( only t he required ones) are post ed t o t he legacy
receive queues. The FC header in t he packet s header cont ains t he OX_I D field. This field indicat es
t o soft ware it s cont ext and it s user buffer list . During nominal operat ion, all packet s headers except
packet s wit h FC opt ional headers are t rashed by t he hardware minimizing soft ware overhead.
3. The t arget sends t he FCP_RSP frame t ype indicat ing t he complet ion of t he read exchange. As a
response, t he hardware invalidat es t he FC read cont ext ( if it was used) and indicat es t he number of
byt es post ed direct ly t o t he user buffers in t he receive descript or ( see Sect ion 7. 13. 3. 3.13) .
Soft ware indicat es t he read complet ion t o t he applicat ion.
Fi gur e 7.52. Ex ampl e f or FC Cl ass 3 Read Ex change Fl ow
Initiator Target FC Seq. x': CMND packet = FC Read Request
FC Seq. i: First DATA packet in the sequence
FC Seq. i: DATA packet 2
FC Seq. i: Last DATA packet in the sequence
. . .
FC Seq. m: First DATA packet in the sequence
FC Seq. m: Last DATA packet in the sequence
. . .
FC Seq. n: RSP packet = Read completion
First FC
Sequence
i
Last FC
Data
Sequence
m
FC Sequence
n
. . .

425
7.13.3.3.3 FC Wr i t e Ex change Fl ow
Figure 7.53 shows an example of an FC ( class 3) writ e request ( on which t he Seq_CNT st art s from zero
on each new sequence) . This flow is det ailed in t he sect ions t hat follow.
1. The host ( originat or) sends an FC writ e request t o t he t arget ( responder) .
2. Soft ware in t he t arget checks if t he writ e request can use large FC receive offload depending on FC
cont ext resources and some crit eria as list ed in Sect ion 7.13. 3.3.5.
3. I f t he previous condit ions are met , soft ware can use DDP for t his FC writ e exchange.
4. The t arget soft ware locks t he relevant user buffers ( t he t arget buffers for t he FC writ e request ) and
program t he FC cont ext t able. I t t hen init iat es t he FC ready indicat ion t o t he host .
5. As a response, t he host sends t he dat a frames t o be writ t en t o t he t arget . The frames are received
in t he t arget . I f DDP is used, t he FC payload is post ed direct ly t o t he user buffers while most ( see
addit ional det ails below) packet s headers are t rashed minimizing soft ware overhead.
6. The host marks t he last dat a frame it was request ed t o send by set t ing t he Sequence I nit iat ive bit
in t he F_CTL field.
7. The t arget ident ifies t he last dat a frame and invalidat es t he DDP cont ext . As indicat ed above,
during nominal operat ion, most packet s headers are t rashed. Only headers t hat have meaningful
cont ent are post ed t o host memory as: Headers of packet s wit h FC opt ional headers and t he header
of t he last packet in a sequence wit h act ive sequence init iat ive bit are post ed t o t he legacy receive
queues. The hardware indicat es t he number of byt es post ed direct ly t o t he user buffers in t he
receive descript or ( see Sect ion 7.13. 3.3.13) . Not e t hat t he FC header cont ains t he RX_I D field t hat
can be used by soft ware t o ident ifies it s associat ed DDP cont ext and user buffer list .
8. The t arget may repeat st ep 4, which is followed by st ep 5 unt il t he ent ire request ed dat a is
t ransferred.
9. The t arget sends t he FCP_RSP frame indicat ing t o t he init iat or t he complet ion of t he writ e
exchange.
Fi gur e 7.53. Ex ampl e f or FC Cl ass 3 Wr i t e Ex change Fl ow
Initiator Target CMND packet = FC Write Request: FC Seq. k', Seq_CNT = 0
Data: FC Seq. i, Seq_CNT = 0
Data: FC Seq. i, Seq_CNT = 1
Data: FC Seq. i, Seq_CNT = N-1, Sequence Initiative = 1
. . .
Data: FC Seq. j, Seq_CNT = 0
Data: FC Seq. j, Seq_CNT = M-1, Sequence Initiative = 1
. . .
RSP: FC Seq. z, Seq_CNT = 0
First Data
Sequence
(N data
packets)
Data
Sequence
(M data
packets)
XFER_RDY: FC Seq. x, Seq_CNT = 0
XFER_RDY: FC Seq. y, Seq_CNT = 0
I nt el

426
7.13.3.3.4 EOF and SOF Fl ags i dent i f i cat i on
As part of t he DDP funct ionalit y, hardware ident ifies t he SOF and EOF flags in t he received packet s. The
flags ident ificat ion is based on a set t ing of t he RSOFF and REOFF regist ers. These regist ers are ident ical
t o t he TSOFF and TEOFF regist ers and should be programmed by soft ware t o t he same values.
7.13.3.3.5 FCoE Recei ve Fi l t er i ng
Received FCoE frames are associat ed t o one of t he legacy receive queues according t o t he scheme
described in Sect ion 7. 1. 2. When t he legacy receive queue is enabled, large FC receive funct ionalit y is
enabled as well if a mat ched FC receive cont ext is defined. The dat a is post ed t o t he user buffers t hat
are point ed t o by t he FC receive cont ext . Some of t he headers of t hese frames t hat are required for t he
dat a processing are post ed t o t he legacy receive queue ( see Sect ion 7.13.3.3.13) .
FCoE frames t hat carry FC class 3 or class 2 dat a can be post ed t o large receive buffers if t hey meet t he
following condit ions:
I f t he received packet carries Linksec encapsulat ion it must be offloaded ( and de- capsulat ed) by
hardware.
The FC cont ext t able cont ains valid cont ext t hat mat ches t he exchange I D in t he received frame.
Hardware checks t he RX_I D for writ e dat a packet s sent by t he init iat or. These packet s are ident ified
by t he Exchange Cont ext bit in t he F_CTL header equals zero ( originat or of exchange) . Hardware
checks t he OX_I D for read response dat a packet s sent by t he t arget . These packet s are ident ified
by t he Exchange Cont ext bit in t he F_CTL header equals one ( responder of exchange) .
Frames are ident ified as FCoE frame t ype according t o t he Et hernet t ype in t he FCoE header. The
Et hernet t ype t hat hardware associat es wit h FCoE is defined in t he ETQF regist ers by set t ing t he
FCoE bit wit h a specific Et hernet t ype value.
The FC frame carry class 2 or class 3 cont ent as defined by t he SOF flag. The SOF in t he FCoE
header equals SOFi2 or SOFn2 or SOFi3 or SOFn3.
The FCoE version in t he received frame is equal or lower t han FCRXCTRL.FCOEVER.
The frame cont ains dat a cont ent ( wit h dat a payload) as defined in t he Rout ing Cont rol field ( R_CTL)
in t he FC header:
R_CTL.I nformat ion ( least significant four bit s) equals 0x1 ( solicit ed dat a)
R_CTL.Rout ing ( most significant four bit s) equals 0x0 ( device dat a)
Frames t hat do not cont ain device dat a are not post ed t o t he user buffers. St ill t hese frames are
compared against t he expect ed SEQ_I D and SEQ_CNT in t he FC cont ext and updat e t hese
paramet ers as described in Sect ion 7.13.3.3.5.
The FC frame does not include ESP header ( bit 6 in t he DF_CTL field wit hin t he FC header is
cleared) . Frames t hat include ESP opt ion headers are post ed t o t he legacy receive queue. For good
use of hardware resources, soft ware should not program t he large FC receive cont ext t able wit h
flows t hat carry an ESP header.
The FC frame does not include any FC ext ended headers. For good use of hardware resources,
soft ware should not program t he large FC receive cont ext t able wit h flows t hat carry ext ended
headers.
The first packet received t o a new cont ext is ident ified as t he first FC frame in t he exchange. This
packet is expect ed t o have t he SOFi2 or SOFi3 codes. The SEQ_I D on t he first packet may have any
value.
The frame is received in order as defined in Sect ion 7. 13. 3.3.7 and does not carry any except ion
errors as defined in Sect ion 7. 13. 3. 3.14.
The first frame on each FC sequence is ident ified by t he SOFi2 or SOFi3 codes in t he SOF field in t he
FCoE header. I t is expect ed t hat t he SEQ_I D is changed for any new sequence.

427
The last frame on each FC sequence is ident ified by an act ive End Sequence flag in t he F_CTL field
in t he FC header. I t is expect ed t o receive t he EOFt code in t he EOF field; however, hardware does
not check t his rule.
Ot her frames ( t hat do not meet t he previous condit ions) are post ed t o t he legacy receive queues
according t o t he generic Rx filt ering rules.
7.13.3.3.6 DDP Cont ex t
Hardware can provide DDP offload for up t o 512 concurrent out st anding FC read or writ e exchanges.
Each exchange has an associat ed FC cont ext in hardware. Cont ext s are ident ified by t he exchange I D
( OX_I D for FC read and RX_I D for FC writ e) . The exchange I D is a 16- bit field so t hat a syst em could
t heoret ically generat e up t o 64 K concurrent out st anding FC read request s and 64 K concurrent
out st anding FC writ e request s. Hardware cont ains 512 cont ext s for t he 512 concurrent out st anding
exchanges. Using exchange I D values bet ween 0 t o 511, soft ware can benefit from t he DDP offload.
Any exchange I D value in t he range of 0 t o 511 can be used for eit her read or writ e exchange but not
for bot h.
The FC cont ext is a set of paramet ers used t o ident ify a frame and it s user buffers in host memory. The
cont ext paramet ers are split int o t wo cat egories ( according t o t he int ernal hardware implement at ion) :
DMA cont ext ( FCPTRL, FCPTRH, FCBUFF and FCDMARW regist ers) and filt er cont ext ( FCFLT, FCPARAM
and FCFLTRW regist er) as list ed in Table 7. 92 and shown in Figure 7.54.
Soft ware should program bot h t he DMA cont ext and filt er cont ext making t he cont ext usable. During
recept ion, hardware updat es some of t he paramet ers if t he packet mat ches all crit eria det ailed in
Sect ion 7.13.3.3. 5. I nit ializat ion values and t he updat ed ones are list ed in t his sect ion.
Tabl e 7. 92. Lar ge FC Cont ex t Tabl e
Ex change
I D
DMA Cont ex t
( FCPTRL, FCPTRH, FCBUFF, FCDMARW)
Fi l t er Cont ex t
( FCFLT and FCFLTRW)
DMA Fl ags User Descr i pt or Fi l t er Fl ags I n Or der Recept i on
0 Valid, First , Count Size, Offset , Point er Valid, First Seq_I D, Seq_CNT, PARAM
. . . . . . . . .
Fi gur e 7.54. Lar ge FC Recei v e Cont ex t Rel at ed t o t he User Buf f er s
Cont ext Valid
User Descr i pt or PTR
User Buffer Offset s
Buffer Size
First and Null Flags
Lar ge FC Recei ve Cont ex t
( Host memor y buf f er )
User Buffer 0 Address
User Descr i pt or Li st
Buffer 0
Buffer 1
Buffer 2
Buffer N
. . .
Last User Buffer Address + Size
User Buf f er s
. . .
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428
DMA Cont ex t Val i d ( 1 bi t ) and Fi l t er Cont ex t Val i d ( 1 bi t ) These bit s indicat es t he validit y of
t his cont ext .
Not e: During programming t ime, soft ware should enable first t he DMA cont ext . When soft ware
disables a cont ext it should invalidat e first t he filt er cont ext . See more det ails on cont ext
invalidat ion in Sect ion 7. 13. 3. 3. 10.
Fi l t er Fi r st ( 1 bi t ) and DMA Fi r st ( 1 bi t ) The first received frame t hat mat ches an act ive cont ext
in t he filt er unit is marked by t he filt er. This marking is used by t he DMA unit as an indicat ion t hat
recept ion t o t his cont ext has been st art ed. The DMA cont ext does not accept packet s from t he filt er unit
unless it received successfully t he packet t hat was marked as t he first one ( see t he sect ion on
except ion handling in Sect ion 7.13.3. 3. 14) . The Filt er First flag should be cleared by soft ware when
programming t he cont ext . Hardware set s t his bit when t he filt er unit recognizes t he first packet t hat
mat ches a valid cont ext . The DMA First bit should be cleared by soft ware when programming t he
cont ext . Hardware set s t his bit when t he DMA unit received packet t hat mat ches a valid cont ext and
marked as first by t he filt er unit .
Buf f er Count ( 8 bi t ) This field defines t he number of remaining user buffers in t he list . At
programming t ime, soft ware set s t he buffer count t o t he number of t he allocat ed user buffers. During
recept ion, hardware decrement s t he buffer count as each of t hem complet es. The number of act ive
buffers equals t he buffer count value while 0x00 equals 256.
Buf f er Si ze ( 2 bi t ) This field defines t he user buffer size used in t his cont ext . I t can be 4 KB, 8 KB,
16 KB or 64 KB. All buffers except t he first one and t he last one are full size. The address of all buffers
is aligned t o t he buffer size in t he cont ext . The first buffer may st art at a non-zero offset . The size of
t he last buffer may be smaller t han t he buffer size as defined by t he last buffer size paramet er.
User Buf f er Of f set ( 16 bi t ) This field defines t he byt e offset wit hin t he current buffer t o which t he
next packet should be post ed. At cont ext programming, t he soft ware set s t he user buffer offset t o t he
beginning of t he first buffer. During recept ion, hardware updat es t his field at t he end of each packet
processing for t he next received packet .
Last User Buf f er Si ze ( 16 bi t ) This field defines t he size of t he last user buffer in byt e unit s.
User Descr i pt or PTR ( 8 byt e) The user buffers are indicat ed by a list of point ers named as user
descript ors ( see Sect ion 7. 13. 3. 3.9 for a descript ion of t he user descript ors) . The user descript or PTR in
t he FC cont ext is a point er t o t he user descript or list . At programming t ime, soft ware set s t he user
descript or PTR t o t he beginning of t he user descript or list . During recept ion, hardware increment s t he
user descript or PTR by eight ( t he size of t he user descript or) when it complet es a buffer and requires
t he next one.
SEQ_I D ( 8bi t ) The sequence I D ident ifies t he sequence number sent by t he t arget . An FC read or
writ e exchange can be composed of mult iple sequences depending on t he t arget implement at ion. The
SEQ_I D has a different value for each sequence and does not necessarily increment sequent ially.
Hardware uses t he SEQ_I D for checking in- order recept ion as described in Sect ion 7.13. 3.3.7.
Hardware updat es t he SEQ_I D in t he cont ext t able according t o t he value of t he SEQ_I D in t he
incoming frame. The init ializat ion value during programming could be of any value. For fut ure
compat ibilit y soft ware should set it t o zero.
SEQ_CNT ( 16 bi t ) SEQ_CNT is an index of t he expect ed FC frames wit hin a sequence or wit hin t he
ent ire exchange depending on t he t arget implement at ion. Hardware uses t he SEQ_I D for checking in-
order recept ion as described in Sect ion 7. 13. 3. 3.7. On read cont ext , soft ware should init ialize SEQ_CNT
t o zero. On writ e cont ext , soft ware should init ialize SEQ_CNT t o SEQ_CNT + 1 of t he last packet of t he
same exchange received from t he init iat or. For each in- order recept ion, hardware set s SEQ_CNT in t he
cont ext t o t he value of t he received SEQ_CNT + 1.

429
PARAM ( 32 bi t ) The PARAM field in t he FC header may indicat e t he dat a offset wit hin t he FC I O
exchange. I t is indicat ed as an offset by t he Relat ive Offset Present bit in t he F_CTL field in t he FC
header. I n t his case, t he PARAM field indicat es t he expect ed value of t he next received packet . At
programming t ime, soft ware should init ialize it t o zero. During recept ion, hardware increment s t he
PARAM by t he size of t he FC payload if it is used as an offset . The FC payload size equals t he packet size
minus t he lengt h of it s header and t railer. While t he header for t his purpose includes all byt es st art ing
at t he Et hernet dest inat ion address up t o and including t he basic FC header, t he t railer includes t he FC
CRC, FC padding, EOF including t he t hree reserved byt es, and t he Et hernet CRC.
7.13.3.3.7 I n Or der Recept i on Check i ng
Hardware checks in- order recept ion by SEQ_I D, SEQ_CNT and PARAM fields. These paramet ers should
meet t he expect ed values ( as follows) in order t o pass in- order recept ions crit eria.
PARAM When t he PARAM field is used as an offset ( as indicat ed by t he Relat ive Offset Present bit in
t he F_CTL field in t he FC header) , t he PARAM field in t he received packet should be t he same as t he
PARAM field in t he FC cont ext . Soft ware should init ialize t his paramet er t o t he expect ed received value
( equals t o zero in read exchanges) .
SEQ_I D, SEQ_CNT SEQ_I D ident ifies t he FC sequence and SEQ_CNT is t he FC frame index wit hin
t he ent ire exchange or wit hin t he sequence ( according t o specific vendor preference) . SEQ_CNT in t he
received packet could be eit her t he same as t he SEQ_CNT in t he FC cont ext or it could st art from zero
for new SEQ_I D, which is different t han t he SEQ_I D in t he cont ext . Soft ware should init ialize SEQ_CNT
t o t he expect ed received value ( equals zero in read exchanges) . SEQ_I D on t he first packet is always
assumed t o be a new value even if by chance it equals t o t he init ial value in t he cont ext .
7.13.3.3.8 Accessi ng t he Lar ge FC Recei v e Cont ex t
The 82599 support s a large number of FC cont ext s while each cont ext cont ains about 16 byt es. I n
order t o save consumed memory space, t he FC cont ext is accessed by indirect mapping. This sect ion
describes how t he DMA and filt er cont ext s are accessed. The DMA cont ext is consist of t he FCPTRL,
FCPTRH and FCBUFF regist ers while read and writ e accesses are cont rolled by t he FCDMARW regist er.
The filt er cont ext is consist of t he FCFLT regist er while read and writ e accesses are cont rolled by t he
FCFLTRW regist er.
DMA Cont ex t Pr ogr ammi ng Soft ware should program t he FCPTRL, FCPTRH and FCBUFF regist ers
by t he required set t ing. I t t hen programs t he FCDMARW regist er wit h t he following cont ent :
FCoESEL should be set by t he required cont ext index ( OX_I D or RX_I D values)
The WE bit is set t o 1b for writ e access while t he RE bit is set t o 0b.
LASTSI ZE should be set t o t he relevant value for t he cont ext
DMA Cont ex t Read Soft ware should program t he FCDMARW regist er as follows and t hen read t he
cont ext on t he FCPTRL, FCPTRH, FCBUFF and FCDMARW regist ers
Soft ware should init iat e t wo consecut ive writ e cycles t o t he FCDMARW regist er wit h t he following
set t ing: FCoESEL should be set t o t he required FCoE read index while bot h WE and RE should be set
t o 0b.
FCoESEL should be set by t he required cont ext index ( OX_I D or RX_I D values) .
RE bit should be set t o 1b for read access while WE, and LASTSI ZE fields are set t o 0b.
LASTSI ZE should be set t o 0b. I t is ignored by hardware when t he RE bit is set t o 1b. When reading
FCDMARW t he LASTSI ZE field reflect s t he cont ext cont ent .
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430
Fi l t er Cont ex t Pr ogr ammi ng Soft ware should program t he FCFLT regist er by t he required set t ing.
I t t hen programs t he FCFLTRW regist er wit h t he following cont ent :
WE bit is set t o 1b for a writ e access while RE bit is set t o 0b.
Fi l t er Cont ex t Read Soft ware should program t he FCFLTRW regist er as follows and t hen read t he
cont ext on t he FCFLT regist er:
RE bit should be set t o 1b for a read access while WE bit is set t o 0b.
7.13.3.3.9 User Descr i pt or St r uct ur e and User Descr i pt or Li st
The buffers in host memory could be eit her user applicat ion memory or st orage cache named as user
buffers. I n bot h cases t he buffers must be locked ( against soft ware) and convert ed t o physical memory
up front .
The user descript or list is a cont iguous list of point ers t o t he user buffers. The buffers are aligned t o
t heir size as defined in t he FC cont ext . The first buffer can st art at a non-zero offset as t he soft ware
defines it in t he FC cont ext . All ot her buffers st art at a zero offset . The last buffer can be smaller t han
t he full size as defined in t he FC cont ext .
7.13.3.3.10 I nval i dat i ng FC Recei ve Cont ex t
During nominal act ivit y, hardware invalidat es aut onomously t he FC cont ext s. The t arget indicat es a
complet ion of an FC read by sending t he FCP_RSP frame. Hardware ident ifies t he FCP_RSP frame and
invalidat es t he FC cont ext t hat mat ches t he OX_I D in t he incoming frame. The FCP_RSP frame is post ed
t o t he legacy Rx queues wit h appropriat e st at us indicat ion. Hardware ident ifies t he FCP_RSP frame by
t he following crit eria:
The frame is ident ified as FCoE frame by it s et hernet t ype
R_CTL.I nformat ion ( least significant four bit s) equals 0x7 ( command st at us)
R_CTL.Rout ing ( most significant four bit s) equals 0x0 ( device dat a)
Cont ext t hat is invalidat ed aut onomously by hardware is indicat ed by set t ing t he FCSTAT field in t he
receive descript or t o 10b. When soft ware get s t his indicat ion it can unlock t he user buffers inst ant ly and
reuse t he cont ext for a new FC exchange.
I n some erroneous cases soft ware might invalidat e a cont ext before a read exchange complet es ( such
as a t ime out event ) . I n such cases, soft ware should clear t he Filt er Cont ext Valid bit and t hen t he DMA
Cont ext Valid bit . Hardware invalidat es t he cont ext at a packet ' s boundaries. Therefore, aft er soft ware
clears t he DMA Cont ext Valid bit , soft ware should eit her poll it unt il it is grant ed ( cleared) by hardware
or opt ionally soft ware could wait ~ 100 s ( guarant eed t ime for any associat ed DMA cycles t o
complet e) . I n addit ion, soft ware should also ensure t hat t he receive packet buffer does not cont ain any
residual packet s of t he same flow. See Sect ion 4.6. 7. 1 for t he required soft ware flow. Only t hen t he
soft ware can unlock t he user buffers and reuse t he cont ext for a new FC exchange.
Tabl e 7.93. FC User Descr i pt or
63= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 0
User buffer address defined in byt e unit s. N LS bit s must be set t o zero while N equals 12 for a 4 KB buffer size, 13 for 8 KB buffer
size, 14 for 16 KB buffer size and 16 for 64 KB buffer size.

431
7.13.3.3.11 I nval i dat i ng FC Wr i t e Cont ex t
During nominal act ivit y, hardware invalidat es aut onomously t he FC cont ext s. The init iat or indicat es a
complet ion of a grant ed port ion of an FC writ e by sending a dat a frame wit h act ive sequence init iat ive
flag. Aft er receiving t his t ype of frame, hardware invalidat es t he mat ched FC cont ext . The header of
t his frame is post ed t o t he legacy Rx queues wit h appropriat e st at us indicat ion. Hardware ident ifies t his
frame by t he following crit eria:
The frame is ident ified as FCoE frame by it s et hernet t ype
R_CTL - > I nformat ion ( least significant four bit s) equals 0x1 ( solicit ed dat a)
R_CTL - > Rout ing ( most significant four bit s) equals 0x0 ( device dat a)
F_CTL - > Sequence init iat ive equals 1b indicat ing t ransfer init iat ive t o t he t arget
F_CTL - > End sequence equals 1b indicat ing last frame in a sequence
Cont ext t hat is invalidat ed aut onomously by hardware is indicat ed by set t ing t he FCSTAT field in t he
receive descript or t o 10b. When soft ware get s t his indicat ion, it can unlock t he user buffers inst ant ly
and reuse t he cont ext for a new FC exchange. I f t he FC writ e is not complet e, soft ware can reuse t he
same cont ext for t he complet ion of t he exchange. I t can also define a new user buffer list and indicat e
it t o hardware by programming t he DMA cont ext . I t t hen can enable t he filt er cont ext by set t ing t he Re-
Validat ion bit t he WE bit and t he FCoESEL field in t he FCFLTRW regist er.
Soft ware can also invalidat e a cont ext in case of a t ime out event or ot her reasons. Soft ware
invalidat ion flow is described in Sect ion 7.13.3. 3. 10.
7.13.3.3.12 OX_I D and RX_I D Pool Management
As previously indicat ed, hardware enables Large FC receive offload for up t o 512 concurrent
out st anding read or writ e request s. I n some cases more t han 512 concurrent out st anding request s are
generat ed by t he FCoE st ack. Therefore, soft ware would need t o manage t wo separat e queues for t he
request s: one queue for t hose FC request ed support ed by t he large FC receive offload and anot her one
for t hose request s t hat do not gain t he large FC receive offload. Soft ware should claim an ent ry in t he
cont ext t able, and it s associat ed OX_I D or RX_I D for t he durat ion of t he read or writ e request s,
respect ively. Once a request complet es and it s cont ext is invalidat ed, soft ware can reuse it s cont ext
ent ry for a new request .
Table 7.94 defines an example for an OX_I D list t hat can be used for new FC read request s managed by
soft ware at init ializat ion t ime and during run t ime. Similarly, t his t able could be helpful for writ e
request s and t heir RX_I D or shared pool for bot h read and writ e request s.
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432
SW Not e: Soft ware is aware of which read request s can be offloaded by t he large FC receive and
use OX_I Ds in t he hardware range ( 0 t o 511) only for t hose ones.
7.13.3.3.13 Pack et s and Header s I ndi cat i on i n t he Legacy Recei ve Queue
The following packet s or packet s headers are post ed t o t he legacy receive queues:
All FCoE frames t hat are not offloaded by t he DDP logic
Any packet wit h except ion errors as described in Sect ion 7.13.3. 3. 14
Headers of packet s post ed t o t he user buffers by t he DDP logic t hat cont ain meaningful dat a ( as
det ailed in Sect ion 7. 13. 3.3.2 and Sect ion 7.13.3.3. 3)
There are a few new fields in t he receive descript or dedicat ed t o FCoE described in Sect ion 7. 1. 6. 2:
Pack et Ty pe FCoE packet s are ident ified by t heir Et hernet t ype t hat is programmed in t he ETQF
regist ers.
FCoE_PARAM Reflect s t he value of t he PARAM field in t he DDP cont ext .
FCSTAT FCoE DDP cont ext indicat ion.
FCERR FCoE Error indicat ion. DDP offload is provided only when no errors are found.
FCEOFs and FCEOFe St at us indicat ion on t he EOF and SOF flags in t he Rx packet .
7.13.3.3.14 Ex cept i on Handl i ng
Table 7. 95 list s t he except ion errors relat ed t o FC receive funct ionalit y. Packet s wit h any of t he following
except ion errors are post ed t o t he legacy receive queues wit h no DDP unless specified different ly. I n
t hese cases, t he except ion error is indicat ed in t he Ext ended Error field in t he receive descript or. The
except ions are list ed in priorit y order in t he t able wit h highest priorit y first . Ot her t hen t he EOF
except ion, any high priorit y except ion hides all ot her ones wit h a lower priorit y.
Tabl e 7.94. Sof t w ar e OX_I D Tabl e
I ni t St at e of
t he OX_I D
Tabl e
Run- Ti me
Ev ent s
Updat ed St at e
of t he OX_I D
Tabl e
Run- Ti me
Ev ent s
Updat ed St at e
of t he OX_I D
Tabl e
Run- Ti me ev ent s
Updat ed St at e
of t he OX_I D
Tabl e
0
Soft ware is
using 50 OX_I D
values
support ed by
large FC
receive.
50
The following FC
read request s are
complet ed ( and
released by
soft ware) in t he
following order:
44, 21, 9, 0.
50
Soft ware is using
addit ional 50 OX_I D
values support ed by
large FC receive.
The following FC read
request s are
complet ed ( and
released by soft ware)
in t he following order:
75, 10, 38.
Ordering bet ween
soft ware request s and
releases does not
mat t er in t his
example.
100
1 51 51 101
. . . . . . . . . . . .
. . . . . . . . . 510
. . . . . . . . . 511
. . . 510 510 44
. . . 511 511 21
. . . 44 9
. . . 21 0
. . . 9 75
510 0 10
511 38

433
Tabl e 7. 95. Ex cept i on Er r or Tabl e
Ev ent Descr i pt i on Act i ons and I ndi cat i ons
Unsupport ed FCoE version ( Rx Version >
FCRXCTRL. FCOEVER)
The packet is ident ified as an FCoE packet t ype. DDP cont ext paramet ers are left
int act . Speculat ive CRC check is done. The packet is post ed t o legacy Rx queue
regardless of CRC correct ness ( independent of FCRXCTRL. SavBad set t ing) . I f
t he packet mat ches t he FCoE redirect ion t able, t he packet is post ed t o Rx queue
index defined by t he FCRETA[ 0] .
RDESC. STATUS. FCSTAT = 00b.
RDESC. ERRORS. FCERR = 100b.
I ncorrect FC CRC ( see not e 1) .
I ncrement bad FC CRC count . FC cont ext paramet ers are left int act . The packet
can be post ed t o t he legacy receive queues only if t he FCRXCTRL. SavBad is set .
I f t he packet mat ches t he FCoE redirect ion t able, t he packet is post ed t o Rx
queue index defined by t he FCRETA[ 0] .
Rx packet wit h ESP opt ion header.
I f it mat ches t he DDP cont ext t hen aut o invalidat e t he filt er cont ext while
keeping t he paramet ers int act . Not e t hat t his except ion is not expect ed since
soft ware should not enable a cont ext t o an exchange t hat uses ESP
encapsulat ion.
RDESC. STATUS. FCSTAT = 00b / 01b / 10b.
Received EOFa or EOFni or any unrecognized EOF
or SOF flags.
keeping t he paramet ers int act .
RDESC. ERRORS. FCERR = 010b ( even if no DDP mat ch) .
RDESC. ERRORS. FCEOFe = 1b.
RDESC. STATUS. FCEOFs = 1b.
Received non-zero abort sequence condit ion in
FC read exchange.
keeping t he paramet ers int act .
RDESC. ERRORS. FCERR = 010b ( even if no DDP mat ch) .
Out of order recept ion of packet t hat mat ches a
DDP cont ext ( see not e 2) .
Aut o invalidat e t he filt er cont ext while keeping t he paramet ers int act .
Received unexpect ed EOF / SOF:
1) New sequence I D and SOF is not SOFi.
2) Last packet in a sequence and EOF is not
EOFt .
No DDP while filt er cont ext is updat ed ( if mat ched and ot her paramet ers are in
order) .
RDESC. STATUS. FCSTAT = 00b. / 01b.
RDESC. ERRORS. FCEOFe = 1b.
RDESC. STATUS. FCEOFs = 0b.
The DMA unit get s FCoE packet s while it missed
t he packet t hat was marked as first by t he filt er
unit ( see not e 3) .
Filt er cont ext paramet ers are updat ed while DMA cont ext paramet ers are left
int act .
RDESC. ERRORS. FCERR = 011b or 101b.
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Not e ( 1) : Out of order might be one of t he following cases. SEQ_CNT does not meet expect ed value.
The PARAM field in t he Rx packet does not mat ch t he DDP cont ext . SEQ_I D keeps t he same
value as t he previous packet in a new sequence ident ified by t he presence of SOFi code in t he
SOF field.
Not e ( 2) : Lost sync bet ween Filt er and DMA cont ext s could be a result of cont ext invalidat ion by
soft ware t oget her wit h misbehaved t arget t hat sends packet wit h no host request .
7.13.3.3.15 FC Ex change Compl et i on I nt er r upt
One of t he performance indicat ors of an init iat or is measured by t he number of I / O operat ions per
second it can generat e. The number of FC exchanges per second is affect ed mainly by t he CPU
overhead associat ed wit h t he FC exchange processing and soft ware lat encies. The number of
concurrent out st anding FC exchanges support ed by large FC receive is limit ed by hardware resources.
Reducing t he lat ency associat ed wit h processing complet ions increases t he number of FC exchanges
per second t hat t he syst em support s.
The 82599 enables LLI for FCP_RSP frames or last FC dat a frame in a sequence wit h act ive Sequence
I nit iat ive flag. Any such frames can generat e an LLI int errupt if t he FCOELLI bit in t he FCRXCTRL
regist er is set .
Similarly, reducing t he lat ency associat ed wit h processing FC writ e exchange can increase responder
performance. During an FC writ e exchange, t he originat or handles t he init iat ive t o t he responder aft er it
sends all t he dat a t hat t he responder is ready t o receive. Therefore, t he 82599 enables LLI aft er
receiving t he last packet in a sequence wit h t he Sequence I nit iat ive bit set in t he F_CTL field. The LLI is
enabled by t he same FCOELLI bit in t he FCRXCTRL regist er previously indicat ed.
Last user buffer is exhaust ed ( not enough space
for t he FC payload) .
The filt er cont ext is updat ed while DMA cont ext is aut o invalidat ed.
Legacy receive queue is not enabled or no legacy
receive descript or.
The ent ire packet is dropped. Aut o invalidat es t he DMA cont ext while t he filt er
cont ext remains act ive and cont inues t o be updat ed regularly. Once legacy
descript ors become valid again, packet s are post ed t o t he legacy queues wit h
t he following indicat ion.
Packet missed ( lost ) by t he Rx packet buffer.
Normally a case when flow cont rol is not enabled
or flow cont rol does not work properly.
The ent ire packet is dropped ( by t he Rx packet buffer) . Aut o invalidat e t he DMA
cont ext while t he filt er cont ext remains act ive and cont inues t o be updat ed
regularly. Once t he Rx packet buffer get s free, furt her Rx packet s are post ed t o
t he legacy queues wit h t he following indicat ion.
RDESC. STATUS. FCSTAT = 00b / 01b / 10b / 11b.
Not e t hat t he soft ware might ignore t his error when FCSTAT equals 00b.
1
Tabl e 7.95. Ex cept i on Er r or Tabl e ( Cont i nued)
Event Descr i pt i on Act i ons and I ndi cat i ons

435
7.14 Rel i abi l i t y
7.14.1 Memor y I nt egr i t y Pr ot ect i on
All t he 82599 int ernal memories are prot ect ed against soft errors. Most of t hem are covered by ECC
t hat correct single error per memory line and det ect double errors per memory line. Few of t he smaller
memories are covered by parit y prot ect ion t hat det ect s a single error per memory line.
Single errors in memories wit h ECC prot ect ion are named also as correct able errors. Such errors are
silent ly correct ed. Two errors in memories wit h ECC prot ect ion or single error in memories wit h parit y
prot ect ion are also named as uncorrect able errors. Un- correct able errors are considered as fat al
errors. I f an uncorrect able error is det ect ed in Tx packet dat a, t he packet is t ransmit t ed wit h a CRC
error. I f uncorrect able error is det ect ed in Rx packet dat a, t he packet is report ed t o t he host ( or
manageabilit y) wit h a CRC error. I f an uncorrect able error is det ect ed anywhere else, t he 82599 halt s
t he t raffic and set s t he ECC error int errupt . Soft ware is t hen required t o init iat e a complet e init ializat ion
cycle t o resume nominal operat ion.
7.14.2 PCI e Er r or Handl i ng
For PCI e error event s and error report ing see Sect ion 3.1. 7.
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Pr ogr ammi ng I nt er f ace I nt el

437
8. 0 Pr ogr ammi ng I nt er f ace
8.1 Addr ess Regi ons
The 82599' s address space is mapped int o four regions wit h t he PCI - Based Address Regist ers ( BARs)
list ed in Table 8.1 and explained more in Sect ion 9. 3. 6. 1 and Sect ion 9. 3.6.2.
Tabl e 8. 1. t he 82599 Addr ess Regi ons
8. 1. 1 Memor y - Mapped Access
8.1.1.1 Memor y - Mapped Access t o I nt er nal Regi st er s and Memor i es
The int ernal regist ers and memories can be accessed as direct memory- mapped offset s from t he
memory CSR BAR. See t he following sect ions for det ailed descript ions of t he Device regist ers.
I n I OV mode, t his area is part ially duplicat ed per Virt ual Funct ion ( VF) . All replicat ions cont ain only t he
subset of t he regist er set t hat is available for VF programming.
8.1.1.2 Memor y - Mapped Accesses t o Fl ash
The ext ernal Flash can be accessed using direct memory- mapped offset s from t he CSR BAR ( BAR0 in
32- bit addressing or BAR0/ BAR1 in 64- bit addressing) . The Flash is only accessible if enabled t hrough
t he EEPROM I nit ializat ion Cont rol word. For accesses, t he offset from t he CSR BAR minus 128 KB
corresponds t o t he physical address wit hin t he ext ernal Flash device.
8.1.1.3 Memor y - Mapped Access t o MSI - X Tabl es
The MSI -X t ables can be accessed as direct memory- mapped offset s from BAR3. The MSI X regist ers are
described in Sect ion 8.2. 3. 6.
I n I OV mode, t his area is duplicat ed per VF.
Addr essabl e Cont ent Mappi ng St yl e Regi on Si ze
I nt ernal regist ers memories and Flash ( memory BAR) Direct memory mapped 128 KB + Flash Size
Flash ( opt ional)
1
1. The Flash space in t he memory CSR and expansion ROM base address map is t he same Flash memory. Accessing t he memory BAR
at offset 128 KB and expansion ROM at offset 0x0 are mapped t o t he Flash device at offset 0x0.
Direct memory- mapped 64 KB t o 8 MB
Expansion ROM ( opt ional)
2
Direct memory- mapped 64 KB t o 8 MB
I nt ernal regist ers and memories ( opt ional)
2
2. The int ernal regist ers and memories can be accessed t hough I / O space as explained in t he sect ions t hat follow.
I / O window mapped 32 byt es
MSI -X ( opt ional) Direct memory mapped 16 KB
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82599 10 GbE Cont r ol l er Pr ogr ammi ng I nt er f ace

438
8. 1.1. 4 Memor y - Mapped Access t o Ex pansi on ROM
The ext ernal Flash can also be accessed as a memory- mapped expansion ROM. Accesses t o offset s
st art ing from t he expansion ROM base address reference t he Flash, provided t hat access is enabled
t hrough t he EEPROM I nit ializat ion Cont rol word, and if t he expansion ROM base address regist er
cont ains a valid ( non-zero) base memory address.
8.1.2 I / O- Mapped Access
All int ernal regist ers and memories can be accessed using I / O operat ions. I / O accesses are support ed
only if an I / O base address is allocat ed and mapped ( BAR2) , t he BAR cont ains a valid ( non-zero value) ,
and I / O address decoding is enabled in t he PCI e configurat ion.
When an I / O BAR is mapped, t he I / O address range allocat ed opens a 32- byt e window in t he syst em I /
O address map. Wit hin t his window, t wo I / O addressable regist ers are implement ed: I OADDR and
I ODATA. The I OADDR regist er is used t o specify a reference t o an int ernal regist er or memory, and t hen
t he I ODATA regist er is used t o access it at t he address specified by I OADDR:
8. 1.2. 1 I OADDR ( I / O Of f set 0x 0; RW)
The I OADDR regist er must always be writ t en as a Dword access. Writ es t hat are less t han 32 bit s are
ignored. Reads of any size ret urns a Dword of dat a; however, t he chipset or CPU might only ret urn a
subset of t hat Dword.
For soft ware programmers, t he I N and OUT inst ruct ions must be used t o cause I / O cycles t o be used on
t he PCI e bus. Because writ es must be t o a 32- bit quant it y, t he source regist er of t he OUT inst ruct ion
must be EAX ( t he only 32- bit regist er support ed by t he OUT command) . For reads, t he I N inst ruct ion
can have any size t arget regist er, but it is recommended t hat t he 32- bit EAX regist er be used.
Because only a part icular range is addressable, t he upper bit s of t his regist er are hard coded t o zero.
Bit s 31 t hrough 20 are not writ e-able and always read back as 0b.
At hardware reset ( LAN_PWR_GOOD) or PCI reset , t his regist er value reset s t o 0x00000000. Once
writ t en, t he value is ret ained unt il t he next writ e or reset .
8.1.2. 2 I ODATA ( I / O Of f set 0x 04; RW)
The I ODATA regist er must always be writ t en as a Dword access when t he I OADDR regist er cont ains a
value for t he int ernal regist er and memories ( such as 0x00000- 0x1FFFC) . I n t his case, writ es t hat are
less t han 32 bit s are ignored.
Writ es and reads t o I ODATA when t he I OADDR regist er value is in an undefined range ( 0x20000-
0x7FFFC) should not be performed. Result s cannot be det ermined.
Of f set Abbr evi at i on Name RW Si ze
0x0 I OADDR
I nt ernal Regist er, I nt ernal Memory, or Flash Locat ion Address.
0x00000- 0x1FFFF I nt ernal regist ers/ memories.
0x20000- 0x7FFFF Undefined.
RW 4 byt es
0x04 I ODATA
Dat a field for reads or writ es t o t he int ernal regist er, int ernal memory, or
Flash Locat ion as ident ified by t he current value in I OADDR. All 32 bit s of
t his regist er are read/ writ e capable.
RW 4 byt es
0x08- 0x1F Reserved Reserved O 4 byt es

439
Not e: There are no special soft ware t iming requirement s on accesses t o I OADDR or I ODATA. All
accesses are immediat e except when dat a is not readily available or accept able. I n t his case,
t he 82599 delays t he result s t hrough normal bus met hods ( like split t ransact ion or
t ransact ion ret ry) .
Because a regist er/ memory read or writ e t akes t wo I / O cycles t o complet e, soft ware must
provide a guarant ee t hat t he t wo I / O cycles occur as an at omic operat ion. Ot herwise, result s
can be non- det erminist ic from t he soft ware viewpoint .
8.1.2.3 Undef i ned I / O Of f set s
I / O offset s 0x08 t hrough 0x1F are considered t o be reserved offset s wit h t he I / O window. Dword reads
from t hese addresses ret urn 0xFFFF; writ es t o t hese addresses are discarded.
8. 1. 3 Regi st er s Ter mi nol ogy
8.2 Dev i ce Regi st er s PF
8.2.1 MSI - X BAR Regi st er Summar y PF
See Sect ion 9. 3. 6. 1 for t he MSI -X BAR offset in 32- bit and 64- bit BAR opt ions.
8. 2. 2 Regi st er s Summar y PF BAR 0
All of t he 82599' s non- PCI e configurat ion regist ers are list ed in t he following t able. These regist ers are
ordered by grouping and are not necessarily list ed in t he order t hat t hey appear in t he address space.
Shor t hand Descr i pt i on
RW
Read/ Writ e. A regist er wit h t his at t ribut e can be read and writ t en. I f writ t en since reset , t he value read
reflect s t he value writ t en.
RO Read Only. I f a regist er is read only, writ es t o t his regist er have no effect .
WO Writ e Only. Reading t his regist er might not ret urn a meaningful value.
RW1C
Read/ Writ e Clear. A regist er wit h t his at t ribut e can be read and writ t en. However, a writ e of a 1b clears ( set s t o
0b) t he corresponding bit and a writ e of a 0b has no effect .
W1C Writ e t o clear regist er. Writ ing 1b t o t his regist er clears an event possibly report ed in anot her regist er.
RC Read Clear. A regist er bit wit h t his at t ribut e is cleared aft er read. Writ es have no effect on t he bit value.
RW/ RC Read/ Writ e and Read Clear.
RWS
Read Writ e Set : Regist er t hat is set t o 1b by soft ware by writ ing a 1b t o t he regist er, and cleared t o 0b by
hardware.
Reserved
Reserved field can ret urn any value on read access and must be set t o it s init ial value on writ e access unless
specified different ly in t he field descript ion.
Cat egor y BAR 3 Of f set Al i as Of f set Abbr ev i at i on Name RW
MSI -X 0x0000 ( N- 1) * 0x10 N/ A MSI XTADD MSI X t able ent ry lower address. RW
MSI -X 0x0004 ( N- 1) * 0x10 N/ A MSI XTUADD MSI X t able ent ry upper address. RW
MSI -X 0x0008 ( N- 1) * 0x10 N/ A MSI XTMSG MSI X t able ent ry message. RW
MSI -X 0x000C ( N- 1) * 0x10 N/ A MSI XTVCTRL MSI X t able vect or cont rol. RW
MSI -X 0x2000 0x200C N/ A MSI XPBA MSI -X Pending bit array. RO
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Not e: All regist ers should be accessed as a 32- bit widt h on reads wit h an appropriat e soft ware
mask, if needed. A soft ware read/ modify/ writ e mechanism should be invoked for part ial
writ es.
Tabl e 8.2. Regi st er Summar y
Of f set / Al i as Of f set Abbr evi at i on Name Bl ock RW
Reset
Sour ce
Page
Gener al Cont r ol Regi st er s
0x00000 / 0x00004 CTRL Device Cont rol Regist er Target RW 453
0x00008 STATUS Device St at us Regist er Target RO 454
0x00018 CTRL_EXT Ext ended Device Cont rol Regist er Target RW 454
0x00020 ESDP Ext ended SDP Cont rol Target RW 455
0x00028 I 2CCTL I 2C Cont rol Target RW PERST 457
0x00200 LEDCTL LED Cont rol Target RW 458
0x00600 CORESPARE Core Spare Bit s Target RW 459
0x05078 EXVET Ext ended VLAN Et her Type Target RW 459
EEPROM/ Fl ash Regi st er s
0x10010 EEC EEPROM/ Flash Cont rol Regist er FLEEP RW 460
0x10014 EERD EEPROM Read Regist er FLEEP RW 461
0x1001C FLA Flash Access Regist er FLEEP RW 462
0x10114 EEMNGDATA
Manageabilit y EEPROM Read/
Writ e Dat a
FLEEP RW 463
0x10118 FLMNGCTL
Manageabilit y Flash Cont rol
Regist er
FLEEP RW 464
0x1011C FLMNGDATA Manageabilit y Flash Read Dat a FLEEP RW 464
0x01013C FLOP Flash Opcode Regist er FLEEP RW 464
0x10200 GRC General Receive Cont rol FLEEP RW 465
Fl ow Cont r ol Regi st er s
0x0431C / 0x03008 PFCTOP Priorit y Flow Cont rol Type Opcode MAC RW 465
0x03200+ 4* n, n= 0. . . 3 FCTTVn
Flow Cont rol Transmit Timer
Value n
DBU- Rx RW 465
0x03220+ 4* n, n= 0. . . 7 FCRTL[ n]
Flow Cont rol Receive Threshold
Low
DBU- Rx RW 466
0x03260+ 4* n, n= 0. . . 7 FCRTH[ n]
Flow Cont rol Receive Threshold
High
DBU- Rx RW 466
0x032A0 FCRTV
Flow Cont rol Refresh Threshold
Value
DBU- Rx RW 466
0x0CE00 TFCS Transmit Flow Cont rol St at us DBU-Tx RO 467
0x03D00 FCCFG Flow Cont r ol Configurat ion DBU- Rx RW 467
PCI e Regi st er s
0x11000 GCR PCI e Cont rol Regist er PCI e RW 467
0x11010 GSCL_1 PCI e St at ist ic Cont rol Regist er # 1 PCI e RW 468
0x11014 GSCL_2
PCI e St at ist ic Cont rol Regist ers
# 2
PCI e RW 468

441
0x011030+ 4* n, n= 0. . . 3 GSCL_5_8
PCI e St at ist ic Cont rol Regist er
# 5. . . # 8
PCI e RW 469
0x11020+ 4* n, n= 0. . . 3 GSCN_0_3
PCI e St at ist ic Count er Regist ers
# 0. . . # 3
PCI e RO 470
0x10150 FACTPS
Funct ion Act ive and Power St at e
t o Manageabilit y
FLEEP RO 470
0x11040 PCI EPHYADR PCI e PHY Address Regist er PCI e RW 471
0x11044 PCI EPHYDAT PCI e PHY Dat a Regist er PCI e RW 471
0x10140 SWSM Soft ware Semaphore Regist er FLEEP RW 471
0x10148 FWSM Firmware Semaphore Regist er FLEEP RW 471
0x10160 SW_FW_SYNC
Soft wareFirmware
Synchronizat ion
FLEEP RW 473
0x11050 GCR_EXT PCI e Cont rol Ext ended Regist er PCI e RW 473
0x11064 MREVI D Mirrored Revision I D PCI e RO 473
0x110B0 PI CAUSE PCI e I nt errupt Cause PCI e RO 474
0x110B8 PI ENA PCI e I nt errupt s Enable PCI e RW 474
I nt er r upt Regi st er s
0x00800 EI CR
Ext ended I nt errupt Cause
Regist er
I nt errupt RW1C 474
0x00808 EI CS
Ext ended I nt errupt Cause Set
Regist er
I nt errupt WO 475
0x00880 EI MS
Ext ended I nt errupt Mask Set /
Read Regist er
I nt errupt RWS 475
0x00888 EI MC
Ext ended I nt errupt Mask Clear
Regist er
I nt errupt WO 475
0x00810 EI AC
Ext ended I nt errupt Aut o Clear
Regist er
I nt errupt RW 476
0x00890 EI AM
Ext ended I nt errupt Aut o Mask
Enable Regist er
I nt errupt RW 476
0x00A90+ 4* ( n- 1) , n= 1. . . 2 EI CS[ n]
Ext ended I nt errupt Cause Set
Regist ers
I nt errupt WO 476
0x00AA0+ 4* ( n- 1) , n= 1. . . 2 EI MS[ n]
Ext ended I nt errupt Mask Set /
Read Regist ers
I nt errupt RWS 476
0x00AB0+ 4* ( n- 1) , n= 1. . . 2 EI MC[ n]
Ext ended I nt errupt Mask Clear
Regist ers
I nt errupt WO 476
0x00AD0+ 4* ( n- 1) , n= 1. . . 2 EI AM[ n]
Ext ended I nt errupt Aut o Mask
Enable regist ers
I nt errupt RW 477
0x00894 EI TRSEL MSI t o EI TR Select I nt errupt RW 477
0x00820+ 4* n, n= 0. . . 23 and
0x012300+ 4* ( n- 24) , n= 24. . . 128
EI TR[ n]
Ext ended I nt errupt Throt t le
Regist ers
I nt errupt RW 477
0x0E800+ 4* n, n= 0. . . 127 L34TI MI R[ n]
L3 L4 Tuples I mmediat e I nt errupt
Rx
DBU- Rx RW 478
0x0EC90 LLI THRESH LLI Size Threshold DBU- Rx RW 478
0x0EC60 / 0x05AC0 I MI RVP
I mmediat e I nt errupt Rx VLAN
Priorit y Regist er
DBU- Rx RW 478
0x00900+ 4* n, n= 0. . . 63 I VAR[ n] I nt errupt Vect or Allocat ion I nt errupt RW 479
Tabl e 8. 2. Regi st er Summar y ( Cont i nued)
Of f set / Al i as Of f set Abbr ev i at i on Name Bl ock RW
Reset
Sour ce
Page
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0x00A00 I VAR_MI SC
Miscellaneous I nt errupt Vect or
Allocat ion
I nt errupt RW 479
0x00898 GPI E General Purpose I nt errupt Enable I nt errupt RW 480
MSI - X Tabl e Regi st er s
0x110C0+ 4* n, n= 0. . . 7 /
0x11068 [ n= 0]
PBACL[ n] MSI -X PBA Clear PCI e RW 481
Recei ve Regi st er s
0x05080 FCTRL Filt er Cont rol Regist er Rx- Filt er RW 481
0x05088 VLNCTRL VLAN Cont rol Regist er Rx- Filt er RW 482
0x05090 MCSTCTRL Mult icast Cont rol Regist er Rx- Filt er RW 482
0x0EA00+ 4* n, n= 0. . . 63 /
0x05480+ 4* n, n= 015
PSRTYPE[ n]
Packet Split Receive Type
Regist er
DBU- Rx RW 483
0x05000 RXCSUM Receive Checksum Cont rol Rx- Filt er RW 483
0x05008 RFCTL Receive Filt er Cont rol Regist er Rx- Filt er RW 484
0x05200+ 4* n, n= 0. . . 127 MTA[ n] Mult icast Table Array Rx- Filt er RW 485
0x0A200+ 8* n, n= 0. . . 127 RAL[ n] Receive Address Low Rx- Filt er RW 485
0x0A204+ 8* n, n= 0. . . 127 RAH[ n] Receive Address High Rx- Filt er RW 485
0x0A600+ 4* n, n= 0. . . 255 MPSAR[ n] MAC Pool Select Array Rx- Filt er RW 486
0x0A000+ 4* n, n= 0. . . 127 VFTA[ n] VLAN Filt er Table Array Rx- Filt er RW 486
0x0EC80 / 0x05818 MRQC
Mult iple Receive Queues
Command Regist er
DBU- Rx RW 487
0x0EC70 RQTC
RSS Queues Per Traffic Class
Regist er
DBU- Rx RW 487
0x0EB80+ 4* n, n= 0. . . 9 /
0x05C80+ 4* n, n= 0. . . 9
RSSRK[ n] RSS Random Key Regist er DBU- Rx RW 488
0x0EB00+ 4* n, n= 0. . . 31 /
0x05C00+ 4* n, n= 0. . . 31
RETA[ n] Redirect ion Table DBU- Rx RW 488
0x0E000+ 4* n, n= 0. . . 127 SAQF[ n] Source Address Queue Filt er DBU- Rx RW 489
0x0E200+ 4* n, n= 0. . . 127 DAQF[ n] Dest inat ion Address Queue Filt er DBU- Rx RW 489
0x0E400+ 4* n, n= 0. . . 127 SDPQF[ n]
Source Dest inat ion Port Queue
Filt er
DBU- Rx RW 489
0x0E600+ 4* n, n= 0. . . 127 FTQF[ n] Five Tuple Queue Filt er DBU- Rx RW 490
0x0EC30 SYNQF SYN Packet Queue Filt er DBU- Rx RW 491
0x05128+ 4* n, n= 0. . . 7 ETQF[ n] EType Queue Filt er Rx- Filt er RW 491
0x0EC00+ 4* n, n= 0. . . 7 ETQS[ n] EType Queue Select DBU- Rx RW 491
Recei ve DMA Regi st er s
0x01000+ 0x40* n, n= 0. . . 63 and
0x0D000+ 0x40* ( n- 64) ,
n= 64. . . 127
RDBAL[ n]
Receive Descript or Base Address
Low
DMA- Rx RW 493
0x01004+ 0x40* n, n= 0. . . 63 and
0x0D004+ 0x40* ( n- 64) ,
n= 64. . . 127
RDBAH[ n]
Receive Descript or Base Address
High
DMA- Rx RW 493
0x01008+ 0x40* n, n= 0. . . 63 and
0x0D008+ 0x40* ( n- 64) ,
n= 64. . . 127
RDLEN[ n] Receive Descript or Lengt h DMA- Rx RW 493
Tabl e 8.2. Regi st er Summar y ( Cont i nued)
Reset
Sour ce
Page

443
0x01010+ 0x40* n, n= 0. . . 63 and
0x0D010+ 0x40* ( n- 64) ,
n= 64. . . 127
RDH[ n] Receive Descript or Head DMA- Rx RO 493
0x01018+ 0x40* n, n= 0. . . 63 and
0x0D018+ 0x40* ( n- 64) ,
n= 64. . . 127
RDT[ n] Receive Descript or Tail DMA- Rx RW 493
0x01028+ 0x40* n, n= 0. . . 63 and
0x0D028+ 0x40* ( n- 64) ,
n= 64. . . 127
RXDCTL[ n] Receive Descript or Cont rol DMA- Rx RW 494
0x01014+ 0x40* n, n= 0. . . 63 and
0x0D014+ 0x40* ( n- 64) ,
n= 64. . . 127 / 0x02100+ 4* n,
[ n= 0. . . 15]
SRRCTL[ n] Split Receive Cont rol Regist ers DMA- Rx RW 494
0x02F00 RDRXCTL Receive DMA Cont rol Regist er DMA- Rx RW 495
0x02F20 RDDCC
Receive DMA Descript or Cache
Config
DMA- Rx RW 495
0x03C00+ 4* n, n= 0. . . 7 RXPBSI ZE[ n] Receive Packet Buffer Size DBU- Rx RW 495
0x03000 RXCTRL Receive Cont rol Regist er DBU- Rx RW 496
0x03190 RXMEMWRAP Rx Packet Buffer Flush Det ect DBU- Rx RO 496
0x03028 RSCDBU RSC Dat a Buffer Cont rol Regist er DBU- Rx RW 497
0x0102C+ 0x40* n, n= 0. . . 63 and
0x0D02C+ 0x40* ( n- 64) ,
n= 64. . . 127
RSCCTL[ n] RSC Cont rol DMA- Rx RW 497
Tr ansmi t Regi st er s
0x08100 DTXMXSZRQ
DMA Tx TCP Max Allow Size
Request s
DMA-Tx RW 497
0x04A80 DMATXCTL DMA Tx Cont rol DMA-Tx RW 498
0x04A88 DTXTCPFLGL DMA Tx TCP Flags Cont rol Low DMA-Tx RW 498
0x04A8C DTXTCPFLGH DMA Tx TCP Flags Cont rol High DMA-Tx RW 498
0x06000+ 0x40* n, n= 0. . . 127 TDBAL[ n]
Transmit Descript or Base Address
Low
DMA-Tx RW 499
0x06004+ 0x40* n, n= 0. . . 127 TDBAH[ n]
Transmit Descript or Base Address
High
DMA-Tx RW 499
0x06008+ 0x40* n, n= 0. . . 127 TDLEN[ n] Transmit Descript or Lengt h DMA-Tx RW 499
0x06010+ 0x40* n, n= 0. . . 127 TDH[ n] Transmit Descript or Head DMA-Tx RO 499
0x06018+ 0x40* n, n= 0. . . 127 TDT[ n] Transmit Descript or Tail DMA-Tx RW 500
0x06028+ 0x40* n, n= 0. . . 127 TXDCTL[ n] Transmit Descript or Cont rol DMA-Tx RW 500
0x06038+ 0x40* n, n= 0. . . 127 TDWBAL[ n]
Tx Descript or Complet ion Writ e
Back Address Low
DMA-Tx RW 501
0x0603C+ 0x40* n, n= 0. . . 127 TDWBAH[ n]
Tx Descript or Complet ion Writ e
Back Address High
DMA-Tx RW 501
0x0CC00+ 0x4* n, n= 0. . . 7 TXPBSI ZE[ n] Transmit Packet Buffer Size DBU-Tx RW 501
0x0CD10 MNGTXMAP
Manageabilit y Transmit TC
Mapping
DBU-Tx RW 502
0x08120 MTQC
Mult iple Transmit Queues
Command Regist er
DMA-Tx RW 502
0x04950 + 0x4* n, n= 0. . . 7 TXPBTHRESH Tx Packet Buffer Threshold DMA-Tx RW 503
Reset
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DCB Regi st er s
0x02430 RTRPCS
DCB Receive Packet plane Cont rol
and St at us
DMA- Rx RW 503
0x04900 RTTDCS
DCB Transmit Descript or Plane
Cont rol and St at us
DMA-Tx RW 503
0x0CD00 RTTPCS
DCB Transmit Packet Plane
Cont rol and St at us
DBU-Tx RW 508
0x03020 RTRUP2TC
DCB Receive User Priorit y t o
Traffic Class
DBU- Rx RW 504
0x0C800 RTTUP2TC
DCB Transmit User Priorit y t o
Traffic Class
DBU-Tx RW 506
0x02140+ 4* n, n= 0. . . 7 RTRPT4C[ n]
DCB Receive Packet Plane T4
Config
DMA- Rx RW 506
0x082E0+ 4* n, n= 0. . . 3 TXLLQ[ n] St rict Low Lat ency Tx Queues DMA-Tx RW 507
0x02160+ 4* n, n= 0. . . 7 RTRPT4S[ n]
DCB Receive Packet plane T4
St at us
DMA- Rx RO 507
0x04910+ 4* n, n= 0. . . 7 RTTDT2C[ n]
DCB Transmit Descript or plane T2
Config
DMA-Tx RW 507
0x0CD20+ 4* n, n= 0. . . 7 RTTPT2C[ n]
DCB Transmit Packet Plane T2
Config
DBU-Tx RW 508
0x0CD40+ 4* n, n= 0. . . 7 RTTPT2S[ n]
DCB Transmit Packet Plane T2
St at us
DBU-Tx RO 508
0x04980 RTTBCNRM
DCB Transmit Rat eScheduler
MMW
DMA-Tx RW 508
0x04904 RTTDQSEL
DCB Transmit Descript or Plane
Queue Select
DMA-Tx RW 508
0x04908 RTTDT1C
DCB Transmit Descript or Plane T1
Config
DMA-Tx RW 509
0x0490C RTTDT1S
DCB Transmit Descript or Plane T1
St at us
DMA-Tx RO 509
0x04984 RTTBCNRC
DCB Transmit Rat e- Scheduler
Config
DMA-Tx RW 509
0x04988 RTTBCNRS
DCB Transmit Rat e- Scheduler
St at us
DMA-Tx RW 510
0x0498C RTTBCNRD
DCB Transmit Rat e Scheduler
Rat e Drift
DMA-Tx RW 510
DCA Regi st er s
0x0100C+ 0x40* n, n= 0. . . 63 and
0x0D00C+ 0x40* ( n- 64) ,
n= 64. . . 127 / 0x02200+ 4* n,
[ n= 0. . . 15]
DCA_RXCTRL[ n] Rx DCA Cont rol Regist er DMA- Rx RW 511
0x0600C+ 0x40* n, n= 0. . . 127 DCA_TXCTRL[ n] Tx DCA Cont rol Regist er DMA-Tx RW 511
0x11070 DCA_I D
DCA Request er I D I nformat ion
Regist er
PCI e RO 512
0x11074 DCA_CTRL DCA Cont rol Regist er PCI e RW 511
Secur i t y Regi st er s
0x08800 SECTXCTRL Securit y Tx Cont rol SEC-Tx RW 513
0x08804 SECTXSTAT Securit y Tx St at us SEC-Tx RO 514
Reset
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0x08808 SECTXBUFFAF Securit y Tx Buffer Almost Full SEC-Tx RW 514
0x08810 SECTXMI NI FG Securit y Tx Buffer Minimum I FG SEC-Tx RW 514
0x08D00 SECRXCTRL Securit y Rx Cont rol SEC- Rx RW 515
0x08D04 SECRXSTAT Securit y Rx St at us SEC- Rx RO 515
Li nk Sec Regi st er s
0x08A00 LSECTXCAP LinkSec Tx Capabilit ies Regist er SEC-Tx RW 515
0x08F00 LSECRXCAP LinkSec Rx Capabilit ies Regist er SEC- Rx RW 516
0x08A04 LSECTXCTRL LinkSec Tx Cont rol Regist er SEC-Tx RW 517
0x08F04 LSECRXCTRL LinkSec Rx Cont rol Regist er SEC- Rx RW 517
0x08A08 LSECTXSCL LinkSec Tx SCI Low SEC-Tx RW 518
0x08A0C LSECTXSCH LinkSec Tx SCI High SEC-Tx RO 518
0x08A10 LSECTXSA LinkSec Tx SA SEC-Tx RW 518
0x08A14 LSECTXPN0 LinkSec Tx SA PN 0 SEC-Tx RW 519
0x08A18 LSECTXPN1 LinkSec Tx SA PN 1 SEC-Tx RW 520
0x08A1C+ 4* n, n= 0. . . 3 LSECTXKEY0[ n] LinkSec Tx Key 0 SEC-Tx WO 520
0x08A2C+ 4* n, n= 0. . . 3 LSECTXKEY1[ n] LinkSec Tx Key 1 SEC-Tx WO 520
0x08F08 LSECRXSCL LinkSec Rx SCI Low SEC- Rx RW 520
0x08F0C LSECRXSCH LinkSec Rx SCI High SEC- Rx RW 521
0x08F10+ 4* n, n= 0. . . 1 LSECRXSA[ n] LinkSec Rx SA SEC- Rx RW 521
0x08F18+ 4* n, n= 0. . . 1 LSECRXPN[ n] LinkSec Rx SA PN SEC- Rx RW 521
0x08F20+ 0x10* n+ 4* m, n= 0. . . 1,
m= 0. . . 3
LSECRXKEY[ n, m] LinkSec Rx Key SEC- Rx WO 522
0x08A3C LSECTXUT Tx Unt agged Packet Count er SEC-Tx RO 522
0x08A40 LSECTXPKTE Encrypt ed Tx Packet s SEC-Tx RO 522
0x08A44 LSECTXPKTP Prot ect ed Tx Packet s SEC-Tx RO 522
0x08A48 LSECTXOCTE Encrypt ed Tx Oct et s SEC-Tx RO 523
0x08A4C LSECTXOCTP Prot ect ed Tx Oct et s SEC-Tx RO 523
0x08F40 LSECRXUT LinkSec Unt agged Rx Packet SEC- Rx RO 523
0x08F44 LSECRXOCTE LinkSec Rx Oct et s Decrypt ed SEC- Rx RO 523
0x08F48 LSECRXOCTP LinkSec Rx Oct et s Validat ed SEC- Rx RO 523
0x08F4C LSECRXBAD LinkSec Rx Packet wit h Bad Tag SEC- Rx RO 524
0x08F50 LSECRXNOSCI LinkSec No SCI SEC- Rx RO 524
0x08F54 LSECRXUNSCI LinkSec Unknown SCI SEC- Rx RO 524
0x08F58 LSECRXUC LinkSec Rx Unchecked Packet s SEC- Rx RO 524
0x08F5C LSECRXDELAY LinkSec Rx Delayed Packet s SEC- Rx RO 524
0x08F60 LSECRXLATE LinkSec Rx Lat e Packet s SEC- Rx RO 524
0x08F64+ 4* n, n= 0. . . 1 LSECRXOK[ n] LinkSec Rx Packet OK SEC- Rx RO 525
0x08F6C+ 4* n, n= 0. . . 1 LSECRXI NV[ n] LinkSec Rx I nvalid SEC- Rx RO 525
0x08F74+ 4* n, n= 0. . . 1 LSECRXNV[ n] LinkSec Rx Not Valid SEC- Rx RC 525
0x08F7C LSECRXUNSA LinkSec Rx Unused SA SEC- Rx RC 525
Reset
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0x08F80 LSECRXNUSA LinkSec Rx Not Using SA SEC- Rx RC 525
I Psec Regi st er s
0x08900 I PSTXI DX I Psec Tx I ndex SEC-Tx RW 526
0x08908+ 4* n, n= 0. . . 3 I PSTXKEY[ n] I Psec Tx Key Regist ers SEC-Tx RW 526
0x08904 I PSTXSALT I Psec Tx Salt Regist er SEC-Tx RW 526
0x08E00 I PSRXI DX I Psec Rx I ndex SEC- Rx RW 526
0x08E04+ 4* n, n= [ 0. . . 3] I PSRXI PADDR I Psec Rx I P address Regist er SEC- Rx RW 527
0x08E14 I PSRXSPI I Psec Rx SPI Regist er SEC- Rx RW 527
0x08E18 I PSRXI PI DX I Psec Rx SPI Regist er SEC- Rx RW 528
0x08E1C+ 4* n, n= 0. . . 3 I PSRXKEY[ n] I Psec Rx Key Regist er SEC- Rx RW 528
0x08E2C I PSRXSALT I Psec Rx Salt Regist er SEC- Rx RW 528
0x08E30 I PSRXMOD I Psec Rx Mode Regist er SEC- Rx RW 528
Ti mer s Regi st er s
0x0004C TCPTI MER TCP Timer Target RW 529
FCoE Regi st er s
0x05100 FCRXCTRL FC Receive Cont rol Rx- Filt er RW 529
0x0ED00 FCRECTL FCoE Redirect ion Cont rol DBU- Rx RW 530
0x0ED10+ 4* n, n= 0. . . 7 FCRETA[ n] FCoE Redirect ion Table DBU- Rx RW 530
0x02410 FCPTRL FC User Descript or PTR Low DMA- Rx RW 530
0x02414 FCPTRH FC User Descript or PTR High DMA- Rx RW 530
0x02418 FCBUFF FC Buffer Cont rol DMA- Rx RW 530
0x02420 FCDMARW FC Receive DMA RW DMA- Rx RW 532
0x05108 FCFLT FC FLT Cont ext Rx- Filt er RW 532
0x051D8 FCPARAM FC Offset Paramet er Rx- Filt er RW 532
0x05110 FCFLTRW FC Filt er RW Cont rol Rx- Filt er WO 532
Fl ow Di r ect or Regi st er s
Global Set t ings Regist ers
0x0EE00 FDI RCTRL
Flow Direct or Filt ers Cont rol
Regist er
DBU- Rx RW 533
0x0EE68 FDI RHKEY
Flow Direct or Filt ers Lookup Table
Hash Key
DBU- Rx RW 534
0x0EE6C FDI RSKEY
Flow Direct or Filt ers Signat ure
Hash Key
DBU- Rx RW 534
0x0EE3C FDI RDI P4M Flow Direct or Filt ers I Pv4 Mask DBU- Rx RW 534
0x0EE40 FDI RSI P4M
Flow Direct or Filt ers Source I Pv4
Mask
DBU- Rx RW 534
0x0EE44 FDI RTCPM Flow Direct or Filt ers TCP Mask DBU- Rx RW 534
0x0EE48 FDI RUDPM Flow Direct or Filt ers UDP Mask DBU- Rx RW 535
0x0EE74 FDI RI P6M Flow Direct or Filt ers I Pv6 Mask DBU- Rx RW 535
Reset
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0x0EE70 FDI RM Flow Direct or Filt ers Ot her Mask DBU- Rx RW 535
Gl obal St at us / St at i st i cs
Regi st er s
0x0EE38 FDI RFREE Flow Direct or Filt ers Free DBU- Rx RW 536
0x0EE4C FDI RLEN Flow Direct or Filt ers Lengt h DBU- Rx RC 536
0x0EE50 FDI RUSTAT
Flow Direct or Filt ers Usage
St at ist ics
DBU- Rx
RW /
RC
536
0x0EE54 FDI RFSTAT
Flow Direct or Filt ers Failed Usage
St at ist ics
DBU- Rx
RW /
RC
536
0x0EE58 FDI RMATCH
Flow Direct or Filt ers Mat ch
St at ist ics
DBU- Rx RC 537
0x0EE5C FDI RMI SS
Flow Direct or Filt ers Miss Mat ch
St at ist ics
DBU- Rx RC 537
Fl ow Pr ogr ammi ng Regi st er s
0x0EE0C+ 4* n, n= 02 FDI RSI Pv6[ n] Flow Direct or Filt ers Source I Pv6 DBU- Rx RW 537
0x0EE18 FDI RI PSA Flow Direct or Filt ers I P SA DBU- Rx RW 537
0x0EE1C FDI RI PDA Flow Direct or Filt ers I P DA DBU- Rx RW 537
0x0EE20 FDI RPORT Flow Direct or Filt ers Port DBU- Rx RW 537
0x0EE24 FDI RVLAN
Flow Direct or Filt ers VLAN and
FLEX byt es
DBU- Rx RW 538
0x0EE28 FDI RHASH
Flow Direct or Filt ers Hash
Signat ure
DBU- Rx RW 538
0x0EE2C FDI RCMD
Flow Direct or Filt ers Command
Regist er
DBU- Rx RW 538
MAC Regi st er s
0x04200 PCS1GCFI G PCS_1G Global Config Regist er 1 MAC RW 539
0x04208 PCS1GLCTL PCG_1G link Cont rol Regist er MAC RW 539
0x0420C PCS1GLSTA PCS_1G Link St at us Regist er MAC RO 540
0x04218 PCS1GANA
PCS_1 Gb/ s Aut o- Negot iat ion
Advanced Regist er
MAC RW 540
0x0421C PCS1GANLP PCS_1GAN LP Abilit y Regist er MAC RO 541
0x04220 PCS1GANNP
PCS_1G Aut o- Negot iat ion Next
Page Transmit Regist er
MAC RW 542
0x04224 PCS1GANLPNP
PCS_1G Aut o- Negot iat ion LP' s
Next Page Regist er
MAC RO 542
0x04240 HLREG0 MAC Core Cont rol 0 Regist er MAC RW 543
0x04244 HLREG1 MAC Core St at us 1 Regist er MAC RO 543
0x04248 PAP Pause and Pace Regist er MAC RW 544
0x0425C MSCA
MDI Single Command and
Address
MAC RW 544
0x04260 MSRWD MDI Single Read and Writ e Dat a MAC RW 545
0x04268 MAXFRS Max Frame Size MAC RW 545
0x4288 PCSS1 XGXS St at us 1 MAC RO 545
Reset
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0x0428C PCSS2 XGXS St at us 2 MAC RO 545
0x04290 XPCSS 10GBASE-X PCS St at us MAC RO 546
0x04298 SERDESC SerDes I nt erface Cont rol Regist er MAC RW 547
0x0429C MACS FI FO St at us/ CNTL report Regist er MAC RW 548
0x042A0 AUTOC Aut o- Negot iat ion Cont rol Regist er MAC RW 549
0x042A4 LI NKS Link St at us Regist er MAC RO 550
0x04324 LI NKS2 Link St at us Regist er 2 MAC RO 552
0x042A8 AUTOC2
Aut o- Negot iat ion Cont rol 2
Regist er
MAC RW 553
0x042B0 ANLP1
Aut o- Negot iat ion Link Part ner
Link Cont rol Word 1 Regist er
MAC RO 553
0x042B4 ANLP2
Link Cont rol Word 2 Regist er
MAC RO 553
0x042D0 MMNGC
MAC Manageabilit y Cont rol
Regist er
MAC RO 554
0x042D4 ANLPNP1
Next Page 1 regist er
MAC RO 554
0x042D8 ANLPNP2
Next Page 2 regist er
MAC RO 554
0x042E0 KRPCSFC KR PCS and FEC Cont rol Regist er MAC RW 555
0x042E4 KRPCSS KR PCS St at us Regist er MAC RO 555
0x042E8 FECS1 FEC St at us 1 Regist er MAC RC 557
0x042EC FECS2 FEC St at us 2 Regist er MAC RC 557
0x014F00 CoreCTL
Core Analog Configurat ion
Regist er
MAC RW 557
0x014F10 SMADARCTL
Core Common Configurat ion
Regist er
MAC RW 558
0x04294 MFLCN MAC Flow Cont rol Regist er MAC RW 558
0x04314 SGMI I C SGMI I Cont rol Regist er MAC RW 559
St at i st i c Regi st er s
0x04000 CRCERRS CRC Error Count STAT RC 560
0x04004 I LLERRC I llegal Byt e Error Count STAT RC 560
0x04008 ERRBC Error Byt e Count STAT RC 560
0x04034 MLFC MAC Local Fault Count STAT RC 560
0x04038 MRFC MAC Remot e Fault Count STAT RC 561
0x04040 RLEC Receive Lengt h Error Count STAT RC 561
0x08780 SSVPC
Swit ch Securit y Violat ion Packet
Count
DMA-Tx RC 561
0x041A4 LXONRXCNT Link XON Received Count STAT RC 561
0x041A8 LXOFFRXCNT Link XOFF Received Count STAT RC 562
0x04140+ 4* n, n= 0. . . 7 PXONRXCNT[ n] Priorit y XON Received Count STAT RC 562
0x04160+ 4* n, n= 0. . . 7 PXOFFRXCNT[ n] Priorit y XOFF Received Count STAT RC 562
0x0405C PRC64
Packet s Received [ 64 Byt es]
Count
STAT RW 563
Reset
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0x04060 PRC127
Packet s Received [ 65127 Byt es]
Count
STAT RW 563
0x04064 PRC255
Packet s Received [ 128255
Byt es] Count
STAT RW 563
0x04068 PRC511
Byt es] Count
STAT RW 563
0x0406C PRC1023
Byt es] Count
STAT RW 563
0x04070 PRC1522
Packet s Received [ 1024 t o Max
Byt es] Count
STAT RW 564
0x04078 BPRC
Broadcast Packet s Received
Count
STAT RC 564
0x0407C MPRC Mult icast Packet s Received Count STAT RC 564
0x04074 GPRC Good Packet s Received Count STAT RC 564
0x04088 GORCL Good Oct et s Received Count Low STAT RC 564
0x0408C GORCH Good Oct et s Received Count High STAT RC 565
0x041B0 RXNFGPC
Good Rx Non- Filt ered Packet
Count er
STAT RC 565
0x041B4 RXNFGBCL
Good Rx Non- Filt er Byt e Count er
Low
STAT RC 565
0x041B8 RXNFGBCH
Good Rx Non- Filt er Byt e Count er
High
STAT RC 565
0x02F50 RXDGPC DMA Good Rx Packet Count er DMA- Rx RC 565
0x02F54 RXDGBCL DMA Good Rx Byt e Count er Low DMA- Rx RC 565
0x02F58 RXDGBCH DMA Good Rx Byt e Count er High DMA- Rx RC 566
0x02F5C RXDDPC
DMA Duplicat ed Good Rx Packet
Count er
DMA- Rx RC 566
0x02F60 RXDDBCL
DMA Duplicat ed Good Rx Byt e
Count er Low
DMA- Rx RC 566
0x02F64 RXDDBCH
DMA Duplicat ed Good Rx Byt e
Count er High
DMA- Rx RC 566
0x02F68 RXLPBKPC
DMA Good Rx LPBK Packet
Count er
DMA- Rx RC 566
0x02F6C RXLPBKBCL
DMA Good Rx LPBK Byt e Count er
Low
DMA- Rx RC 566
0x02F70 RXLPBKBCH
DMA Good Rx LPBK Byt e Count er
High
DMA- Rx RC 567
0x02F74 RXDLPBKPC
DMA Duplicat ed Good Rx LPBK
Packet Count er
DMA- Rx RC 567
0x02F78 RXDLPBKBCL
Byt e Count er Low
DMA- Rx RC 567
0x02F7C RXDLPBKBCH
Byt e Count er High
DMA- Rx RC 567
0x04080 GPTC Good Packet s Transmit t ed Count STAT RO 567
0x04090 GOTCL
Good Oct et s Transmit t ed Count
Low
STAT RC 567
0x04094 GOTCH
Good Oct et s Transmit t ed Count
High
STAT RC 568
Reset
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0x087A0 TXDGPC DMA Good Tx Packet Count er DMA-Tx RC 568
0x087A4 TXDGBCL DMA Good Tx Byt e Count er Low DMA-Tx RC 568
0x087A8 TXDGBCH DMA Good Tx Byt e Count er High DMA-Tx RC 568
0x040A4 RUC Receive Undersize Count STAT RC 569
0x040A8 RFC Receive Fragment Count STAT RC 569
0x040AC ROC Receive Oversize Count STAT RC 569
0x040B0 RJC Receive Jabber Count STAT RC 569
0x040B4 MNGPRC
Management Packet s Received
Count
STAT RO 569
0x040B8 MNGPDC
Management Packet s Dropped
Count
STAT RO 569
0x040C0 TORL Tot al Oct et s Received STAT RC 570
0x040C4 TORH Tot al Oct et s Received STAT RC 570
0x040D0 TPR Tot al Packet s Received STAT RC 570
0x040D4 TPT Tot al Packet s Transmit t ed STAT RC 570
0x040D8 PTC64
Packet s Transmit t ed ( 64 Byt es)
Count
STAT RC 570
0x040DC PTC127
Packet s Transmit t ed [ 65127
Byt es] Count
STAT RC 571
0x040E0 PTC255
Byt es] Count
STAT RC 571
0x040E4 PTC511
Byt es] Count
STAT RC 571
0x040E8 PTC1023
Byt es] Count
STAT RC 571
0x040EC PTC1522
Packet s Transmit t ed [ Great er
t han 1024 Byt es] Count
STAT RC 571
0x040F0 MPTC
Mult icast Packet s Transmit t ed
Count
STAT RC 571
0x040F4 BPTC
Broadcast Packet s Transmit t ed
Count
STAT RC 572
0x04010 MSPDC MAC short Packet Discard Count STAT RC 572
0x04120 XEC XSUM Error Count STAT RC 572
0x02300+ 4* n, n= 0. . . 31 RQSMR[ n]
Receive Queue St at ist ic Mapping
Regist ers
DMA- Rx RW 572
0x02F40 RXDSTATCTRL Rx DMA St at ist ic Count er Cont rol DMA-Tx RW 573
0x08600+ 4* n, n= 0. . . 31 /
0x07300+ 4* n, n= 07
TQSM[ n]
Transmit Queue St at ist ic Mapping
Regist ers
DMA-Tx RW 573
0x01030+ 0x40* n, n= 0. . . 15 QPRC[ n] Queue Packet s Received Count DMA- Rx RC 573
0x01430+ 0x40* n, n= 0. . . 15 QPRDC[ n]
Queue Packet s Received Dr op
Count
DMA- Rx RC 573
0x1034+ 0x40* n, n= 0. . . 15 QBRC_L[ n] Queue Byt es Received Count Low DMA- Rx RC 573
0x1038+ 0x40* n, n= 0. . . 15 QBRC_H[ n] Queue Byt es Received Count High DMA- Rx RC 573
0x08680+ 0x4* n, n= 0. . . 15 /
0x06030+ 0x40* n, n= 0. . . 15
QPTC Queue Packet s Transmit t ed Count DMA-Tx RC 574
Reset
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0x08700+ 0x8* n, n= 0. . . 15 QBTC_L[ n]
Queue Byt es Transmit t ed Count
Low
DMA-Tx RC 574
0x08704+ 0x8* n, n= 0. . . 15 QBTC_H[ n]
Queue Byt es Transmit t ed Count
High
DMA-Tx RC 574
0x05118 FCCRC FC CRC Error Count Rx- Filt er RC 575
0x0241C FCOERPDC FCoE Rx Packet s Dropped Count DMA- Rx RC 575
0x02424 FCLAST FC Last Error Count DMA- Rx RC 575
0x02428 FCOEPRC FCoE Packet s Received Count DMA- Rx RC 575
0x0242C FCOEDWRC FCOE DWord Received Count DMA- Rx RC 576
0x08784 FCOEPTC FCoE Packet s Transmit t ed Count DMA-Tx RC 576
0x08788 FCOEDWTC FCoE DWord Transmit t ed Count DMA-Tx RC 576
Wak e- Up Cont r ol Regi st er s
0x05800 WUC Wake Up Cont rol Regist er Rx- Filt er RW 576
0x05808 WUFC Wake Up Filt er Cont rol Regist er Rx- Filt er RW 577
0x5838 I PAV I P Address Valid Rx- Filt er RW 577
0x05840+ 8* n, n = 0. . . 3 I P4AT[ n] I Pv4 Address Table Rx- Filt er RW 578
0x05880+ 4* n, n = 0. . . 3 I P6AT[ n] I Pv6 Address Table Rx- Filt er RW 578
0x05900 WUPL Wake Up Packet Lengt h Rx- Filt er RO 578
0x05A00+ 4* n, n= 0. . . 31 WUPM[ n]
Wake Up Packet Memory ( 128
Byt es)
Rx- Filt er RO 578
0x09000 0x093FC, 0x09800
0x099FC
FHFT Flexible Host Filt er Table regist ers Rx- Filt er RW 578
Management Fi l t er s Regi st er s
0x5010 + 4* n, n= 0. . . 7 MAVTV[ n] Management VLAN TAG Value Rx- Filt er RW 580
0x5030+ 4* n, n= 0. . . 7 MFUTP[ n] Management Flex UDP/ TCP Port s Rx- Filt er RW 580
0x05190+ 4* n, n= 0. . . 3 METF[ n]
Management Et hernet Type
Filt ers
Rx- Filt er RW 581
0x05820 MANC Management Cont rol Regist er Rx- Filt er RW 581
0x5824 MFVAL Manageabilit y Filt ers Valid Rx- Filt er RW 581
0x5860 MANC2H
Management Cont rol To Host
Regist er
Rx- Filt er RW 582
0x5890+ 4* n, n= 0. . . 7 MDEF[ n] Manageabilit y Decision Filt ers Rx- Filt er RW 582
0x05160+ 4* n, n= 0. . . 7 MDEF_EXT[ n] Manageabilit y Decision Filt ers Rx- Filt er RW 583
0x58B0+ 0x10* m+ 4* n, m= 0. . . 3,
n= 0. . . 3
MI PAF Manageabilit y I P Address Filt er Rx- Filt er RW 583
0x5910+ 8* n, n= 0. . . 3 MMAL[ n]
Manageabilit y Et hernet MAC
Address Low
Rx- Filt er RW 583
0x5914+ 8* n, n= 0. . . 3 MMAH[ n]
Manageabilit y Et hernet MAC
Address High
Rx- Filt er RW 583
0x09400- 0x097FC FTFT Flexible TCO Filt er Table regist ers Rx- Filt er RW 584
0x015F14 LSWFW LinkSec SW/ FW I nt erface MNG RO 585
Ti me Sy nc ( I EEE 1588)
Regi st er s
Reset
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0x05188 TSYNCRXCTL Rx Time Sync Cont rol Regist er Rx- Filt er RW 586
0x051E8 RXSTMPL Rx Timest amp Low Rx- Filt er RO 586
0x051A4 RXSTMPH Rx Timest amp High Rx- Filt er RO 587
0x051A0 RXSATRL Rx Timest amp At t ribut es Low Rx- Filt er RO 587
0x051A8 RXSATRH Rx Timest amp At t ribut es High Rx- Filt er RO 587
0x05120 RXMTRL Rx Message Type Regist er Low Rx- Filt er RW 587
0x08C00 TSYNCTXCTL Tx Time Sync Cont rol Regist er SEC-Tx RW 587
0x08C04 TXSTMPL Tx Timest amp Value Low SEC-Tx RO 588
0x08C08 TXSTMPH Tx Timest amp Value High SEC-Tx RO 588
0x08C0C SYSTI ML Syst em Time Regist er Low SEC-Tx RW 588
0x08C10 SYSTI MH Syst em Time Regist er High SEC-Tx RW 588
0x08C14 TI MI NCA I ncrement At t ribut es Regist er SEC-Tx RW 588
0x08C18 TI MADJL
Time Adj ust ment Offset Regist er
low
SEC-Tx RW 588
0x08C1C TI MADJH
Time Adj ust ment Offset Regist er
High
SEC-Tx RW 588
0x08C20 TSAUXC
TimeSync Auxiliary Cont rol
Regist er
SEC-Tx RW 589
0x08C24 TRGTTI ML0 Target Time Regist er 0 Low SEC-Tx RW 589
0x08C28 TRGTTI MH0 Target Time Regist er 0 High SEC-Tx RW 589
0x08C2C TRGTTI ML1 Target Time Regist er 1 Low SEC-Tx RW 589
0x08C30 TRGTTI MH1 Target Time Regist er 1 High SEC-Tx RW 589
0x08C3C AUXSTMPL0
Auxiliary Time St amp 0 Regist er
low
SEC-Tx RO 590
0x08C40 AUXSTMPH0
high
SEC-Tx RO 590
0x08C44 AUXSTMPL1
low
SEC-Tx RO 590
0x08C48 AUXSTMPH1
high
SEC-Tx RO 590
Vi r t ual i zat i on PF Regi st er s
0x051B0 PFVTCTL PF Virt ual Cont rol Regist er Rx- Filt er RW 591
0x04B00+ 4* n, n= 0. . . 63 PFMailbox[ n] PF Mailbox Target RW 591
0x00710+ 4* n, n= 0. . . 3 PFMBI CR[ n]
PF Mailbox I nt errupt Causes
Regist er
Target RW1C 591
0x00720+ 4* n, n= 0. . . 1 PFMBI MR[ n]
PF Mailbox I nt errupt Mask
Regist er
Target RW 592
0x00600, 0x001C0 PFVFLRE[ n] PF VFLR Event s I ndicat ion Target RO 592
0x00700+ 4* n, n= 0. . . 1 PFVFLREC[ n] PF VFLR Event s Clear Target W1C 592
0x051E0+ 4* n, n= 0. . . 1 PFVFRE[ n] PF VF Receive Enable RW 592
0x08110+ 4* n, n= 0. . . 1 PFVFTE[ n] PF VF Transmit Enable DMA-Tx RW 592
0x02F04 PFQDE PF Queue Drop Enable Regist er DMA- Rx RW 592
0x05180+ 4 * n, n= 0. . . 1 PFVMTXSW[ n] PF VM Tx Swit ch Loopback Enable Rx- Filt er RW 593
Reset
Sour ce
Page

453
Not e: ( * ) The MAC Manageabilit y Cont rol Regist er is read only t o t he host and read/ writ e t o
manageabilit y.
8. 2. 3 Det ai l ed Regi st er Descr i pt i ons PF
8.2.3.1 Gener al Cont r ol Regi st er s
Devi ce Cont r ol Regi st er CTRL ( 0x 00000 / 0x 00004; RW) CTRL is also mapped t o address
0x00004 t o maint ain compat ibilit y wit h previous devices.
0x08200+ 4* n, n= 0. . . 7 PFVFSPOOF[ n] PF VF Ant i Spoof Cont rol DMA-Tx RW 593
0x08220 PFDTXGSWC
PF DMA Tx General Swit ch
Cont rol
DMA-Tx RW 593
0x08000+ 4* n, n= 0. . . 63 PFVMVI R[ n] PF VM VLAN I nsert Regist er DMA-Tx RW 593
0x0F000+ 4* n, n= 0. . . 63 PFVML2FLT[ n] PF VM L2 Cont rol Regist er Rx- Filt er RW 594
0x0F100+ 4* n, n= 0. . . 63 PFVLVF[ n] PF VM VLAN Pool Filt er Rx- Filt er RW 594
0x0F200+ 4* n, n= 0. . . 127 PFVLVFB[ n] PF VM VLAN Pool Filt er Bit map Rx- Filt er RW 594
0x0F400+ 4* n, n= 0. . . 127 PFUTA[ n] PF Unicast Table Array Rx- Filt er RW 595
0x0F600+ 4* n, n= 0. . . 3 PFMRCTL[ n] PF Mirror Rule Cont rol Rx- Filt er RW 595
0x0F610+ 4* n, n= 0. . . 7 PFMRVLAN[ n] PF Mirror Rule VLAN Rx- Filt er RW 595
0x0F630+ 4* n, n= 0. . . 7 PFMRVM[ n] PF Mirror Rule Pool Rx- Filt er RW 596
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 1: 0 0b
Reserved
Writ e as 0b for fut ure compat ibilit y.
PCI e Mast er Disable 2 0b
When set , t he 82599 blocks new mast er request s, including manageabilit y request s, by
using t his funct ion. Once no mast er request s are pending by using t his funct ion, t he
PCI e Mast er Enable St at us bit is cleared.
LRST 3 0b
Link Reset
This bit performs a reset of t he MAC, PCS, and aut o negot iat ion funct ions and t he ent ire
I nt el
82599 10 GbE Cont roller ( soft ware reset ) result ing in a st at e nearly
approximat ing t he st at e following a power- up reset or int ernal PCI e reset , except for t he
syst em PCI configurat ion. Normally 0b, writ ing 1b init iat es t he reset . This bit is self-
clearing. Also referred t o as MAC reset .
Reser ved 25: 4 0b Reserved
RST 26 0b
Device Reset
This bit performs a complet e reset of t he 82599, result ing in a st at e nearly
approximat ing t he st at e following a power- up reset or int ernal PCI e reset , except for t he
syst em PCI configurat ion. Normally 0b, writ ing 1b init iat es t he reset . This bit is self-
clearing. Also referred t o as a soft ware reset or global reset .
Reserved 31: 27 0x0 Reserved
Reset
Sour ce
Page
I nt el

454
LRST and RST can be used t o globally reset t he ent ire I nt el
82599 10 GbE Cont roller. This regist er is

provided primarily as a last - dit ch soft ware mechanism t o recover from an indet erminat e or suspect ed
hung hardware st at e. Most regist ers ( receive, t ransmit , int errupt , st at ist ics, et c. ) and st at e machines
are set t o t heir power- on reset values, approximat ing t he st at e following a power- on or PCI reset .
However, PCI e Configurat ion regist ers are not reset , t hereby leaving t he 82599 mapped int o syst em
memory space and accessible by a soft ware device driver.
To ensure t hat a global device reset has fully complet ed and t hat t he 82599 responds t o subsequent
accesses, programmers must wait approximat ely 1 ms aft er set t ing before at t empt ing t o check if t he
bit has cleared or t o access ( read or writ e) any ot her device regist er.
8.2.3. 1.1 Devi ce St at us Regi st er STATUS ( 0x 00008; RO)
8.2.3. 1.2 Ex t ended Devi ce Cont r ol Regi st er CTRL_EXT ( 0x 00018; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LAN I D 3: 2 0b
LAN I D. Provides soft ware a mechanism t o det ermine t he device LAN ident ifier for t his
MAC. Read as: [ 0, 0] LAN 0, [ 0, 1] LAN 1.
LinkUp 7 0b
Linkup St at us I ndicat ion. This bit is useful for I OV mode. The PF soft ware driver set s it
according t o Links regist er and PHY st at e. I t is reflect ed in t he VFSTATUS regist er
indicat ing linkup t o t he VF drivers.
Num VFs 17: 10 0x0
The Num VFs field r eflect s t he value of t he Num VFs in t he I OV capabilit y st r uct ur e
( not e t hat bit 17 is always 0b) .
I OV Act ive 18 0b
The I O Act ive bit , reflect s t he value of t he VF Enable ( VFE) bit in t he I OV Cont rol/ St at us
regist er.
PCI e Mast er Enable
St at us
19 1b
This is a st at us bit of t he appropriat e CTRL. PCI e Mast er Disable bit .
1b = Associat ed LAN funct ion can issue mast er request s.
0b = Associat ed LAN funct ion does not issue any mast er request and all previously
issued request s are complet e.
Reserved 31: 20 0b
Reserved
Reads as 0b.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 13: 0 0x0 Reserved.
PFRSTD ( SC) 14 0b
PF Reset Done. When set , t he RSTI bit in all t he VFMailbox regist ers are cleared and t he
RSTD bit in all t he VFMailbox regs is set .
Reserved 16: 15 00b Reserved
RO_DI S 17 0b
Relaxed Ordering Disable. When set t o 1b, t he device does not request any relaxed
ordering t ransact ions. When t his bit is cleared and t he Enable Relaxed Ordering bit in
t he Device Cont rol regist er is set , t he device request s relaxed ordering t ransact ions per
queues as configured in t he DCA_RXCTRL[ n] and DCA_TXCTRL[ n] regist ers.
Reserved 25: 18 0b Reserved.

455
8. 2.3. 1.3 Ex t ended SDP Cont r ol ESDP ( 0x 00020; RW)
This regist er is init ialized only at LAN Power Good preserving t he SDP st at es across soft ware and PCI e
reset s. Some specific I / O pins are init ialized in ot her reset s in nat ive mode as expect ed for t he specific
behavior and described explicit ly as follows.
Ext ended VLAN 26 0b
Ext ended VLAN. When set , all incoming Rx packet s are expect ed t o have at least one
VLAN wit h t he Et her t ype as defined in EXVET regist er. The packet s can have an inner-
VLAN t hat should be used for all filt ering purposes. All Tx packet s are expect ed t o have
at least one VLAN added t o t hem by t he host . I n t he case of an addit ional VLAN request
( VLE) , t he inner-VLAN is added by t he hardware aft er t he out er-VLAN is added by t he
host . This bit should only be reset by a PCI e reset and should only be changed while Tx
and Rx processes are st opped.
The except ion t o t his rule are MAC cont rol packet s such as flow cont rol, 802. 1x, LACP,
et c. t hat never carry a VLAN t ag of any t ype.
Reserved 27 0b Reserved.
DRV_LOAD 28 0b
Driver loaded and t he corresponding net work int erface is enabled. This bit should be set
by t he soft ware device driver aft er it was loaded and cleared when it unloads or at PCI e
soft reset . The Manageabilit y Cont roller ( MC) loads t his bit as an indicat ion t hat t he
driver successfully loaded t o it .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SDP0_DATA 0 0b
1
SDP0 Dat a Value. Used t o read ( writ e) a value of t he soft ware- cont rolled I / O pin SDP0.
I f SDP0 is configured as an out put ( SDP0_I ODI R = 1b) , t his bit cont rols t he value driven
on t he pin. I f SDP0 is configured as an input , all reads ret urn t he current value of t he
pin.
SDP1_DATA 1 0b
1
pin.
SDP2_DATA 2 0b
1
SDP2 Dat a Value. Used t o read ( writ e) a value of soft ware- cont rolled I / O pin SDP2. I f
SDP2 is configured as an out put ( SDP2_I ODI R = 1b) , t his bit cont rols t he value driven
pin.
SDP3_DATA 3 0b
1
pin.
SDP4_DATA 4 0b
pin.
SDP5_DATA 5 0b
pin.
SDP6_DATA 6 0b
pin.
SDP7_DATA 7 0b
pin.
SDP0_I ODI R 8 0b
1
SDP0 Pin Direct ionalit y. Cont rols whet her or not soft ware- cont rolled pin SDP0 is
configured as an input or out put ( 0b = input , 1b = out put ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

456
SDP1_I ODI R 9 0b
1
SDP2_I ODI R 10 0b
1
SDP3_I ODI R 11 0b
1
SDP4_I ODI R 12 0b
SDP5_I ODI R 13 0b
SDP6_I ODI R 14 0b
SDP7_I ODI R 15 0b
SDP0_NATI VE 16 0b
SDP0 Operat ing Mode.
0b = Generic soft ware cont rolled I / O by SDP0_DATA and SDP0_I ODI R.
1b = Reserved.
SDP1_NATI VE 17 0b
1
1b = Nat ive mode operat ion ( connect ed t o hardware funct ion) . I n t his mode, t he
SDP1_I ODI R must be set t o 1b.
SDP2_NATI VE 18 0b
SDP2 operat ing mode:
0b = Generic soft ware cont rolled I O by SDP2_DATA and SDP2_I ODI R.
1b = Nat ive mode operat ion ( Connect ed t o hardware funct ion) . I n t his mode pin
funct ions as defined by t he SDP2_TSync_TT1 bit
SDP3_NATI VE 19 0b
1b = Nat ive mode operat ion ( connect ed t o hardware funct ion) . I n t his mode pin
funct ions as defined by t he SDP3_TSync_TT0 bit .
SDP4_NATI VE 20 0b
1b = Nat ive mode operat ion ( connect ed t o hardware funct ion) . Drives opt ical module
reset according t o funct ionalit y defined by t he SDP4_Funct ion bit .
SDP5_NATI VE 21 0b
1b = Nat ive mode operat ion ( connect ed t o hardware funct ion) . Drives opt ical module
t ransmit disable according t o funct ionalit y defined by t he SDP5_Funct ion bit .
SDP6_NATI VE 22 0b
1b = Nat ive mode operat ion ( connect ed t o hardware funct ion) . I n t his mode, pin
SDP7_NATI VE 23 0b
1b = Nat ive mode operat ion ( connect ed t o hardware funct ion) . I n t his mode, pin
Reserved 25: 24 0 Reserved
SDP2_TSync_TT1 26 0b
SDP2 Nat ive Mode Funct ionalit y ( SDP2_NATI VE = 1) .
0b = TS0 funct ionalit y. Samples I EEE 1588 t ime st amp int o Auxiliary Time St amp 0
regist er on level change of SDP2 signal ( For TS0 funct ionalit y, SDP2_I ODI R should be
configured as input ) .
1b = TT1 funct ionalit y. Assert s SDP2 t o 1 when I EEE 1588 t ime st amp equals Target
Time regist er 1 ( For TT1 funct ionalit y, SDP2_I ODI R should be configured as out put ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

457
8.2.3.1.4 I 2C Cont r ol I 2CCTL ( 0x 00028; RW)
0b = TS1 funct ionalit y. Samples I EEE 1588 t ime st amp int o Auxiliary Time St amp 1
regist er on level change of SDP3 signal ( For TS1 funct ionalit y, SDP3_I ODI R should be
configured as input ) .
1b = TT0 funct ionalit y. Assert s SDP3 t o 1b when I EEE 1588 t ime st amp equals Target
SDP4_Funct ion 28 0b
0b = Pin funct ionalit y is driven by soft ware ( SDP4_dat a bit ) except when t he MAC is
reset or when ent ering D3 power st at e when management funct ionalit y is disabled. I n
t he previous case SDP4 pin moves t o t ri- st at e ( by reset t ing SDP4_I ODI R bit ) and
opt ical module is reset by placing an appropriat e ext ernal pullup or pull- down resist or
on t he SDP4 pin.
1b = SDP4 pin is driven high when t he MAC is reset or powered down ( D3 st at e) .
SDP4_I ODI R should be configured as out put for t his funct ionalit y.
SDP5_Funct ion 29 0b
0b = Pin funct ionalit y is driven by soft ware ( SDP5_dat a bit ) except when t he MAC is
reset or when ent ering D3 power st at e when management funct ionalit y is disabled. I n
t he previous case, SDP5 pin moves t o t ri- st at e ( by reset t ing SDP5_I ODI R bit ) and
opt ical module t ransmission is disabled by placing an appropriat e ext ernal pullup or
pull- down resist or on t he SDP5 pin.
1b = SDP5 pin is driven high when t he MAC is reset or powered down ( D3 st at e) .
SDP5_I ODI R should be configured as out put for t his funct ionalit y.
0b = CLK0 funct ionalit y. Drives a reference clock wit h t he frequency defined in t he
Frequency Out 0 Cont rol regist er ( For CLK0 funct ionalit y, SDP6_I ODI R should be
configured as out put ) .
0b = CLK1 funct ionalit y. Drives a reference clock wit h t he frequency defined in t he
Frequency Out 1 Cont rol regist er ( for CLK1 funct ionalit y, SDP7_I ODI R should be
configured as out put ) .
1. I nit ial value can be configured using t he EEPROM.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I 2C_CLK_I N 0 0b
I 2C_CLK I n Value
Provides t he value of I 2C_CLK ( input from ext ernal PAD) . This bit is RO.
I 2C_CLK_OUT 1 1b
I 2C_CLK Out Value
Used t o drive t he value of I 2C_CLK ( out put t o PAD) .
I 2C_DATA_I N 2 0b
I 2C_DATA I n Value
Provides t he value of I 2C_DATA ( input from ext ernal PAD) . This bit is RO.
I 2C_DATA_OUT 3 1b
I 2C_DATA Out Value
Used t o drive t he value of I 2C_DATA ( out put t o PAD) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

458
8.2.3. 1.5 LED Cont r ol LEDCTL ( 0x 00200; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LED0_MODE 3: 0 0x0
1
LED0 Mode. This field specifies t he cont rol source for t he LED0 out put . An init ial value of
0000b select s t he LI NK_UP indicat ion.
Reserved 4 0b
1
Reserved
GLOBAL_BLI NK_
MODE
5 0b
1
GLOBAL Blink Mode. This field specifies t he blink mode of all LEDs.
0b = Blink at 200 ms on and 200 ms off.
1b = Blink at 83 ms on and 83 ms off.
LED0_I VRT 6 0b
1
LED0 I nvert . This field specifies t he polarit y/ inversion of t he LED source prior t o out put
or blink cont rol. By default t he out put drives t he cat hode of t he LED so when t he LED
out put is 0b t he LED is on.
0b = LED out put is act ive low.
1b = LED out put is act ive high.
LED0_BLI NK 7 0b
1
LED0 Blink. This field specifies whet her or not t o apply blink logic t o t he ( invert ed) LED
cont rol source prior t o t he LED out put .
0b = Do not blink LED out put .
1b = Blink LED out put .
LED1_MODE 11: 8 0x1
1
0001b select s t he 10 Gb/ s link indicat ion.
Reserved 13: 12 0b
1
Reserved
LED1_I VRT 14 0b
1
LED1_BLI NK 15 1b
1
LED2_MODE 19: 16 0x4
1
0100 select s LI NK/ ACTI VI TY indicat ion.
Reserved 21: 20 0
1
Reserved
LED2_I VRT 22 0
1
LED2_BLI NK 23 0
1
LED3_MODE 27: 24 0x5
1
0101b select s t he 1 Gb/ s link indicat ion.
Reserved 29: 28 0b
1
Reserved
LED3_I VRT 30 0b
1

459
The following mapping is used t o specify t he LED cont rol source ( MODE) for each LED out put :
8.2.3.1.6 Ex t ended VLAN Et her Ty pe EXVET ( 0x 05078; RW)
LED3_BLI NK 31 0b
1
1. These bit s are read from t he EEPROM.
MODE Sel ect ed Mode Sour ce I ndi cat i on
0000b LI NK_UP
Assert ed or blinking according t o t he LEDx_BLI NK set t ing when any speed link is
est ablished and maint ained.
0001b LI NK_10G
Assert ed or blinking according t o t he LEDx_BLI NK set t ing when a 10 Gb/ s link is
0010b MAC_ACTI VI TY
Act ive when link is est ablished and packet s are being t ransmit t ed or received. I n t his
mode, t he LEDx_BLI NK must be set .
0011b FI LTER_ACTI VI TY
Act ive when link is est ablished and packet s are being t ransmit t ed or received t hat
passed MAC filt ering. I n t his mode, t he LEDx_BLI NK must be set .
0100b LI NK/ ACTI VI TY
Assert ed st eady when link is est ablished and t here is no t ransmit or receive act ivit y.
Blinking when t here is link and receive or Transmit act ivit y. I n t his mode LEDx_BLI NK
must be cleared at 0b.
0101b LI NK_1G
Assert ed or blinking according t o t he LEDx_BLI NK set t ing when a 1 Gb/ s link is
0110 LI NK_100
Assert ed or blinking according t o t he LEDx_BLI NK set t ing when a 100 Mb/ s link is
0111b: 1101b Reserved Reserved
1110b LED_ON Always assert ed or blinking according t o t he LEDx_BLI NK set t ing.
1111b LED_OFF Always deassert ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VET EXT 31: 16 0x8100
Out er-VLAN Et her Type ( VLAN Tag Prot ocol I dent ifier - TPI D) .
Not e: This field appears in lit t le endian ( MS byt e first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

460
8. 2.3. 2 EEPROM/ Fl ash Regi st er s
8.2.3. 2.1 EEPROM/ Fl ash Cont r ol Regi st er EEC ( 0x 10010; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EE_SK 0 0b
Clock input t o t he EEPROM. When EE_GNT is set t o 1b, t he EE_SK out put signal is
mapped t o t his bit and provides t he serial clock input t o t he EEPROM. Soft ware clocks
t he EEPROM via t oggling t his bit wit h successive writ es.
EE_CS 1 0b
Chip select input t o t he EEPROM. When EE_GNT is set t o 1b, t he EE_CS out put signal is
mapped t o t he chip select of t he EEPROM device. Soft ware enables t he EEPROM by
writ ing a 0b t o t his bit .
EE_DI 2 0b
Dat a input t o t he EEPROM. When EE_GNT is set t o 1b, t he EE_DI out put signal is
mapped direct ly t o t his bit . Soft ware provides dat a input t o t he EEPROM via writ es t o
t his bit .
EE_DO ( RO field) 3 X
Dat a out put bit from t he EEPROM. The EE_DO input signal is mapped direct ly t o t his bit
in t he regist er and cont ains t he EEPROM dat a out put . This bit is read- only from a
soft ware perspect ive; writ es t o t his bit have no effect .
FWE 5: 4 01b
Flash Writ e Enable Cont rol. These t wo bit s cont rol whet her or not writ es t o t he Flash are
allowed.
00b = Flash erase ( along wit h bit 31 in t he FLA regist er) .
01b = Flash writ es disabled.
10b = Flash writ es enabled.
11b = Not allowed.
EE_REQ 6 0b
Request EEPROM Access. Soft ware must writ e a 1b t o t his bit t o get direct EEPROM
access. I t has access when EE_GNT is set t o 1b. When soft ware complet es t he access, it
must t hen writ e a 0b.
EE_GNT ( RO field) 7 0b
Grant EEPROM Access. When t his bit is set t o 1b, soft ware can access t he EEPROM
using t he EE_SK, EE_CS, EE_DI , and EE_DO bit s.
EE_PRES ( RO field) 8
( see
desc. )
EEPROM Present . Set t ing t his bit t o 1b indicat es t hat an EEPROM is present and has t he
correct signat ure field. This bit is read- only.
Aut o_RD ( RO field) 9 0b
EEPROM Aut o- Read Done. When set t o 1b, t his bit indicat es t hat t he aut o- read by
hardware from t he EEPROM is done. This bit is also set when t he EEPROM is not present
or when it s signat ure field is not valid.
EE_Size ( RO field) 14: 11 0010b
1
EEPROM Size. This field defines t he size of t he EEPROM ( see Table 8. 3) .
PCI _ANA_done ( RO
field)
15 0b
PCI e Analog Done. When set t o 1b, indicat es t hat t he PCI e analog sect ion read from
EEPROM is done. This bit is cleared when aut o- read st art s. This bit is also set when t he
EEPROM is not present or when it s signat ure field is not valid.
PCI _Core_done ( RO
field)
16 0b
PCI e Core Done. When set t o 1b, indicat es t hat t he Core analog sect ion read from
Not e: This bit ret urns t he relevant done indicat ion for t he funct ion t hat reads t he
regist er.
PCI _genarl _done
( RO field)
17 0b
PCI e General Done. When set t o 1b, indicat es t hat t he PCI e general sect ion read from
t he EEPROM is done. This bit is cleared when aut o- read st art s. This bit is also set when
t he EEPROM is not present or when it s signat ure field is not valid.
PCI _FUNC_DONE ( RO
field)
18 0b
PCI e Funct ion Done. When set t o 1b, indicat es t hat t he PCI e funct ion sect ion read from
regist er.
CORE_DONE ( RO
field)
19 0b
Core Done. When set t o 1b, indicat es t hat t he Core analog sect ion read from t he
regist er.

461
This regist er provides soft ware- direct access t o t he EEPROM. Soft ware can cont rol t he EEPROM by
successive writ es t o t his regist er. Dat a and address informat ion is clocked int o t he EEPROM by soft ware
t oggling t he EESK bit ( 2) of t his regist er. Dat a out put from t he EEPROM is lat ched int o bit 3 of t his
regist er via t he int ernal 62.5 MHz clock and can be accessed by soft ware via reads of t his regist er.
Not e: At t empt s t o writ e t o t he Flash device when writ es are disabled ( FWE = 01b) should not be
at t empt ed. Behavior aft er such an operat ion is undefined, and might result in component
and/ or syst em hangs.
8.2.3.2.2 EEPROM Read Regi st er EERD ( 0x 10014; RW)
CORE_CSR_DONE
( RO field)
20 0b
Core CSR Done. When set t o 1b, indicat es t hat t he Core CSR sect ion read from t he
regist er.
MAC_DONE ( RO field) 21 0b
MAC Done. When set t o 1b, indicat es t hat t he MAC sect ion read from t he EEPROM is
done. This bit is cleared when aut o- read st art s. This bit is also set when t he EEPROM is
not present or when it s signat ure field is not valid.
regist er.
Reserved 31: 22 0x0 Reserved. Reads as 0b.
1. These bit s are read from t he EEPROM.
Tabl e 8. 3. EEPROM Si zes ( Bi t s 14: 11)
Fi el d Val ue EEPROM Si ze EEPROM Addr ess Si ze
0100b 16 Kb 2 byt es
0111b 128 Kb 2 byt es
1000b 256 Kb 2 byt es
1001b: 1111b Reserved Reserved
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
START 0 0b
St art Read
Writ ing a 1b t o t his bit causes t he EEPROM t o read a 16- bit word at t he address st ored
in t he EE_ADDR field and t hen st ores t he result in t he EE_DATA field. This bit is self-
clearing.
DONE 1 0b
Read Done
Set t his bit t o 1b when t he EEPROM read complet es.
Set t his bit t o 0b when t he EEPROM read is in progress.
Not e t hat writ es by soft ware are ignored.
ADDR 15: 2 0x0
Read Address
This field is writ t en by soft ware along wit h St art Read t o indicat e t hat t he address of t he
word t o read.
DATA 31: 16 0x0
Read Dat a
Dat a ret urned from t he EEPROM read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

462
This regist er is used by soft ware t o cause t he 82599 t o read individual words in t he EEPROM. To read a
word, soft ware writ es t he address t o t he Read Address field and simult aneously writ es a 1b t o t he St art
Read field. The 82599 reads t he word from t he EEPROM and places it in t he Read Dat a field, set t ing t he
Read Done field t o 1b. Soft ware can poll t his regist er, looking for a 1b in t he Read Done field and t hen
using t he value in t he Read Dat a field.
When t his regist er is used t o read a word from t he EEPROM, t hat word is not writ t en t o any of t he
82599' s int ernal regist ers even if it is normally a hardware- accessed word.
8.2.3. 2.3 Fl ash Access Regi st er FLA ( 0x 1001C; RW)
This regist er provides soft ware direct access t o t he Flash. Soft ware can cont rol t he Flash by successive
writ es t o t his regist er. Dat a and address informat ion is clocked int o t he EEPROM by soft ware t oggling
FL_SCK in t his regist er. Dat a out put from t he Flash is lat ched int o bit 3 of t his regist er via t he int ernal
125 MHz clock and can be accessed by soft ware via reads of t his regist er.
Not e: I n t he 82599, t he FLA regist er is only reset at LAN_PWR_GOOD as opposed t o legacy devices
at soft ware reset .
8.2.3. 2.4 Manageabi l i t y EEPROM Cont r ol Regi st er EEMNGCTL ( 0x 10110; RW)
Not e: This regist er can be read/ writ e by manageabilit y firmware and is read- only t o host soft ware.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FL_SCK 0 0b
Clock input t o t he Flash. When FL_GNT is set t o 1b, t he FL_SCK out put signal is mapped
t o t his bit and provides t he serial clock input t o t he Flash. Soft ware clocks t he Flash via
t oggling t his bit wit h successive writ es.
FL_CE 1 0b
Chip select input t o t he Flash. When FL_GNT is set t o 1b, t he FL_CE out put signal is
mapped t o t he chip select of t he Flash device. Soft ware enables t he Flash by writ ing a
0b t o t his bit .
FL_SI 2 0b
Dat a input t o t he Flash. When FL_GNT is set t o 1b, t he FL_SI out put signal is mapped
direct ly t o t his bit . Soft ware provides dat a input t o t he Flash via writ es t o t his bit .
FL_SO 3 X
Dat a out put bit from t he Flash. The FL_SO input signal is mapped direct ly t o t his bit in
t he regist er and cont ains t he Flash serial dat a out put . This bit is read- only from a
soft ware perspect ive. Not e t hat writ es t o t his bit have no effect .
FL_REQ 4 0b
Request Flash Access. Soft ware must writ e a 1b t o t his bit t o get direct Flash access. I t
has access when FL_GNT is set t o 1b. When soft ware complet es t he access, it must
t hen writ e a 0b.
FL_GNT 5 0b
Grant Flash Access. When t his bit is set t o 1b, soft ware can access t he Flash using t he
FL_SCK, FL_CE, FL_SI , and FL_SO bit s.
Reserved 29: 6 0b Reserved. Reads as 0b.
FL_BUSY 30 0b
Flash Busy. This bit is set t o 1b while a writ e or an erase t o t he Flash is in progress,
While t his bit is cleared ( reads as 0b) , soft ware can access t o writ e a new byt e t o t he
Flash.
Not e: This bit is read- only from a soft ware perspect ive.
FL_ER 31 0b
Flash Erase Command. This command is sent t o t he Flash only if bit s 5: 4 of regist er EEC
are also set t o 00b. This bit is aut o- cleared and reads as 0b.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
ADDR 14: 0 0x0
Address. This field is writ t en by manageabilit y along wit h St art bit and t he Writ e bit t o
indicat e which EEPROM address t o read or writ e.
START 15 0b
St art . Writ ing a 1b t o t his bit causes t he EEPROM t o st art t he read or writ e operat ion
according t o t he writ e bit . This bit is self cleared by hardware.

463
8. 2.3. 2.5 Manageabi l i t y EEPROM Read/ Wr i t e Dat a EEMNGDATA ( 0x 10114; RW)
WRI TE 16 0b
Writ e. This bit signals t he EEPROM if t he current operat ion is read or writ e.
0b = Read.
1b = Writ e.
EEBUSY 17 0b
EPROM Busy. This bit indicat es t hat t he EEPROM is busy processing an EEPROM
t ransact ion and should not be accessed.
DONE 31 1b
Transact ion Done. This bit is cleared aft er t he St art bit and Writ e bit are set by
manageabilit y and is set back again when t he EEPROM writ e or read t ransact ion
complet es.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
WRDATA 15: 0 0x0 Writ e Dat a. Dat a t o be writ t en t o t he EEPROM.
RDDATA 31: 16 X
Read Dat a. Dat a ret urned from t he EEPROM read.
Not e: This field is read only.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

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8.2.3. 2.6 Manageabi l i t y Fl ash Cont r ol Regi st er FLMNGCTL ( 0x 10118; RW)
8.2.3. 2.7 Manageabi l i t y Fl ash Read Dat a FLMNGDATA ( 0x 1011C; RW)
8.2.3. 2.8 Fl ash Opcode Regi st er FLOP ( 0x 01013C; RW)
This regist er enables t he host or firmware t o define t he opcode used in order t o erase a sect or of t he
Flash or erase t he ent ire Flash. This regist er is reset only at power on or during LAN_PWR_GOOD
assert ion.
Not e: The default values are applicable t o At mel* Serial Flash Memory devices.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
ADDR 23: 0 0x0
Address. This field is writ t en by manageabilit y along wit h CMD and CMDV t o indicat e
which Flash address t o read or writ e.
CMD 25: 24 00b
Command. I ndicat es which command should be execut ed. Valid only when t he CMDV
bit is set .
00b = Read command.
01b = Writ e command ( single byt e) .
10b = Sect or erase. Not e: Sect or erase is applicable only for At mel Flashes.
11b = Erase.
CMDV 26 0b
Command Valid. When set , indicat es t hat t he manageabilit y firmware issues a new
command and is cleared by hardware at t he end of t he command.
FLBUSY 27 0b
Flash Busy. This bit indicat es t hat t he Flash is busy processing a Flash t ransact ion and
should not be accessed.
DONE 30 1b
Read Done. This bit is cleared by firmware when it set s t he CMDV bit . I t is set by
hardware for each Dword read t hat complet es. This bit is read/ clear by hardware
enabling t he mult iple Dword read flow.
WRDONE 31 1b
Global Done. This bit clears aft er t he CMDV bit is set by manageabilit y and is set back
again aft er all Flash t ransact ions complet e. For example, t he Flash device finished
reading all t he request ed read or ot her accesses ( writ e and erase) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
DATA 31: 0 0x0
Read/ Writ e Dat a
On a read t ransact ion, t his regist er cont ains t he dat a ret urned from t he Flash read.
On writ e t ransact ions, bit s 7: 0 are writ t en t o t he Flash.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SERASE 7: 0 0x52
Flash Block Erase I nst ruct ion
The opcode for t he Flash block erase inst ruct ion and is relevant only t o Flash access by
manageabilit y.
DERASE 15: 8 0x62
Flash Device Erase I nst ruct ion
The opcode for t he Flash erase inst ruct ion.

465
8. 2.3. 2.9 Gener al Recei ve Cont r ol GRC ( 0x 10200; RW)
8.2.3.3 Fl ow Cont r ol Regi st er s
8. 2.3. 3.1 Pr i or i t y Fl ow Cont r ol Ty pe Opcode PFCTOP ( 0x 0431C / 0x 03008; RW)
This regist er is also mapped t o address 0x0431C t o maint ain compat ibilit y wit h t he 82598.
This regist er cont ains t he Type and Opcode fields t hat are mat ched against a recognized priorit y flow
cont rol packet .
8.2.3.3.2 Fl ow Cont r ol Tr ansmi t Ti mer Val ue n FCTTVn ( 0x 03200 + 4* n, n= 0...3; RW)
Each 32- bit regist er ( n= 03) refers t o t wo t imer values ( regist er 0 refers t o t imer 0 and 1, regist er 1
refers t o t imer 2 and 3, et c. ) .
The 16- bit value in t he TTV field is insert ed int o a t ransmit t ed frame ( eit her XOFF frames or any pause
frame value in any soft ware t ransmit t ed packet s) . I t count s in unit s of slot t ime ( usually 64 byt es) .
Not e: The 82599 uses a fixed slot t ime value of 64 byt e t imes.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MNG_EN 0 1b
1
1. Loaded from t he EEPROM.
Manageabilit y Enable
This read- only bit indicat es whet her or not manageabilit y funct ionalit y is enabled.
APME 1 0b
1
Advance Power Management Enable
I f set t o 1b, APM wake up is enabled. When APM wake up is enabled and The 82599
receives a mat ching magic packet , it set s t he PME_St at us bit in t he Power Management
Cont rol/ St at us regist er ( PMCSR) and assert s t he PE_WAKE_N pin. I t is a single read/
writ e bit in a single regist er, but has t wo values depending on t he funct ion t hat accesses
t he r egist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FCT 15: 0 0x8808
Priorit y Flow Cont rol Et herType.
Not e: This field appears in lit t le endian ( MS byt e first on t he wire) .
FCOP 31: 16 0x0101
Priorit y Flow Cont rol Opcode.
Not e: This field appears in big endian ( LS byt e first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TTV( 2n) 15: 0 0x0
Transmit Timer Value 2n
Timer value included in XOFF frames as Timer ( 2n) . The same value shall be set t o User
Priorit ies at t ached t o t he same TC, as defined in RTTUP2TC regist er. For legacy 802. 3X
flow cont rol packet s, TTV0 is t he only t imer t hat is used.
TTV( 2n+ 1) 31: 16 0x0
Transmit Timer Value 2n+ 1
Timer value included in XOFF frames as Timer 2n+ 1. The same value shall be set t o
User Priorit ies at t ached t o t he same TC, as defined in RTTUP2TC regist er.
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466
8.2.3. 3.3 Fl ow Cont r ol Recei ve Thr eshol d Low FCRTL[ n] ( 0x 03220 + 4* n, n= 0...7; RW)
Each 32- bit regist er ( n= 07) refers t o a different receive packet buffer.
This regist er cont ains t he receive t hreshold used t o det ermine when t o send an XON packet and count s
in unit s of byt es. The lower four bit s must be programmed t o 0x0 ( 16- byt e granularit y) . Soft ware must
set XONE t o enable t he t ransmission of XON frames. Each t ime incoming packet s cross t he receive high
t hreshold ( become more full) , and t hen crosses t he receive low t hreshold, wit h XONE enabled ( 1b) ,
hardware t ransmit s an XON frame.
8.2.3. 3.4 Fl ow Cont r ol Recei ve Thr eshol d Hi gh FCRTH[ n] ( 0x 03260 + 4* n, n= 0...7;
RW)
Each 32- bit regist er ( n= 07) refers t o a different receive packet buffer.
This regist er cont ains t he receive t hreshold used t o det ermine when t o send an XOFF packet and count s
in unit s of byt es. This value must be at least eight byt es less t han t he maximum number of byt es
allocat ed t o t he receive packet buffer and t he lower four bit s must be programmed t o 0x0 ( 16- byt e
granularit y) . Each t ime t he receive FI FO reaches t he fullness indicat ed by RTH, hardware t ransmit s a
pause frame if t he t ransmission of flow cont rol frames is enabled.
8.2.3. 3.5 Fl ow Cont r ol Ref r esh Thr eshol d Val ue FCRTV ( 0x 032A0; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RTL 18: 5 0x0
Receive Threshold Low n. Receive packet buffer n FI FO low wat er mark for flow cont rol
t ransmission ( 32 byt es granularit y) .
XONE 31 0b
XON Enable n. Per t he receive packet buffer XON enable.
0b = Disabled.
1b = Enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RTH 18: 5 0x0
Receive Threshold High n. Receive packet buffer n FI FO high wat er mark for flow cont rol
t ransmission ( 32 byt es granularit y) .
FCEN 31 0b Transmit flow cont rol enable for packet buffer n.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FC_refresh_t h 15: 0 0x0
Flow Cont rol Refresh Threshold. This value is used t o calculat e t he act ual refresh period
for sending t he next pause frame if condit ions for a pause st at e are st ill valid ( buffer
fullness above low t hreshold value) . The formula for t he refresh period for priorit y group
N is FCTTV[ N/ 2] . TTV[ Nmod2] FCRTV. FC_refresh_t h
Not e: The FC_refresh_t h must be smaller t han TTV of t he TC and larger t han t he max
packet size in t he TC + FC packet size + link lat ency and Tx lat ency and Rx lat ency in 64
byt e unit s.

467
8.2.3.3.6 Tr ansmi t Fl ow Cont r ol St at us TFCS ( 0x 0CE00; RO)
8.2.3.3.7 Fl ow Cont r ol Conf i gur at i on FCCFG ( 0x 03D00; RW)
8.2.3.4 PCI e Regi st er s
8. 2.3. 4.1 PCI e Cont r ol Regi st er GCR ( 0x 11000; RW)
Not e: This regist er is shared for bot h LAN port s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TC_XON 7: 0 0xFF
Set if flow cont rol is in XON st at e. I f in link flow cont rol mode, only bit 0 should be used.
I n case of priorit y flow cont rol mode, each bit represent s a TC.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TFCE 4: 3 0x0
Transmit Flow Cont rol Enable. These bit s I ndicat e t hat t he 82599 t ransmit s flow cont rol
packet s ( XON/ XOFF frames) based on receive fullness. I f aut o- negot iat ion is enabled,
t hen t his bit should be set by soft ware t o t he negot iat ed flow cont rol value.
00b = Transmit flow cont rol disabled.
01b = Link flow cont rol enabled.
10b = Priorit y flow cont rol enabled.
11b = Reserved.
Not e: Priorit y flow cont rol should be enabled in DCB mode only.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 8: 3 X Reserved
Complet ion Timeout
resend enable
9 1b
When set , enables a resend request aft er t he complet ion t imeout expires. This field is
loaded from t he Complet ion Timeout Resend bit in t he EEPROM ( PCI e General Config
word 5 bit 15) .
Reserved 10 0b Reserved
Number of resends 12: 11 11b The number of resends in case of t imeout or poisoned.
PCI e Capabilit y
Version
18 1b
1
Read only field report ing support ed PCI e capabilit y version.
0b = Capabilit y version: 0x1.
1b = Capabilit y version: 0x2.
hdr_log inversion 21 0b
I f set , t he header log in error report ing is writ t en as 31: 0 t o log1, 63: 32 in log2, et c. I f
not , t he header is writ t en as 127: 96 in log1, 95: 64 in log 2, et c.
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468
8.2.3. 4.2 PCI e St at i st i c Cont r ol Regi st er # 1 GSCL_1 ( 0x 11010; RW)
8.2.3. 4.3 PCI e St at i st i c Cont r ol Regi st er s # 2- GSCL_2 ( 0x 11014; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GI O_COUNT_EN_0 0 0b Enables PCI e st at ist ic count er number 0.
LBC Enable 0 4 0b
When set , st at ist ics count er 0 operat es in leaky bucket mode. I n t his mode t here is an
int ernal count er t hat is increment ed by one for each event and is decrement ed by one
each t ime t he LBC t imer n ( n= 0) expires. When t he int ernal count er reaches t he value
of LBC t hreshold n ( n= 0) t he int ernal count er is cleared and t he visible associat ed
st at ist ic count er GSCN_0_3[ 0] is increment ed by one.
When cleared, Leaky Bucket mode is disabled and t he count er is increment ed by one
for each event .
LBC Enable 1 5 0b
When set , st at ist ics count er 1 operat es in leaky bucket mode. See det ailed descript ion
for LBC Enable 0.
LBC Enable 2 6 0b
for LBC Enable 0.
LBC Enable 3 7 0b
for LBC Enable 0.
GI O_COUNT_TEST 27 0b
Test Bit
Forward count ers for t est abilit y.
GI O_64_BI T_EN 28 0b Enables t wo 64- bit count ers inst ead of four 32- bit count ers.
GI O_COUNT_RESET 29 0b Reset indicat ion of PCI e st at ist ic count ers.
GI O_COUNT_STOP 30 0b St op indicat ion of PCI e st at ist ic count ers.
GI O_COUNT_START 31 0b St art indicat ion of PCI e st at ist ic count ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GI O_EVENT_NUM_0 7: 0 0x0 Event number t hat count er 0 count s ( GSCN_0) .

469
8.2.3.4.4 PCI e St at i st i c Cont r ol Regi st er # 5...# 8 GSCL_5_8 ( 0x 011030 + 4* n, n= 0... 3;
RW)
Not e: These regist ers are shared for bot h LAN port s.
These regist ers cont rol t he operat ion of t he leaky bucket count er n. While it is GSCL_5 for n= 0. GSCL_6
for n= 1, GSCL_7 for n= 2 and GSCL_8 for n= 3. Not e t hat t here are no GSCL_3 and GSCL_4 regist ers.
Tabl e 8. 4. PCI e St at i st i c Ev ent s Encodi ng
Tr ansact i on l ay er Ev ent s
Ev ent
Mappi ng
( Hex )
Descr i pt i on
Bad TLP from LL 00
For each cycle, t he count er increases by one, if a bad TLP is received ( bad
CRC, error report ed by AL, misplaced special charact er, reset in t hI of
received t lp) .
Request s t hat reached t imeout 10 Number of request s t hat reached t ime out .
NACK DLLP received 20
For each cycle, t he count er increases by one, if a message was
t ransmit t ed.
Replay happened in ret ry buffer 21
Occurs when a replay happened due t o t imeout ( not assert ed when replay
init iat ed due t o NACK.
Receive error 22
Set when one of t he following occurs:
1. Decoder error occurred during t raining in t he PHY. I t is report ed only
when t raining ends.
2. Decoder error occurred during linkup or unt il t he end of t he current
packet ( in case t he link failed) . This error is masked when ent ering/ exit ing
Elect rical I dle ( EI ) .
Replay roll over 23
Occurs when replay was init iat ed for more t han t hree t imes ( t hreshold is
configurable by t he PHY CSRs) .
Re- sending packet s 24 Occurs when TLP is resent in case of complet ion t imeout .
Surprise link down 25 Occurs when link is unpredict ably down ( not because of reset or DFT) .
LTSSM in L0s in bot h Rx and Tx 30 Occurs when LTSSM ent ers L0s st at e in bot h Tx & Rx.
LTSSM in L0s in Rx 31 Occurs when LTSSM ent ers L0s st at e in Rx.
LTSSM in L0s in Tx 32 Occurs when LTSSM ent ers L0s st at e in Tx.
LTSSM in L1 act ive 33 Occurs when LTSSM ent ers L1- act ive st at e ( request ed from host side) .
LTSSM in L1 soft ware 34 Occurs when LTSSM ent ers L1- swit ch ( request ed from swit ch side) .
LTSSM in recovery 35 Occurs when LTSSM ent ers recovery st at e.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LBC t hreshold n 15: 0 0x0 Threshold for t he leaky bucket count er n.
LBC t imer n 31: 16 0x0
Time period bet ween decrement ing t he value in leaky bucket Count er n. The t ime
period is defined in s unit s.
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470
8.2.3. 4.5 PCI e St at i st i c Count er Regi st er s # 0...# 3 GSCN_0_3 ( 0x 11020 + 4* n, n= 0...3;
RO)
While it is GSCN_0 for n= 0. GSCN_1 for n= 1, GSCN_2 for n= 2 and GSCN_3 for n= 3.
8.2.3. 4.6 Funct i on Act i ve and Pow er St at e t o Manageabi l i t y FACTPS ( 0x 10150; RO)
Regist er for use by t he device firmware for configurat ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Event Count er 31: 0 0x0
Event count er as defined in GSCL_2. GI O_EVENT_NUM fields. These regist ers are st uck
at t heir maximum value of 0xFF. . . F and cleared on read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Func0 Power St at e 1: 0 00b
Power st at e indicat ion of funct ion 0.
00b = DR.
01b = D0u.
10b = D0a.
11b = D3.
LAN0 Valid 2 0b
LAN 0 Enable. When t his bit is set t o 0b, it indicat es t hat t he LAN 0 funct ion is disabled.
When t he funct ion is enabled, t he bit is set t o 1b.
This bit is reflect ed if t he funct ion is disabled t hrough t he ext ernal pad.
Func0 Aux_En 3 0b Funct ion 0 Auxiliary ( AUX) Power PM Enable bit shadow from t he configurat ion space.
Func1 Power St at e 7: 6 00b
Power st at e indicat ion of funct ion 1.
00b = DR.
01b = D0u.
10b = D0a.
11b = D3.
LAN1 Valid 8 0b
LAN 1 Enable. When t his bit is set t o 0b, it indicat es t hat t he LAN 1 funct ion is disabled.
When t he funct ion is enabled, t he bit is set t o 1b.
This bit is reflect ed if t he funct ion is disabled t hrough t he ext ernal pad.
Func1 Aux_En 9 0b Funct ion 1 Auxiliary ( AUX) Power PM Enable bit shadow from t he configurat ion space.
MNGCG 29 0b
Manageabilit y Clock Gat ed.
When set , indicat es t hat t he manageabilit y clock is gat ed.
LAN Funct ion Sel 30 0b
1
1. Loaded from t he EEPROM.
When bot h LAN port s are enabled and LAN Funct ion Sel equals 0b, LAN 0 is rout ed t o
PCI funct ion 0 and LAN 1 is rout ed t o PCI funct ion 1. I f LAN Funct ion Sel equals 1b, LAN
0 is rout ed t o PCI funct ion 1 and LAN 1 is rout ed t o PCI funct ion 0. This bit is loaded
from t he LAN Funct ion Select bit in t he PCI e Cont rol 2 EEPROM word at offset 0x05.
PM St at e changed 31 0b
I ndicat ion t hat one or more of t he funct ions power st at es had changed. This bit is also
a signal t o t he manageabilit y unit t o creat e an int errupt .
This bit is cleared on read, and is not set for at least eight cycles aft er it was cleared.

471
8.2.3.4.7 PCI e Anal og Conf i gur at i on Regi st er PCI EPHYADR ( 0x 11040; RW)
8. 2.3. 4.8 PCI e PHY Dat a Regi st er PCI EPHYDAT ( 0x 11044; RW)
8. 2.3. 4.9 Sof t w ar e Semaphor e Regi st er SWSM ( 0x 10140; RW)
8. 2.3. 4.10 Fi r mw ar e Semaphor e Regi st er FWSM ( 0x 10148; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Address 11: 0 0x0 The indirect access' address.
Byt e Enable 28: 25 0x0 The indirect access' byt e enable ( 4- bit ) .
Read enable 29 0b The indirect access is read t ransact ion.
Writ e enable 30 0b The indirect access is writ e t ransact ion.
Done indicat ion 31 0b Acknowledge for t he indirect access t o t he CSR.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Dat a 31: 0 0x0 The dat a t o writ e in t he indirect access or t he ret urned dat a of t he indirect read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SMBI 0 0b
Semaphore Bit . This bit is set by hardware, when t his regist er is read by t he device
driver ( one of t wo PCI funct ions) and cleared when t he host driver writ es 0b t o it .
The first t ime t his regist er is read, t he value is 0b. I n t he next read t he value is 1b
( hardware mechanism) . The value remains 1b unt il t he device driver clears it .
This bit can be used as a semaphore bet ween t he t wo devices drivers.
This bit is cleared on PCI e reset .
SWESMBI 1 0b
Soft ware Semaphore bit . This bit is set by t he device driver ( read only t o t he firmware)
before accessing t he SW_FW_SYNC regist er. This bit can be read as 1b only if t he
FWSM. FWSMBI bit is cleared.
The device driver should clear t his bit aft er accessing t he SW_FW_SYNC regist er as
described in Sect ion 10. 5. 4. Hardware clears t his bit on PCI e reset .
RSV 31: 2 0x0 Reserved.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FWSMBI 0 0b
Firmware Semaphore. Firmware should set t his bit t o 1b before accessing t he
SW_FW_SYNC regist er. This bit can be read as 1b only if t he SWSM. SMBI is cleared.
Firmware should set it back t o 0b aft er modifying t he SW_FW_SYNC regist er as
described in Sect ion 10. 5. 4.
I nt el

472
Not es: This regist er should be writ t en only by t he manageabilit y firmware. The device driver should
only read t his regist er.
The firmware ignores t he EEPROM semaphore in operat ing syst em hung st at es.
Bit s 15: 0 are cleared on firmware reset .
FW_mode 3: 1 000b
Firmware Mode. I ndicat es t he firmware mode as follows:
0x0 = None ( manageabilit y off ) .
0x1 = Reserved.
0x2 = PT mode.
0x3 = Reserved.
0x4 = Host int erface enable only.
Else = Reserved.
EEP_reload_ ind 6 0b
EEPROM Reloaded I ndicat ion. Set t o 1b aft er firmware reloads t he EEPROM.
Cleared by firmware once t he Clear Bit host command is received from host soft ware.
FW_Val_bit 15 0b
Firmware Valid Bit . Hardware clears t his bit in reset deassert ion so soft ware can know
firmware mode ( bit s 1- 5) is invalid. firmware should set t his bit t o 1b when it is ready
( end of boot sequence) .
Reset _cnt 18: 16 000b Reset Count er. Firmware increment s t his count er aft er every reset .
Ext _err_ind 24: 19 0x0
Ext ernal Error I ndicat ion. Firmware uses t his regist er t o st ore t he reason t hat t he
firmware has reset / clock gat ed ( such as EEPROM, Flash, pat ch corrupt ion, et c. ) .
Possible values:
0x00 = No error.
0x01 = I nvalid EEPROM checksum.
0x02 = Unlocked secured EEPROM.
0x03 = Clock off host command.
0x04 = I nvalid Flash checksum.
0x05 = C0 checksum failed.
0x09 = TLB t able exceeded.
0x0A = DMA load failed.
0x0B = Bad hardware version in pat ch load.
0x0C = Flash device not support ed in t he 82599.
0x0D = Unspecified error.
0x3F = Reserved ( maximum error value) .
PCI e_config_ err_ind 25 0b
PCI e Configurat ion Error I ndicat ion. Set t o 1b by firmware when it fails t o configure
PCI e int er face.
Cleared by firmware upon successful configurat ion of PCI e int erface.
PHY_SERDES0_config
_ err_ind
26 0b
PHY/ SERDES0 Configurat ion Error I ndicat ion. Set t o 1b by firmware when it fails t o
configure PHY/ SERDES of LAN0.
Cleared by firmware upon successful configurat ion of PHY/ SERDES of LAN0.
PHY_SERDES1_config
_ err_ind
27 0b
PHY/ SERDES1 Configurat ion Error I ndicat ion. Set t o 1b by firmware when it fails t o
configure PHY/ SERDES of LAN1.
Cleared by firmware upon successful configurat ion of PHY/ SERDES of LAN1.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

473
8.2.3.4.11 Sof t w ar eFi r mw ar e Sy nchr oni zat i on SW_FW_SYNC ( 0x 10160; RW)
See Sect ion 10.5.4 for more det ails on soft ware and firmware synchronizat ion.
8.2.3.4.12 PCI e Cont r ol Ex t ended Regi st er GCR_EXT ( 0x 11050; RW)
8.2.3.4.13 Mi r r or ed Revi si on I D- MREVI D ( 0x 11064; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SMBI TS 9: 0 0x0
Semaphore Bit s. Each bit represent s a different soft ware semaphore agreed bet ween
soft ware and firmware as list ed. Bit s 4: 0 are owned by soft ware while bit s 9: 5 are
owned by firmware. Not e t hat hardware does not lock access t o t hese bit s.
Bit 0 = SW_EEP_SM - at 1b, EEPROM access is owned by soft ware.
Bit 1 = SW_PHY_SM0 - at 1b, PHY 0 access is owned by soft ware.
Bit 2 = SW_PHY_SM1 - at 1b, PHY 1 access is owned by soft ware.
Bit 3 = SW_MAC_CSR_SM - at 1b, Soft ware owns access t o shared CSRs.
Bit 4 = SW_FLASH_SM - Soft ware Flash semaphore.
Bit 5 = FW_EEP_SM - at 1b, EEPROM access is owned by firmware.
Bit 6 = FW_PHY_SM0 - at 1b, PHY 0 access is owned by firmware.
Bit 7 = FW_PHY_SM1 - at 1b, PHY 1 access is owned by firmware.
Bit 8 = FW_MAC_CSR_SM - at 1b, firmware owns access t o shared CSRs.
Bit 9 = FW_FLASH_SM - at 1b, firmware owns access t o t he Flash. Not e t hat current ly
t he FW does not access t he FLASH.
Reserved 30: 10 0x0 Reserved for fut ure use.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VT_Mode 1: 0 00b
VT mode of operat ion defines t he allocat ion of physical regist ers t o t he VFs. Soft ware
must set t his field t he same as GPI E. VT_Mode.
00b = No VT - Reserved for t he case t hat STSTUS. I OV Ena is not set .
01b = VT16 - Resources are allocat ed t o 16 VFs.
APBACD 4 0b
Aut o PBA Clear Disable. When set t o 1b, Soft ware can clear t he PBA only by direct writ e
t o clear access t o t he PBA bit . When set t o 0b, any act ive PBA ent ry is cleared on t he
falling edge of t he appropriat e int errupt request t o t he PCI e block. The appropriat e
int errupt request is cleared when soft ware set s t he associat ed int errupt mask bit in t he
EI MS ( re- enabling t he int errupt ) or by direct writ e t o clear t o t he PBA.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EEPROM_RevI D 7: 0 0x0 Mirroring of rev I D loaded from EEPROM.
DEFAULT_RevI D 15: 8 0x0 Mirroring of default rev I D, before EEPROM load ( 0x0 for t he 82599 A0) .
I nt el

474
8.2. 3. 4.14 PCI e I nt er r upt Cause PI CAUSE ( 0x 110B0; RW1/ C)
8.2.3. 4.15 PCI e I nt er r upt Enabl e PI ENA ( 0x 110B8; RW)
8. 2.3. 5 I nt er r upt Regi st er s
8.2.3. 5.1 Ex t ended I nt er r upt Cause Regi st er - EI CR ( 0x 00800; RW1C)
The EI CR regist er is RW1C and can be opt ionally cleared on a read depending on t he ODC flag set t ing in
t he GPI E regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CA 0 0b PCI complet ion abort except ion.
UA 1 0b Unsupport ed I / O address except ion.
BE 2 0b Wrong byt e- enable except ion in t he FUNC unit .
TO 3 0b PCI t imeout except ion in t he FUNC unit .
BMEF 4 0b Assert ed when bus mast er enable of t he PF or one of t he VFs is deassert ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CA 0 0b When set t o 1b, t he PCI complet ion abort int errupt is enabled.
UA 1 0b When set t o 1b, t he unsupport ed I / O address int errupt is enabled.
BE 2 0b When set t o 1b, t he wrong byt e- enable int errupt is enabled.
TO 3 0b When set t o 1b, t he PCI t imeout int errupt is enabled.
BMEF 4 0b When set t o 1b, t he bus mast er enable int errupt is enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RTxQ 15: 0 0x0
Receive/ Transmit Queue I nt errupt s. One bit per queue or a bundle of queues, act ivat ed
on receive/ t ransmit event s.
The mapping of t he queue t o t he RTxQ bit s is done by t he I VAR regist ers.
Flow Direct or 16 0b
Flow direct or except ion is act ivat ed by one of t he following event s:
1. Filt er Removal failed ( no mat ched filt er t o be removed) .
2. The number of remaining free filt ers in t he flexible filt er t able exceeds ( goes
below) t he FDI RCTRL. Full-Thresh.
3. Filt er Programming failed due t o no space in t he Flow Direct or t able ( not e t hat t his
case should not happen if t he driver handles t he FDI RCTRL. Full-Thresh event )
Rx Miss 17 0b
Missed packet int errupt is act ivat ed for each received packet t hat overflows t he Rx
packet buffer ( overrun) . Not e t hat t he packet is dropped and also increment s t he
associat ed RXMPC[ n] count er.
PCI Except ion 18 0b
The PCI t imeout except ion is act ivat ed by one of t he following event s while t he specific
PCI event is r epor t ed in t he I NTRPT_CSR regist er:
1. I / O complet ion abort ( writ e t o Flash when Flash is writ e- disabled) .
2. Unsupport ed I / O request ( wrong address) .
3. Byt e- Enable Error. Access t o a client t hat does not support part ial byt e- enable
access ( all but Flash, MSI -X and PCI e t arget ) .
4. Timeout occurred in t he FUNC block.
MailBox 19 0b VF t o PF MailBox I nt errupt . Cause by a VF writ e access t o t he PF mailbox.

475
8.2.3.5.2 Ex t ended I nt er r upt Cause Set Regi st er - EI CS ( 0x 00808; WO)
8. 2.3. 5.3 Ex t ended I nt er r upt Mask Set / Read Regi st er - EI MS ( 0x 00880; RWS)
8. 2.3. 5.4 Ex t ended I nt er r upt Mask Cl ear Regi st er - EI MC ( 0x 00888; WO)
LSC 20 0b
Link St at us Change. This bit is set each t ime t he link st at us changes ( eit her from up t o
down, or from down t o up) .
LinkSec 21 0b
I ndicat es t hat t he Tx LinkSec packet count er reached t he t hreshold requiring key
exchange.
MNG 22 0b
Manageabilit y Event Det ect ed. I ndicat es t hat a manageabilit y event happened. When
t he device is at power down mode, t he MC might generat e a PME for t he same event s
t hat would cause an int errupt when t he device is at t he D0 st at e.
GPI _SDP0 24 0b
General Purpose I nt errupt on SDP0. I f GPI int errupt det ect ion is enabled on t his pin
( via GPI E) , t his int errupt cause is set when t he SDP0 is sampled high.
GPI _SDP1 25 0b
GPI _SDP2 26 0b
GPI _SDP3 27 0b
ECC 28 0b
Unrecoverable ECC Error. This bit is set when an unrecoverable error is det ect ed in one
of t he device memories. Soft ware should issue a soft ware reset following t his error.
TCP Timer 30 0b TCP Timer Expired. This bit is set when t he t imer expires.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt errupt Cause Set 30: 0 0x0
Set t ing any bit in t his field, set s it s corresponding bit in t he EI CR regist er and generat es
an int errupt if enabled by t he EI MS regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt errupt Enable 30: 0 0x0
Each bit set t o 1b enables it s corresponding int errupt in t he EI CR. Writ ing 1b t o any bit
set s it . Writ ing 0b has no impact . Reading t his regist er provides a map of t hose
int errupt s t hat are enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt errupt Mask 30: 0 0x0
Writ ing a 1b t o any bit clears it s corresponding bit in t he EI MS regist er disabling t he
corresponding int errupt in t he EI CR regist er. Writ ing 0b has no impact . Reading t his
regist er provides no meaningful dat a.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

476
8.2.3. 5.5 Ex t ended I nt er r upt Aut o Cl ear Regi st er EI AC ( 0x 00810; RW)
Not e: Bit s 29: 20 should never set aut o clear since t hey share t he same MSI -X vect or.
8.2.3. 5.6 Ex t ended I nt er r upt Aut o Mask Enabl e Regi st er EI AM ( 0x 00890; RW)
8.2.3. 5.7 Ex t ended I nt er r upt Cause Set Regi st er s EI CS[ n] ( 0x 00A90 + 4* ( n- 1) ,
n= 1...2; WO)
8.2.3. 5.8 Ex t ended I nt er r upt Mask Set / Read Regi st er s EI MS[ n] ( 0x 00AA0 + 4* ( n- 1) ,
n= 1...2; RWS)
8.2.3. 5.9 Ex t ended I nt er r upt Mask Cl ear Regi st er s EI MC[ n] ( 0x 00AB0 + 4* ( n- 1) ,
n= 1...2; WO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RTxQ Aut o Clear 15: 0 0x0
At 1b, each bit enables aut o clear of t he corresponding RTxQ bit s in t he EI CR regist er
following int errupt assert ion. At 0b, t he corresponding bit s in t he EI CR regist er are not
aut o cleared.
TCP Timer Aut o Clear 30 0b
At 1b, t his bit enables aut o clear of t he TCP t imer int errupt cause in t he EI CR regist er
following int errupt assert ion. At 0b aut o clear is not enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Aut o Mask 30: 0 0x0
At 1b, each bit enables aut o set and clear of it s corresponding bit s in t he EI MS regist er.
Not e t hat Not e t hat in MSI -X mode, if any of t he Aut o Mask enable bit s is set , t he
GPI E. EI AME bit must be set as well.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt errupt Cause Set 31: 0 0x0
Set t ing any bit in t hese regist ers set s it s corresponding bit in t he EI CR[ n] regist er and
generat es an int errupt if enabled by EI MS[ n] regist er.
Reading t his regist er provides no meaningful dat a.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt errupt Enable 31: 0 0
Each bit set at 1b enables it s corresponding int errupt in t he EI CR[ n] regist er. Writ ing 1b
t o any bit set s it . Writ ing 0b has no impact . Reading t his regist er provides a map of
t hose int errupt s t hat are enabled.
Bit s 15: 0 of EI MS1 are mirrored in EI MS bit s 15: 0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt errupt Mask 31: 0 0x0
Writ ing a 1b t o any bit clears it s corresponding bit in t he EI MS[ n] regist er disabling t he
corresponding int errupt in t he EI CR[ n] regist er. Writ ing 0b has no impact . Reading t his
regist er provides no meaningful dat a.

477
8.2.3.5.10 Ex t ended I nt er r upt Aut o Mask Enabl e r egi st er s EI AM[ n] ( 0x 00AD0 + 4* ( n-
1) , n= 1...2; RW)
8.2.3.5.11 MSI X t o EI TR Sel ect EI TRSEL ( 0x 00894; RW)
8. 2.3. 5.12 Ex t ended I nt er r upt Thr ot t l e Regi st er s EI TR[ n] ( 0x 00820 + 4* n, n= 0.. .23 and
0x 012300 + 4* ( n- 24) , n= 24...128; RW)
Mapping of t he EI TR regist ers t o t he MSI -X vect ors is described in Sect ion 7. 3.4.3. 3.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Aut o Mask 31: 0 0x0
At 1b, each bit enables aut o set and clear of it s corresponding bit s in t he EI MS[ n]
regist er. Bit s 15: 0 of EI AM1 are mirrored in EI AM bit s 15: 0.
Not e t hat Not e t hat in MSI -X mode, if any of t he Aut o Mask enable bit s is set , t he
GPI E. EI AME bit must be set as well.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VFSelect 31: 0 0x0
Each bit n in t his regist er select s t he VF index ( 32+ n) or PF int errupt source for t he
EI TR regist ers ( VF 0- 31 are not mult iplexed as described in Sect ion 7. 3. 4. 3. 3) . At 0b, it
select s t he PF and at 1b it select s t he VF.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I TR I nt erval 11: 3 0x0
Minimum int er- int errupt int erval specified in 2 s unit s at 1 Gb/ 2 and 10 Gb/ s link. At
100 Mb/ s link, t he int erval is specified in 20 s unit s.
At 0x0 int errupt t hrot t ling is disabled while any event causes an immediat e int errupt .
LLI Moderat ion 15 0b
When set , LLI moderat ion is enabled. Ot herwise, any LLI packet generat es an
immediat e int errupt .
LLI moderat ion might be set only if int errupt t hrot t ling is enabled by t he I TR I nt erval
field in t his regist er and LLI moderat ion is enabled by t he LL I nt erval field in t he GPI E
regist er.
LLI Credit 20: 16 0x0
Reflect s t he current credit s for associat ed int errupt . When CNT_WDI S is not set on a
writ e cycle, t his field must be set t o 0x0.
I TR Count er 27: 21 0x0
This field represent s t he seven MS bit s ( out of nine bit s) of t he I TR count er. I t is a down
count er t hat is loaded wit h an I TR int erval value each t ime t he associat ed int errupt is
assert ed. When t he I TR count er reaches zero it st ops count ing and t riggers an
int errupt .
On a writ e cycle, soft ware must set t his field t o 0 if CNT_WDI S in t his regist er is cleared
( writ e enable t o t he I TR count er) .
CNT_WDI S 31 0b
Writ e disable t o t he LLI credit and I TR count er. When set , t he LLI credit and I TR count er
are not overwrit t en by t he writ e access. When cleared, soft ware must set t he LLI credit
and I TR count er t o zero, which enables an immediat e int errupt on packet recept ion.
This bit is writ e only. Always read as 0b.
I nt el

478
8.2.3. 5.13 L3 L4 Tupl es I mmedi at e I nt er r upt Rx L34TI MI R[ n] ( 0x 0E800 + 4* n,
n= 0...127; RW)
This regist er must be init ialized by soft ware.
8.2.3. 5.14 LLI Si ze Thr eshol d LLI THRESH ( 0x 0EC90; RW)
8.2.3. 5.15 I mmedi at e I nt er r upt Rx VLAN Pr i or i t y Regi st er - I MI RVP ( 0x 0EC60 / 0x 05AC0;
RW)
I MI RVP is also mapped t o address 0x05AC0 t o maint ain compat ibilit y wit h t he 82598.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Size_BP 12 X
Size Bypass. When 1b, t he size check is bypassed.
When0b, t he size check is performed.
Reserved 19: 13 X Reserved. Must be set t o 1000000b on any programmed filt er.
Low Lat ency I nt errupt 20 X
Enables issuing a LLI when t he following condit ions are met :
The 5- t uple filt er associat ed wit h t his regist er mat ches.
I f enabled by t he Size_BP bit , t he packet lengt h is smaller t han t he lengt h defined
by LLI THRESH. SizeThresh.
Rx Queue 27: 21 X I dent ifies t he Rx queue associat ed wit h t his 5- t uple filt er.
Fi el d Bi t ( s) I ni t Val . Descr i pt i on
SizeThresh 11: 0 0x000
Size Threshold. A packet wit h lengt h below t his t hreshold t hat mat ches one of t he 5-
t uple filt ers wit h an act ive Low Lat ency I nt errupt flag in t he L34TI MI R[ n] regist ers might
t rigger an LLI .
Reser ved 25: 12 0x0 Reserved
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Vlan_Pri 2: 0 000b
VLAN Priorit y. This field includes t he VLAN priorit y t hreshold. When Vlan_pri_en is set t o
1b, t hen an incoming packet wit h VLAN t ag wit h a priorit y equal or higher t o VlanPri
must t rigger a LLI , regardless of t he I TR moderat ion.
Vlan_pri_en 3 0
VLAN Priorit y Enable. When 1b, an incoming packet wit h VLAN t ag wit h a priorit y equal
or higher t o Vlan_Pri must t rigger a LLI , regardless of t he I TR moderat ion.
When 0b, t he int errupt is moderat ed by I TR.
Reserved 31: 4 Reserved

479
8.2.3.5.16 I nt er r upt Vect or Al l ocat i on Regi st er s I VAR[ n] ( 0x 00900 + 4* n, n= 0... 63;
RW)
These regist ers map int errupt causes int o EI CR ent ries ( legacy/ MSI modes) or int o MSI -X vect ors ( MSI -
X modes) . See Sect ion 7. 3. 4 for mapping and use of t hese regist ers.
Transmit and receive queues mapping t o I VAR regist ers is shown in Figure 8.1:
Fi gur e 8.1. Tr ansmi t and Recei ve Queues Mappi ng t o I VAR Regi st er s
Fields of t he I VAR regist ers are described in Table 8. 5.
8.2.3.5.17 Mi scel l aneous I nt er r upt Vect or Al l ocat i on I VAR_MI SC ( 0x 00A00; RW)
These regist er maps int errupt causes int o MSI -X vect ors ( MSI -X modes) . See Sect ion 7.3. 4 for mapping
and use of t hese regist ers.
Not e: The I NT_ALLOC_VAL[ 1] bit default value is one t o enable legacy driver funct ionalit y.
Tabl e 8. 5. Fi el ds of I VAR Regi st er
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I NT_Alloc[ 0] 5: 0 X The int errupt allocat ion for Rx queue ( 2xN for I VAR regist er N) .
Reser ved 6 0b Reserved
I NT_Alloc_val[ 0] 7 0b I nt errupt allocat ion valid indicat ion for I NT_Alloc[ 0] .
I NT_Alloc[ 1] 13: 8 X The int errupt allocat ion for Tx queue ( 2xN for I VAR regist er N) .
I NT_Alloc[ 2] 21: 16 X The int errupt allocat ion for Rx queue ( 2xN+ 1 for I VAR regist er N) .
I NT_Alloc[ 3] 29: 24 X The int errupt allocat ion for Tx queue ( 2xN+ 1 for I VAR regist er N) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I NT_Alloc[ 0] 6: 0 X Defines t he MSI -X vect or assigned t o t he TCP t imer int errupt cause.
I NT_Alloc_val[ 0] 7 0b Valid bit for I NT_Alloc[ 0] .
I NT_Alloc[ 1] 14: 8 X Defines t he MSI -X vect or assigned t o t he ot her int errupt cause.
Rx 0
Tx 0
Rx 1
Tx 1
IVAR 0
Rx 2
Tx 2
Rx 3
Tx 3
IVAR 1
Rx 4
Tx 4
Rx 5
Tx 5
IVAR 2
Rx 124
Tx 124
Rx 125
Tx 125
IVAR 62
Rx 126
Tx 126
Rx 127
Tx 127
IVAR 63
. . .
I nt el

480
8.2. 3. 5.18 Gener al Pur pose I nt er r upt Enabl e GPI E ( 0x 00898; RW)
The 82599 allows for up t o four ext ernally cont rolled int errupt s. The lower four soft ware- definable pins,
SDP[ 3: 0] , can be mapped for use as GPI int errupt bit s. These mappings are enabled by t he
SDPx_GPI EN bit s only when t hese signals are also configured as input s via SDPx_I ODI R. When
configured t o funct ion as ext ernal int errupt pins, a GPI int errupt is generat ed when t he corresponding
pin is sampled in an act ive- high st at e.
The bit mappings are list ed in Table 8.6 for clarit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SDP0_GPI EN 0 0b
General Purpose I nt errupt Det ect ion Enable for SDP0. I f soft ware- cont rollable I / O pin
SDP0 is configured as an input , t his bit ( when 1b) enables use for GPI int errupt
det ect ion.
SDP1_GPI EN 1 0b
det ect ion.
SDP2_GPI EN 2 0b
det ect ion.
SDP3_GPI EN 3 0b
det ect ion.
Mult iple_MSI X 4 0b
MSI -X Mode. Select s bet ween MSI -X int errupt s and ot her int errupt modes.
0b = Legacy and MSI mode ( non- MSI -X mode) .
1b = MSI -X mode.
OCD 5 0b
Ot her Clear Disable. When set , indicat es t hat only bit s 29: 16 of t he EI CR regist er are
cleared on read. When cleared, t he ent ire EI CR is cleared on read.
EI MEN 6 0b
EI CS I mmediat e I nt errupt Enable. When set , set t ing t his bit in t he EI CS regist er causes
a LLI . I f not set , t he EI CS int errupt wait s for EI TR expirat ion.
LL I nt erval 10: 7 0x0
Low lat ency Credit s I ncrement Rat e. The int erval is specified in 4 s increment s at
1 Gb/ s and 10 Gb/ s link. I t is defined as 40 s at 100 Mb/ s link. A value of 0x0 disables
moderat ion of LLI for all int errupt vect ors. When LLI is disabled by t he LL I nt erval bit ,
t he LLI Moderat ion bit in all EI TR regist ers must not be set .
RSC Delay 13: 11 000b
Delay from RSC complet ion t riggered by I TR and int errupt assert ion. The delay = ( RSC
Delay + 1) x 4 s = 4, 8, 12. . . 32 s.
VT_Mode 15: 14 00b
Specify t he number of act ive VFs. Soft ware must set t his field t he same as
GCR_Ext . VT_Mode.
00b = Non- I OV mode.
10b = 32 VF mode.
01b = 16 VF mode.
11b = 64 VF mode.
EI AME 30 0b
Ext ended I nt errupt Aut o Mask Enable. When set , t he EI MS regist er can be aut o- cleared
( depending on EI AM set t ing) upon int errupt assert ion. I n any case, t he EI MS regist er
can be aut o- cleared ( depending on EI AM set t ing) following a writ e- t o- clear ( or read) t o
t he EI CR regist er.
Soft ware may set t he EI AME only in MSI -X mode.
PBA_
support
31 0b
PBA Support . When set , set t ing one of t he ext ended int errupt s masks via EI MS causes
t he PBA bit of t he associat ed MSI -X vect or t o be cleared. Ot herwise, t he 82599 behaves
in a way support ing legacy I NT-x int errupt s.
Not e: Should be cleared when working in I NT-x or MSI mode and set in MSI -X mode.

481
8.2.3.6 MSI - X Tabl e Regi st er s
MSI -X capabilit y is described in sect ion Sect ion 9. 3.8. The MSI -X t able is described in Sect ion 9.3.8. 2
and t he Pending Bit Array ( PBA) is described in Sect ion 9.3.8. 3. These regist ers are locat ed in t he MSI -
X BAR.
8.2.3.6.1 MSI - X PBA Cl ear PBACL[ n] ( 0x 110C0 + 4* n, n= 0...7 / 0x 11068 [ n= 0] ; RW)
PBACL[ 0] is also mapped t o address 0x11068 t o maint ain compat ibilit y wit h t he 82598.
8.2.3.7 Recei v e Regi st er s
8. 2.3. 7.1 Fi l t er Cont r ol Regi st er FCTRL ( 0x 05080; RW)
Tabl e 8. 6. GPI - t o- SDP Bi t Mappi ngs
SDP ( pi n t o be used as GPI ) ESDP Fi el d Set t i ngs Resul t i ng EI CR Bi t ( GPI )
Di r ect i onal i t y Enabl e as GPI i nt er r upt
3 SDP3_I ODI R SDP3_GPI EN 27
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PENBI TCLR 31: 0 0x0
MSI -X Pending Bit s Clear. Writ ing 1b t o any bit clears it s cont ent ; writ ing 0b has no
effect .
Reading t his regist er ret urns t he MSI PBA. PENBI T value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SBP 1 0b
St ore Bad Packet s.
0b = Do not st ore.
1b = St ore.
Not e t hat CRC errors before t he SFD are ignored. Any packet must have a valid SFD
( RX_DV wit h no RX_ER in t he XGMI I / GMI I i/ f ) in order t o be recognized by t he device
( even bad packet s) .
Not e: Packet s wit h errors are not rout ed t o manageabilit y even if t his bit is set .
Not e: Erroneous packet s can be rout ed t o t he default queue rat her t han t he originally
int ended queue.
Not e: I n packet s short er t han 64 byt es, t he checksum errors can be hidden while MAC
errors are report ed.
Not e: A packet wit h a valid error ( caused by byt e error or illegal error) might have dat a
cont aminat ion in t he last eight byt es when st ored in t he host memory if t he St ore Bad
Packet bit is set .
MPE 8 0b
Mult icast Promiscuous Enable.
0b = Disabled.
1b = Enabled. When set , all received mult icast and broadcast packet s pass L2 filt ering
and can be direct ed t o manageabilit y or t he host by a one of t he decision filt ers.
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482
Not e: Before receive filt ers are updat ed/ modified t he RXCTRL.RXEN bit should be set t o 0b. Aft er
t he proper filt ers have been set t he RXCTRL. RXEN bit can be set t o 1b t o re- enable t he
receiver.
8.2.3. 7.2 VLAN Cont r ol Regi st er VLNCTRL ( 0x 05088; RW)
8.2.3. 7.3 Mul t i cast Cont r ol Regi st er MCSTCTRL ( 0x 05090; RW)
UPE 9 0b
Unicast Promiscuous Enable.
0b = Disabled.
1b = Enabled.
BAM 10 0b
Broadcast Accept Mode.
0b = I gnore broadcast packet s t o host .
1b = Accept broadcast packet s t o host .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VET 15: 0 0x8100
VLAN Et her Type ( t he VLAN Tag Prot ocol I dent ifier TPI D) . This regist er cont ains t he
t ype field hardware mat ches against t o recognize an 802. 1Q ( VLAN) Et hernet packet .
For proper operat ion, soft ware must not change t he default set t ing of t his field
( 802. 3ac st andard defines it as 0x8100) .
This field must be set t o t he same value as t he VT field in t he DMATXCTL regist er.
Not e: This field appears in lit t le endian order ( t he upper byt e is first on t he wire
( VLNCTRL. VET[ 15: 8] ) .
CFI 28 0b
Canonical Form I ndicat or Bit Value.
I f CFI EN is set t o 1b, t hen 802. 1q packet s wit h CFI equal t o t his field are accept ed;
ot herwise, t he 802. 1q packet is discarded.
CFI EN 29 0b
Canonical Form I ndicat or Enable.
0b = Disabled ( CFI bit not compared t o decide packet accept ance) .
1b = Enabled ( CFI from packet must mat ch next CFI field t o accept 802. 1q packet ) .
VFE 30 0b
VLAN Filt er Enable.
0b = Disabled ( filt er t able does not decide packet accept ance) .
1b = Enabled ( filt er t able decides packet accept ance for 802. 1q packet s) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MO 1: 0 00b
Mult icast Offset . This det ermines which bit s of t he incoming mult icast address are used
in looking up t he bit vect or.
00b = [ 47: 36] .
01b = [ 46: 35] .
10b = [ 45: 34] .
11b = [ 43: 32] .
MFE 2 0b
Mult icast Filt er Enable.
0b = The mult icast t able array filt er ( MTA[ n] ) is disabled.
1b = The mult icast t able array ( MTA[ n] ) is enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

483
8.2.3.7.4 Pack et Spl i t Recei v e Type Regi st er PSRTYPE[ n] ( 0x 0EA00 + 4* n, n= 0.. .63 /
0x 05480 + 4* n, n= 015; RW)
Regist ers 0.. .15 are also mapped t o 0x05480 t o maint ain compat ibilit y wit h t he 82598.
Not es:
Packet s are split according t o t he lowest - indexed ent ry t hat applies t o t he packet and t hat is
enabled. For example, if bit s 4 and 8 are set , t hen an I Pv4 packet t hat is not TCP is split aft er t he
I Pv4 header.
This bit mask t able enables or disables each t ype of header t o be split . A value of 1b enables an
ent ry.
I n virt ualizat ion mode, a separat e PSRTYPE regist er is provided per pool up t o t he number of pools
enabled. I n non-virt ualizat ion mode, only PSRTYPE[ 0] is used.
8. 2.3. 7.5 Recei ve Check sum Cont r ol RXCSUM ( 0x 05000; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PSR_t ype0 0 X Reserved
PSR_t ype1 1 X Split received NFS packet s aft er NFS header.
PSR_t ype4 4 X Split received TCP packet s aft er TCP header.
PSR_t ype5 5 X Split received UDP packet s aft er UDP header.
PSR_t ype8 8 X Split received I Pv4 packet s aft er I Pv4 header.
PSR_t ype9 9 X Split received I Pv6 packet s aft er I Pv6 header.
PSR_t ype12 12 X Split received L2 packet s aft er L2 header.
RQPL 31: 29 X
Defines t he number of bit s t o use for RSS redirect ion of packet s dedicat ed t o t his pool.
Valid values are zero, 0001b and 0010b. The default value should be 0010b, meaning
t hat up t o 4 queues can be enabled for t his pool. A value of 0001b means t hat up t o 2
queues can be enabled for t his pool.
A value of zero means t hat all t he t raffic of t he pool is sent t o queue 0 of t he pool. This
field is used only if MRQC. MRQE equals 1010b or 1011b.
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484
The Receive Checksum Cont rol regist er cont rols t he receive checksum offloading feat ures of t he 82599.
The 82599 support s t he offloading of t hree receive checksum calculat ions: t he fragment checksum, t he
I P header checksum, and t he TCP/ UDP checksum.
PCSD: The Fragment Checksum and I P I dent ificat ion fields are mut ually exclusive wit h t he RSS hash.
Only one of t he t wo opt ions is report ed in t he Rx descript or. The RXCSUM.PCSD affect is shown in
Table 8. 7.
I PPCSE: I PPCSE cont rols t he fragment checksum calculat ion. As previously not ed, t he fragment
checksum shares t he same locat ion as t he RSS field. The fragment checksum is report ed in t he receive
descript or when t he RXCSUM.PCSD bit is cleared.
I f RXCSUM.I PPCSE is cleared ( t he default value) , t he checksum calculat ion is not done and t he value
t hat is report ed in t he Rx fragment checksum field is 0b.
I f RXCSUM.I PPCSE is set , t he fragment checksum is aimed t o accelerat e checksum calculat ion of
fragment ed UDP packet s. See Sect ion 7. 1.13 for a det ailed explanat ion.
This regist er should only be init ialized ( writ t en) when t he receiver is not enabled ( for example, only
writ e t his regist er when RXCTRL. RXEN = 0b) .
8.2.3. 7.6 Recei ve Fi l t er Cont r ol Regi st er RFCTL ( 0x 05008; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PPCSE 12 0b I P Payload Checksum Enable.
PCSD 13 0b
RSS/ Fragment Checksum St at us Select ion. When set t o 1b, t he ext ended descript or
wr it e back has t he RSS field. When set t o 0b, it cont ains t he fragment checksum.
Tabl e 8.7. Check sum Enabl e/ Di sabl e
RXCSUM. PCSD 0b ( Check sum En abl e) 1b ( Check sum Di sabl e)
Fragment checksum and I P ident ificat ion are
report ed in t he Rx descript or.
RSS hash value is report ed in t he Rx descript or.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RSC_DI S 5 0
RSC Disable. When set , disable RSC for t he port by t he Rx filt er unit . The default value
is 0b ( RSC feat ure is enabled) .
NFSW_DI S 6 0b NFS Writ e disable. Disable filt ering of NFS writ e request headers.
NFSR_DI S 7 0b NFS Read disable. Disable filt ering of NFS read reply headers.
NFS_VER 9: 8 00b
NFS version recognized by t he hardware.
00b = NFS version 2
01b = NFS version 3
10b = NFS version 4
11b = Reserved for fut ure use
I Pv6_dis 10 0b
I Pv6 Disable.
Disable I Pv6 packet filt ering
I nt ernal use only should not be set t o 1b.

485
8.2.3.7.7 Mul t i cast Tabl e Ar r ay MTA[ n] ( 0x 05200 + 4* n, n= 0...127; RW)
This t able should be init ialized by soft ware before t ransmit and receive are enabled.
8.2.3.7.8 Recei ve Addr ess Low RAL[ n] ( 0x 0A200 + 8* n, n= 0...127; RW)
While "n" is t he exact unicast / mult icast address ent ry and it is equals t o 0,1,127.
These regist ers cont ain t he lower bit s of t he 48- bit Et hernet MAC address. All 32 bit s are valid.
I f t he EEPROM is present , t he first regist er ( RAL0) is loaded from t he EEPROM.
8.2.3.7.9 Recei ve Addr ess Hi gh RAH[ n] ( 0x 0A204 + 8* n, n= 0...127; RW)
While "n" is t he exact unicast / mult icast address ent ry and it is equals t o 0,1,127.
Reserved 11 0b Reserved, always set t o 0b.
I PFRSP_DI S 14 0b
I P Fragment Split Disable
When t his bit is set t he header of I P fragment ed packet s are not set .
I nt ernal use only. Should not be set t o 1b.
Reserved 31: 18 0x0 Reserved. Should be writ t en wit h 0x0 t o ensure fut ure compat ibilit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Bit Vect or 31: 0 X
Word wide bit vect or specifying 32 bit s in t he mult icast address filt er t able. The 82599
provides mult icast filt ering for 4096 mult icast addresses by providing single- bit ent ry
per mult icast address. Those 4096 address locat ions are organized in t he Mult icast
Table Array ( MTA) ; 128 regist ers of 32 bit s for each one. Only 12 bit s out of t he 48- bit
dest inat ion address are considered as a mult icast address. Those 12 bit s can be
select ed by t he MO field of MCSTCTRL regist er. The 7 MS bit s of t he Et hernet MAC
address ( out of t he 12 bit s) select s t he regist er index while t he 5 LS bit s ( out of t he 12
bit s) select s t he bit wit hin a regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RAL 31: 0 X
Receive Address Low. The lower 32 bit s of t he 48- bit Et hernet MAC address.
Not e: Field is defined in big endian ( LS byt e of RAL is first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RAH 15: 0 X
Receive Address High. The upper 16 bit s of t he 48 bit Et hernet MAC Address.
Not e: Field is defined in Big Endian ( MS byt e of RAH is Last on t he wire) .
Reserved 30: 22 0x0 Reserved. Reads as 0. I gnored on writ e.
AV 31
X
see
desc.
Address Valid. All receive addresses are not init ialized by hardware and soft ware should
init ialize t hem before receive is enabled. I f t he EEPROM is present , Receive Address[ 0]
is loaded from t he EEPROM and it s Address Valid field is set t o 1b aft er a soft ware, PCI
reset or EEPROM read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

486
These regist ers cont ain t he upper bit s of t he 48- bit Et hernet MAC address. The complet e address is
{ RAH, RAL} . AV det ermines whet her t his address is compared against t he incoming packet . AV is
cleared by a mast er reset .
Not e: The first Receive Address regist er ( RAR0) is also used for exact mat ch pause frame checking
( DA mat ches t he first regist er) . RAR0 should always be used t o st ore t he individual Et hernet
MAC address of t he adapt er.
Aft er reset , if t he EEPROM is present , t he first regist er ( Receive Address Regist er 0) is loaded from t he
I A field in t he EEPROM, it s Address Select field is 00b, and it s Address Valid field is 1b. I f no EEPROM is
present , t he Address Valid field is 0b. The Address Valid field for all of t he ot her regist ers are 0b.
8.2.3. 7.10 MAC Pool Sel ect Ar r ay MPSAR[ n] ( 0x 0A600 + 4* n, n= 0...255; RW)
Soft ware should init ialize t hese regist ers before t ransmit and receive are enabled.
8.2.3. 7.11 VLAN Fi l t er Tabl e Ar r ay VFTA[ n] ( 0x 0A000 + 4* n, n= 0...127; RW)
This t able should be init ialized by soft ware before t ransmit and receive are enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
POOL_ENA 31: 0 X
Pool Enable Bit Array. Each couple of regist ers 2* n and 2* n+ 1 are associat ed wit h
Et hernet MAC address filt er n as defined by RAL[ n] and RAH[ n] . Each bit when set ,
enables packet recept ion wit h t he associat ed pools as follows:
Bit i in regist er 2* n is associat ed wit h POOL i.
Bit i in regist er 2* n+ 1 is associat ed wit h POOL 32+ i.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VLAN_FLT 31: 0 X
VLAN Filt er. Each bit i in regist er n affect s packet s wit h VLAN t ags equal t o 32* n+ i.
128 VLAN Filt er regist ers compose a t able of 4096 bit s t hat cover all possible VLAN t ags.
Each bit when set , enables packet s wit h t he associat ed VLAN t ags t o pass. Each bit
when cleared, blocks packet s wit h t his VLAN t ag.

487
8. 2.3. 7.12 Mul t i pl e Recei ve Queues Command Regi st er - MRQC ( 0x 0EC80 / 0x 05818; RW)
MRQC is also mapped t o address 0x05818 t o maint ain compat ibilit y wit h t he 82598.
8. 2.3. 7.13 RSS Queues Per Tr af f i c Cl ass Regi st er RQTC ( 0x 0EC70; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MRQE 3: 0 0x0
Mult iple Receive Queues Enable. Defines t he allocat ion of t he Rx queues per RSS,
virt ualizat ion and DCB.
0000b = RSS disabled.
0001b = RSS only Single set of RSS 16 queues.
0010b = DCB enabled and RSS disabled 8 TCs, each allocat ed 1 queue.
0011b = DCB enabled and RSS disabled 4 TCs, each allocat ed 1 queue.
0100b = DCB and RSS 8 TCs, each allocat ed 16 RSS queues.
0101b = DCB and RSS 4 TCs, each allocat ed 16 RSS queues.
0110b = Reserved
0111b = Reserved
1000b = Virt ualizat ion only 64 pools, no RSS, each pool allocat ed 2 queues.
1001b = Reserved
1010b = Virt ualizat ion and RSS 32 pools, each allocat ed 4 RSS queues.
1011b = Virt ualizat ion and RSS 64 pools, each allocat ed 2 RSS queues.
1100b = Virt ualizat ion and DCB 16 pools, each allocat ed 8 TCs.
1101b = Virt ualizat ion and DCB 32 pools, each allocat ed 4 TCs.
1110b = Reserved
1111b = Reserved
Reserved 15 0x0 Reserved
RSS Field Enable 31: 16 0x0
Each bit , when set , enables a specific field select ion t o be used by t he hash funct ion.
Several bit s can be set at t he same t ime.
Bit [ 16] Enable TcpI Pv4 hash funct ion.
Bit [ 17] Enable I Pv4 hash funct ion.
Bit [ 19: 18] Reserved
Bit [ 20] Enable I Pv6 hash funct ion.
Bit [ 21] Enable TcpI Pv6 hash funct ion.
Bit [ 22] Enable UdpI PV4.
Bit [ 23] Enable UdpI PV6.
Bit s[ 31: 24] Reserved
Not e: On Tunnel packet s I Pv4- I Pv6 only t he I Pv4 header can be used for t he RSS
filt ering.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RQTC0 2: 0 0x4
Defines t he number of bit s t o use for RSS redirect ion of packet s dedicat ed t o Traffic
Class ( TC) 0.
A value of zero means t hat all t he t raffic of TC0 is sent t o queue 0 of t he TC.
This field is used only if MRQC. MRQE equals 0100b or 0101b.
RQTC1 6: 4 0x4
Defines t he number of bit s t o use for RSS redirect ion of packet s dedicat ed t o TC 1.
RQTC2 10: 8 0x4
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488
8.2.3. 7.14 RSS Random Key Regi st er RSSRK ( 0x 0EB80 + 4* n, n= 0...9 / 0x 05C80 + 4* n,
n= 0...9; RW)
RSSRK is also mapped t o addresses 0x05C80- 0x05CA4 t o maint ain compat ibilit y wit h t he 82598. The
RSS Random Key is 40 byt es wide ( see RSS hash in Sect ion 7.1.2. 8. 1) .
8.2.3. 7.15 Redi r ect i on Tabl e RETA[ n] ( 0x 0EB00 + 4* n, n= 0...31 / 0x 05C00 + 4* n,
n= 0...31; RW)
RETA is also mapped t o addresses 0x05C00- 0x05C7C t o maint ain compat ibilit y wit h t he 82598. The
redirect ion t able has 128- ent ries in 32 regist ers.
RQTC3 14: 12 0x4
RQTC4 18: 16 0x4
RQTC5 22: 20 0x4
RQTC6 26: 24 0x4
RQTC7 30: 28 0x4
Fi el d Bi t ( s)
I ni t i al
Val ue
Descr i pt i on
K0 7: 0 0x0 RSS Key Byt e 4* n+ 0 of t he RSS random key, for each regist er n.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Ent ry0 3: 0 X
Ent ry0 defines t he RSS out put index for hash value 4* n+ 0. While n is t he regist er
index, equals t o 0. . . 31.
Ent ry1 11: 8 X
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

489
The cont ent s of t he redirect ion t able are not defined following reset of t he Memory Configurat ion
regist ers. Syst em soft ware must init ialize t he t able prior t o enabling mult iple receive queues. I t can
also updat e t he redirect ion t able during run t ime. Such updat es of t he t able are not synchronized wit h
t he arrival t ime of received packet s. Therefore, it is not guarant eed t hat a t able updat e t akes effect on
a specific packet boundary.
8.2.3.7.16 Sour ce Addr ess Queue Fi l t er SAQF[ n] ( 0x 0E000 + 4* n, n= 0...127; RW)
This regist er must be init ialized by soft ware
.
8.2.3.7.17 Dest i nat i on Addr ess Queue Fi l t er DAQF[ n] ( 0x 0E200 + 4* n, n= 0...127; RW)
8.2.3.7.18 Sour ce Dest i nat i on Por t Queue Fi l t er SDPQF[ n] ( 0x 0E400 + 4* n, n= 0...127;
RW)
Ent ry2 19: 16 X
Ent ry3 27: 24 X
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Source Address 31: 0 X
I P Source Address. Part of t he 5- t uple queue filt ers.
Not e: Field is defined in big endian ( LS byt e is first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Dest inat ion Address 31: 0 X
I P Dest inat ion Address. Par t of t he 5- t uple queue filt er s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Source Port 15: 0 X
TCP/ UDP Source Port . Part of t he 5- t uple queue filt ers.
Not e: Field is defined in Big Endian ( LS byt e is first on t he wire) .
Dest inat ion Port 31: 16 X TCP/ UDP Dest inat ion Port . Part of t he 5- t uple queue filt ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

490
8.2.3. 7.19 Fi ve t upl e Queue Fi l t er FTQF[ n] ( 0x 0E600 + 4* n, n= 0...127; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Prot ocol 1: 0 X
I P L4 prot ocol, part of t he 5- t uple queue filt ers.
00b = TCP.
01b = UDP.
10b = SCTP.
11b = Ot her.
Not e: Encoding of t he prot ocol t ype for t he 128 x 5- t uple filt ers is defined different ly
t han t he L4TYPE encoding for t he flow direct or filt ers.
Priorit y 4: 2 X
Priorit y value in case more t han one 5- t uple filt er mat ches.
000b = Reserved
001b = Lowest priorit y.
. . .
111b = Highest priorit y.
Pool 13: 8 X The pool I ndex of t he pool associat ed wit h t his filt er.
Reserved 24: 14 X Reserved for ext ension of t he Pool field.
Mask 29: 25 X
Mask bit s for t he 5- t uple fields ( 1b = dont compare) . The corresponding field
part icipat es in t he mat ch if t he following bit is cleared:
Bit 25 = Mask source address comparison.
Bit 26 = Mask dest inat ion address comparison.
Bit 27 = Mask source port comparison.
Bit 28 = Mask dest inat ion port comparison.
Bit 29 = Mask prot ocol comparison.
Pool Mask 30 X
Mask bit for t he Pool field. When set t o 1b, t he Pool field is not compared as part of t he
5- t uple filt er. Soft ware can clear ( act ivat e) t he Pool Mask bit only when operat ing in I OV
mode.
Queue Enable 31 X
When set , enables filt ering of Rx packet s by t he 5- t uple defined in t his filt er t o t he
queue indicat ed in regist er L34TI MI R.
Not e: There are 128 different 5- t uple filt er configurat ion regist ers set s, wit h indexes [ 0]
t o [ 127] . The mapping t o a specific Rx queue is done by t he Rx Queue field in t he
L34TI MI R regist er, and not by t he index of t he regist er set .

491
8.2.3.7.20 SYN Pack et Queue Fi l t er SYNQF ( 0x 0EC30; RW)
8.2.3.7.21 ETy pe Queue Fi l t er ETQF[ n] ( 0x 05128 + 4* n, n= 0...7; RW)
See Sect ion 7. 1. 2. 3 for more det ails on t he use of t his regist er.
.
8.2.3.7.22 ETy pe Queue Sel ect ETQS[ n] ( 0x 0EC00 + 4* n, n= 0...7; RW)
See Sect ion 7. 1. 2. 3 for more det ails on t he use of t his regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Queue Enable 0 0b When set , enables rout ing of Rx packet s t o t he queue indicat ed in t his regist er.
Rx Queue 7: 1 0x0 I dent ifies an Rx queue associat ed wit h SYN packet s.
Reserved 9: 8 00b Reserved for ext ension of t he Rx Queue field.
SYNQFP 31 0b
Defines t he priorit y bet ween SYNQF and 5- t uples filt er.
0b = 5- t uple filt er priorit y
1b = SYN filt er priorit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EType 15: 0 0x0
I dent ifies t he prot ocol running on t op of I EEE 802. Used t o rout e Rx packet s cont aining
t his Et herType t o a specific Rx queue.
Not e: Field is defined in lit t le endian ( MS byt e is first on t he wire) .
UP 18: 16 0x0
User Priorit y. A 802. 1Q UP value t o be compared against t he User Priorit y field in t he Rx
packet . Enabled by t he UP Enable bit .
UP Enable 19 0b
User Priorit y Enable. Enables comparison of t he User Priorit y field in t he received
packet .
Pool 25: 20 0x0 I n virt ualizat ion modes, det ermines t he t arget pool for t he packet .
Pool Enable 26 0b I n virt ualizat ion modes, enables t he Pool field.
FCoE 27 0b When set , packet s t hat mat ch t his filt er are ident ified as FCoE packet s.
1588 t ime st amp 30 0b
When set , packet s wit h t his EType are t ime st amped according t o t he I EEE 1588
specificat ion.
Filt er Enable 31 0b
0b = The filt er is disabled for any funct ionalit y.
1b = The filt er is enabled. Exact act ions are det ermined by separat e bit s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Rx Queue 22: 16 0x0 I dent ifies t he Rx queue associat ed wit h t his EType.
Reserved 24: 23 0x0 Reserved for fut ure ext ension of t he Rx Queue field.
Low Lat ency I nt errupt 29 0b When set , packet s t hat mat ch t his filt er generat e a LLI .
Reserved 30 0x0 Reserved
Queue Enable 31 0b
When set , enables filt ering of Rx packet s by t he EType defined in t his regist er t o t he
queue indicat ed in t his r egist er.
I nt el

492
8.2. 3. 7.23 Rx Fi l t er ECC Er r I nser t i on 0 RXFECCERR0 ( 0x 051B8; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 8: 0 0x1FF Reserved.
ECCFLT_EN 9 0b
Filt er ECC Error indicat ion Enablement . When set t o 1b, enables t he ECC- I NT + t he RXF-
blocking during ECC- ERR in one of t he Rx filt er memories. At 0b, t he ECC logic can st ill
funct ion overcoming only single errors while dual or mult iple errors can be ignored
silent ly.

493
8.2.3.8 Recei v e DMA Regi st er s
8.2.3.8.1 Recei ve Descr i pt or Base Addr ess Low RDBAL[ n] ( 0x 01000 + 0x 40* n,
n= 0...63 and 0x 0D000 + 0x 40* ( n- 64) , n= 64.. .127; RW)
This regist er cont ains t he lower bit s of t he 64- bit descript or base address. The lower 7 bit s are always
ignored. The receive descript or base address must point t o a 128 byt e- aligned block of dat a.
8.2.3.8.2 Recei ve Descr i pt or Base Addr ess Hi gh RDBAH[ n] ( 0x 01004 + 0x 40* n,
n= 0...63 and 0x 0D004 + 0x 40* ( n- 64) , n= 64.. .127; RW)
This regist er cont ains t he upper 32 bit s of t he 64- bit descript or base address.
8.2.3.8.3 Recei ve Descr i pt or Lengt h RDLEN[ n] ( 0x 01008 + 0x 40* n, n= 0...63 and
0x 0D008 + 0x 40* ( n- 64) , n= 64...127; RW)
8.2.3.8.4 Recei ve Descr i pt or Head RDH[ n] ( 0x 01010 + 0x 40* n, n= 0...63 and 0x 0D010
+ 0x 40* ( n- 64) , n= 64...127; RO)
8.2.3.8.5 Recei ve Descr i pt or Tai l RDT[ n] ( 0x 01018 + 0x 40* n, n= 0...63 and 0x 0D018 +
0x 40* ( n- 64) , n= 64...127; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
0 6: 0 0x0 I gnored on writ es. Ret urns 0x0 on reads.
RDBAL 31: 7 X Receive Descript or Base Address Low.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RDBAH 31: 0 X Receive Descript or Base Address [ 63: 32] .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LEN 19: 0 0x0
Descript or Ring Lengt h. This regist er set s t he number of byt es allocat ed for descript ors
in t he circular descript or buffer. I t must be 128- byt e aligned ( 7 LS bit must be set t o
zero) .
Not e: Validat ed lengt hs up t o 128 K ( 8 K descript ors) .
Reserved 31: 20 0x0 Reads as 0x0. Should be writ t en t o 0x0 for fut ure compat ibilit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RDH 15: 0 0x0
Receive Descript or Head. This regist er holds t he head point er for t he receive descript or
buffer in descript or unit s ( 16- byt e dat um) . The RDH is cont rolled by hardware.
Reserved 31: 16 0x0 Reserved. Should be writ t en wit h 0x0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RDT 15: 0 0x0 Receive Descript or Tail.
Reserved 31: 16 0x0 Reads as 0x0. Should be writ t en t o 0x0 for fut ure compat ibilit y.
I nt el

494
This regist er cont ains t he t ail point er for t he receive descript or buffer. The regist er point s t o a 16- byt e
dat um. Soft ware writ es t he t ail regist er t o add receive descript ors t o t he hardware free list for t he ring.
Not e:
The t ail point er should be set t o one descript or beyond t he last empt y descript or in host
descript or ring.
8.2.3. 8.6 Recei ve Descr i pt or Cont r ol RXDCTL[ n] ( 0x 01028 + 0x 40* n, n= 0. ..63 and
0x 0D028 + 0x 40* ( n- 64) , n= 64...127; RW)
8.2.3. 8.7 Spl i t Recei ve Cont r ol Regi st er s SRRCTL[ n] ( 0x 01014 + 0x 40* n, n= 0...63 and
0x 0D014 + 0x 40* ( n- 64) , n= 64...127 / 0x 02100 + 4* n, [ n= 0...15] ; RW)
SRRCTL[ 0. .. 15] are also mapped t o address 0x02100. .. t o maint ain compat ibilit y wit h t he 82598.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 14 0b Reserved ( soft waremight read and writ e in order t o maint ain backward compat ibilit y. )
Reserved 22: 16 0x0 Reserved ( soft ware might read and writ e in order t o maint ain backward compat ibilit y. )
ENABLE 25 0b
Receive Queue Enable. When set , t he ENABLE bit enables t he operat ion of t he specific
receive queue. Upon read it get s t he act ual st at us of t he queue ( int ernal indicat ion t hat
t he queue is act ually enabled/ disabled) .
Reserved 26 0b Reserved ( soft ware can read and writ e in order t o maint ain backward compat ibilit y. )
VME 30 0b
VLAN Mode Enable.
1b = St rip VLAN t ag from received 802. 1Q packet s dest ined t o t his queue.
0b = Do not st rip VLAN t ag.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BSI ZEPACKET 4: 0 0x2
Receive Buffer Size for Packet Buffer. The value is in 1 KB resolut ion. Value can be from
1 KB t o 16 KB. Default buffer size is 2 KB. This field should not be set t o 0x0. This field
should be great er or equal t o 0x2 in queues where RSC is enabled.
Rsv 7: 5 000b
Reserved.
Should be writ t en wit h 000b t o ensure fut ure compat ibilit y.
BSI ZEHEADER 13: 8 0x4
Receive Buffer Size for Header Buffer. The value is in 64 byt es resolut ion. Value can be
from 64 byt es t o 1024 byt es. Not e t hat t he maximum support ed header size is limit ed
t o 1023. Default buffer size is 256 byt es. This field must be great er t han zero if t he
value of DESCTYPE is great er or equal t o t wo.
Values above 1024 byt es are reserved for int ernal use only.
RDMTS 24: 22 000b
Receive Descript or Minimum Threshold Size. A LLI associat ed wit h t his queue is
assert ed each t ime t he number of free descript ors is decreased t o RDMTS * 64 ( t his
event is considered as Rx ring buffer almost empt y) .

495
Not e: BSI ZEHEADER must be bigger t han zero if DESCTYPE is equal t o 010b, 011b, 100b or 101b.
8.2.3.8.8 Recei ve DMA Cont r ol Regi st er RDRXCTL ( 0x 02F00; RW)
8.2.3.8.9 Recei ve Pack et Buf f er Si ze RXPBSI ZE[ n] ( 0x 03C00 + 4* n, n= 0...7; RW)
DESCTYPE 27: 25 000b
Define t he descript or t ype in Rx:
000b = Legacy.
001b = Advanced descript or one buffer.
010b = Advanced descript or header split t ing.
011b = Reserved.
100b = Reserved.
101b = Advanced descript or header split t ing always use header buffer.
110b and 111b = Reserved.
Drop_En 28 0b
Drop Enabled. I f set t o 1b, packet s received t o t he queue when no descript ors are
available t o st ore t hem are dropped.
Rsv 31: 29 000b
Reserved.
Should be writ t en wit h 000b t o ensure fut ure compat ibilit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CRCSt rip 1 0
Rx CRC St rip indicat ion t o t he Rx DMA unit . This bit must be set t he same as
HLREG0. RXCRCSTRP.
1 - St rip CRC by HW. 0 - No CRC St rip by HW ( Default ) .
Reser ved 2 0 Reserved
DMAI DONE 3 0b
DMA I nit Done. When read as 1b, indicat es t hat t he DMA init ializat ion cycle is done
( RO) .
RSCFRSTSI ZE 21: 17 0x8
Defines a minimum packet size ( aft er VLAN st ripping, if applicable) for a packet wit h a
payload t hat can open a new RSC ( in unit s of 16 byt e. ) . See RSCDBU. RSCACKDI S for
packet s wit hout payload.
Not e: RSCFRSTSI ZE is reserved for int ernal use. Soft ware should set t his field t o 0x0.
RSCACKC 25 0b
RSC Coalescing on ACK Change. When set , an act ive RSC complet es when t he ACK bit
in t he Rx packet is different t han t he ACK bit in t he RSC cont ext . When cleared, an
act ive RSC complet es only when t he ACK bit in t he Rx packet is cleared while t he ACK
bit in t he RSC cont ext is set .
Not e: RSCACKC is reserved for int ernal use. Soft ware should set t his bit t o 1b.
FCOE_WRFI X 26 0b
FCoE Writ e Exchange Fix. When set , DDP cont ext of FC writ e exchange is closed
following a recept ion of a last packet in a sequence wit h an act ive Sequence I nit iat ive
bit in t he F_CTL field. When cleared, t he DDP cont ext is not closed.
Not e: FCOE_WRFI X is reserved for int ernal use. Soft ware should set t his bit t o 1b.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

496
8.2.3. 8.10 Recei ve Cont r ol Regi st er RXCTRL ( 0x 03000; RW)
8.2.3. 8.11 Rx Pack et Buf f er Fl ush Det ect RXMEMWRAP ( 0x 03190; RO)
This regist er is used by soft ware as part of a queue disable procedure ( described in Sect ion 4.6.7. 1)
SI ZE 19: 10 0x200
Receive Packet Buffer Size for t raffic class n while n is t he regist er index. The size is
defined in KB unit s and t he default size of PB[ 0] is 512 KB. The default size of PB[ 1- 7]
is also 512 KB but it is meaningless in non- DCB mode. When DCB mode is enabled t he
size of PB[ 1- 7] must be set t o meaningful values. The t ot al meaningful allocat ed PB
sizes plus t he size allocat ed t o t he flow direct or filt ers should be less or equal t o 512
KB. Possible PB allocat ion in DCB mode for 8 x TCs is 0x40 ( 64 KB) for all PBs. Ot her
possible set t ing of 4 x TCs is 0x80 ( 128 KB) for all PB[ 0- 3] and 0x0 for PB[ 4- 7] . See
sect ion 3. 7. 7. 3. 5 for ot her opt ional set t ings wit h/ wit hout t he flow direct or filt ers
Not e: I n any set t ing t he RXPBSI ZE[ 0] must always be enabled ( great er t han zero) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RXEN 0 0b Receive Enable. When set t o 0b, filt er input s t o t he packet buffer are ignored.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TC0Wrap 2: 0 000b
Packet Buffer 0 Wrap Around Count er. A 3- bit count er t hat increment s on each full cycle
t hrough t he buffer. Once reaching 111b, t he count er warps around t o 000b on t he next
count .
TC0Empt y 3 1b
Packet Buffer 0 Empt y
0b = Packet buffer is not empt y.
1b = Packet buffer is empt y.
TC1Wrap 6: 4 000b
count .
TC1Empt y 7 1b
TC2Wrap 10: 8 000b
count .
TC2Empt y 11 1b
TC3Wrap 14: 12 000b
count .
TC3Empt y 15 1b
TC4Wrap 18: 16 000b
count .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

497
8.2.3.8.12 RSC Dat a Buf f er Cont r ol Regi st er RSCDBU ( 0x 03028; RW)
8.2.3.8.13 RSC Cont r ol RSCCTL[ n] ( 0x 0102C + 0x 40* n, n= 0...63 and 0x 0D02C +
0x 40* ( n- 64) , n= 64...127; RW)
8.2.3.9 Tr ansmi t Regi st er s
8.2.3.9.1 DMA Tx TCP Max Al l ow Si ze Request s DTXMXSZRQ ( 0x 08100; RW)
This regist er limit s t he t ot al number of dat a byt es t hat may be in out st anding PCI e request s from t he
host memory. This allows request s t o send low lat ency packet s t o be serviced in a t imely manner, as
t his request will be serviced right aft er t he current out st anding request s are complet ed.
TC4Empt y 19 1b
TC5Wrap 22: 20 000b
count .
TC5Empt y 23 1b
TC6Wrap 26: 24 000b
count .
TC6Empt y 27 1b
TC7Wrap 30: 28 000b
count .
TC7Empt y 31 1b
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RSCEN 0 0b RSC Enable. When t he RSCEN bit is set , RSC is enabled on t his queue.
MAXDESC 3: 2 00b
Maximum descript ors per Large receive as follow:
00b = Maximum of 1 descript or per large receive.
01b = Maximum of 4 descript ors per large receive.
Not e: MAXDESC * SRRCTL. BSI ZEPKT must not exceed 64 KB minus one, which is t he
maximum t ot al lengt h in t he I P header and must be larger t han t he expect ed received
MSS.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

498
8.2.3. 9.2 DMA Tx Cont r ol DMATXCTL ( 0x 04A80; RW)
8.2.3. 9.3 DMA Tx TCP Fl ags Cont r ol Low DTXTCPFLGL ( 0x 04A88; RW)
This regist er holds t he mask bit s for t he TCP flags in Tx segment at ion ( described in Sect ion 7. 2. 4.7.1
and Sect ion 7. 2. 4.7.2) .
8.2.3. 9.4 DMA Tx TCP Fl ags Cont r ol Hi gh- DTXTCPFLGH ( 0x 04A8C; RW)
This regist er holds t he mask bit s for t he TCP flags in Tx segment at ion ( described in Sect ion 7. 2. 4.7.3) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Max_byt es_num_req 11: 0 0x10
Max allowed number of byt es request s. The maximum allowed amount of 256 byt es
out st anding request s. I f t he t ot al size request is higher t han t he amount in t he field no
arbit rat ion is done and no new packet is request ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TE 0 0b
Transmit Enable.
When set , t his bit enables t he t ransmit operat ion of t he DMA-Tx.
GDV 3 0b
Global Double VLAN Mode.
When set , t his bit enables t he Double VLAN mode.
VT 31: 16 0x8100
VLAN Et her-Type ( t he VLAN Tag Prot ocol I dent ifier TPI D) . For proper operat ion,
soft ware must not change t he default set t ing of t his field ( 802. 3ac st andard defines it
as 0x8100) .
This field must be set t o t he same value as t he VET field in t he VLNCTRL regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TCP_flg_first _seg 11: 0 0xFF6
TCP Flags First Segment . Bit s t hat make AND operat ion wit h t he TCP flags at TCP header
in t he first segment .
TCP_Flg_mid_seg 27: 16 0xFF6
TCP Flags Middle Segment s. The low bit s t hat make AND operat ion wit h t he TCP flags at
TCP header in t he middle segment s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TCP_Flg_lst _seg 11: 0 0xF7F
TCP Flags Last Segment . Bit s t hat make AND operat ion wit h t he TCP flags at TCP
header in t he last segment .

499
8.2.3.9.5 Tr ansmi t Descr i pt or Base Addr ess Low TDBAL[ n] ( 0x 06000+ 0x 40* n,
n= 0...127; RW)
This regist er cont ains t he lower bit s of t he 64- bit descript or base address. The lower seven bit s are
ignored. The Transmit Descript or Base Address must point t o a 128 byt e- aligned block of dat a.
8.2.3.9.6 Tr ansmi t Descr i pt or Base Addr ess Hi gh TDBAH[ n] ( 0x 06004+ 0x 40* n,
n= 0...127; RW)
This regist er cont ains t he upper 32 bit s of t he 64 bit Descript or base address.
8.2.3.9.7 Tr ansmi t Descr i pt or Lengt h TDLEN[ n] ( 0x 06008+ 0x 40* n, n= 0...127; RW)
8.2.3.9.8 Tr ansmi t Descr i pt or Head TDH[ n] ( 0x 06010+ 0x 40* n, n= 0...127; RO)
This regist er cont ains t he head point er for t he t ransmit descript or ring. I t point s t o a 16- byt e dat um.
Hardware cont rols t his point er.
The values in t hese regist ers might point t o descript ors t hat are st ill not in t he host memory. As a
result , t he host cannot rely on t hese values in order t o det ermine which descript or t o release.
The only t ime t hat soft ware should writ e t o t his regist er is aft er a reset ( hardware reset or CTRL.RST)
and before enabling t he t ransmit funct ion ( TXDCTL.ENABLE) . I f soft ware were t o writ e t o t his regist er
while t he t ransmit funct ion was enabled, t he on- chip descript or buffers might be invalidat ed and t he
hardware could become confused.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
0 6: 0 0b I gnored on writ es. Ret urns 0b on reads.
TDBAL 31: 7 X Transmit Descript or Base Address Low.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TDBAH 31: 0 X Transmit Descript or Base Address [ 63: 32] .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LEN 19: 0 0x0
Descript or Ring Lengt h. This regist er set s t he number of byt es allocat ed for descript ors
in t he circular descript or buffer. I t must be 128byt e- aligned ( 7 LS bit must be set t o
zero) .
Not e: Validat ed Lengt hs up t o 128K ( 8K descript ors) .
Reserved 31: 20 0x0 Reads as 0x0. Should be writ t en t o 0x0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TDH 15: 0 0x0 Transmit Descript or Head.
Reserved 31: 16 0x0 Reserved. Should be writ t en wit h 0x0.
I nt el

500
8.2.3. 9.9 Tr ansmi t Descr i pt or Tai l TDT[ n] ( 0x 06018+ 0x 40* n, n= 0. ..127; RW)
This regist er cont ains t he t ail point er for t he t ransmit descript or ring. I t point s t o a 16- byt e dat um.
Soft ware writ es t he t ail point er t o add more descript ors t o t he t ransmit ready queue. Hardware
at t empt s t o t ransmit all packet s referenced by descript ors bet ween head and t ail.
8.2.3. 9.10 Tr ansmi t Descr i pt or Cont r ol TXDCTL[ n] ( 0x 06028+ 0x 40* n, n= 0...127; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TDT 15: 0 0x0 Transmit Descript or Tail.
Reserved 31: 16 0x0 Reads as 0x0. Should be writ t en t o 0x0for fut ure compat ibilit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTHRESH 6: 0 0x0
Pre- Fet ch Thr eshold
Cont rols when a prefet ch of descript ors is considered. This t hreshold refers t o t he
number of valid, unprocessed t ransmit descript ors t he 82599 has in it s on- chip buffer. I f
t his number drops below PTHRESH, t he algorit hm considers prefet ching descript ors
from host memory. However, t his fet ch does not happen unless t here are at least
HTHRESH valid descript ors in host memory t o fet ch.
Not e: HTHRESH should be given a non-zero value each t ime PTHRESH is used.
Rsv 7 0x0 Reserved
HTHRESH 14: 8 0x0 Host Threshold.
Rsv 15 0x0 Reserved
WTHRESH 22: 16 0x0
Writ e- Back Threshold.
Cont rols t he writ e- back of processed t ransmit descript ors. This t hreshold refers t o t he
number of t ransmit descript ors in t he on- chip buffer t hat are ready t o be writ t en back t o
host memory. I n t he absence of ext ernal event s ( explicit flushes) , t he writ e- back occurs
only aft er at least WTHRESH descript ors are available for writ e- back.
Not e: Since t he default value for writ e- back t hreshold is 0b, descript ors are normally
writ t en back as soon as t hey are processed. WTHRESH must be writ t en t o a non- zero
value t o t ake advant age of t he writ e- back burst ing capabilit ies of t he 82599.
Not e: When WTHRESH is set t o a non- zero value, t he soft ware driver should not set t he
RS bit in t he Tx descript ors. When WTHRESH is set t o zero t he soft ware driver should
set t he RS bit in t he last Tx descript ors of every packet ( in t he case of TSO it is t he last
descript or of t he ent ire large send) .
Not e: When Head writ e- back is enabled ( TDWBAL[ n] . Head_WB_En = 1b) , t he
WTHRESH must be set t o zero.
ENABLE 25 0b
Transmit Queue Enable.
When set , t his bit enables t he operat ion of a specific t ransmit queue:
Default value for all queues is 0b.
Set t ing t his bit init ializes all t he int ernal regist ers of a specific queue. Unt il t hen, t he
st at e of t he queue is kept and can be used for debug purposes.
When disabling a queue, t his bit is cleared only aft er all act ivit y at t he queue st opped.
Not e: This bit is valid only if t he queue is act ually enabled.
Upon read get t he act ual st at us of t he queue ( int ernal indicat ion t hat t he queue is
act ually enabled/ disabled)
Not e: When set t ing t he global Tx enable DMATXCTL. TE t he ENABLE bit of Tx queue zero
is enabled as well.
SWFLSH 26 0b
Transmit Soft ware Flush. This bit enables soft ware t o t rigger descript or writ e- back
flushing, independent ly of ot her condit ions.
This bit is self cleared by hardware.

501
This regist er cont rols t he fet ching and writ e- back of t ransmit descript ors. The t hree t hreshold values
are used t o det ermine when descript ors is read from and writ t en t o host memory.
Not e: When WTHRESH = 0b only descript ors wit h t he RS bit set are writ t en back.
For PTHRESH and HTHRESH recommended set t ing please refer t o Sect ion 7.2. 3. 4.
8. 2.3. 9.11 Tx Descr i pt or Compl et i on Wr i t e Back Addr ess Low TDWBAL[ n]
( 0x 06038+ 0x 40* n, n= 0...127; RW)
8. 2.3. 9.12 Tx Descr i pt or Compl et i on Wr i t e Back Addr ess Hi gh TDWBAH[ n]
( 0x 0603C+ 0x 40* n, n= 0...127; RW)
8.2.3.9.13 Tr ansmi t Pack et Buf f er Si ze TXPBSI ZE[ n] ( 0x 0CC00 + 0x 4* n, n= 0...7; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Head_WB_En 0 0b
Head Writ e- Back Enable.
At 1b, Head writ e- back is enabled.
At 0b, Head writ e- back is disabled.
When head_WB_en is set , t he 82599 does not writ e- back Tx descript ors.
Reser ved 1 0 Reserved.
HeadWB_Low 31: 2 0x0
Lowest 32 bit s of t he head writ e- back memory locat ion ( Dword aligned) . Last 2 bit s of
t his field are ignored and are always read as 0. 0, meaning t hat t he act ual address is
Qword aligned.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
HeadWB_High 31: 0 0x0 Highest 32 bit s of head writ e- back memory locat ion ( for 64- bit addressing) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SI ZE 19: 10
0xA0
( 160
KB)
Transmit packet buffer size of TCn. At default set t ing ( no DCB) only packet buffer 0 is
enabled and TXPBSI ZE values for TC 1- 7 are meaningless.
Ot her t han t he default configurat ion t he 82599 support s part it ioned configurat ions when
DCB is enabled.
Symmet rical 8 TCs part it ioning: 0x14 ( 20KB) for TXPBSI ZE[ 0. . . 7] .
Symmet rical 4 TCs part it ioning: 0x28 ( 40KB) for TXPBSI ZE[ 0. . . 3] and 0x0 ( 0KB) for
TXPBSI ZE[ 4. . . 7] .
Non- symmet rical part it ioning are support ed as well. I n order t o enable wire speed
t ransmission it is recommended t o set t he t ransmit packet buffers t o: ( 1) At least 2
t imes MSS plus PCI e lat ency ( approximat e 1 KB) when I PSec AH is not enabled ( securit y
block is not enabled or operat es in pat h t hrough mode) . ( 2) At least 3 t imes MSS plus
PCI e lat ency when I PSec AH is enabled ( securit y block operat es in st ore and forward
mode)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

502
8.2.3. 9.14 Manageabi l i t y Tr ansmi t TC Mappi ng MNGTXMAP ( 0x 0CD10; RW)
8.2.3. 9.15 Mul t i pl e Tr ansmi t Queues Command Regi st er MTQC ( 0x 08120; RW)
This regist er can be modified only as part of t he init phase.
Permit t ed value and funct ionalit y of: RT_Ena; VT_Ena; NUM_TC_OR_Q. For Tx queue assignment in
DCB and VT modes refer t o Table 7.25 in Sect ion 7.2.1. 2. 1.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MAP 2: 0 0x0 Map value indicat es t he TC t hat t he t ransmit manageabilit y t raffic is rout ed t o.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RT_Ena 0 0b DCB Enabled Mode. See funct ionalit y in t he following t able.
VT_Ena 1 0b
Virt ualizat ion Enabled Mode. When set , t he 82599 support s eit her 16, 32, or 64 pools.
See funct ionalit y in t he following t able.
This bit should be set t he same as PFVTCTL. VT_Ena.
NUM_TC_OR_Q 3: 2 00b
Number of TCs or Number of Tx Queues per Pools. See funct ionalit y in t he following
t able.
Dev i ce Set t i ng Devi ce Funct i onal i t y
RT_Ena VT_Ena NUM_TC_OR_Q Tx Queues TC & VT
0b 0b 00b 0 63 -
< > 0b < > 0b 00b Reserved
0b 0b < > 00 Reserved
1b 0b 01b Reserved
1b 0b 10b 0 127 TC0 TC3
1b 0b 11b 0 127 TC0 TC7
0b 1b 01b 0 127 64 VMs
0b 1b 10b 0 127 32 VMs
0b 1b 11b Reserved
1b 1b 01b Reserved
1b 1b 10b 0 127 TC0 TC3 & 32 VMs
1b 1b 11b 0 127 TC0 TC7 & 16 VMs

503
8.2.3.9.16 Tx Pack et Buf f er Thr eshol d TXPBTHRESH ( 0x 04950 + 0x 4* n, n= 0...7; RW)
8.2.3.10 DCB Regi st er s
DCB regist ers are owned by t he PF in an I OV mode.
8.2.3.10.1 DCB Recei ve Pack et Pl ane Cont r ol and St at us RTRPCS ( 0x 02430; RW)
RTRPCS is equivalent t o t he 82598s RMCS.
8.2.3.10.2 DCB Tr ansmi t Descr i pt or Pl ane Cont r ol and St at us RTTDCS ( 0x 04900; RW)
DMA- Tx
RTTDCS was DPMCS mapped t o 0x07F40 in t he 82598.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
THRESH 9: 0
0x96/
0x0
Threshold used for checking room place in Tx packet buffer of TCn.
Threshold in KB unit s, when t he packet buffer is filled up wit h payload over t hat
t hreshold, no more dat a read request is sent .
Default values:
0x96 ( 150 KB) for TXPBSI ZE0.
0x0 ( 0 KB) for TXPBSI ZE1- 7.
I t should be set t o: ( packet buffer size) MSS.
For inst ance, if packet buf fer size is set t o 20 KB in corresponding TXPBSI ZE. SI ZE, if
MSS of 9. 5 KB ( 9728- byt e) j umbo frames is support ed for TCn, it is set t o: 0xA ( 10 KB) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RRM 1 0b
Receive Recycle Mode defines t he recycle mode wit hin a BWG.
0b= No recycle.
1b = Recycle wit hin t he BWG. I t is t he only support ed mode when DCB is enabled.
RAC 2 0b
Receive Arbit rat ion Cont rol.
0b= Round Robin ( RR) .
1b = Weight ed St rict Priorit y ( WSP) .
LRPB 18: 16 0x0
Last Received Packet Buffer St at us I ndicat ion. I ndicat es t he last packet buffer t hat was
used in Rx arbit er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TDPAC 0 0b
TC Transmit Descript or Plane Arbit rat ion Cont rol.
0b = RR.
1b = WSP.
VMPAC 1 0b
VM Transmit Descript or Plane Arbit rat ion Cont rol.
0b = RR.
1b = Weight ed Round Robin ( WRR) .
I nt el

504
8.2.3. 10.3 DCB Tr ansmi t Pack et Pl ane Cont r ol and St at us- RTTPCS ( 0x 0CD00; RW)
RTTPCS is mapped t o 0x0CD00 for compat ibilit y wit h t he 82598s PDPMCS.
8.2.3. 10.4 DCB Recei ve User Pr i or i t y t o Tr af f i c Cl ass RTRUP2TC ( 0x 03020; RW)
TDRM 4 0b
TC Transmit descript or plane recycle mode defines t he recycle mode wit hin a BWG.
0b = No recycle.
1b = Recycle wit hin t he BWG. I t is t he only support ed mode.
ARBDI S 6 0
DCB Arbit ers Disable
When set t o 1 t his bit pauses t he Tx Descript or plane arbit rat ion st at e- machine.
Therefore, during nominal operat ion t his bit should be set t o 0.
LTTDESC ( RO) 19: 17 0x0
Last Transmit t ed TC ( RO)
This field indicat es t he last t ransmit t ed TC in XMI T descript or arbit er DMA.
BDPM 22 1b
Bypass Dat a_Pipe Monit or. I n order t o enable bypassing t he above limit .
I n DCB mode, t his bit must be cleared.
BPBFSM 23 1b
Bypass Packet Buffer Free Space Monit or. I n order t o enable bypassing t he packet buffer
free space monit or ( not checking if t here is enough free space in t he packet buffer
before request ing t he dat a) .
This bit must be cleared in DCB mode or SR- I OV mode.
SPEED_CHG 31 0b
Link speed has changed. Read and clear flag.
Set by hardware t o indicat e t hat t he link speed has changed.
Cleared by soft ware at t he end of t he link speed change procedure. Refer t o
Sect ion 4. 6. 11. 2.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TPPAC 5 0b
Transmit Packet Plane Arbit rat ion Cont rol
0b = RR ( wit h respect t o st op markers) .
1b = St rict Priorit y ( SP) , wit h respect t o st op markers)
TPRM 8 0b
Transmit packet plane recycle mode defines t he recycle mode wit hin a BWG.
0b = No recycle.
1b = Recycle wit hin t he BWG.
ARBD 31: 22 0x224
ARB_delay. Minimum cycles delay bet ween a packet s arbit rat ion. When RTTPCS. TPPAC
is set t o 1b t he arbit rat ion delay is according t o ARBD, ot herwise t he arbit rat ion delay is
0x0. Should be kept at default in non- DCB mode. I n DCB mode, should be set t o
0x004.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

505
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
UP0MAP 2: 0 0x0
Receive UP 0 t o TC Mapping.
When set t o n, UP 0 is bound t o TC n.
Used for t wo purposes:
Define int o which Rx packet buffer incoming t raffic carrying 802. 1p field set t o 0 is
rout ed.
Define according t o t he filling st at us of which Rx packet puffer a Priorit y Flow
Cont rol ( PFC) frame wit h t he Timer 0 field and Class Enable Vect or bit 0 set is sent .
UP1MAP 5: 3 0x0
rout ed.
Define according t o t he filling st at us of which Rx Packet Buffer a P FC frame wit h t he
Timer 1 field and Class Enable Vect or bit 1 set is sent .
UP2MAP 8: 6 0x0
rout ed.
Define according t o t he filling st at us of which Rx Packet Buffer a PFC frame wit h t he
UP3MAP 11: 9 0x0
rout ed.
Define according t o t he filling st at us of which Rx packet buffer a PFC frame wit h t he
UP4MAP 14: 12 0x0
rout ed.
UP5MAP 17: 15 0x0
rout ed.
UP6MAP 20: 18 0x0
rout ed.
UP7MAP 23: 21 0x0
rout ed.
I nt el

506
8.2.3. 10.5 DCB Tr ansmi t User Pr i or i t y t o Tr af f i c Cl ass RTTUP2TC ( 0x 0C800; RW)
8.2.3. 10.6 DCB Recei ve Pack et Pl ane T4 Conf i g RTRPT4C[ n] ( 0x 02140 + 4* n, n= 0...7;
RW)
RTRPT4C is equivalent t o t he 82598s RT2CR.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
UP0MAP 2: 0 0x0
Transmit UP 0 t o TC Mapping.
Used when receiving a PFC frame wit h t he Timer 0 field and Class Enable Vect or bit 0
set , t o det ermine which TC must be paused.
UP1MAP 5: 3 0x0
UP2MAP 8: 6 0x0
UP3MAP 11: 9 0x0
UP4MAP 14: 12 0x0
set , t o det ermine which t raffic class must be paused.
UP5MAP 17: 15 0x0
UP6MAP 20: 18 0x0
When set t o n, UP 6 is bound t o V n.
UP7MAP 23: 21 0x0
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CRQ 8: 0 0x0
Credit Refill Quant um.Amount of credit s t o refill in 64- byt e granularit y.
Possible values 0x000: 0x1FF ( 0 t o 32, 704 byt es) .
BWG 11: 9 0x0 Bandwidt h Group I ndex.Bandwidt h Group ( BWG) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

507
8.2.3.10.7 St r i ct Low Lat ency Tx Queues TXLLQ[ n] ( 0x 082E0 + 4* n, n= 0...3; RW)
8.2.3.10.8 DCB Recei ve Pack et Pl ane T4 St at us RTRPT4S[ n] ( 0x 02160 + 4* n, n= 0. ..7;
RO)
RTRPT4S is equivalent t o t he 82598s RT2SR.
8.2.3.10.9 DCB Tr ansmi t Descr i pt or Pl ane T2 Conf i g - RTTDT2C[ n] ( 0x 04910 + 4* n,
n= 0...7; RW) DMA- Tx
RTTDT2C was TDTQ2TCCR in t he 82598 at 0x0602C + 0x40* n, n= 0. .. 7.
MCL 23: 12 0x0
Max Credit Limit . Maximum amount of credit s for a configured packet buffer in 64- byt e
granularit y.
Possible values 0x000: 0xFFF ( 0t o 262, 080byt es) .
GSP 30 0b
Group St rict Priorit y. When set t o 1b enables st rict priorit y t o t he appropriat e packet
buffer over any t raffic of ot her packet buffers wit hin t he group.
LSP 31 0b
Link St rict Priorit y. I f set t o 1b enables st rict priorit y t o t he appropriat e packet buffer
over any t raffic of ot her packet buffers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
St rict Low lat ency 31: 0 0x0
St rict Low Lat ency Enable. When set , defines t he relevant Tx queue as st rict low
lat ency. All queues belong t o a LSP TC must be set as st rict low lat ency queues.
Bit ' m' in regist er ' n' correspond t o Tx queue 32 x ' n' + ' m' .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CRQ 8: 0 0x0
Credit Refill Quant um.
Amount of credit s t o refill t he TC in 64- byt e granularit y
Possible values 0x000 0x1FF ( 0 32, 704 byt es)
BWG 11: 9 0x0
Bandwidt h Group I ndex.
Assignment of t his TC t o a bandwidt h group.
MCL 23: 12 0x0
Max Credit Limit .
Max amount of credit s for a configured TC in 64- byt e granularit y
Possible values 0x000 0xFFF ( 0 262, 080 byt es)
GSP 30 0b
Group St rict Priorit y.
When set t o 1b enables st rict priorit y t o t he appropriat e TC over any t raffic of ot her TCs
wit hin t he group.
LSP 31 0b
Link St rict Priorit y.
When set t o 1b enables st rict priorit y t o t he appropriat e TC over any t raffic of ot her
TCs.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

508
8.2.3. 10.10 DCB Tr ansmi t Pack et Pl ane T2 Conf i g RTTPT2C[ n] ( 0x 0CD20 + 4* n, n= 0...7;
RW)
RTTPT2C is mapped t o 0x0CD20 + 4* n [ n= 0...7] for compat ibilit y wit h t he 82598s TDPT2TCCR.
8.2.3. 10.11 DCB Tr ansmi t Pack et pl ane T2 St at us RTTPT2S[ n] ( 0x 0CD40 + 4* n, n= 0...7;
RO)
RTTPT2S is mapped t o 0x0CD40 + 4* n [ n= 0.. .7] for compat ibilit y wit h t he 82598s TDPT2TCSR.
8.2.3. 10.12 DCB Tr ansmi t Rat eSchedul er MMW RTTBCNRM ( 0x 04980; RW)
8.2.3. 10.13 DCB Tr ansmi t Descr i pt or Pl ane Queue Sel ect RTTDQSEL ( 0x 04904; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CRQ 8: 0 0x0
Amount of credit s t o refill t he TC in 64- byt e granularit y.
Possible values 0x000: 0x1FF ( 0 t o 32, 704 byt es) .
BWG 11: 9 0x0
Bandwidt h Group.
Assignment of t his TC t o a BWG.
MCL 23: 12 0x0
Max Credit Limit .
Max amount of credit s for a configured TC in 64- byt e granularit y.
Possible values 0x000: 0xFFF ( 0 262, 080 byt es) .
GSP 30 0b
Group St rict Priorit y.
When set t o 1b enables st rict priorit y t o t he appropriat e TC over any t raffic of ot her TCs
wit hin t he group.
LSP 31 0b
Link St rict Priorit y.
When set t o 1b enables st rict priorit y t o t he appropriat e TC over any t raffic of ot her
TCs.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MMW_SI ZE 10: 0 0x0
Maximum memory window size for t he rat e- scheduler ( for all Tx queues) .
This is t he maximum amount of 1 KB unit s of payload compensat ion t ime t hat can be
accumulat ed for Tx queues at t ached t o TCn. This number must be mult iplied by t he
rat e- fact or of t he Tx queue before performing t he MMW sat urat ion check for t hat queue.

509
8.2.3.10.14 DCB Tr ansmi t Descr i pt or Pl ane T1 Conf i g RTTDT1C ( 0x 04908; RW)
128 int ernal regist ers indirect ly addressed via RTTDQSEL.TXDQ_I DX. When DCB is disabled, configure
t he pool index wit h t he credit s allocat ed t o t he ent ire pool.
8.2.3.10.15 DCB Tr ansmi t Descr i pt or Pl ane T1 St at us RTTDT1S ( 0x 0490C; RO)
128 int ernal regist ers indirect ly addressed via RTTDQSEL. TXDQ_I DX.
8.2.3.10.16 DCB Tr ansmi t Rat e- Schedul er Conf i g RTTBCNRC ( 0x 04984; RW)
128 int ernal regist ers indirect ly addressed via RTTDQSEL. TXDQ_I DX.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TXDQ_I DX 6: 0 0x0
Tx Descript or Queue I ndex or TX Pool of Queues I ndex
This regist er is used t o set VM and Transmit Scheduler paramet ers t hat are configured
per Tx queue or per Tx pool of queues via indirect access. I t means t hat prior t o read or
writ e access such regist ers, soft ware has t o make sure t his field cont ains t he index of
t he Tx queue or Tx pool of queue t o be accessed.
When DCB is disabled, VM paramet ers include a pool of Tx queues. As a result , t his field
point s t o t he index of t he pool ( and not a queue index) .
When DCB is enabled, and/ or when programming rat e limit ers, t his field point s t o a Tx
queue index.
The regist ers t hat are affect ed by t his index are:
RTTDT1C, RTTDT1S, RTTBCNRC, RTTBCNRS
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CRQ 13: 0 X
Amount of credit s t o refill t he VM in 64- byt e granularit y.
Possible values 0x000: 0x3FFF ( 0 t o 1, 048, 512 byt es) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RF_DEC 13: 0 X
Tx rat e- scheduler rat e fact or hexadecimal part , for t he Tx queue indexed by TXDQ_I DX
field in t he RTTDQSEL regist er.
Rat e fact or bit s t hat come aft er t he hexadecimal point .
Meaningful only if t he RS_ENA bit is set .
When RTTBCNRD. DRI FT_ENA is set , t his field is periodically modified by hardware as
well.
I nt el

510
8.2.3. 10.17 DCB Tr ansmi t Rat e- Schedul er St at us RTTBCNRS ( 0x 04988; RW)
128 int ernal regist ers indirect ly addressed via RTTDQSEL.TXDQ_I DX.
8.2.3. 10.18 DCB Tr ansmi t BCN Rat e Dr i f t RTTBCNRD ( 0x 0498C; RW)
RF_I NT 23: 14 X
Tx rat e- scheduler rat e fact or int egral part , for t he Tx queue indexed by TXDQ_I DX field
in t he RTTDQSEL regist er
Rat e fact or bit s t hat come before t he hexadecimal point .
Rat e fact or is defined as t he rat io bet ween t he nominal link rat e ( such as 1 GbE) and t he
maximum rat e allowed t o t hat queue .
Minimum allowed bandwidt h share for a queue is 0. 1% of t he link rat e. For example, 10
Mb/ s for t he 82599 operat ed at 10 GbE, leading t o a maximum allowed rat e fact or of
1000.
Meaningful only if t he RS_ENA bit is set .
When RTTBCNRD. DRI FT_ENA is set , t his field is periodically modified by hardware as
well.
RS_ENA ( SC) 31b 0
Tx rat e- scheduler enable, for t he Tx queue indexed by TXDQ_I DX field in t he
RTTDQSEL regist er
When set , t he rat e programmed in t his regist er is enforced ( t he queue is rat e
cont rolled) . At t he t ime it is set , t he current t imer value is loaded int o t he t ime st amp
st ored f or t hat ent ry. The bit can be self- cleared int ernally if t he full line rat e is
recovered via t he rat e- drift mechanism.
When cleared, t he rat e fact or programmed in t his regist er is meaningless, t he swit ch
for t hat queue is always forced t o on. The queue is not rat e- cont rolled . Bandwidt h
group assignment of t his TC t o a BWG.
Each TC must be assigned t o a different BWG number, unless t he TC is a member of a
BWG. No more t han t wo TCs can share t he same BWG.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MI FS 31: 0
Tx rat e- scheduler current Minimum I nt er- Frame Spacing ( MI FS) , for t he Tx queue
indexed by TXDQ_I DX field in t he RTTDQSEL regist er.
When read, it is t he current algebraic value of t he MI FS int erval for t he queue,
expressed in byt e unit s ( 31 LS- bit s t aken) , relat ive t o t he rat e- scheduler. I t is obt ained
by hardware subt ract ing t he current value of t he t imer associat ed t o t hat rat e-
scheduler from t he t ime st amp st ored for t hat queue. A st rict posit ive value means a
swit ch in off st at e. I t is expressed in 2s complement format .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BCN_CLEAR_ALL 1 0b/ SC
Clear all BCN rat e- limit ers.
When set , t he 128 RTTBCNRC. RS_ENA bit s are cleared releasing any act ive BCN rat e-
limit er. This bit must be set by soft ware each t ime t he link speed has changed.
This bit is self cleared by hardware.
DRI FT_FAC 15: 2 0b
BCN Rat e Drift Fact or
Rat e drift fact or bit s t hat come aft er t he hexadecimal point , while a zero is always
assumed before t he hexadecimal point ( because rat e drift fact or must be smaller t han
unit y) . The rat e drift fact or ranges from 0. 00006 t o 0. 99994.
Rat e drift fact or is a decreasing fact or by which every rat e- fact or of BCN rat e- cont rolled
queues must be mult iplied periodically, once every DRI FT_I NT s. Each t ime t he rat e-
fact or of a queue reaches unit y, t he RS_ENA bit in it s corresponding RTTBCNRC regist er
is int ernally cleared.
Meaningful only when t he DRI FT_ENA bit is set .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

511
8.2.3.11 DCA Regi st er s
8.2.3.11.1 Rx DCA Cont r ol Regi st er DCA_RXCTRL[ n] ( 0x 0100C + 0x 40* n, n= 0... 63 and
0x 0D00C + 0x 40* ( n- 64) , n= 64...127 / 0x 02200 + 4* n, [ n= 0...15] ; RW)
DCA_RXCTRL[ 0.. .15] are also mapped t o address 0x02200.. . t o maint ain compat ibilit y wit h t he 82598.
8.2.3.11.2 Tx DCA Cont r ol Regi st er s DCA_TXCTRL[ n] ( 0x 0600C + 0x 40* n, n= 0...127;
RW)
DRI FT_I NT 30: 16 0b
BCN Rat e Drift I nt erval Timer.
I nt erval in s used int ernally t o periodically increase t he rat e of BCN rat e- cont rolled
queues ( namely t he rat e- drift mechanism) .
Meaningful only when t he DRI FT_ENA bit is set .
DRI FT_ENA 31 0b
BCN Rat e Drift Enable bit .
When cleared, t he rat e- drift mechanism performed by hardware is disabled. I t is
assumed soft ware handles it .
When set , t he rat e- drift mechanism performed by hardware is enabled. Rat e of BCN
rat e- cont rolled queues are periodically incr eased in a mult iplicat ive manner. Relevant
only for Tx queues for which t he RX_ENA bit is set in t he RTBCNRC regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 4: 0 00x Reserved
Rx Descript or DCA
EN
5 0b
Descript or DCA EN. When set , hardware enables DCA for all Rx descript ors writ t en back
int o memory. When cleared, hardware does not enable DCA for descript or writ e- backs.
1
1.
Rx Header DCA EN 6 0b
Rx Header DCA EN. When set , hardware enables DCA for all received header buffers.
When cleared, hardware does not enable DCA for Rx Headers.
1
Rx Payload DCA EN 7 0b
Payload DCA EN. When set , hardware enables DCA for all Et hernet payloads writ t en int o
memory. When cleared, hardware does not enable DCA for Et hernet payloads. Default
cleared.
RXdescReadROEn 9 1b Rx Descript or Read Relax Order Enable
RXdescWBROen 11 0b ( RO)
Rx Descript or Writ e Back Relax Order Enable. This bit must be 0b t o enable correct
funct ionalit y of t he descript ors writ e back.
RXdat aWrit eROEn 13 1b Rx dat a Writ e Relax Order Enable
RxRepHeaderROEn 15 1b Rx Split Header Relax Order Enable
CPUI D 31: 24 0x0
Physical I D ( see complet e descript ion in Sect ion 3. 1. 3. 1. 2) .
Legacy DCA capable plat forms t he device driver, upon discovery of t he physical CPU
I D and CPU bus I D, programs t he CPUI D field wit h t he physical CPU and bus I D
associat ed wit h t his Rx queue.
DCA 1. 0 capable plat forms t he device driver programs a value, based on t he relevant
API C I D, associat ed wit h t his Rx queue.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

512
8.2.3. 11.3 DCA Request er I D I nf or mat i on Regi st er DCA_I D ( 0x 11070; RO)
To ease soft ware implement at ion, a DCA request er I D field, composed of device I D, bus # and funct ion
# is set up in MMI O space for soft ware t o program t he chipset DCA Request er I D Aut hent icat ion
regist er.
8.2.3. 11.4 DCA Cont r ol Regi st er DCA_CTRL ( 0x 11074; RW)
Not e: This regist er is shared by bot h LAN funct ions.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Tx Descript or DCA EN 5 0b
Descript or DCA Enable. When set , hardware enables DCA for all Tx descript ors writ t en
back int o memory. When cleared, hardware does not enable DCA for descript or writ e-
backs. This bit is cleared as a default and also applies t o head writ e back when enabled.
TXdescRDROEn 9 1b Tx Descript or Read Relax Order Enable.
TXdescWBROen 11 1b Relax Order Enable of Tx Descript or as well as head point er writ e back ( when set ) .
TXDat aReadROEn 13 1b Tx Dat a Read Relax Order Enable.
CPUI D 31: 24 0x0
Physical I D ( see complet e descript ion in Sect ion 3. 1. 3. 1. 2)
Legacy DCA capable plat forms t he device driver, upon discovery of t he physical CPU
I D and CPU bus I D, programs t he CPUI D field wit h t he physical CPU and bus I D
associat ed wit h t his Tx queue.
DCA 1. 0 capable plat forms t he device driver programs a value, based on t he relevant
API C I D, associat ed wit h t his Tx queue.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Funct ion Number 2: 0 0x0
Funct ion Number.
Funct ion number assigned t o t he funct ion based on BI OS/ OS enumerat ion.
Device Number 7: 3 0x0
Device Number.
Device number assigned t o t he funct ion based on BI OS/ OS enumerat ion.
Bus Number 15: 8 0x0
Bus Number.
Bus Number assigned t o t he funct ion based on BI OS/ OS enumerat ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
DCA_DI S 0 1b
DCA Disable.
When 0b, DCA t agging is enabled for t his device.
When1b, DCA t agging is disabled for t his device.

513
8.2.3.12 Secur i t y Regi st er s
Securit y regist ers are mainly concerned wit h t he int ernal set t ings of t he AES crypt o engine shared by
LinkSec and I Psec. They are owned by t he PF in an I OV mode.
Refer t o Sect ion 4.6.12 for t he way t o modify t hese regist ers prior t o enabling or disabling a securit y
offload. Not e t hat only one securit y offload, eit her LinkSec or I Psec, can be enabled at a t ime.
Securit y offload can be disabled via int ernal securit y fuses. I n t his case, t he following securit y relat ed
fields are not writ able:
SECTXCTRL. SECTX_DI S is read as 0x1.
SECRXCTRL. SECRX_DI S is read as 0x1.
I PSTXI DX. I PS_TX_EN is read as 0x0.
I PSRXI DX. I PS_RX_EN is read as 0x0.
LSECTXCTRL bit s 1: 0 are read as 00b.
LSECRXCTRL bit s 3: 2 are read as 00b.
8.2.3.12.1 Secur i t y Tx Cont r ol SECTXCTRL ( 0x 08800; RW)
DCA_MODE 4: 1 0x0
DCA Mode
0000b = Legacy DCA is support ed. The TAG field in t he TLP header is based on t he
following coding: bit 0 is DCA enable; bit s 3: 1 are CPU I D) .
0001b = DCA 1. 0 is support ed. When DCA is disabled for a given message, t he TAG
field is 0000b, 0000b. I f DCA is enabled, t he TAG is set per queue as programmed in t he
relevant DCA Cont rol regist er.
All ot her values are undefined.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SECTX_DI S 0
1b
RW /
RO if
fused-
off
Tx Securit y Offload Disable Bit .
When set , t he AES crypt o engine used in Tx by LinkSec and I Psec off loads is disabled.
This mode must be used t o save t he 82599s power consumpt ion when no securit y
offload is enabled.
When cleared, t he AES crypt o engine used in Tx by LinkSec or I Psec off load is enabled.
Normal operat ing mode when a securit y offload is enabled.
TX_DI S 1 0b
Disable Sec Tx Pat h.
When set , no new packet is fet ched out from t he Tx packet buffers, so t hat t he Tx
securit y block can be int ernally empt ied prior t o changing t he securit y mode.
SECTXSTAT. SECTX_RDY bit is deassert ed unt il t he pat h is empt ied by hardware.
When cleared, Tx dat a pat h is enabled. Normal operat ing mode.
STORE_FORWARD 2 0b
Tx Sec Buffer Mode.
When set , a complet e frame is st ored in t he int ernal securit y Tx buffer prior t o being
forwarded t o t he MAC. Operat ing mode when I Psec offload is enabled ( as request ed t o
overwrit e I CV field in AH frames) . Not e t hat it increases t he Tx int ernal lat encies ( for all
TCs) .
When cleared, Tx sec buffer is operat ed in pass- t hr ough mode. Operat ing mode when
LinkSec is enabled or when no securit y offload is enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

514
8.2.3. 12.2 Secur i t y Tx St at us SECTXSTAT ( 0x 08804; RO)
8.2.3. 12.3 Secur i t y Tx Buf f er Al most Ful l SECTXBUFFAF ( 0x 08808; RW)
8.2.3. 12.4 Secur i t y Tx Buf f er Mi ni mum I FG SECTXMI NI FG ( 0x 08810; RW) SEC- Tx
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SECTX_RDY 0 0b
Tx securit y block ready for mode change.
When set , it indicat es t hat t he int ernal dat a pat h from t he Tx packet buffers t o t he Tx
securit y block has been empt ied, and t hus t he securit y mode can be changed by
soft ware.
When cleared, it indicat es t hat t he int ernal dat a pat h from t he Tx packet buffers t o t he
Tx securit y block is not empt y, and t hus soft ware cannot change t he securit y mode.
This bit is polled by soft ware once t he SECTXCTRL. TX_DI S bit was set .
SECTX_OFF_DI S 1 0b Securit y offload is disabled by fuse or st rapping pin.
ECC_TXERR 2 0b
Unrecoverable ECC error in t he Tx SA t able or SEC Tx FI FO occurred.
When set , it indicat es t hat an unrecoverable ECC error occurred when accessing
int ernally t he Tx SA t able. The ECC int errupt is set as well, unt il t he device is reset by
soft ware.
When cleared, no ECC er ror occurred on t he Tx SA t able from t he last t ime t he device
has reset .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FULLTHRESH 9: 0 0x250
Tx Securit y Buffer Almost Full Threshold ( relat ively t o full capacit y) . The size of t he
securit y buffer is 0x274 lines of 16 byt es. I n LinkSec offload, t he buffer operat es in
pass- t hrough mode and t he recommended t hreshold is 0x250. I t means t hat t he
almost full indicat ion is generat ed very soon while only a fract ion of a packet is st ored
in t he buffer. I n I PSec mode, t he buffer operat es in a st ore and forward mode and t he
recommended t hreshold is 0x15. I t means t hat t he almost full indicat ion is generat ed
only aft er t he buffer cont ains at least an ent ire j umbo packet .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MI NSECI FG 3: 0 0x1
Minimum I FG bet ween packet s. I t is t he minimum gap bet ween consecut ive frames
from t he DBU-Tx required for t he securit y block. The MI NSECI FG is measured in Wake
DMA clock unit s ( equal t o 6. 4 ns in 10 GbE) .
SECTXDCB 12: 8 0x10
This field is used t o configure t he Securit y Tx Buffer.
I f PFC is enabled, t hen t he SECTXDCB field should be set t o 0x1F.
I f PFC is not enabled, t hen t he default value should be used ( 0x10) .

515
8.2.3.12.5 Secur i t y Rx Cont r ol SECRXCTRL ( 0x 08D00; RW)
8. 2.3. 12. 6 Secur i t y Rx St at us SECRXSTAT ( 0x 08D04; RO)
8.2.3.13 Li nk Sec Regi st er s
The LinkSec regist ers are init ialized at soft ware reset . When LinkSec is disabled, t he LinkSec st at ist ic
regist ers are meaningless and t heir values are unpredict able.
8.2.3.13.1 Li nk Sec Tx Capabi l i t i es Regi st er LSECTXCAP ( 0x 08A00; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SECRX_DI S 0
1b
RW /
RO if
fused-
off
Rx Securit y Offload Disable Bit .
When set , t he AES crypt o engine used in Rx by LinkSec and I Psec offloads is disabled.
This mode must be used t o save t he 82599s power consumpt ion when no securit y
offload is enabled.
When cleared, t he AES crypt o engine used in Rx by LinkSec or I Psec offload is enabled.
Normal operat ing mode when a securit y offload is enabled.
RX_DI S 1 0b
Disable Sec Rx Pat h.
When set , any new packet received from t he Rx MAC is filt ered out , so t hat t he Rx
securit y block can be int ernally empt ied prior t o changing t he securit y mode.
SECRXSTAT. SECRX_RDY bit is deassert ed unt il t he pat h is empt ied by hardware.
When cleared, Rx dat a pat h is enabled. Normal operat ing mode.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SECRX_RDY 0 0b
Rx securit y block ready for mode change.
When set , it indicat es t hat t he int ernal dat a pat h from t he Rx MAC t o t he Rx securit y
block has been empt ied, and t hus t he securit y mode can be changed by soft ware.
When cleared, it indicat es t hat t he int ernal dat a pat h from t he Rx MAC t o t he Rx
securit y block is not empt y, and t hus soft ware cannot change t he securit y mode.
This bit is polled by soft ware once t he SECRXCTRL. RX_DI S bit was set .
SECRX_OFF_DI S 1 0b Securit y offload is disabled by fuse or st rapping pin.
ECC_RXERR 2 0b
Unrecoverable ECC error in an Rx SA t able occurred.
When set , it indicat es t hat an unrecoverable ECC error occurred when accessing
int ernally one Rx SA t able. The ECC int errupt is set as well, unt il t he device is reset by
soft ware.
When cleared, no ECC error occurred on t he Rx SA t able from t he last t ime device has
reset .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
NCA 2: 0 1b Tx CA- Support ed. Number of CAs support ed by t he device.
NSC 6: 3 1b
Tx SC Capable. Number of SCs support ed by t he device on t he t ransmit dat a pat h. The
82599 support s t wice t he number of SAs as t he Tx SC for seamless re- keying, such as
2 SAs.
LSECTXSUM 23: 16 0x0
Tx LSEC Key SUM. A bit wise XOR of t he LSECTXKEY 0 byt es and LSECTXKEY 1 byt es.
This regist er can be used by KaY ( t he programming ent it y) t o validat e key
programming.
I nt el

516
8.2.3. 13.2 Li nk Sec Rx Capabi l i t i es Regi st er LSECRXCAP ( 0x 08F00; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
NCA 2: 0 1b Rx CA- support ed. Number of CAs support ed by t he device.
NSC 6: 3 1b
Rx SC Capable. Number of SCs support ed by t he device on t he receive dat a pat h. The
82599 support s t wice t he number SAs as t he Rx SC for seamless re- keying, such as 2
SAs.
RXLKM 23: 16 0x0
Rx LSEC Key SUM. A byt e wise XOR of all byt es of t he Rx LinkSec keys 01 as defined in
regist ers LSECRXKEY [ n, m] . This regist er can be used by KaY ( t he programming ent it y)
t o validat e key programming.

517
8. 2.3. 13. 3 Li nk Sec Tx Cont r ol Regi st er LSECTXCTRL ( 0x 08A04; RW)
Not e: Bit s 1: 0 are RW, but t hey are RO if fused- off and/ or if SECTXCTRL. SECTX_DI S is set t o 1b, and/ or if I PSTXI DX. I PS_TX_EN is
set t o 1b.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LSTXEN 1: 0
00b
( see
Table
Not e)
Enable Tx LinkSec. Enable Tx LinkSec offloading.
00b = Disable Tx LinkSec ( Tx all packet s wit hout LinkSec offload) .
01b = Add int egrit y signat ure.
10b = Encrypt and add int egrit y signat ure.
11b = Reserved.
When t his field equals 00b ( LinkSec offload is disabled) .
The Tx Unt agged Packet regist er is not increment ed for t ransmit t ed packet s when
Enable Tx LinkSec equals 00b.
Reserved 3 0 Reserved
AI SCI 5 1b
Always I nclude SCI . This field cont rols whet her SCI is explicit ly included in t he
t ransmit t ed SecTag. Since t he ES bit in t he SecTag is fixed at Zero, t he AI SCI must
always be set t o 1b.
0b = False.
1b = True.
PNTRH 31: 8 11. . 1b
PN Exhaust ion Threshold. MSB of t he t hreshold over which hardware needs t o int errupt
KaY t o warn Tx SA PN exhaust ion and t riggers a new SA re- negot iat ion. Bit s 7: 0 of t he
t hreshold are all 1s.
I nt el

518
8.2.3. 13.4 Li nk Sec Rx Cont r ol r egi st er LSECRXCTRL ( 0x 08F04; RW)
Not e: Bit s 3: 2 are RW, but t hey are RO if fused- off and/ or if SECRXCTRL. SECRX_DI S is set t o 1b, and/ or if I PSRXI DX. I PS_RX_EN is
set t o 1b.
8.2.3. 13.5 Li nk Sec Tx SCI Low LSECTXSCL ( 0x 08A08; RW)
8.2.3. 13.6 Li nk Sec Tx SCI Hi gh LSECTXSCH ( 0x 08A0C; RW)
8.2.3. 13.7 Li nk Sec Tx SA LSECTXSA ( 0x 08A10; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LSRXEN 3: 2
00b
( see
Table
Not e)
Enable Rx LinkSec. Cont rols t he level of LinkSec packet filt ering.
00b = Disable Rx LinkSec ( pass all packet s t o host wit hout LinkSec processing and no
LinkSec header st rip) .
01b = Check ( execut e LinkSec offload and post frame t o host and ME even when it fails
LinkSec operat ion unless failed I CV and C bit was set ) .
10b = St rict ( execut e LinkSec offload and post frame t o host and ME only if it does not
fail LinkSec operat ion) .
11b = Rx LinkSec Drop ( drop all packet s t hat include LinkSec header) .
PLSH 6 0b
Post LinkSec Header. When set , t he device post s t he LinkSec header and signat ure
( I CV) t o host memory. During normal operat ion t his bit should be cleared.
RP 7 1b Replay Prot ect . Enable replay prot ect ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SecYL 31: 0 0x0
Et hernet MAC Address SecY Low. The 4 LS byt es of t he Et hernet MAC address copied t o
t he SCI field in t he LinkSec header.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SecYH 15: 0 0x0
Et hernet MAC Address SecY High. The 2 MS byt es of t he Et hernet MAC address copied
t o t he SCI field in t he LinkSec header.
PI 31: 16 0x0 Port I dent ifier. Always zero for t ransmit t ed packet s. This field is RO.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AN0 1: 0 0b
AN0 Associat ion Number 0. This 2- bit field is post ed t o t he AN field in t he t ransmit t ed
LinkSec header when SA 0 is act ive.
AN1 3: 2 0b
AN1 Associat ion Number 1. This 2- bit field is post ed t o t he AN field in t he t ransmit t ed
LinkSec header when SA 1 is act ive.
SelSA 4 0b
SA Select ( SelSA) . This bit select s bet ween SA 0 or SA 1 smoot hly, such as on a packet
boundary. A value of 0b select s SA 0 and a value of 1b select s SA 1.

519
8.2.3.13.8 Li nk Sec Tx SA PN 0 LSECTXPN0 ( 0x 08A14; RW)
Act SA ( RO) 5 0b
Act ive SA ( Act SA) . This bit indicat es t he act ive SA. The Act SA follows t he value of t he
SelSA on a packet boundary. The KaY ( t he programming ent it y) can use t his indicat ion
t o ret ire t he old SA.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PN 31: 0 0x0
PN Packet Number. This field is post ed t o t he PN field in t he t ransmit t ed LinkSec
header when SA 0 is act ive. I t is init ialized by t he KaY at SA creat ion and t hen
increment s by 1 for each t ransmit t ed packet using t his SA.
Packet s should never be t ransmit t ed if t he PN repeat s it self. I n order t o prot ect against
such an event hardware generat es an LSECPN int errupt t o KaY when t he PN reaches t he
exhaust ion t hreshold as defined in t he LSECTXCTRL regist er. There is an addit ional level
of defense against repeat ing t he PN. Hardware never t ransmit s packet s aft er t he PN
reaches a value of 0xFF. . . FF. I n order t o guarant ee it , hardware clears t he Enable Tx
LinkSec field in t he LSECTXCTRL regist er t o 00b once a packet is t ransmit t ed wit h a PN
t hat equals t o 0xFFF0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

520
8.2.3. 13.9 Li nk Sec Tx SA PN 1 LSECTXPN1 ( 0x 08A18; RW)
8.2.3. 13.10 Li nk Sec Tx Key 0 LSECTXKEY0[ n] ( 0x 08A1C + 4* n, n= 0...3; WO)
8.2.3. 13.11 Li nk Sec Tx Key 1 LSECTXKEY1[ n] ( 0x 08A2C + 4* n, n= 0...3; WO)
8.2.3. 13.12 Li nk Sec Rx SCI Low LSECRXSCL ( 0x 08F08; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PN 31: 0 0x0
PN Packet Number. This field is post ed t o t he PN field in t he t ransmit t ed LinkSec
header when SA 1 is act ive. I t is init ialized by t he KaY at SA creat ion and t hen
increment s by 1 for each t ransmit t ed packet using t his SA.
Packet s should never be t ransmit t ed if t he PN repeat s it self. I n order t o prot ect against
such an event hardware generat es an LSECPN int errupt t o KaY when t he PN reaches t he
exhaust ion t hreshold as defined in t he LSECTXCTRL regist er. There is addit ional level of
defense against repeat ing t he PN. hardware never t ransmit s packet s aft er t he PN
reaches a value of 0xFF. . . FF. I n order t o guarant ee it , hardware clears t he Enable Tx
LinkSec field in t he LSECTXCTRL regist er t o 00b once a packet is t ransmit t ed wit h a PN
t hat equals t o 0xFFF0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LSECK0 31: 0 0x0
LSEC Key 0. Transmit LinkSec key of SA 0.
n= 0 LSEC Key defines bit s 31: 0 of t he Tx LinkSec key.
This field is WO for confident ialit y prot ect ion. For dat a int egrit y check, hash value is
accessible by t he LSECTXSUM field in t he LSECCAP regist er. I f for some reason a read
request is aimed t o t his regist er a value of all zeros are ret urned.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LSECK1 31: 0 0x0
LSEC Key 1. Transmit LinkSec key of SA 1.
This field is WO for confident ialit y prot ect ion. For dat a int egrit y check, hash value is
accessible by t he LSECTXSUM field in t he LSECCAP regist er. I f for some reason a read
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MAL 31: 0 0x0
Et hernet MAC Address SecY low. The 4 LS byt es of t he Et hernet MAC address in t he SCI
field in t he incoming packet t hat are compared wit h t his field for SCI mat ching.
Comparison result is meaningful only if t he SC bit in t he TCI header is set .

521
8. 2.3. 13. 13 Li nk Sec Rx SCI Hi gh LSECRXSCH ( 0x 08F0C; RW)
8.2.3.13.14 Li nk Sec Rx SA Regi st er s
The regist ers in t his sect ion relat e t o t he LinkSec receive SA cont ext . There are 2 SA( s) in t he receive
dat a pat h defined as SA0 and SA1. The following regist ers wit h index n relat es t o t he SA index.
8.2.3.13.15 Li nk Sec Rx SA LSECRXSA[ n] ( 0x 08F10 + 4* n, n= 0...1; RW)
8.2.3.13.16 Li nk Sec Rx SA PN LSECRXPN[ n] ( 0x 08F18 + 4* n, n= 0...1; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MAH 15: 0 0x0
Et hernet MAC Address SecY High. The 2 MS byt es of t he Et hernet MAC address in t he
SCI field in t he incoming packet t hat are compared wit h t his field for SCI mat ching.
Comparison result is meaningful only if t he SC bit in t he TCI header is set .
Not e: Field is defined in Big Endian ( MS byt e is last on t he wire) .
PI 31: 16 0x0
Por t I dent ifier. The por t number in t he SCI field in t he incoming packet t hat is
compared wit h t his field for SCI mat ching. Comparison result is meaningful only if t he
SC bit in t he TCI header is set .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AN 1: 0 00b
AN Associat ion Number. This field is compared wit h t he AN field in t he TCI field in t he
incoming packet for mat ch.
SAV 2 0b SA Valid. This bit is set or cleared by t he KaY t o validat e or invalidat e t he SA.
FRR ( RO) 3 0b
Frame Received. This bit is cleared when t he SA Valid ( bit 2) t ransit ions from 0b t o 1b,
and is set when a frame is received wit h t his SA. When t he Frame Received bit is set
t he Ret ired bit of t he ot her SA of t he same SC is set .
Not e t hat a single frame recept ion wit h t he new SA is sufficient t o ret ire t he old SA
since it is assumed t hat t he replay window is zero.
Ret ired ( RO) 4 0b
Ret ired. When t his bit is set , t he SA is invalid ( ret ired) . This bit is cleared when a new
SA is configured by t he KaY ( SA Valid t ransit ion t o 1b) . I t is set t o 1b when a packet is
received wit h t he ot her SA of t he same SC.
Not e t hat a single frame recept ion wit h t he new SA is sufficient t o ret ire t he old SA
since it is assumed t hat t he replay window is zero.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PN 31: 0 0x0
PN Packet Number. Regist er n holds t he PN field of t he next incoming packet t hat
uses SA n, n = 0, 1. The PN field in t he incoming packet must be great er or equal t o
t he PN regist er. The PN regist er is set by KaY at SA creat ion. I t is updat ed by hardware
for each received packet using t his SA t o be received PN + 1.
Not e: Field is defined in Big Endian ( LS byt e is first on t he wire) .
I nt el

522
8.2.3. 13.17 Li nk Sec Rx Key LSECRXKEY[ n, m] ( 0x 08F20 + 0x 10* n + 4* m, n= 0...1,
m= 0...3; WO)
8. 2.3. 14 Li nk Sec Tx Por t St at i st i cs
These count ers are defined by t he specificat ion as 64 bit s while implement ing only 32 bit s in hardware.
The KaY must implement t he 64- bit count er in soft ware by polling regularly t he hardware st at ist ic
count ers. Hardware count ers wrap around from 0xFF. .F t o 0x0 and cleared on read.
Not e t hat 82599 includes a 10 KB FI FO bet ween t he securit y block out put and t he MAC block. I n t he
case of a pause event , packet s st ored in t his FI FO are dropped for inst ant response t o t he pause
request . When it is t ime t o resume t ransmission, t he packet s are re- t ransmit t ed from t he t ransmit
packet buffer t o t he securit y block. These re- t ransmit t ed packet s are count ed t wice in all t he relevant
securit y t ransmit count ers.
8.2.3. 14.1 Tx Unt agged Pack et Count er LSECTXUT ( 0x 08A3C; RW)
8.2.3. 14.2 Encr ypt ed Tx Pack et s LSECTXPKTE ( 0x 08A40; RW)
8.2.3. 14.3 Pr ot ect ed Tx Pack et s LSECTXPKTP ( 0x 08A44; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LSECK 31: 0 0x0
LSEC Key. Receive LinkSec key of SA n, while n= 0. . . 1.
m= 0 LSEC Key defines bit s 31: 0 of t he Rx LinkSec key.
This field is WO for confident ialit y prot ect ion. For dat a int egrit y check, KaY hash value is
accessible by t he LSECRXSUM field in t he LSECCAP regist ers. I f for some reason a read
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
UPC 31: 0 0x0
Unt agged Packet CNT. I ncrement s for each t ransmit t ed packet t hat is t ransmit t ed wit h
t he I LSec bit cleared in t he packet descript or while Enable Tx LinkSec field in t he
LSECTXCTRL regist er is eit her 01b or 10b. The KaY must implement a 64- bit count er. I t
can do t hat by reading t he LSECTXUT regist er regularly.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EPC 31: 0 0x0
Encrypt ed Packet CNT. I ncrement s for each t ransmit t ed packet t hrough t he cont rolled
port wit h t he E bit set ( such as confident ialit y was prescribed for t his packet by
soft ware/ firmware) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PPC 31: 0 0x0
Prot ect ed Packet CNT. I ncrement s for each t ransmit t ed packet t hrough t he cont rolled
port wit h t he E bit cleared ( such as int egrit y only was prescribed for t his packet by
soft ware/ firmware) .

523
8. 2.3. 14. 4 Encr y pt ed Tx Oct et s LSECTXOCTE ( 0x 08A48; RW)
8.2.3.14.5 Pr ot ect ed Tx Oct et s LSECTXOCTP ( 0x 08A4C; RW)
8.2.3.15 Li nk Sec Rx Por t St at i st i c Count er s
count ers.
8.2.3.15.1 Li nk Sec Unt agged Rx Pack et LSECRXUT ( 0x 08F40; RC)
8.2.3.15.2 Li nk Sec Rx Oct et s Decr ypt ed LSECRXOCTE ( 0x 08F44; RC)
8.2.3.15.3 Li nk Sec Rx Oct et s Val i dat ed LSECRXOCTP ( 0x 08F48; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EOC 31: 0 0x0
Encrypt ed Oct et CNT. I ncrement s for each byt e of user dat a t hrough t he cont rolled port
wit h t he E bit set ( such as confident ialit y prescribed for t his packet by soft ware/
firmware) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
POC 31: 0 0x0
Prot ect ed Oct et CNT. I ncrement s for each byt e of user dat a t hrough t he cont rolled port
wit h t he E bit cleared such as int egrit y only was prescribed for t his packet by soft ware/
firmware) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
UPC 31: 0 0x0
Unt agged Packet CNT. I ncrement s for each packet received having no t ag. Also
increment s for any KaY packet s regardless of t he LinkSec t ag. I ncrement s only when
t he Enable Rx LinkSec field in t he LSECRXCTRL regist er is eit her 01b or 10b.
Not e t hat flow cont rol frames are also count ed by t his count er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
DROC 31: 0 0x0
Decrypt ed Rx Oct et CNT. The number of oct et s of user dat a recovered from received
frames t hat were bot h int egrit y prot ect ed and encrypt ed. This includes t he oct et s from
SecTag t o I CV not inclusive. These count s are increment ed even if t he user dat a
recovered failed t he int egrit y check or could not be recovered.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VOC 31: 0 0b
Validat ed Rx Oct et CNT. The number of oct et s of user dat a recovered from received
frames t hat were int egrit y prot ect ed but not encrypt ed. This includes t he oct et s from
SecTag t o I CV not inclusive. These count s are increment ed even if t he user dat a
recovered failed t he int egrit y check or could not be recovered.
I nt el

524
8.2.3. 15.4 Li nk Sec Rx Pack et w i t h Bad Tag LSECRXBAD ( 0x 08F4C; RC)
8.2.3. 15.5 Li nk Sec Rx Pack et No SCI LSECRXNOSCI ( 0x 08F50; RC)
8.2.3. 15.6 Li nk Sec Rx Pack et Unk now n SCI LSECRXUNSCI ( 0x 08F54; RC)
8. 2.3. 16 Li nk Sec Rx SC St at i st i c Count er s
count ers. Hardware count ers wrap around from 0xFF. .F t o 0x0 and cleared on read.
8.2.3. 16.1 Li nk Sec Rx Uncheck ed Pack et s LSECRXUC ( 0x 08F58; RC)
Soft ware/ firmware needs t o maint ain t he full- sized regist er.
8.2.3. 16.2 Li nk Sec Rx Del ayed Pack et s LSECRXDELAY ( 0x 08F5C; RC)
8.2.3. 16.3 Li nk Sec Rx Lat e Pack et s LSECRXLATE ( 0x 08F60; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BRPC 31: 0 0b Bad Rx Packet CNT. Number of packet s received having a invalid t ag.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
USRPC 31: 0 0b
No SCI Rx Packet CNT. Number of packet s r eceived wit h unrecognizable SCI and
dropped due t o t hat condit ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
USRPC 31: 0 0b
Unknown SCI Rx Packet CNT. Number of packet s received wit h an unrecognized SCI but
st ill forwarded t o t he host .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
URPC 31: 0 0x0
Unchecked Rx Packet CNT. Number of packet s received wit h LinkSec encapsulat ion
( SecTag) while Validat e Frames is disabled ( LSECRXCTRL bit s 3: 2 equal 00b) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
DRPC 31: 0 0x0
Delayed Rx Packet CNT. Number of packet s received and accept ed for validat ion having
failed replay prot ect ion and Replay Prot ect is false ( LSECRXCTRL bit 7 is 0b) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LRPC 31: 0 0x0
Lat e Rx Packet CNT. Number of packet s received and accept ed for validat ion having
failed replay- prot ect ion and Replay Prot ect is t rue ( LSECRXCTRL bit 7 is 1b) .

525
8.2.3.17 Li nk Sec Rx SA St at i st i c Count er s
count ers. Hardware count ers wrap around from 0xFF.. F t o 0x0 and cleared on read.
8.2.3.17.1 Li nk Sec Rx Pack et OK LSECRXOK[ n] ( 0x 08F64 + 4* n, n= 0...1; RC)
8.2.3.17.2 Li nk Sec Rx I nval i d LSECRXI NV[ n] ( 0x 08F6C + 4* n, n= 0...1; RC)
8.2.3.17.3 Li nk Sec Rx Not val i d count LSECRXNV[ n] ( 0x 08F74 + 4* n, n= 0...1; RC)
8.2.3.17.4 Li nk Sec Rx Unused SA Count LSECRXUNSA ( 0x 08F7C; RC)
8.2.3.17.5 Li nk Sec Rx Not Usi ng SA Count LSECRXNUSA ( 0x 08F80; RC)
8.2.3.18 I Psec Regi st er s
I Psec regist ers are owned by t he PF in an I OV mode.
Unlike LinkSec, t here is no added value here t o encrypt t he SA cont ent s when being read by soft ware
because t he SA cont ent s is available in clear t ext from syst em memory like for any I Psec flow handled
in soft ware.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
ORPC 31: 0 0x0
OK Rx Packet CNT. Number of packet s received t hat were valid ( aut hent icat ed) and
passed replay prot ect ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I CRPC 31: 0 0x0
I nvalid Rx Packet CNT. Number of packet s received t hat were not valid ( aut hent icat ion
failed) and were forwarded t o host .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I CRPC 31: 0 0x0
Not valid Rx Packet CNT. Number of packet s received t hat were not valid ( aut hent icat ion
failed) and were dropped.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I SSRPC 31: 0 0x0
I nvalid SA Rx Packet CNT. Number of packet s received t hat were associat ed wit h an SA
t hat is not in use ( no mat ch on aut o- negot iat ion or not valid or ret ired) and were
forwarded t o host .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I SSRPC 31: 0 0x0
I nvalid SA Rx Packet CNT. Number of packet s received t hat were associat ed wit h an SA
t hat is not in use ( No mat ch on aut o- negot iat ion or not valid or ret ired) and were
dropped.
I nt el

526
8.2.3. 18.1 I Psec Tx I ndex I PSTXI DX ( 0x 08900; RW)
Not es: Writ e and Read bit s must not be set at t he same t ime by soft ware.
I PS_TX_EN is RW, but it is RO if fused- off and/ or if SECTXCTRL. SECTX_DI S is set t o 1b.
8.2.3. 18.2 I Psec Tx Key Regi st er s I PSTXKEY[ n] ( 0x 08908 + 4* n, n= 0...3; RW)
8.2.3. 18.3 I Psec Tx Sal t Regi st er I PSTXSALT ( 0x 08904; RW)
8.2.3. 18.4 I Psec Rx I ndex I PSRXI DX ( 0x 08E00; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PS_TX_EN 0
0b
( see
t able
not e)
I Psec Tx offload enable bit .
When set , I Psec offload abilit y is enabled for t he Tx pat h.
When cleared, I Psec offload abilit y is disabled for t he Tx pat h, regardless of t he
cont ent s of t he Tx SA t able.
SA_I DX 12: 3 0x0 SA index for indirect access int o t he Tx SA t able.
READ 30
0b
SC by
HW
Read Command.
When set , t he cont ent s of t he Tx SA t able ent ry point ed by t he SA_I DX field is loaded
int o t he I PSTXKEY 0. . . 3 and I PSTXSALT regist ers.
I mmediat ely self cleared by hardware once t he ent ry cont ent s has been loaded int o t he
regist ers.
WRI TE 31
0b
SC by
HW
Writ e Command.
When set , t he cont ent s of t he I PSTXKEY 0.. . 3 and I PSTXSALT regist ers are loaded int o
t he Tx SA t able ent ry point ed t o by t he SA_I DX field.
I mmediat ely self cleared by hardware once t he ent ry cont ent s have been loaded int o
t he memory.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AES- 128 KEY 31: 0 0x0
4 byt es of a 16- byt e key t hat has been read/ writ t en from/ int o t he Tx SA ent ry point ed
t o by SA_I DX.
n= 0 cont ains t he LSB of t he key.
n= 3 cont ains t he MSB of t he key.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AES- 128 SALT 31: 0 0x0 4- byt e salt t hat has been read/ writ t en from/ int o t he Tx SA ent ry point ed t o by SA_I DX.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PS_RX_EN 0
0b
( see
t able
not e)
I Psec Rx offload enable bit .
When set , I Psec offload abilit y is enabled for t he Rx pat h.
When cleared, I Psec offload abilit y is disabled for t he Rx pat h, regardless of t he
cont ent s of Rx SA t ables.
TABLE 2: 1 00b
Table select bit s.
00b = No Rx SA t able is accessed.
01b = I P address t able is accessed.
10b = SPI t able is accessed.
11b = Key t able is accessed.

527
Not es: Writ e and Read bit s must not be set at t he same t ime by soft ware.
I PS_RX_EN is RW, but it is RO if fused- off and/ or if SECRXCTRL. SECRX_DI S is set t o 1b.
Soft ware is not allowed t o writ e/ read access regist ers t hat belong t o different Rx SA t ables wit hout writ ing t he I PSRXI DX
regist er in bet ween for set t ing t he Writ eRead bit . Refer t o Rx SA t ables access rules described in Sect ion 7. 12. 9. 2.
Soft ware should not make changes in t he Rx SA t ables while changing t he I PSEC_EN bit .
8.2.3.18.5 I Psec Rx I P addr ess Regi st er I PSRXI PADDR ( 0x 08E04 + 4* n, n= 0.. . 3; RW)
These regist ers are relat ed t o t he I P Address t able.
8.2.3.18.6 I Psec Rx SPI Regi st er I PSRXSPI ( 0x 08E14; RW)
This regist er is relat ed t o t he Rx SPI t able.
TB_I DX 12: 3 0x0
Table index bit s for indirect access int o t he Rx SA t able select ed by t he Table bit s.
When accessing t he I P address t able, only t he seven least significant bit s of t his field
are meaningful.
READ 30
0b
SC by
HW
Read Command.
When set , t he cont ent s of t he Rx SA t able ent ry as point ed t o by t he [ TABLE, TB_I DX]
fields is loaded int o t he corresponding regist ers.
t he corresponding regist ers.
For inst ance, if t his bit is set t oget her wit h Table= 10b and TB_I DX= 0x9, t hen t he SPI
value st ored in ent ry nine is loaded int o t he I PSRXSPI 0. . . 3 regist ers. Rx SA regist ers
relat ed t o anot her Rx SA t able ( like I PSRXKEY 0. . . 3 regist ers) must not be read when
Table= 01b.
WRI TE 31
0b
SC by
HW
Writ e command.
When set , t he cont ent s of t he regist ers affect ed by t he Rx SA t able point ed t o by t he
Table field is loaded int o t he t able ent ry point ed t o by t he TB_I DX field.
t he memory.
For inst ance, if t his bit is set t oget her wit h Table= 10b and TB_I DX= 0x9, t hen t he value
writ t en in I PSRXSPI 0. . . 3 regist ers is loaded int o t he SPI t able ent ry nine.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PADDR 31: 0 0x0
4 byt es of a16- byt e dest inat ion I P address for t he associat ed Rx SA( s) .
n= 0 cont ains t he MSB for an I Pv6 I P address.
n= 3 cont ains an I Pv4 I P address or t he LSB for an I Pv6 I P address.
For an I Pv4 address, I PSRXI PADDR 0. . . 2 must be writ t en wit h zeros.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SPI 31: 0 0x0
SPI field for t he SPI ent ry.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

528
8.2.3. 18.7 I Psec Rx SPI Regi st er I PSRXI PI DX ( 0x 08E18; RW)
This regist er is relat ed t o t he Rx SPI t able.
8.2.3. 18.8 I Psec Rx Key Regi st er I PSRXKEY[ n] ( 0x 08E1C + 4* n, n= 0. ..3; RW)
These regist ers are relat ed t o t he Rx KEY t able.
8.2.3. 18.9 I Psec Rx Sal t Regi st er I PSRXSALT ( 0x 08E2C; RW)
This regist er is relat ed t o t he Rx KEY t able.
8.2.3. 18.10 I Psec Rx Mode Regi st er I PSRXMOD ( 0x 08E30; RW)
This regist er is relat ed t o t he Rx KEY t able.

Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I P_I DX 6: 0 0x0
I P I ndex.
I ndex in t he I P address t able where t he dest inat ion I P address associat ed t o t hat SPI
ent ry is found.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AES- 128 KEY 31: 0 0x0
4 byt es of a16- byt e key of t he KEY ent ry.
n= 0 cont ains t he LSB of t he key.
n= 3 cont ains t he MSB of t he key.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AES- 128 SALT 31: 0 0x0 4- byt e salt associat ed t o t he KEY ent ry.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VALI D 0 0b
Valid Bit .
When set , t he KEY ent ry is valid.
When cleared, t he KEY ent ry is not valid.
PROTO 2 0b
I Psec Prot ocol Select .
When set , t he KEY ent ry offloads ESP packet s.
When cleared, t he KEY ent ry offloads AH packet s.
DECRYPT 3 0b
Decrypt ion Bit .
When set , hardware performs decrypt ion offload for t his KEY ent ry.
Meaningful only if t he Prot o bit is set ( like ESP mode) .
I Pv6 4 0b
I Pv6 Type.
When set , only mat ched I Pv6 packet s are offloaded for t hat KEY ent ry.
When cleared, only mat ched I Pv4 packet s are offloaded for t hat KEY ent ry.

529
8.2.3.19 Ti mer s Regi st er s
8.2.3.19.1 TCP Ti mer TCPTI MER ( 0x 0004C; RW)
8.2.3.20 FCoE Regi st er s
FCoE Rx regist ers
8.2.3.20.1 FC Recei ve Cont r ol FCRXCTRL ( 0x 05100; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Durat ion 7: 0 0x0
Durat ion.
Durat ion of t he TCP int errupt int erval, in ms.
KickSt art 8 0b
Count er kickst art .
Writ ing a 1b t o t his bit kickst art s t he count er down- count from t he init ial value defined
in t he Durat ion field. Writ ing 0b has no effect ( WS) .
TCPCount En 9 0b
TCP Count Enable.
When 1b, TCP t imer count ing is enabled. When 0b, it is disabled.
Upon enabling, TCP count er must count from it s int ernal st at e. I f t he int ernal st at e is
equal t o zero, down- count does not rest art unt il KickSt art is act ivat ed. I f t he int ernal
st at e is not 0b, down- count cont inues from t he int ernal st at e. This enables a pause of
t he count ing for debug purposes.
TCPCount Finish 10 0b
TCP Count Finish.
This bit enables soft ware t o t rigger a TCP t imer int errupt , regardless of t he int ernal
st at e.
Writ ing a 1b t o t his bit t riggers an int errupt and reset s t he int ernal count er t o it s init ial
value. Down- count does not rest art unt il eit her KickSt art is act ivat ed or Loop is set .
Writ ing 0b t o t his bit has no effect ( WS) .
Loop 11 0b
TCP Loop.
When 1b, t he TCP count er must reload durat ion each t ime it reaches zero, and must go
on down- count ing from t his point wit hout kickst art ing.
When 0b, TCP count er must st op at a zero value, and must not rest art unt il KickSt art is
act ivat ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FCOELLI 0 0b
Low Lat ency I nt errupt by FCoE Frame. When set t o 1b any FCP- RSP frame or last dat a
packet in a sequence wit h t he Sequence I nit iat ive bit set , generat es a Low Lat ency
I nt errupt ( LLI ) .
SavBad 1 0
Enable Save Bad Frame. Whenset t o 1b, frames wit h good Et hernet CRC and bad FC
CRC are post ed t o t he legacy receive queues. I f t he SavBad bit is set t o 0b, such frames
are discarded. I n bot h cases frames wit h bad FC CRC increment t he FCCRC st at ist ic
count er.
FRSTRDH 2 0
Enable First Read Packet Header. This field impact s received packet s t hat are offloaded
by Large FC receive while t heir FC payload is post ed direct ly t o t he user buffers. When
set , headers of t he first frame t hat mat ches an FC DDP cont ext are post ed t o t he legacy
receive queues.
LASTSEQH 3 0
Enable Headers of Last Frame in a Sequence. This field impact s received packet s t hat
are offloaded by Large FC receive while t heir FC payload is post ed direct ly t o t he user
buffers. When set , headers of Last Frame in a Sequence are post ed t o t he legacy receive
queues.
I nt el

530
8.2.3. 20.2 FCoE Redi r ect i on Cont r ol FCRECTL ( 0x 0ED00; RW)
8.2.3. 20.3 FCoE Redi r ect i on Tabl e FCRETA[ n] ( 0x 0ED10 + 4* n, n= 0...7; RW)
8.2.3. 20.4 FC User Descr i pt or PTR Low FCPTRL ( 0x 02410; RW)
8.2.3. 20.5 FC User Descr i pt or PTR Hi gh FCPTRH ( 0x 02414; RW)
8.2.3. 20.6 FC Buf f er Cont r ol FCBUFF ( 0x 02418; RW)
ALLH 4 0
Enable All Headers. This field impact s received packet s t hat are offloaded by Large FC
receive while t heir FC payload is post ed direct ly t o t he user buffers. When set , headers
of any received packet are post ed t o t he legacy receive queues.
FRSTSEQH 5 0
Enable First Sequence Packet Header. This field impact s received packet s t hat are off-
loaded by Large FC receive while t heir FC payload is post ed direct ly t o t he user buffers.
When set , headers of t he first frame in any sequence are post ed t o t he legacy receive
queues.
I CRC 6 0
I gnore Bad FC CRC. When set , t he 82599 ignores bad FC CRC. I n t his case packet s
might be processed by t he Large FC receive even if t hey car r y bad FC CRC.
FCCRCBO 7 1
FC CRC Byt e Ordering. Whenset t o 1b, t he FC CRC byt es are t reat ed in Rx as big Endian.
Whenset t o 0b, t he FC CRC are t reat ed as lit t le endian ( as Et hernet CRC) . This bit should
be set t o t he same value as DMATXCTL. FCCRCBO.
FCOEVER 11: 8 0
Support ed FCoE Version Number. FCoE frames t hat carry higher version number t han
FCOEVER are not processed by t he FCoE Rx offload logic.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
ENA 0 0b
FC Redirect ion Enable. When cleared, t he redirect ion t able is not act ive. When set t o 1b
t he FC redirect ion is enabled.
Sof t w ar e Not e: When FC redirect ion is enabled, t he Pool Enable and t he Queue Enable
bit s in t he ETQF and ETQS regist ers must be cleared for FCoE dat a packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Table Ent ry 6: 0 0x0
Table Ent ry. Defines t he redirect ion out put queue number. Regist er ' n' is t he t able ent ry
index ' n' which is t he mat ched value t o t he 3 LS bit s of t he FC exchange I D.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTR_LOW 31: 0 N/ A
User Descript or PTR Low. Four least significant byt es of t he physical point er t o t he user
descript or list . The point er must be 16- byt e aligned so t he four LS bit s are read only as
zeros.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTR_HI 31: 0 N/ A
User Descript or PTR High. Four most significant byt es of t he physical point er t o t he user
descript or list .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

531
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Valid 0 0b
DMA Cont ext Valid. When set t o 1b indicat es t hat t he cont ext is valid. I f soft ware clears
t he Cont ext Valid bit , soft ware should poll it unt il it is act ually cleared by hardware
before unlocking t he user buffers.
First 1 0b
DMA First . This bit is a st at us indicat ion. Soft ware should clear it during FC cont ext
programming. The DMA unit set s t his bit when it receives a frame t hat mat ches t he
cont ext and marked by t he filt er unit as first .
Last 2 0b
DMA Last . This bit is a st at us indicat ion. Soft ware should clear it during FC cont ext
programming. Hardware set s t his bit when it exhaust s t he last user buffer.
BUFFSI ZE 4: 3 00b
Buffer Size. This field defines t he user buffer size used in t his cont ext as follows:
00b = 4 KB.
10b = 16 KB.
01b = 8 KB.
11b = 64 KB.
WRCONTX 7 0b
Writ e DDP Cont ext . This bit should be set t o 1b for writ e exchange cont ext aimed for
t arget ( responder) usage. This bit should be set t o 0b for read exchange cont ext aimed
for init iat or ( originat or) usage.
BUFFCNT 15: 8 0x0
Buffer Count . Defines t he number of t he user buffers while 0x0 equals 256. I t is
programmed by soft ware and updat ed by hardware during recept ion.
Offset 31: 16 0x0
User Buffer Offset . Byt e offset wit hin t he user buffer t o which t he FC dat a of large FC
receive should be post ed.
I nt el

532
8.2.3. 20.7 FC Recei ve DMA RW FCDMARW ( 0x 02420; RW)
8.2.3. 20.8 FC FLT Cont ex t FCFLT ( 0x 05108; RW)
8.2.3. 20.9 FC Of f set Par amet er FCPARAM ( 0x 051D8; RW)
8.2.3. 20.10 FC Fi l t er RW Cont r ol FCFLTRW ( 0x 05110; WO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FCoESEL 8: 0 0x0
FCoE cont ext Select . This field defines t he FCoE Rx cont ext index ( equals t he OX_I D for
t hat cont ext ) .
Reserve 12: 9 0x0 Reserved.
Reserved 13 0 Reserved
WE 14 0b
Writ e Enable. When t his bit is set , t he cont ent of FCPTRL, FCPTRH and FCBUFF regist ers
are programmed t o t he FCoE DMA cont ext of index FCoESEL. This bit should never be
set t oget her wit h t he RE bit in t his regist er.
RE 15 0b
Read Enable. When t his bit is set , t he int ernal FCoE DMA cont ext of index FCoESEL is
fet ched t o t he FCPTRL, FCPTRH and FCBUFF regist ers. This bit should never be set
t oget her wit h t he WE bit in t his regist er.
LASTSI ZE 31: 16 0x0 Last User Buffer Size. Defines t he size in byt es of t he last user buffer.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Valid 0 N/ A Filt er Cont ext Valid. When set t o 1b indicat es t hat t he cont ext is valid.
First 1 N/ A
Filt er First . This bit is a st at us indicat ion. Soft ware should clear it during FC cont ext
programming. The filt er unit set s t his bit when it receives a first frame t hat mat ches t he
cont ext .
Reserved 7: 2 N/ A Reserved.
SEQ_I D 15: 8 N/ A
Sequence I D. The sequence I D of t he last received frame. I nit ialized t o 0x0 by t he
driver at cont ext programming.
SEQ_CNT 31: 16 N/ A
Sequence Count . The sequence count of t he expect ed received frame. I nit ialized t o 0x0
by t he driver at cont ext programming.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PARAM 31: 0 0x0
FC Paramet er. This field cont ains t he expect ed FC paramet er in t he next received frame.
I nit ialized t o 0x0 by t he driver at cont ext programming.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FCoESEL 8: 0 0x0
FCoE cont ext Select . This field defines t he FCoE Rx cont ext index ( equals t he OX_I D for
t hat cont ext ) .
Re-Validat e 13 0b
Fast re-validat ion of t he filt er cont ext . Set t ing t his bit t oget her wit h t he WE bit in t his
regist er validat es t he select ed filt er cont ext . Hardware set s t he Valid bit and clears t he
First bit ( described in t he FCFLT regist er) while keeping all ot her filt er paramet ers int act .
WE 14 0b
Writ e Enable. When t his bit is set , t he cont ent of t he FCFLT regist er is programmed t o
t he filt er of index FCoESEL. This bit should never be set t oget her wit h t he RE bit in t his
regist er.

533
8.2. 3.21 Fl ow Di r ect or Regi st er s
Gl obal set t i ngs r egi st er s.
8.2.3.21.1 Fl ow Di r ect or Fi l t er s Cont r ol Regi st er FDI RCTRL ( 0x 0EE00; RW)
Not e: This regist er should be configured ONLY as part of t he flow direct or init ializat ion flow or
clearing t he flow direct or t able. Programming of t his regist er wit h non-zero value PBALLOC
init ializes t he flow direct or t able.
RE 15 0b
Read Enable. When t his bit is set , t he int ernal filt er cont ext of index FCoESEL is fet ched
t o t he FCFLT regist er. This bit should never be set t oget her wit h t he WE bit in t his
regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PBALLOC 1: 0 00b
Memory allocat ion for t he flow direct or filt ers.
00b = No memory allocat ion Flow Direct or Filt ers are disabled
01b = 64 KB ( 8 K minus 2 signat ure filt ers or 2 K minus 2 perfect mat ch filt ers) .
I NI T- Done 3 0b
Flow direct or init ializat ion complet ion indicat ion ( read only st at us) . I ndicat es t hat
hardware init ialized t he flow direct or t able according t o t he PBALLOC set t ing. Soft ware
must not access any ot her flow direct or filt ers regist ers before t he I NI T- Done bit is set .
When flow direct or filt ers are enabled ( PBALLOC > 0) , soft ware must wait for t he I NI T-
Done indicat ion before Rx is enabled.
Perfect - Mat ch 4 0b
Flow direct or filt ers mode of operat ion. When set t o 1b, hardware support s perfect
mat ch filt ers according t o PBALLOC. When cleared t o 0b, hardware support s signat ure
filt ers according t o PBALLOC.
Report - St at us 5 0b
Report flow direct or filt er' s st at us in t he RSS field of t he Rx descript or for packet s t hat
mat ches a flow direct or filt er. Enabling t he flow direct or filt er' s st at us, t he
RXCSUM. PCSD bit should be set as well ( disabling t he fragment checksum) . Not e t hat
t he Flow Direct or Filt er St at us and Error bit s in t he Ext ended St at us and Error fields in
t he Rx descript or are always enabled.
Report - St at us always 7 0b
Report flow direct or st at us in t he RSS field of t he Rx descript or on any packet t hat can
be candidat es for t he flow direct or filt ers. This bit can be set t o 1b only when bot h t he
RXCSUM. PCSD bit and t he Report - St at us bit in t his regist er are set .
Drop- Queue 14: 8 0x0
Absolut e Rx queue index used for t he dropped packet s. Soft ware can set t his queue t o
an empt y one by set t ing RDLEN[ n] t o 0x0.
Flex- Offset 20: 16 0x0
Offset wit hin t he first 64 byt es of t he packet of a flexible 2- byt e t uple. The offset is
defined in word unit s count ed from t he first byt e of t he dest inat ion Et hernet MAC
address.
Max- Lengt h 27: 24 0x0
Maximum linked list lengt h. This field defines t he maximum recommended linked list
associat ed t o any hash value ( defined in unit s of t wo filt ers) . Packet s t hat mat ch filt ers
t hat exceed t he Max- Lengt h are report ed wit h an act ive Lengt h bit in t he Ext ended Error
field. I n addit ion, drop filt ers t hat exceed t he Max- Lengt h are post ed t o t he Rx queue
defined in t he filt er cont ext rat her t han t he Drop- Queue defined in t his regist er.
Not e: Soft ware should set t his field t o a value t hat indicat es except ional long bucket s.
Support ing 32 K filt ers wit h good hash scheme key, it is expect ed t hat a value of 0xA
can be a good choice.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

534
8.2.3. 21.2 Fl ow Di r ect or Fi l t er s Look up Tabl e HASH Key FDI RHKEY ( 0x 0EE68; RW)
8.2.3. 21.3 Fl ow Di r ect or Fi l t er s Si gnat ur e Hash Key FDI RSKEY ( 0x 0EE6C; RW)
8.2.3. 21.4 Fl ow Di r ect or Fi l t er s DI Pv4 Mask FDI RDI P4M ( 0x 0EE3C; RW)
8.2.3. 21.5 Fl ow Di r ect or Fi l t er s Sour ce I Pv4 Mask FDI RSI P4M ( 0x 0EE40; RW)
8.2.3. 21.6 Fl ow Di r ect or Fi l t er s TCP Mask FDI RTCPM ( 0x 0EE44; RW)
Full-Thresh 31: 28 0x0
Full t hreshold is a recommended minimum number of flows t hat should remain unused
( defined in unit s of 16 filt ers) . When soft ware exceeds t his t hreshold ( t oo low number of
unused flows) , hardware generat es t he flow direct or full int errupt . Soft ware should
avoid addit ional programming following t his int errupt . Not e t hat when t he flow direct or
filt ers are used complet ely, hardware discards silent ly furt her filt ers programming.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Key 31: 0
0x8000
0001
Programmable hash lookup t able key.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Key 31: 0
0x8080
0101
Programmable Signat ure Key.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PM 31: 0 0x0
Mask Dest inat ion I Pv4 Address. Each cleared bit means t hat t he associat ed bit of t he
dest inat ion I Pv4 address is meaningful for t he filt ering funct ionalit y. Each bit set t o 1b
means t hat t he associat ed bit of t he dest inat ion I Pv4 address is ignored ( masked out ) .
The LS bit of t his regist er mat ches t he first byt e on t he wire.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PM 31: 0 0x0
Mask Source I Pv4 Address. Each cleared bit means t hat t he associat ed bit of t he source
I Pv4 address is meaningful for t he filt ering funct ionalit y. Each bit set t o 1b means t hat
t he associat ed bit of t he source I Pv4 address is ignored ( masked out ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SPort M 15: 0 0x0
Mask TCP Source Port . Each cleared bit means t hat t he associat ed bit of t he TCP source
port is meaningful for t he filt ering funct ionalit y. Each bit set t o 1b means t hat t he
associat ed bit of t he TCP source port is ignored ( masked out ) .
Not e t hat t his regist er is swizzle as follows: bit 0 in t he mask affect s bit 15 of t he source
port as defined in FDI RPORT. Source. bit 1 in t he mask affect s bit 14 in
FDI RPORT. Source and so on while bit 15 in t he mask affect s bit 0 in FDI RPORT. Source.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

535
8.2.3.21.7 Fl ow Di r ect or Fi l t er s UDP Mask FDI RUDPM ( 0x 0EE48; RW)
8.2.3.21.8 Fl ow Di r ect or Fi l t er s I Pv6 Mask FDI RI P6M ( 0x 0EE74; RW)
8.2.3.21.9 Fl ow Di r ect or Fi l t er s Ot her Mask FDI RM ( 0x 0EE70; RW)
DPort M 31: 16 0x0
Mask TCP Dest inat ion Port . Each cleared bit means t hat t he associat ed bit of t he TCP
dest inat ion port is meaningful for t he filt er ing funct ionalit y. Each bit set t o 1b means
t hat t he associat ed bit of t he TCP dest inat ion port is ignored ( masked out ) .
Not e t hat t his regist er is swizzle t he same as t he FDI RTCPM. SPort M.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SPort M 15: 0 0x0
Mask UDP Source Port . Each cleared bit means t hat t he associat ed bit of t he UDP source
port is meaningful for t he filt ering funct ionalit y. Each bit set t o 1b means t hat t he
associat ed bit of t he UDP source port is ignored ( masked out ) .
DPort M 31: 16 0x0
Mask UDP Dest inat ion Port . Each cleared bit means t hat t he associat ed bit of t he UDP
dest inat ion port is meaningful for t he filt er ing funct ionalit y. Each bit set t o 1b means
t hat t he associat ed bit of t he UDP dest inat ion port is ignored ( masked out ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SI PM 15: 0 0x0
Mask Source I Pv6 address. Each cleared bit means t hat t he associat ed byt e of t he
source I Pv6 address is meaningful for t he filt ering funct ionalit y. Each bit set t o 1b
means t hat t he associat ed byt e of t he source I Pv6 address is ignored ( masked out ) .
DI PM 31: 16 0x0
Mask Dest inat ion I Pv6 address. Each cleared bit means t hat t he associat ed byt e of t he
dest inat ion I Pv6 address is meaningful for t he filt ering funct ionalit y. Each bit set t o 1b
means t hat t he associat ed byt e of t he dest inat ion I Pv6 address is ignored ( masked
out ) .
The ent ire field is meaningful only for t he hash funct ion and t he signat ure- based filt ers.
The DI Pv6 bit in t he FDI RM regist er is meaningful for perfect mat ch filt ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VLANI D 0 0b
Mask VLAN I D t ag. When cleared t he 12 bit s of t he VLAN I D t ag are meaningful for t he
filt ering funct ionalit y.
VLANP 1 0b
Mask VLAN Priorit y t ag. When cleared t he 3 bit s of t he VLAN Priorit y are meaningful for
t he filt ering funct ionalit y.
POOL 2 0b
Mask Pool. When cleared t he t arget pool number is meaningful for t he filt ering
funct ionalit y.
L4P 3 0b
Mask L4 Prot ocol. When cleared t he UDP/ TCP/ SCTP prot ocol t ype is meaningful for t he
filt ering funct ionalit y. Not e t hat for t he flow direct or filt ering aspect s, SCTP is t reat ed as
if it is TCP.
FLEX 4 0b
Mask Flexible Tuple. When cleared t he 2 byt es of t he flexible t uple are meaningful for
t he filt ering funct ionalit y.
DI Pv6 5 0b
Mask Dest inat ion I Pv6. When cleared t he compare against t he I P6AT filt er is meaningful
for I Pv6 packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

536
Gl obal St at us / St at i st i cs Regi st er s
8.2.3. 21.10 Fl ow Di r ect or Fi l t er s Fr ee FDI RFREE ( 0x 0EE38; RW)
8.2.3. 21.11 Fl ow Di r ect or Fi l t er s Lengt h FDI RLEN ( 0x 0EE4C; RC)
8.2.3. 21.12 Fl ow Di r ect or Fi l t er s Usage St at i st i cs FDI RUSTAT ( 0x 0EE50; RW/ RC)
8.2.3. 21.13 Fl ow Di r ect or Fi l t er s Fai l ed Usage St at i st i cs FDI RFSTAT ( 0x 0EE54; RW/ RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FREE 15: 0 0x8000 Number of free ( non programmed) filt ers in t he flow direct or Filt ers logic.
COLL 30: 16 0x0 Number of filt ers wit h collision indicat ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MAXLEN 5: 0 0x0
Longest linked list of filt ers in t he t able. This field records t he lengt h of t he longest
linked list t hat is updat ed since t he last t ime t his regist er was read by soft ware. The
longest bucket report ed by t his field includes MAXLEN + 1 filt ers.
Bucket Lengt h 13: 8 0x0
The lengt h of t he linked list indicat ed by a query command. This field is valid following a
query command complet ion.
MAXHASH 30: 16 0x0
The Lookup hash value of t he added filt er t hat updat ed t he value of t he MAXLEN field in
t his regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
ADD 15: 0 0x0
Number of added filt ers. This field count s t he number of added filt ers t o t he flow
direct or filt ers logic. The count er is st acked at 0xFFFF and cleared on read.
REMOVE 31: 16 0x0
Number of removed filt ers. This field count s t he number of removed filt ers t o t he flow
direct or filt ers logic. The count er is st acked at 0xFFFF and cleared on read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FADD 7: 0 0x0
Number of failed added filt ers due t o no space in t he filt er t able. The count er is st acked
at 0xFF and cleared on read.
FREMOVE 15: 8 0x0 Number of failed removed filt ers. The count er is st acked at 0xFF and cleared on read.

537
8.2.3.21.14 Fl ow Di r ect or Fi l t er s Mat ch St at i st i cs FDI RMATCH ( 0x 0EE58; RC)
8.2.3.21.15 Fl ow Di r ect or Fi l t er s Mi ss Mat ch St at i st i cs FDI RMI SS ( 0x 0EE5C; RC)
Fl ow Pr ogr ammi ng Regi st er s
8.2.3.21.16 Fl ow Di r ect or Fi l t er s Sour ce I Pv 6 FDI RSI Pv6[ n] ( 0x 0EE0C + 4* n, n= 02;
RW)
8.2.3.21.17 Fl ow Di r ect or Fi l t er s I P SA FDI RI PSA ( 0x 0EE18; RW)
8.2.3.21.18 Fl ow Di r ect or Fi l t er s I P DA FDI RI PDA ( 0x 0EE1C; RW)
8.2.3.21.19 Fl ow Di r ect or Fi l t er s Por t FDI RPORT ( 0x 0EE20; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PCNT 31: 0 0x0
Number of packet s t hat mat ched any flow direct or filt er. The count er is st acked at
0xFFF and cleared on read. Not e t hat t his count er can include packet s t hat mat ch t he
L2 filt ers or 5 t uple filt ers or Syn filt ers even if t hey are enabled for queue assignment .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PCNT 31: 0 0x0
Number of packet s t hat missed mat ched any flow direct or filt er. The count er is st acked
at 0xFFF and cleared on read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I P6SA 31: 0 0x0
Three MS DWords of t he source I Pv6 address. While t he LS byt e of FDI RSI Pv6[ 0] is first
on t he wire. The FDI RI PSA cont ains t he LS Dword of t he I P6 address while it s MS byt e is
last on t he wire.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I P4SA 31: 0 0x0
Source I Pv4 address or LS Dword of t he Source I Pv6 address. While t he field is defined
in big endian ( LS byt e is first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I P4DA 31: 0 0x0
Dest inat ion I Pv4 address. While t he field is defined in big endian ( LS byt e is first on t he
wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Source 15: 0 0x0
Source Port number while t he field is defined in Lit t le Endian ( MS byt e is first on t he
wire) . Not e t hat for SCTP filt er t he Source and Dest inat ion port numbers must be set t o
zero ( while t he HW does not check it ) .
Dest inat ion 31: 16 0x0
Dest inat ion Port number while t he field is defined in Lit t le Endian ( MS byt e is first on
t he wire) . Not e t hat for SCTP filt er t he Source and Dest inat ion port numbers must be
set t o zero ( while t he HW does not check it ) .
I nt el

538
8.2.3. 21.20 Fl ow Di r ect or Fi l t er s VLAN and FLEX Byt es FDI RVLAN ( 0x 0EE24; RW)
8.2.3. 21.21 Fl ow Di r ect or Fi l t er s Hash Si gnat ur e FDI RHASH ( 0x 0EE28; RW)
8.2.3. 21.22 Fl ow Di r ect or Fi l t er s Command Regi st er FDI RCMD ( 0x 0EE2C; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Vlan 15: 0 0x0
Vlan Tag while t he field is defined in big endian ( LS byt e is first on t he wire) . The CFI bit
must be set t o zero while it is not checked by hardware.
Flex 31: 16 0x0
Flexible t uple dat a as defined by t he Flex- Offset field in t he FDI RCTRL regist er while t he
field is defined in big endian ( LS byt e is first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Hash 14: 0 0x0 Bucket hash value t hat ident ifies a filt er s linked list .
Bucket Valid 15 0b
The Valid bit is set by hardware each t ime t here is at least one filt er assigned t o t his
hash.
Signat ure / SW- I ndex 30: 16 0x0
Flow direct or filt er signat ure for signat ure filt ers and soft ware- index for perfect mat ch
filt ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CMD 1: 0 00b
Flow Direct or Filt er Programming Command.
00b = No Act ion
01b = Add Flow.
10b = Remove Flow.
11b = Query Command.
Following a command complet ion hardware clears t he CMD field. I n a query command,
all ot her paramet ers are valid when t he CMD field is zero.
Filt er Valid 2 0b
Valid filt er is found by t he query command. This bit is set by t he 82599 following a
query command complet ion.
Filt er- Updat e 3 0b
Filt er Updat e Command. This bit is relevant only for Add Flow command and must be set
t o zero in any ot her commands. When cleared, t he filt er paramet ers do not override
exist ing ones if exist while set t ing only t he collision bit . When set t o 1b t he new filt er
paramet ers override exist ing ones if exist keeping t he collision bit as is.
I Pv6DMat ch 4 0b
I P Dest inat ion mat ch t o I P6AT filt er. This bit is meaningful only for perfect mat ch I Pv6
filt ers. Ot herwise it should be cleared by soft ware at programming t ime. When set t o 1b
t he dest inat ion I Pv6 address should mat ch t he I P6AT. When cleared, t he dest inat ion
I Pv6 address should not mat ch t he I P6AT.
This field can never mat ch local VM t o VM t raffic.
L4TYPE 6: 5 0b
L4 Packet Type. Defines t he packet as one of t he following L4 t ypes:
00b = Reserved.
01b = UDP.
10b = TCP.
11b = SCTP.
Not e: Encoding of t he L4TYPE for t he flow direct or filt ers is defined different ly t han t he
prot ocol t ype encoding in t he FTQF regist ers for t he 128 x 5 t uple filt ers.
I PV6 7 0b
I Pv6 packet t ype when set t o 1b and I Pv4 packet t ype at 0b. Not e t hat t he I P t ype is
checked always even if t he filt ers do not check for I P address mat ch.
CLEARHT 8 0b
Clear I nt ernal Flow Direct or Head and Tail Regist ers. This bit is set only as part of Flow
Direct or init . During nominal Operat ion it must be kept at 0b.

539
8.2.3.22 MAC Regi st er s
8.2.3.22.1 PCS_1G Gl obal Conf i g Regi st er 1 PCS1GCFI G ( 0x 04200; RW)
8.2.3.22.2 PCG_1G l i nk Cont r ol Regi st er PCS1GLCTL ( 0x 04208; RW)
Drop 9 0b
Packet Drop Act ion. Receive packet s t hat mat ch a filt er wit h act ive Drop bit are post ed
t o t he global queue defined by FDI RCTRL. Drop- Queue. See also FDI RCTRL. Max- Lengt h
field for drop filt ers t hat exceed t he maximum recommended linked list lengt h.
This bit is useful only for perfect mat ch filt ers while it should be cleared by soft ware for
signat ure filt ers.
When t he Drop bit is set , Queue- EN and Rx- Queue in t his regist er must be valid as well.
I NT 10 0b Mat ched packet generat es a LLI .
Last 11 0b
Last filt er indicat ion in t he linked list . At flow programming, soft ware should set t he last
bit t o 1b. Hardware can modify t his bit when adding or removing flows from t he same
linked list .
Collision 12 0b
Collision I ndicat ion. This field is set t o 1b when soft ware programs t he same mult iple
t imes. I n signat ure based filt ering, it is set when soft ware programs a filt er wit h t he
same hash and signat ure mult iple t imes. I t should be cleared by soft ware when it adds
a flow. I t can also be set by hardware when t wo flows collide wit h t he same hash and
signat ure. During recept ion, t his bit is report ed on t he Rx descript or of packet s t hat
mat ch t he filt er.
See bit 7 for descript ion of t he query- t ype.
Queue- EN 15 0b
Enable rout ing mat ched packet t o t he queue defined by t he Rx- Queue. Not e t hat
packet s redirect ion t o t he FDI RCTRL. Drop- Queue is not gat ed by t he Queue- EN bit .
Rx- Queue 22: 16 0x0
Rx Queue I ndex. This field defines t he absolut e Rx queue index in all modes of operat ion
( regardless of DCB and VT enablement ) .
Pool 29: 24 0x0
Pool number is meaningful when VT mode is enabled. When bot h VT is not enabled, t his
field must be set by soft ware t o 0x0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PCS_isolat e 30 0b
PCS I solat e. Set t ing t his bit isolat es t he 1 GbE PCS logic from t he MACs dat a pat h. PCS
cont rol codes are st ill sent and received.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FLV 0 0
Forced Link 1 GbE Value. This bit denot es t he link condit ion when Force Link is set .
0b = Forced link down.
1b = Forced 1 GbE link up.
FORCE 1G LI NK 5 0
Force 1 GbE Link. I f t his bit is set t hen t he int ernal LI NK_OK variable is forced t o Forced
Link Value, bit 0 of t his regist er. Else LI NK_OK is decided by int ernal AN/ SYNC st at e
machines. This bit is only valid when t he link mode is 1 GbE mode.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

540
8.2.3. 22.3 PCS_1G Li nk St at us Regi st er PCS1GLSTA ( 0x 0420C; RO)
8.2.3. 22.4 PCS_1 Gb/ s Aut o Negot i at i on Advanced Regi st er PCS1GANA ( 0x 04218; RW)
LI NK LATCH LOW 6 0
Link Lat ch Low Enable. I f t his bit is set t hen Link OK going LOW; negedge) is lat ched
unt il a CPU read happens. Once a CPU read happens Link OK is cont inuously updat ed
unt il Link OK again goes LOW ( negedge is seen) .
AN 1G TI MEOUT EN 18 1b
Aut o Negot iat ion 1 GbE Timeout Enable. This bit enables t he 1 GbE aut o- negot iat ion
t imeout feat ure. During 1 GbE aut o- negot iat ion, if t he link part ner doesn t respond wit h
aut o- negot iat ion pages but cont inues t o send good idle symbols t hen linkup is
assumed. ( This enables a linkup condit ion when a link part ner is not aut o- negot iat ion
capable and does not affect ot herwise) .
Reserved 20 0b Reserved, must be set t o 0b.
LI NK OK FI X EN 25 1b
Link OK Fix En. Cont rol for enabling/ disabling LinkOK- SyncOK fix. This bit should be set
t o 1b for nominal operat ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SYNC OK 1G 4 0b
Sync OK 1 GbE This bit indicat es t he current value of SYN OK from t he 1G PCS Sync
st at e machine,
AN 1G COMPLETE 16 0b
Aut o Negot iat ion1 GbE Complet e. This bit indicat es t hat t he 1 GbE aut o- negot iat ion
process complet ed.
AN PAGE RECEI VED 17 0b
Aut o- Negot iat ion Page Received. This bit indicat es t hat a link part ner' s page was
received during aut o- negot iat ion process. Clear on read.
AN 1G TI MEDOUT 18 0b
Aut o Negot iat ion1 GbE Timed Out . This bit indicat es 1 GbE aut o- negot iat ion process was
t imed out . Valid aft er AN 1G Complet e bit is set .
AN REMOTE FAULT 19 0b
Aut o Negot iat ion Remot e Fault . This bit indicat es t hat a 1 GbE aut o- negot iat ion page was
received wit h remot e fault indicat ion during 1 GbE aut o- negot iat ion process. Clear on
read.
AN ERROR ( RW) 20 0b
Aut o Negot iat ion Error. This bit indicat es t hat an aut o- negot iat ion error condit ion was
det ect ed in 1 GbE aut o- negot iat ion mode. Valid aft er t he AN 1G Complet e bit is set .
Aut o- negot iat ion error condit ions:
Bot h nodes not full duplex or remot e fault indicat ed or received.
Soft ware can also force an aut o- negot iat ion error condit ion by writ ing t o t his bit ( or can
clear an exist ing aut o- negot iat ion error condit ion) . Cleared at t he st art of aut o-
negot iat ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FDC 5 1b
FD: Full- Duplex. Set t ing t his bit means t he local device is capable of full- duplex
operat ion. This bit should be set t o 1b for normal operat ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

541
8.2.3.22.5 PCS_1GAN LP Abi l i t y Regi st er PCS1GANLP ( 0x 0421C; RO)
ASM 8: 7 11b
ASM_DI R/ PAUSE: Local PAUSE Capabilit ies. The local device' s PAUSE capabilit y is
encoded in t his field.
00b = No PAUSE.
01b = Symmet ric PAUSE.
10b = Asymmet ric PAUSE t oward link part ner.
11b = Bot h symmet ric and asymmet r ic PAUSE t oward local device.
RFLT 13: 12 00b
Remot e Fault . The local device' s remot e fault condit ion is encoded in t his field. Local
device can indicat e a fault by set t ing a non- zero remot e fault encoding and re-
negot iat ing.
00b = No error, link good.
01b = Link failure.
10b = Offline.
11b = Aut o- negot iat ion error.
NEXTP 15 0b
NEXTP: Next Page Capable. The local device assert s t his bit t o request next page
t ransmission. Clear t his bit when local device has no subsequent next pages.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LPFD 5 0b
LP Full- Duplex ( SerDes) . When 1b, link part ner is capable of full- duplex operat ion.
When 0b, link part ner is incapable of full- duplex mode.
LPHD 6 0b
LP Half- Duplex ( SerDes) . When 1b, link part ner is capable of half- duplex operat ion.
When 0b, link part ner is incapable of half- duplex mode.
LPASM 8: 7 00b
LPASMDR/ LPPAUSE( SERDES) . The link part ner' s PAUSE capabilit y is encoded in t his
field.
00b = No PAUSE.
01b = Symmet ric PAUSE.
10b = Asymmet ric PAUSE t oward link part ner.
11b = Bot h symmet ric and asymmet r ic PAUSE t oward local device.
PRF 13: 12 00b
LP Remot e Fault ( SerDes) [ 13: 12] . The link part ner' s remot e fault condit ion is encoded
in t his field.
00b = No error, link good.
10b = Link failure.
01b = Offline.
11b = Aut o- negot iat ion error.
ACK 14 0b Acknowledge ( SerDes) . The link part ner has acknowledged page recept ion.
LPNEXTP 15 0b
LP Next Page Capable ( SerDes) . The link part ner assert s t his bit t o indicat e it s abilit y t o
accept next pages.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

542
8.2.3. 22.6 PCS_1G Aut o Negot i at i on Nex t Page Tr ansmi t Regi st er PCS1GANNP
( 0x 04220; RW)
8.2.3. 22.7 PCS_1G Aut o Negot i at i on LP' s Nex t Page Regi st er PCS1GANLPNP ( 0x 04224;
RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CODE 10: 0 0x0
Message/ Unformat t ed Code Field. The message field is an 11- bit wide field t hat encodes
2048 possible messages. Unformat t ed code field is an 11- bit wide field, which can
cont ain an arbit rary value.
TOGGLE 11 0b
Toggle. This bit is used t o ensure synchronizat ion wit h t he link part ner during a next
page exchange. This bit always t akes t he opposit e value of t he Toggle bit in t he
previously exchanged link code word. The init ial value of t he Toggle bit in t he first next
page t ransmit t ed is t he inverse of bit 11 in t he base link code word and, t herefore, can
assume a value of 0b or 1b. The Toggle bit must be set as follows:
0b = Previous value of t he t ransmit t ed Link Code Word equaled 1b.
1b = Previous value of t he t ransmit t ed Link Code Word equaled 0b.
ACK2 12 0b
Acknowledge2. Acknowledge is used t o indicat e t hat a device has successfully received
it s link part ner s link code word.
PGTYPE 13 0b
Message/ Unformat t ed Page. This bit is used t o different iat e a message page from an
unformat t ed page. The encodings are:
0b = Unformat t ed page.
1b = Message page.
NXTPG 15 0b
Next Page. This bit is used t o indicat e whet her or not t his is t he last next page t o be
t ransmit t ed. The encodings are:
0b = Last page.
1b = Addit ional next pages follow.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CODE 10: 0 0x0
Message/ Unformat t ed Code Field. The message field is an 11- bit wide field t hat encodes
2048 possible messages. Unformat t ed code field is an 11- bit wide field, which can
cont ain an arbit rary value.
TOGGLE 11 0bb
Toggle. This bit is used t o ensure synchronizat ion wit h t he link part ner during a next
page exchange. This bit always t akes t he opposit e value of t he Toggle bit in t he
previously exchanged link code word. The init ial value of t he Toggle bit in t he first next
page t ransmit t ed is t he inverse of bit 11 in t he base link code word and, t herefore, can
assume a value of 0b or 1b. The Toggle bit must be set as follows:
0b = Previous value of t he t ransmit t ed link code word equalled 1b.
1b = Previous value of t he t ransmit t ed link code word equalled 0b.
ACK2 12 0
Acknowledge2. Acknowledge is used t o indicat e t hat a device has successfully received
it s link part ner s link code word.
MSGPG 13 0bb
Message Page. This bit is used t o different iat e a message page from an unformat t ed
page. The encodings are:
0b = Unformat t ed page.
1b = Message page.
ACK 14 0 Acknowledge. The link part ner has acknowledge next page recept ion.
NXTPG 15 0b
Next Page. This bit is used t o indicat e whet her or not t his is t he last next page t o be
t ransmit t ed. The encodings are:
0b = Last page.
1b = Addit ional next pages follow.

543
8.2.3.22.8 MAC Cor e Cont r ol 0 Regi st er HLREG0 ( 0x 04240; RW)
8. 2.3. 22. 9 MAC Cor e St at us 1 Regi st er - HLREG1 ( 0x 04244; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TXCRCEN 0 1b
Tx CRC Enable. : Enables a CRC t o be appended by hardware t o a Tx packet if request ed
by user.
1b = Enable CRC by hardware ( default ) .
0b = No CRC appended, packet s always passed unchanged.
JUMBOEN 2 0b
Jumbo Frame Enable. Enables frames up t o t he size specified in Reg MAXFRS ( 31: 16) .
1b = Enable j umbo frames.
0b = Disable j umbo frames ( default ) .
Reserved 9: 3 0x1 Reserved must be set t o 0x1.
TXPADEN 10 1b
Tx Pad Frame Enable. Pad short Tx frames t o 64 byt es if request ed by user.
1b = Pad frames ( default ) .
0b = Transmit short frames wit h no padding.
LPBK 15 0b
LOOPBACK: Turn On Loopback Where Transmit Dat a I s Sent Back Through Receiver.
1b = Loopback enabled.
0b = Loopback disabled ( Default ) .
MDCSPD 16 1b
MDC SPEED. High or Low Speed MDC Clock Frequency To PCS, XGXS, WI S, et c.
MDCSPD Freq at 10 GbE Freq at 1 GbEs Freq at 100 Mb/ s
0b 2. 4 MHz 240 KHz 240 KHz
1b 24 MHz 2. 4 MHz 240 KHz
Not e: 1b = default .
CONTMDC 17 0b
Cont inuous MDC: Turn Off MDC Bet ween MDI O Packet s
1b = Cont inuous MDC
0b = MDC Off Bet ween Packet s ( default )
PREPEND 23: 20 0x0
Prepend Value. Number Of 32- bit words st art ing aft er t he preamble and SFD, t o
exclude from t he CRC generat or and checker ( default 0x0) .
RXLNGTHERREN 27 1b
Rx Lengt h Error Report ing.
1b = Enable report ing of rx_lengt h_err event s if lengt h field < 0x0600.
0b = Disable report ing of all rx_lengt h_err event s.
RXPADSTRI PEN 28 0b
Rx Padding St rip Enable.
1b = St rip padding from Rx packet s wit h lengt h field < 64 ( debug only) .
0b = Do not st rip padding from Rx packet s wit h lengt h field < 64 ( default ) .
Not e: This funct ionalit y should be used as debug mode only. I f Rx pad st ripping is
enabled, t hen t he Rx CRC st ripping needs t o be enabled as well.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

544
8.2.3. 22.10 Pause and Pace Regi st er PAP ( 0x 04248; RW)
8.2.3. 22.11 MDI Si ngl e Command and Addr ess MSCA ( 0x 0425C; RW)
RXERRSYM 5 0b
Rx Error Symbol: Error Symbol During Rx Packet ( Lat ch High, Clear On Read) .
1b = Error symbol received.
0b = No error symbol ( default ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RXI LLSYM 6 0b
Rx I llegal Symbol: I llegal Symbol During Rx Packet ( Lat ch High, Clear On Read) .
1b = I llegal symbol received.
0b = No illegal symbol received ( default ) .
RXI DLERR 7 0b
Rx I dle Error: Non I dle Symbol During I dle Period ( Lat ch High, Clear On Read) .
1b = I dle error received.
0b = No idle errors received ( default ) .
RXLCLFLT 8 0b
Rx Local Fault : Fault report ed from PMD, PMA, or PCS ( Lat ch High, Clear On Read) .
1b = Local fault is or was act ive.
0b = No local fault ( default ) .
RXRMTFLT 9 0b
Rx Remot e Fault : Link Part ner Report ed Remot e Fault ( Lat ch High, Clear On Read) .
1b = Remot e fault is or was act ive.
0b = No remot e fault ( default ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 15: 0 0xFFFF Reserved
PACE 19: 16 0x0
0000b = 10 GbE ( LAN) .
0001b = 1 GbE.
0010b = 2 GbE.
0011b = 3 GbE.
0100b = 4 GbE.
0101b = 5 GbE.
0110b = 6 GbE.
0111b = 7 GbE.
1000b = 8 GbE.
1001b = 9 GbE.
1111b = 9. 294196 GbE ( WAN) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MDI ADD 15: 0 0x0000 MDI Address. Address used for new prot ocol MDI accesses ( default 0x0000) .
DEVADD 20: 16 0x0
DeviceType/ Regist er Address. Five bit s represent ing eit her device t ype if STCODE = 00b
or r egist er address if STCODE = 01b.
PHYADD 25: 21 0x0b PHY Address. The address of t he ext ernal device.
OPCODE 27: 26 00
OP Code. Two bit s ident ifying operat ion t o be performed ( default 00b) .
00b = Address cycle ( new prot ocol only) .
01b = Writ e operat ion.
10b = Read increment address ( new prot ocol only) or read operat ion ( old prot ocol only) .
11b = Read operat ion ( new prot ocol only) .

545
8.2.3.22.12 MDI Si ngl e Read and Wr i t e Dat a MSRWD ( 0x 04260; RW)
8.2.3.22.13 Max Fr ame Si ze MAXFRS ( 0x 04268; RW)
8.2.3.22.14 XGXS St at us 1 PCSS1 ( 0x 4288; RO)
8.2.3.22.15 XGXS St at us 2 PCSS2 ( 0x 0428C; RO)
STCODE 29: 28 01b
ST Code: Two Bit s I dent ifying St art Of Frame And Old Or New Prot ocol ( Default 01) .
00b = New prot ocol.
01b = Old prot ocol.
1Xb = I llegal.
MDI CMD 30 0b
MDI Command. Perform t he MDI O Operat ion in t his regist er, cleared when done.
1b = Perform operat ion, operat ion in progress.
0b = MDI Ready, operat ion complet e ( default ) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MDI WRDATA 15: 0 0x0 MDI Writ e Dat a: Writ e dat a For MDI writ es t o t he ext ernal device.
MDI RDDATA 31: 16 0x0 MDI Read Dat a: Read dat a from t he ext ernal device ( RO) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MFS 31: 16 0x5EE
This field defines t he maximum frame size in byt es unit s from Et hernet MAC addresses
up t o inclusive t he CRC. Frames received t hat are larger t han t his value are dropped.
This field is meaningful when j umbo frames are enabled ( HLREG0. JUMBOEN = 1b) .
When j umbo frames are not enabled t he 82599 uses a hardwired value of 1518 for t his
field.
The MFS does not include t he 4 byt es of t he VLAN header. Packet s wit h VLAN header
can be as large as MFS + 4. When double VLAN is enabled, t he device adds 8 t o t he MFS
for any packet s.
This value has no effect on t ransmit frames; it is t he responsibilit y of soft ware t o limit
t he size of t ransmit frames.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PCS Receive Link
St at us
2 0b
1b = PCS receive link up. For 10BASE-X - > lanes de- skewed.
0b = PCS receive link down. The receive link st at us remains cleared unt il it is read
( lat ching low) .
Local Fault 7 1b
1b = LF det ect ed on t ransmit or receive pat h. The LF bit is set t o one when eit her of t he
local fault bit s locat ed in PCS St at us 2 regist er are set t o a 1b.
0b = No LF det ect ed on receive pat h.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

546
8.2.3. 22.16 10GBASE- X PCS St at us XPCSS ( 0x 04290; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
10GBASE- R Capable 0 0b
1b = PCS is able t o support 10GBASE- R port t ype.
0b = PCS is not able t o support 10GBASE- R port t ype.
10GBASE-X capable 1 1b
1b = PCS is able t o support 10GBASE-X port t ype.
0b = PCS is not able t o support 10GBASE-X port t ype.
10GBASE-W capable 2 0b
1b = PCS is able t o support 10GBASE-W port t ype.
0b = PCS is not able t o support 10GBASE-W port t ype.
Receive local fault 10 1b
1b = Local fault condit ion on t he receive pat h.
0b = No local fault condit ion on t he receive pat h ( lat ch high)
Transmit local fault 11 0b
1b = Local fault condit ion on t he t ransmit pat h.
0b = No local fault condit ion on t he t ransmit pat h ( lat ch high)
Device present 15: 14 10b
10b = Device responding at t his address.
11b, 01b, 00b = No device responding at t his address.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Lane 0 sync 0 0b
1b = Lane 0 is synchronized.
0b = Lane 0 is not synchronized.
Lane 1 sync 1 0b
Lane 2 sync 2 0b
Lane 3 sync 3 0b
Reserved 11: 4 0b I gnore when read.
10GBASE-X lane
alignment st at us
12 0b
1b = 10GBASE-X PCS receive lanes aligned ( align_st at us good) .
0b = 10GBASE-X PCS receive lanes not aligned.
Reserved 15: 13 0x0 Reserved, ignore when read.
De- skew error 16 0b
1b = I ndicat es a deskew error was det ect ed.
0b = I ndicat es no deskew error was det ect ed ( lat ch high) .
Align column count 4 17 0b
1b = I ndicat es t he align column count has reached four.
0b = I ndicat es t he align column count is less t han four ( lat ch high) .
Lane 0 invalid code 18 0b
1b = I ndicat es an invalid code was det ect ed for t hat lane.
0b = I ndicat es no invalid code was det ect ed ( lat ch high) .
Lane 0 comma count 4 22 0b
1b = I ndicat es t he comma count for t hat lane has reached four.
0b = I ndicat es t he comma count for t hat lane is less t han four ( lat ch high) .

547
8. 2.3. 22. 17 Ser Des I nt er f ace Cont r ol Regi st er SERDESC ( 0x 04298; RW)
Lane 1 comma count
4
23 0b
Lane 2 comma count
4
24 0b
Lane 3 comma count
4
25 0b
Lane 0 Signal Det ect 26 0b
1b = I ndicat es a signal is det ect ed.
0b = I ndicat es noise, no signal is det ect ed.
0b I ndicat es noise, no signal is det ect ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Tx_lanes_polarit y 3: 0 0*
Bit 3 = changes bit s polarit y of MAC Tx lane 3.
Changes bit s polarit y if set t o 1b.
Rx_lanes_polarit y 7: 4 0*
Bit 7 = Changes bit s polarit y of MAC Rx lane 3.
Changes bit s polarit y if set t o 1b.
swizzle_t x_lanes 11: 8 0*
Bit 11 = Swizzles bit s of MAC Tx lane 3.
Swizzles bit s if set t o 1b.
These bit s are for debug only soft ware should not change t he default EEPROM value.
swizzle_rx_lanes 15: 12 0*
Bit 15 = Swizzles bit s of MAC Rx lane 3.
Swizzles bit s if set t o 1b.
These bit s are for debug only soft ware should not change t he default EEPROM value.
swap_t x_lane_3 17: 16 11b* Det ermines Core dest inat ion Tx lane for MAC Tx lane 3.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

548
* Also programmable via EEPROM.
8.2.3. 22.18 FI FO St at us/ CNTL Repor t Regi st er MACS ( 0x 0429C; RW)
This regist er report s FI FO st at us in xgmii_mux.
swap_t x_lane_0 23: 22 00b*
Det ermines Core dest inat ion Tx lane for MAC t x lane 0.
00b = = MAC Tx lane 0 t o Core Tx lane 0.
01b = MAC Tx lane 0 t o Core Tx lane 1.
swap_rx_lane_3 25: 24 11b* Det ermines which Core lane is mapped t o MAC Rx lane 3.
swap_rx_lane_0 31: 30 00b*
Det ermines which Core lane is mapped t o MAC Rx lane 0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
XGXS SYNC Fix
Disable
0 0b
Use shift - fsm cont rol for t he XGXS sync process.
0b Normal funct ionalit y ( default ) .
1b Use shift - fsm cont rol, disable fix ( debug only) .
XGMI I - GMI I Tx END
Fix Disable
1 0b
Disable t x_end on link- down.
0b Normal funct ionalit y, link down causes t x_end ( default ) .
1b Disable t x_end on link- down ( debug only) .
XGXS Deskew Fix
Disable
2 0b
Disable align on invalid fix.
1b Disable align on invalid fix ( debug only) .
Nonce Mat ch Disable 3 0b
Disable nonce mat ch.
1b Disable nonce mat ch ( debug only) .
Reserved 15: 4 0x0 Reserved. On a writ e access t o t his field t he SW should maint ain t he value of t his field.
Config fault lengt h 23: 16 0x1F Set s t he lengt h in clock cycles of LF st ream.
Config FI FO t hreshold 27: 24 0x6
Det ermines t hreshold for asynchronous FI FO ( generat ion of dat a_available signal is
det ermined by cfg_fifo_t h[ 3: 0] ) .
t x FI FO underrun 28 0b I ndicat es FI FO under run in xgmii_mux_t x_fifo.
t x FI FO overrun 29 0b I ndicat es FI FO overrun in xgmii_mux_t x_fifo.
rx FI FO underrun 30 0b I ndicat es FI FO under run in xgmii_mux_rx_fifo.
rx FI FO overrun 31 0b I ndicat es FI FO overrun in xgmii_mux_rx_fifo.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

549
8. 2.3. 22. 19 Aut o Negot i at i on Cont r ol Regi st er AUTOC ( 0x 042A0; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FLU 0 0b
Force Link Up.
0b= Normal mode.
1b = MAC forced t o link_up. Link is act ive in t he speed configured in AUTOC. LMS.
This set t ing forces t he aut o- negot iat ion arbit rat ion st at e machine t o AN_GOOD and set s
t he link_up indicat ion regardless of t he XGXS/ PCS_1G st at us.
ANACK2 1 0b*
Aut o- Negot iat ion Ack2 field. This value is t ransmit t ed in t he Achnowledge2 field of t he
null next page t hat is t ransmit t ed during a next page handshake.
ANSF 6: 2
00001b
*
Aut o- Negot iat ion Select or Field. This value will be used as t he Select or Field in t he Link
Cont rol Word during Clause 73 Backplane Aut oNegot iat ion process. ( Default value set
according t o 802. 3ap- 2007) .
10G_PMA_PMD_PARA
LLEL
8: 7 01b*
Define 10 GbE PMA/ PMD over four different ial pairs ( Tx and Rx each) .
00b = XAUI PMA/ PMD.
01b= KX4 PMA/ PMD.
10b = CX4 PMA/ PMD.
11b = Reserved.
1G_PMA_PMD 9 1b*
PMA/ PMD used for 1 GbE.
0b = SFI PMA/ PMD ( t he AUTOC. LMS should be set t o 000b) .
1b = KX or BX PMA/ PMD.
D10GMP 10 0b*
Disables 10 GbE ( KX4) on Dx ( Dr/ D3) wit hout mainpower.
0b= No specific act ion.
1b = Disables 10 GbE when main power is removed. When t he RATD and MNG_VETO
bit s are set t o 1b, t hey also cause t he link mode t o disable 10 GbE capabilit ies and
rest art aut o- negot iat ion ( if enabled) when main power ( MAI N_PWR_OK) is removed.
RATD 11 0b*
Rest art s aut o- negot iat ion on t ransit ion t o Dx. This bit enables t he funct ionalit y t o
rest art KX/ KX4/ KR backplane aut o- negot iat ion t ransit ion t o Dx ( Dr/ D3) .
0b= Does not rest art aut o- negot iat ion when t he 82599 moves t o t he Dx st at e.
1b = Rest art s aut o- negot iat ion t o reach a lowpower link mode ( 1 GbE link) when t he
82599 t ransit ions t o t he Dx st at e.
Rest art _AN 12 0b*
Applies new link set t ings and rest art s relat ive aut o- negot iat ion process ( selfclearing
bit ) .
0b = No act ion needed.
1b = Applies new link set t ings and rest art s aut o- negot iat ion.
Not e: This bit must be set t o make any new link set t ings affect ive as indicat ed in
Sect ion 3. 7. 4. 2.
LMS 15: 13 100b*
Link Mode Select . Select s t he act ive link mode:
000b = 1 GbE link ( no backplane aut o- negot iat ion) .
001b = 10 GbE parallel link ( KX4 no backplane aut o- negot iat ion) .
010b 1 GbE link wit h clause 37 aut o- negot iat ion enable ( BX int erface) .
011b = 10 GbE serial link ( SFI no backplane aut o- negot iat ion) .
100b = KX/ KX4/ KR backplane aut o- negot iat ion enable. 1 GbE ( Clause 37) aut o-
negot iat ion disabled.
101b = SGMI I 100M/ 1 GbE link.
110b = KX/ KX4/ KR backplane aut o- negot iat ion enable. 1 GbE ( Clause 37) aut o-
negot iat ion enable.
111b = KX/ KX4/ KR aut o- negot iat ion enable. SGMI I 100 Mb/ s and 1GbE ( in KX) enable.
KR_support 16 1b*
Configures t he A2 bit of t he Technology Abilit y Field in t he aut o- negot iat ion word while
A0: A1 fields are configured in t he KX_support field ( bit s 31: 30) :
0b = KR not support ed. Value is I llegal if KX and KX4 are also not support ed
( AUTOC. KX_support 00b) .
1b = KR support ed.
Not e: This bit is not relevant t o t he parallel det ect process.
I nt el

550
* Also programmable via EEPROM.
8.2.3. 22.20 Li nk St at us Regi st er LI NKS ( 0x 042A4; RO)
FECR 17 0b*
FEC Request ed. Configures t he F1 bit in t he backplane aut o- negot iat ion base link code
word. Should be set t o 1b only if KR abilit y is set t o 1b ( AUTOC. KR = 1b) .
0b = FEC not request ed from link part ner.
1b = FEC request ed from link part ner.
FECA 18 1b*
FEC Abilit y. Configures t he F0 bit in t he backplane aut o- negot iat ion base link code word.
Should be set t o 1b only if KR abilit y is set t o 1b ( AUTOC. KR = 1b) .
0b = FEC not support ed.
1b = FEC support ed.
ANRXAT 22: 19 0011b*
Backplane Aut o- Negot iat ion Rx Align Threshold. Set s t hreshold t o det ermine alignment
is st able.
ANRXDM 23 1b*
Aut o- Negot iat ion Rx Drift Mode. Enables following t he drift caused by PPM in t he Rx
dat a.
0b = Disables drift mode.
1b = Enables drift mode.
ANRXLM 24 1b*
Aut o- Negot iat ion Rx Loose Mode. Enables less rest rict ed funct ionalit y ( allow 9/ 11 bit
symbols) .
0b = Disables loose mode.
1b = Enables loose mode.
ANPDT 26: 25 00b*
Aut o- Negot iat ion Parallel Det ect Timer. Configures t he parallel det ect count ers.
00b = 1 ms.
01b = 2 ms.
10b = 5 ms.
11b = 8 ms.
RF 27 0b* This bit is loaded t o t he RF of t he aut o- negot iat ion word.
PB 29: 28 00b*
Pause Bit s. The value of t hese bit s is loaded t o bit s D11D10 of t he Link code word
( pause dat a) .
Bit 29 is loaded t o D11.
KX_support 31: 30 11b*
Configures t he A0: A1 bit s of t he Technology Abilit y Field of t he backplane aut o-
negot iat ion word while A2 field is configured in t he KR_support bit ( bit 16) :
00b= A0 0; A1 0. KX not support ed. KX4 not support ed. Value is I llegal if KR is also
not support ed ( AUTOC. KR_support 0b) .
01b = A0 1; A1 0. KX support ed. KX4 not support ed.
10b = A0 0; A1 1. KX not support ed. KX4 support ed.
11b = A0 1; A1 1. KX support ed. KX4 support ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
KX_SI G_DET 0 0b
Signal Det ect of 1 GbE and 100 Mb/ s.
0b = A signal is not present ( Fail) .
1b = A signal is present ( OK) .
FEC_SI G_DET 1 0b
Signal det ect of FEC
0b = FEC report s signal not det ect ed ( failed) .
1b = FEC report s signal det ect ed ( good) .
FEC_BLOCK_LOCK 2 0b
10 GbE serial PCS FEC block lock.
0b = No FEC block lock.
1b = FEC reached block lock.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

551
KR_HI _BERR 3 0b
10GbE serial KR_PCS high error rat e ( great er t han 10
- 4
) .
0b = Low BERR.
1b= High BERR.
KR_PCS_BLOCK_LOC
K
4 0b
10 GbE serial PCS block lock.
0b = No KR_PCS block lock.
1b= KR_PCS reached block lock.
KX/ KX4/ KR
Backplane AN Next
Page received
5 0b
KX/ KX4/ KR AN Next Page Received. A new link part ner next page was received during
t he backplane aut o- negot iat ion process.
Lat ch high, clear on read.
KX/ KX4/ KR
Backplane AN Page
received
6 0b
KX/ KX4/ KR Backplane Aut o Negot iat ion Page Received: A new link part ner page was
received during t he aut o- negot iat ion process.
Lat ch high, clear on read
Link St at us 7 0b
1b = Link is Up and t here was no link down from last t ime read.
0b = Link is current ly down or link was down since last t ime read.
Self cleared upon read if t he link is low and set if t he link is up.
KX4_SI G_DET 11: 8
Signal Det ect of 10 GbE Parallel ( KX4, CX4 or XAUI ) .
bit [ 11, 10, 9, 8] shows lane < 3, 2, 1, 0> st at us, respect ively.
For each bit :
0b = A signal is not present ( failed) .
1b = A signal is present ( good) .
KR_SI G_DET 12
Signal Det ect of 10 GbE serial ( KR or SFI ) .
0b = Signal not det ect ed ( failed) .
1b = Signal det ect ed ( good) .
10G lane sync_st at us 16: 13
10G Parallel lane sync st at us.
bit [ 16, 15, 14, 13] show lane < 3, 2, 1, 0> st at us accordingly.
per each bit :
0b = sync_st at us is FAI LED ( not synchronized t o code- group) .
1b = sync_st at us is OK ( synchronized t o code- group) .
10G Align St at us 17
10 GbE align_st at us.
0b = Align_st at us failed ( deskew process not complet e) .
1b = Align_st at us good ( all lanes are synchronized and aligned) .
1G Sync St at us 18
1G sync_st at us.
0b = Sync_st at us failed ( not synchronized t o code- group) .
1b = Sync_st at us is good ( synchronized t o code- group) .
KX/ KX4/ KR
Backplane AN
Receiver I dle
19
KX/ KX4/ KR Backplane Aut o Negot iat ion Rx I dle.
0b = Receiver good.
1b = Receiver is in idle- wait ing t o align and sync on DME.
1G AN enabled
( clause 37 AN)
20 PCS_1 GbE aut o- negot iat ion is enabled ( clause 37) .
1G link
Enabled PCS_1G
21 1 GbE PCS enabled for 1 GbE and SGMI I operat ion.
10G link Enabled
( XGXS)
22 XGXS Enabled for 10 GbE operat ion.
FEC_EN 23
St at us of forwarderrorcorrect ion in 10 GbE serial link ( KR operat ing mode) .
0b = FEC disabled.
1b = FEC enabled.
10G_SER_EN 24
St at us of 10 GbE serial PCS ( KR PCS) for KR or SFI operat ion.
0b = KR PCS disabled.
1b = KR PCS enabled.
SGMI I _EN 25
St at us of SGMI I operat ion.
0b = SGMI I disabled.
1b = SGMI I enabled.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

552
8.2.3. 22.21 Li nk St at us Regi st er 2 LI NKS2 ( 0x 04324; RO)
MLI NK_MODE 27: 26
MAC link mode st at us.
00b = 1 GbE.
01b = 10 GbE parallel.
10b = 10 GbE serial.
11b = aut o- negot iat ion.
LI NK_SPEED 29: 28
MAC link speed st at us.
00b = Reserved.
01b = 100 Mb/ s.
10b = 1 GbE.
11b = 10 GbE.
Link Up 30 0b
link up
1b = Link is up.
0b = Link is down.
KX/ KX4/ KR
Backplane AN
Complet ed
31 0b I ndicat es KX/ KX4/ KR backplane aut o- negot iat ion has complet ed successfully.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MAC Rx Link Mode 1: 0 00b
MAC link mode in t he Core Rx pat h.
00b = 1 GbE.
01b = 10 GbE parallel.
10b = 10GbE serial.
11b = aut o- negot iat ion.
MAC Tx Link Mode 4: 3 00b
MAC link mode in t he Core Tx pat h.
00 1G; 01 10G Parallel; 10 10G Serial; 11 aut o negot iat ion
Link- Part ner AN 6 0b
Link Part ner KX/ KX4/ KR Backplane Aut o- Negot iat ion Abilit y.
1b = Link part ner is KX/ KX4/ KR backplane aut o- negot iat ion capable.
0b = Link part ner is not KX/ KX4/ KR backplane aut o- negot iat ion capable.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

553
8.2.3.22.22 Aut o Negot i at i on Cont r ol 2 Regi st er AUTOC2 ( 0x 042A8; RW)
* Loaded from t he AUTOC2 word in t he MAC EEPROM sect ion
8.2.3.22.23 Aut o Negot i at i on Li nk Par t ner Li nk Cont r ol Wor d 1 Regi st er ANLP1 ( 0x 042B0;
RO)
To ensure t hat soft ware has t he abilit y t o read t he same Link Part ner Link Cont rol Word ( locat ed across
t wo regist ers) , once ANLP1 is read, ANLP2 is locked unt il t he ANLP2 regist er is read. ANLP2 does not
hold valid dat a before ANLP1 is read.
8.2.3.22.24 Aut o Negot i at i on Li nk Par t ner Li nk Cont r ol Wor d 2 Regi st er ANLP2 ( 0x 042B4;
RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
10G_PMA_PMD_
Serial
17: 16 00b*
PMAPMD used for 10 GbE serial link operat ion:
00b = KR.
01b = Reserved.
10b = SFI .
11b = Reserved.
DDPT 18 0*
Disable DME Pages Transmit . Set t ing t his bit disables t he DME pages t ransmit t ing while
t he device in aut onegot iat ion mode ( it t ransmit s 0bs inst ead) .
PDD 30 0b*
Disable t he parallel det ect part in t he KX/ KX4/ KR backplane aut o- negot iat ion. When set
t o 1b t he aut o- negot iat ion process avoids any parallel det ect act ivit y, and relies only on
t he DME pages received and t ransmit t ed.
1b = Disable t he parallel det ect ( debug only) .
0b = Enable t he parallel det ect ( normal operat ion) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LP AN page D low 15: 0 0x0
LP aut o- negot iat ion advert isement page fields D[ 15: 0] .
[ 15] = NP.
[ 14] = Acknowledge.
[ 13] = RF.
[ 12] = Reserved.
[ 11: 10] = Pause.
[ 9: 5] = Echoed Nonce field.
[ 4: 0] = Select or field.
ANAS 19: 16 0x0
KX/ KX4/ KR Backplane Aut o- Negot iat ion Arbit rat ion St at e. St at us indicat es t he current
st at e in t he arbit rat ion st at e machine.
Values are same as described in AUTOC2. FANAS.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LP Transmit t ed Nonce
Field
4: 0 0x0 LP aut o- negot iat ion advert isement page fields T[ 4: 0] .
LP Technology Abilit y
Field Low
15: 5 0x0 LP aut o- negot iat ion advert isement page fields A[ 10: 0] .
I nt el

554
8.2.3. 22.25 MAC Manageabi l i t y Cont r ol Regi st er MMNGC ( 0x 042D0; Host - RO/ MNG- RW)
8.2.3. 22.26 Aut o Negot i at i on Li nk Par t ner Nex t Page 1 Regi st er ANLPNP1 ( 0x 042D4; RO)
8.2.3. 22.27 Aut o Negot i at i on Li nk Par t ner Nex t Page 2 Regi st er ANLPNP2 ( 0x 042D8; RO)
t wo regist ers) , once ANLPNP1 is read, ANLPNP2 is locked unt il t he ANLPNP2 regist er is read. ANLPNP2
does not hold valid dat a before ANLPNP1 is read.
LP Technology Abilit y
Field High
31: 16 0x0 LP aut o- negot iat ion advert isement page fields A[ 26: 11] .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MNG_VETO 0 0b
MNG_VETO ( default 0b) . Access read/ writ e by manageabilit y, read only t o t he host .
0b = No specific const raint s on link from manageabilit y.
1b = Hold off any lowpower link mode changes. This is done t o avoid link loss and
int errupt ing manageabilit y act ivit y.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LP AN Next Page Low 31: 0 0x0
LP Aut o- Negot iat ion Next Page Fields D[ 31: 0] .
[ 31: 16] = Unformat t ed Code.
[ 15] = NP.
[ 14] = Acknowledge.
[ 13] = MP.
[ 12] = Acknowledge2
[ 11] = Toggle.
[ 10: 0] = Message/ Unformat t ed Code.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LP AN Next Page high 15: 0 0x0 LP AN Next Page Fields D[ 47: 32] . [ 15: 0] = Unformat t ed Code.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

555
8. 2.3. 22. 28 KR PCS and FEC Cont r ol Regi st er KRPCSFC ( 0x 042EO; RW)
8.2.3.22.29 KR PCS St at us Regi st er KRPCSS ( 0x 042E4; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 10: 0 0x0 Reserved. Bit s should be writ t en as 0x0 and ignored on read.
FEC_ENABLE_ERR 16 1b
FEC Enable Error I ndicat ion t o KR- PCS.
1b = The FEC decoder indicat es error t o t he KR- PCS by means of set t ing bot h sync
bit s t o t he value 11 in t he 1st , 9t h, 17t h, 25t h, and 32nd of t he 32 decoded 64b/ 66b
blocks from t he corresponding erred FEC block.
0b = Disabled.
FEC_N_CNT 19: 18 00b
Good Parit y Block Count . I ndicat es t he number of good parit y blocks required for
block lock.
00b = 4 good blocks.
FEC_M_CNT 21: 20 00b
Bad Parit y Block Count . I ndicat es t he number of bad parit y blocks required for loss of
block lock.
00b = 8 errors.
01b = 4 errors.
10b = 12 errors.
11b = 15 errors.
FEC_LOOSE_MODE 22 0b
Enables FEC Loose Mode
1b = Correct able errors are not count ed.
0b = All errors count ed.
FEC_RX_SWAP 23 0b
FEC Rx Bit Order Swap. Swaps t he bit order of t he FEC_RX input s. Swaps bot h din and
sync_in bit order.
FEC_TX_SWAP 24 0b
FEC Tx Bit Order Swap. Swaps t he bit order of t he FEC_TX input s. Swaps bot h din and
sync_in bit order.
SLI PASS 26 0b
Loss of Sync ( frame_align) I dle Pass-Through Select .
1b = Decoder out put dat a passed t o XGMI I out put when loss of sync.
0b = LF passed t o XGMI I out put when loss of sync.
SSYNC 27 0b
Rx Block Lock Override. Once block lock sync has been acquired on t he Rx input , Rx
input remains in block lock sync regardless of Rx input dat a.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reserved 2: 0 0x0 Reserved writ e 0 ignore read.
ERRCNT_BLK 10: 3 0x0
Rx Decoder Error Count er. This count er does not rollover and holds it s value unt il it is
read if it reaches it s maximum value. This count is cleared when t his regist er is read.
BERBAD_CNTR 16: 11 0x0
BER Bad Count er ( count cleared on regist er read)
Field indicat es number of t imes BER_BAD st at e was ent ered.
I nt el

556
RX_FI FO_ERR_LH 17 0b
Elast ic Buffer Error ( lat ched high, clear on read) .
0b = No Rx elast ic buffer overflow or underflow condit ion since last read.
1b = I ndicat es t hat Rx elast ic buffer overflow or underflow condit ion occurred since
last read.
RX_LF_DET 18 0b
RX_LF Det ect ( lat ched high, clear on read) .
0b = No local fault message was det ect ed in t he Rx pat h since last read.
1b = I ndicat es t hat t he local fault message was det ect ed in t he Rx pat h since last
read.
RX_FRM_ALI GN_ERR 19 0b
Frame Align Error ( lat ched high, clear on read) .
0b = No hi_ber or miss of frame_lock occurred since last read.
1b = I ndicat es t hat t he hi_ber or miss of frame_lock occurred since last t ime t he
regist er was read.
BLKLCK 20 0b
Rx Block Lock St at us bit ( lat ched low, set on read) .
0b = Link lost block lock since last regist er read.
1b = I ndicat es t hat t he link has remained in t he block lock st at e since t he last read of
t his regist er.
HBER_STS 21 0b
Rx High Bit Error Rat e St at us bit ( lat ched high, clear on read) .
0b = Link has not been in high BER st at e since previous read.
1b = I ndicat es t hat t he link has been in t he high BER st at e since t he last t ime t he
regist er was read.
RX_LF_DET 22 0b
RX_LF Det ect ( lat ched high, clear on read) .
0b = No local fault message was det ect ed in t he Rx pat h.
1b = I ndicat es t hat t he local fault message was det ect ed in t he Rx pat h.
LNK_STS 23 0b
Rx Link St at us ( lat ched low, set on read) .
0b = I ndicat es t hat t he link has been lost since t he last t ime t he bit was read.
1b = No loss of link since last t ime bit was read.
RX_UNDERFLOW 24 0b
Rx Underflow St at us ( lat ched high, clear on read) .
0b = No underflow condit ion in rx_fifo.
1b = I ndicat es t hat t he rx_fifo has reached t he underflow condit ion and dat a might
have been lost / corrupt ed.
RX_OVERFLOW 25 0b
Rx Overflow St at us ( lat ched high, clear on read) .
0b = No overflow condit ion in rx_fifo.
1b = I ndicat es t hat t he rx_fifo has reached t he overflow condit ion and dat a might
have been lost or corrupt ed.
RX_FI FO_ERR 26 0b
Rx Elast ic Buffer Error
0b = No elast ic buffer error.
1b = I ndicat es t hat Rx elast ic buffer is current ly in t he overflow or underflow
condit ion. This bit is not lat ched and is assert ed only when t he FI FO is in t he overflow
or underflow condit ion.
RX_DATA_VALI D 27 1b
Dat a Valid St at us ( lat ched low, set on read) . This bit indicat es t hat t he rx_fifo has not
experienced an overflow or underflow since t he last t ime t his regist er was read.
TX_UNDERFLOW 28 0b
Tx Underflow St at us ( lat ched high, clear on read) . This bit indicat es t hat t he t x_fifo
has reached t he underflow condit ion and dat a might have been lost / corrupt ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

557
8.2.3.22.30 FEC St at us 1 Regi st er FECS1 ( 0x 042E8; RC)
8.2.3.22.31 FEC St at us 2 Regi st er FECS2 ( 0x 042EC; RC)
8.2.3.22.32 Cor e Anal og Conf i gur at i on Regi st er Cor eCTL ( 0x 014F00; RW)
Reading t he Core regist ers must be done in t wo st eps:
1. Send a Writ e command wit h bit 16 set , and t he desired reading offset in t he Address field ( bit s
[ 15: 8] ) .
2. Send a Read command t o CoreCTL. The ret urned dat a is from t he indirect address in t he Core
regist er space, which was provided in st ep ( 1) .
To configure ( writ e) regist ers in t he Core block, t he driver should writ e t he proper address t o
CoreCTL.Address and dat a writ t en t o CoreCTL.Dat a.
TX_OVERFLOW 29 0b
Tx Overflow St at us ( lat ched high, clear on read) . This bit indicat es t hat t he t x_fifo
has reached t he overflow condit ion and dat a might have been lost / corrupt ed.
TX_FI FO_ERR 30 0b
Unlat ched FI FO Error St at us. This bit indicat es t hat t he t x_fifo has reached t he
overflow or underflow condit ion and dat a might have been lost / corrupt ed. This bit is
not lat ched and is only assert ed while t he FI FO is in t he overflow or underflow
condit ion.
TX_DATA_VALI D 31 1b
Dat a Valid St at us ( lat ched low, set on read) .
1b = t x_fifo has not experienced an overflow or underflow since t he last t ime t his
regist er was read.
0b = t x_fifo has experienced an overflow or underflow since t he last t ime t his regist er
was read.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FEC_CR_OUT 31: 0 0x0
FEC Correct able Error Count er. The FECS1 count s t he correct able FEC dat a blocks,
det ect ed and correct ed by t he FEC Rx logic.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
FEC_UNCR_OUT 31: 0 0x0
FEC Uncorrect able Error Count er. The FECS2 count s t he bad uncorrect able FEC dat a
blocks, det ect ed by t he FEC Rx logic.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Dat a 7: 0 0x0 Dat a t o Core Analog Regist ers. Dat a is ignored when bit 16 is set .
Address 15: 8 0x0 Address t o Core Analog Regist ers.
Lat ch address 16 0b
0b = Normal writ e operat ion.
1b = Lat ch t his address for t he next read t ransact ion. Dat a is ignored and is not writ t en
on t his t ransact ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

558
8.2.3. 22.33 Cor e Common Conf i gur at i on Regi st er SMADARCTL ( 0x 014F10; RW)
Reading t he Smadar regist ers must be done in t wo st eps:
1. Send a Writ e command wit h bit 16 set , and t he desired reading offset in t he Address field ( bit s
[ 15: 8] ) .
2. Send a Read command t o SMADARCTL. The ret urned dat a is from t he indirect address in t he Core
regist er space, which was provided in st ep ( 1) .
To configure ( writ e) regist ers in t he Smadar block, t he driver should writ e t he proper address t o
SMADARCTL. Address and dat a writ t en t o SMADARCTL.Dat a.
8.2.3. 22.34 MAC Fl ow Cont r ol Regi st er MFLCN ( 0x 04294; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Dat a 7: 0 0b Dat a t o Core Analog Regist ers. Dat a is ignored when bit 16 is set .
Address 15: 8 0x0 Address t o Core Analog Regist ers.
Lat ch address 16 0b
0b = Normal writ e operat ion.
1b = Lat ch t his address for t he next read t ransact ion. Dat a is ignored and is not writ t en
on t his t ransact ion.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PMCF 0 0b
Pass MAC Cont rol Frames. Filt er out unrecognizable pause ( flow cont rol opcode doesn t
mat ch) and ot her cont rol frames.
0b = Filt er unrecognizable pause frames.
1b = Pass/ forward unrecognizable pause frames.
DPF 1 0b
Discard Pause Frame
When set t o 0b, pause frames are sent t o t he host . Set t ing t his bit t o 1b causes pause
frames t o be discarded only when RFCE or RPFCE are set t o 1b. I f bot h RFCE and RPFCE
are set t o 0b, t his bit has no effect on incoming pause frames.
RPFCE 2 0b
Receive Priorit y Flow Cont rol Enable.
I ndicat es t hat t he 82599 responds t o receiving PFC packet s. I f aut o- negot iat ion is
enabled, t his bit should be set by soft ware t o t he negot iat ed flow cont rol value.
Not e: PFC should be enabled in DCB mode only.
Not e: Receive PFC and receive link flow cont rol are mut ually exclusive and
programmers should not configure bot h of t hem t o be enabled at t he same t ime.
Not e: This bit should not be set if bit 3 is set .
RFCE 3 0b
Receive Flow Cont rol Enable
I ndicat es t hat t he 82599 responds t o t he recept ion of link flow cont rol packet s. I f aut o-
negot iat ion is enabled, t his bit should be set by soft ware t o t he negot iat ed flow cont rol
value.
Not e: This bit should not be set if bit 2 is set .

559
8.2.3.22.35 SGMI I Cont r ol Regi st er SGMI I C ( 0x 04314; RW)
8.2.3.23 St at i st i c Regi st er s
General not es:
All st at ist ics regist ers are cleared on read. I n addit ion, t hey st ick at 0xFF...F when t he maximum
value is reached.
For t he receive st at ist ics it should be not ed t hat a packet is indicat ed as received if it passes t he
device filt ers and is placed int o t he packet buffer memory. A packet does not have t o be DMA' d t o
host memory in order t o be count ed as received.
Due t o divergent pat hs bet ween int errupt - generat ion and logging of relevant st at ist ics count s, it
might be possible t o generat e an int errupt t o t he syst em for a not ewort hy event prior t o t he
associat ed st at ist ics count act ually being increment ed. This is ext remely unlikely due t o expect ed
delays associat ed wit h t he syst em int errupt - collect ion and I SR delay, but might be an explanat ion
for int errupt st at ist ics values t hat do not quit e make sense. Hardware guarant ees t hat any event
not ewort hy of inclusion in a st at ist ics count is reflect ed in t he appropriat e count wit hin 1 s; a small
t ime- delay prior t o reading t he st at ist ics is required t o avoid a pot ent ial mismat ch bet ween an
int errupt and it s cause.
I f RSC is enabled, st at ist ics are collect ed before RSC is applied t o t he packet s.
I f TSO is enabled, st at ist ics are collect ed aft er segment at ion.
All byt e ( oct et ) count ers composed of t wo regist ers can be fet ched by t wo consecut ive 32- bit
accesses while reading t he low 32- bit regist er first or a single 64- bit access.
All receive st at ist ic count ers count t he packet s and byt es before coalescing by t he RSC logic or
FCoE DDP logic.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SRXRASSMP 3: 0 0x0
Shift Rx Rat e-Adapt Single Dat a Sampling. This value det ermines t he sampling point of
t he sampled received dat a in t he fast domain by t he fast clock relat ive t o t he slow clock.
SRXRARSMP 7: 4 0x0
Shift Rx Rat e-Adapt Replicat ed Dat a Sampling. This value det ermines t he sampling
point of t he received replicat ed dat a in t he fast domain by t he fast clock.
STXRASMP 11: 8 0x0
Shift Tx Rat e-Adapt Sampling. This value det ermines t he sampling point of t he
t ransmit t ed dat a in t he slow domain by t he fast clock.
ANSFLU100 12 0b
AN SGMI I Force Link Up 100 Mb/ s.
0b = Normal mode.
1b = PGS_1G forced t o 100 Mb/ s link. This set t ing forces t he PCS_1G Link_Ok
indicat ion and forced t he 100 Mb/ s speed indicat ion t oward t he aut o- negot iat ion ARB
st at e machine regardless of t he PCS_1G st at us.
ANSBYP 13 0b
AN SGMI I Bypass. I f t his bit is set , t he I DLE det ect st at e is bypassed during aut o-
negot iat ion ( Clause 37) in SGMI I mode. This reduces t he acknowledge t ime in SGMI I
mode.
ANSTRI G 14 0b
AN SGMI I Trigger. I f t his bit is set , aut o- negot iat ion ( Clause 37) is not aut omat ically
t riggered in SGMI I mode even if SYNC fails. Aut o- negot iat ion is t riggered only in
response t o PHY messages or by a manual set t ing like changing aut o- negot iat ion
Enable/ Rest art bit s.
ANSLNKTMR 15 0b
AN SGMI I Link-Timer ( Configure t he SGMI I Link Timer) .
0b = 1. 6 ms.
1b = 3. 2 ms.
ANI GNRRXRF 17 0b
Aut o- Negot iat ion I gnore Received RF Field.
0b = I f t he received page cont ains RF ! = 00b, don' t set link_up indicat ion.
1b = I gnore from t he received RF field cont ent .
I nt el

560
All receive st at ist ic count ers in t he filt er unit ( list ed as follows) include also packet s t hat might be
dropped by t he packet buffer or receive DMA. Same comment is valid for t he byt e count ers
associat ed wit h t hese packet count ers: PRC64, PRC127, PRC255, PRC511, PRC1023, PRC1522,
BPRC, MPRC, GPRC, RXNFGPC, RUC and ROC
8.2. 3. 23. 1 CRC Er r or Count CRCERRS ( 0x 04000; RC)
8.2.3. 23.2 I l l egal By t e Er r or Count I LLERRC ( 0x 04004; RC)
8.2.3. 23.3 Er r or By t e Count ERRBC ( 0x 04008; RC)
8.2.3. 23.4 Rx Mi ssed Pack et s Count RXMPC[ n] ( 0x 03FA0 + 4* n, n= 0...7; RC) DBU- Rx
Not e: This is a RO regist er only.
8.2.3. 23.5 MAC Local Faul t Count MLFC ( 0x 04034; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CEC 31: 0 0x0
CRC Error Count . Count s t he number of receive packet s wit h CRC errors. I n order for a
packet t o be count ed in t his regist er, it must be 64 byt es or great er ( from < Dest inat ion
Address> t hrough < CRC> , inclusively) in lengt h. This regist er count s all packet s
received, regardless of L2 filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I BEC 31: 0 0x0
I llegal Byt e Error Count . Count s t he number of receive packet s wit h illegal byt es errors
( such as t here is an illegal symbol in t he packet ) . This regist ers count s all packet s
received, regardless of L2 filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EBC 31: 0 0x0
Error Byt e Count . Count s t he number of receive packet s wit h error byt es ( such as t here
is an error symbol in t he packet ) . This regist ers count s all packet s received, regardless
of L2 filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MPC 31: 0 0x0
Regist er n count s t he number of missed packet s per packet buffer n.
Packet s are missed when t he receive FI FO has insufficient space t o st ore t he incoming
packet . This may be caused due t o insufficient buffers allocat ed, or because t here is
insufficient bandwidt h on t he I O bus. Event s set t ing t his count er also set t he receiver
overrun int errupt ( RXO) . These regist ers do not increment if receive is not enabled and
count only packet s t hat would have been post ed t o t he SW driver.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MLFC 31: 0 0x0
Number of fault s in t he local MAC. This regist er is valid only when t he link speed is
10 Gb/ s.

561
8. 2.3. 23. 6 MAC Remot e Faul t Count MRFC ( 0x 04038; RC)
8.2.3.23.7 Recei ve Lengt h Er r or Count RLEC ( 0x 04040; RC)
8. 2.3. 23. 8 Sw i t ch Secur i t y Vi ol at i on Pack et Count SSVPC ( 0x 08780; RC)
8. 2.3. 23. 9 Li nk XON Tr ansmi t t ed Count LXONTXC ( 0x 03F60; RC)
8.2.3.23.10 Li nk XON Recei ved Count LXONRXCNT ( 0x 041A4; RC)
Not e: This count er is similar t o LXONRXC in t he 82598 t hat was in address 0x0CF60.
8. 2.3. 23. 11 Li nk XOFF Tr ansmi t t ed Count LXOFFTXC ( 0x 03F68; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MRFC 31: 0 0x0
Number of fault s in t he remot e MAC. This regist er is valid only when t he link speed is
10 Gb/ s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RLEC 31: 0 0x0
Number of packet s wit h receive lengt h errors. A lengt h error occurs if an incoming
packet lengt h field in t he MAC header doesn' t mat ch t he packet lengt h. To enable t he
receive lengt h error count , t he HLREG. RXLNGTHERREN bit needs t o be set t o 1b. This
regist ers count s all packet s received, regardless of L2 filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SSVPC 31: 0 0x0
Swit ch Securit y Violat ion Packet Count . This regist er count s Tx packet s dropped due t o
swit ch securit y violat ions such as SA or VLAN ant i- spoof filt ering or a packet t hat has
( inner) VLAN t hat cont radict s wit h PFVMVI R regist er definit ions. Valid only in VMDq or
I OV mode.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
XONRXC 15: 0 0
Number of XON packet s received. St icks t o 0xFFFF. XON packet s can use t he global
address, or t he st at ion address. This regist er count s any XON packet whet her it is a
legacy XON or a priorit y XON. Each XON packet is count ed once even if it is designat ed
t o a few priorit ies. I f a priorit y FC packet cont ains bot h XOFF and XON, only t he
LXOFFRXCNT count er is increment ed.
I nt el

562
8.2.3. 23.12 Li nk XOFF Recei v ed Count LXOFFRXCNT ( 0x 041A8; RC)
Not e: This count er is similar t o LXOFFRXC in t he 82598 t hat was in address 0x0CF68.
8.2.3. 23.13 Pr i or i t y XON Tr ansmi t t ed Count PXONTXC[ n] ( 0x 03F00 + 4* n, n= 0...7; RC)
8.2.3. 23.14 Pr i or i t y XON Recei ved Count PXONRXCNT[ n] ( 0x 04140 + 4* n, n= 0...7; RC)
Not e: These count ers are similar t o PXONRXC[ n] in t he 82598 t hat were in address 0x0CF00 + 4* n,
n= 0.. .7.
8.2.3. 23.15 Pr i or i t y XOFF Tr ansmi t t ed Count PXOFFTXCNT[ n] ( 0x 03F20 + 4* n, n= 0...7;
RC)
8.2.3. 23.16 Pr i or i t y XOFF Recei v ed Count PXOFFRXCNT[ n] ( 0x 04160 + 4* n, n= 0... 7; RC)
Not e: These count ers are similar t o PXOFFRXC[ n] in t he 82598 t hat were in address 0x0CF20 +
4* n, n= 0. .. 7.
8.2.3. 23.17 Pr i or i t y XON t o XOFF Count PXON2OFFCNT[ n] ( 0x 03240 + 4* n, n= 0...7; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
XOFFRXC 15: 0 0x0
Number of XOFF packet s received. St icks t o 0xFFFF. XOFF packet s can use t he global
address or t he st at ion address. This regist er count s any XOFF packet whet her it is a
legacy XOFF or a priorit y XOFF. Each XOFF packet is count ed once even if it is
designat ed t o a few priorit ies. I f a priorit y FC packet cont ains bot h XOFF and XON, only
t his count er is increment ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
XONRXC 15: 0 0x0
Number of XON packet s received. St icks t o 0xFFFF. The regist er at t ached t o User
Priorit y 0 also report s link flow cont rol st at ist ics.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
XOFFRXC 15: 0 0x0
Number of XOFF packet s received. St icks t o 0xFFFF. The regist er at t ached t o User
Priorit y 0 also report s link flow cont rol st at ist ics.

563
8.2.3.23.18 Pack et s Recei v ed [ 64 Byt es] Count PRC64 ( 0x 0405C; RW)
8.2.3.23.19 Pack et s Recei v ed [ 65127 Byt es] Count PRC127 ( 0x 04060; RW)
8.2.3.23.20 Pack et s Recei v ed [ 128255 By t es] Count PRC255 ( 0x 04064; RW)
8.2.3.23.21 Pack et s Recei v ed [ 256511 By t es] Count PRC511 ( 0x 04068; RW)
8.2.3.23.22 Pack et s Recei v ed [ 5121023 Byt es] Count PRC1023 ( 0x 0406C; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC64 31: 0 0x0
Number of good packet s received t hat are 64 byt es in lengt h ( from < Dest inat ion
Address> t hrough < CRC> , inclusively) . This regist ers count s packet s t hat pass L2
filt ering regardless on receive enablement and does not include received flow cont rol
packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC127 31: 0 0x0
Number of packet s received t hat are 65- 127 byt es in lengt h ( from < Dest inat ion
packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC255 31: 0 0x0
packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC511 31: 0 0x0
Address> t hr ough < CRC> , inclusively) . This regist ers count s packet s t hat pass L2
packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC1023 31: 0 0x0
Address> t hr ough < CRC> , inclusively) . This regist ers count s packet s t hat pass L2
packet s.
I nt el

564
8.2. 3. 23. 23 Pack et s Recei ved [ 1024 t o Max By t es] Count PRC1522 ( 0x 04070; RW)
8.2.3. 23.24 Br oadcast Pack et s Recei ved Count BPRC ( 0x 04078; RO)
8.2. 3. 23. 25 Mul t i cast Pack et s Recei ved Count MPRC ( 0x 0407C; RO)
8.2.3. 23.26 Good Pack et s Recei ved Count GPRC ( 0x 04074; RO)
8.2.3. 23.27 Good Oct et s Recei v ed Count Low GORCL ( 0x 04088; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC1522 31: 0 0x0
Number of packet s received t hat are 1024- max byt es in lengt h ( from < Dest inat ion
packet s.
The maximum is dependent on t he current receiver configurat ion and t he t ype of
packet being received. I f a packet is count ed in receive oversized count , it is not
count ed in t his regist er ( see Sect ion 8. 2. 3. 23. 52) . Due t o changes in t he st andard for
maximum frame size for VLAN t agged frames in 802. 3, t his device accept s packet s t hat
have a maximum lengt h of 1522 byt es. The RMON st at ist ics associat ed wit h t his range
has been ext ended t o count 1522 byt e long packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BPRC 31: 0 0x0
Number of good ( non- erred) broadcast packet s received. This regist er does not count
received broadcast packet s when t he broadcast address filt er is disabled. The count er
count s packet s regardless on receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MPRC 31: 0 0x0
Number of good ( non- erred) mult icast packet s received t hat pass L2 filt ering ( excluding
broadcast packet s) . This regist er does not count received flow cont rol packet s. This
regist ers count s packet s regardless on receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPRC 31: 0 0x0
Number of good ( non- erred) Rx packet s ( from t he net work) t hat pass L2 filt ering and
has a legal lengt h as defined by LongPacket Enable. This regist ers count s packet s
regardless on receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CNT_L 31: 0 0x0
Lower 32 bit s of t he good oct et s received count er. The GORCL and GORCH regist ers
make up a logical 36- bit oct et count er of t he packet s count ed by GPRC. This regist er
includes byt es received in a packet from t he < Dest inat ion Address> field t hrough t he
< CRC> field, inclusively.

565
8.2.3.23.28 Good Oct et s Recei ved Count Hi gh GORCH ( 0x 0408C; RC)
8.2.3.23.29 Good Rx Non- Fi l t er ed Pack et Count er RXNFGPC ( 0x 041B0; RC)
8.2.3.23.30 Good Rx Non- Fi l t er By t e Count er Low RXNFGBCL ( 0x 041B4; RC)
8.2.3.23.31 Good Rx Non- Fi l t er By t e Count er Hi gh RXNFGBCH ( 0x 041B8; RC)
8. 2.3. 23. 32 DMA Good Rx Pack et Count er RXDGPC ( 0x 02F50; RC)
8. 2.3. 23. 33 DMA Good Rx By t e Count er Low RXDGBCL ( 0x 02F54; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CNT_H 3: 0 0x0 Higher four bit s of t he good oct et s received count er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPC 31: 0 0x0
Number of good ( non- erred wit h legal lengt h) Rx packet s ( from t he net work)
regardless of packet filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BCL 31: 0 0x0
Low 32 bit s of t he 36- bit byt e count er of good ( non- erred) Rx packet s t hat mat ch
RXNFGPC. The count er count s all byt es from < Dest inat ion Address> field t hrough t he
< CRC> field, inclusively.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BCH 3: 0 0x0 Higher four bit s of t he 36- bit byt e count er associat ed wit h RXFGBCL.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPC 31: 0 0x0
Number of good ( non- erred) Rx packet s from t he net work post ed t o t he host memory.
I n case of packet replicat ion ( or mirrored) , t he count er count s each packet only once.
The count er count s packet s direct ed t o ALL Rx queues or specific Rx queues as
defined by t he RXDSTATCTRL regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCL 31: 0 0x0
Lower 32 bit s of t he 36- bit byt e count er of good ( non- erred) Rx packet s t hat mat ch
RXDGPC. The count er count s all byt es post ed t o t he host before VLAN st rip.
Furt hermore, byt es of RSC and FCoE are count ed before coalescing or DDP.
I nt el

566
8.2.3. 23.34 DMA Good Rx Byt e Count er Hi gh RXDGBCH ( 0x 02F58; RC)
8.2.3. 23.35 DMA Dupl i cat ed Good Rx Pack et Count er RXDDPC ( 0x 02F5C; RC)
8.2.3. 23.36 DMA Dupl i cat ed Good Rx Byt e Count er Low RXDDBCL ( 0x 02F60; RC)
8.2.3. 23.37 DMA Dupl i cat ed Good Rx Byt e Count er Hi gh RXDDBCH ( 0x 02F64; RC)
8.2.3. 23.38 DMA Good Rx LPBK Pack et Count er RXLPBKPC ( 0x 02F68; RC)
8.2.3. 23.39 DMA Good Rx LPBK By t e Count er Low RXLPBKBCL ( 0x 02F6C; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCH 3: 0 0x0 Higher four bit s of t he 36- bit byt e count er associat ed wit h RXDGBCL.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPC 31: 0 0x0
Number of replicat ed or mirrored packet s t hat meet t he RXDGPC condit ions. The sum
of RXDDPC and RXDGPC is t he t ot al good ( non- erred) Rx packet s from t he net work
t hat are post ed t o t he host .
Not e: The count er count s packet s direct ed t o ALL Rx queues or specific Rx queues as
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCL 31: 0 0x0
RXDDPC. The count er count s all byt es post ed t o t he host before VLAN st rip.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCH 3: 0 0x0 Higher four bit s of t he 36- bit byt e count er associat ed wit h RXDDBCL.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPC 31: 0 0x0
Number of good ( non- erred) Rx packet s from a local VM post ed t o t he host memory.
I n case of packet replicat ion ( or mirrored) , t he count er count s each packet only once.
The count er count s packet s direct ed t o ALL Rx queues or specific Rx queues as
defined by t he RXDSTATCTRL regist er. The count er is not affect ed by RSC and FCoE
DDP since bot h funct ions are not support ed for LPBK t raffic.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCL 31: 0 0x0
RXLPBKPC. The count er count s all byt es post ed t o t he host before VLAN st rip.

567
8. 2.3. 23. 40 DMA Good Rx LPBK By t e Count er Hi gh RXLPBKBCH ( 0x 02F70; RC)
8.2.3.23.41 DMA Dupl i cat ed Good Rx LPBK Pack et Count er RXDLPBKPC ( 0x 02F74; RC)
8. 2.3. 23. 42 DMA Dupl i cat ed Good Rx LPBK Byt e Count er Low RXDLPBKBCL ( 0x 02F78; RC)
8.2.3.23.43 DMA Dupl i cat ed Good Rx LPBK By t e Count er Hi gh RXDLPBKBCH ( 0x 02F7C;
RC)
8.2.3.23.44 Good Pack et s Tr ansmi t t ed Count GPTC ( 0x 04080; RC)
8. 2.3. 23. 45 Good Oct et s Tr ansmi t t ed Count Low GOTCL ( 0x 04090; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCH 3: 0 0x0 Higher four bit s of t he 36- bit byt e count er associat ed wit h RXLPBKBCL.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPC 31: 0 0x0
Number of replicat ed or mirrored packet s t hat meet t he RXLPBKPC condit ions. The
sum of RXDLPBKPC and RXLPBKPC is t he t ot al good ( non- erred) Rx packet s from a
local VM post ed t o t he host .
Not e: The count er count s packet s direct ed t o ALL Rx queues or specific Rx queues as
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCL 31: 0 0x0
Low 32 bit s of t he 36- bit byt e count er of good ( non- erred) Rx packet s t hat mat ch
RXDLPBKPC. The count er count s all byt es post ed t o t he host before VLAN st rip.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GBCH 3: 0 0x0 Higher four bit s of t he 36- bit byt e count er associat ed wit h RXDLPBKBCL.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPTC 31: 0 0x0
Number of good packet s t ransmit t ed. This regist er count s good ( non- erred) t ransmit t ed
packet s. A good t ransmit packet is considered one t hat is 64 or more byt es ( from
< Dest inat ion Address> t hrough < CRC> , inclusively) in lengt h. The regist er count s
t ransmit t ed clear packet s, secure packet s and FC packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CNT_L 31: 0 0x0
Lower 32 bit s of t he good oct et s t ransmit t ed count er. See complet e descript ion in t he
GOTCH regist er sect ion.
I nt el

568
8.2.3. 23.46 Good Oct et s Tr ansmi t t ed Count Hi gh GOTCH ( 0x 04094; RC)
8.2.3. 23.47 DMA Good Tx Pack et Count er TXDGPC ( 0x 087A0; RC)
8.2.3. 23.48 DMA Good Tx Byt e Count er Low TXDGBCL ( 0x 087A4; RC)
8.2.3. 23.49 DMA Good Tx Byt e Count er Hi gh TXDGBCH ( 0x 087A8; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CNT_H 3: 0 0x0
Higher four bit s of t he good oct et s t ransmit t ed count er. The GOTCL and GOTCH
regist ers make up a logical 36- bit count er of successfully t ransmit t ed oct et s ( in
packet s count ed by GPTC) . This regist er includes t ransmit t ed byt es in a packet from
t he < Dest inat ion Address> field t hrough t he < CRC> field, inclusively.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPTC 31: 0 0x0
Number of Tx packet s from t he host memory. This count er includes packet s t hat are
t ransmit t ed t o t he ext ernal net work as well as packet s t hat are t ransmit t ed only t o local
VMs. The lat er case can happen only in VT mode when t he local swit ch is enabled.
Packet s dropped due t o ant i- spoofing filt ering or VLAN t ag validat ion ( as described in
Sect ion 7. 10. 3. 9. 2) are not count ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BCL 31: 0 0x0
Lower 32 bit s of t he 36- bit byt e count er of t he Tx packet s t hat mat ch TXDGPC. The
count er count s all byt es post ed by t he host AND t he VLAN ( if byt es were added by
hardware) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BCH 3: 0 0x0 Higher four bit s of t he 36- bit byt e count er associat ed t o TXDGBCL.

569
8. 2.3. 23. 50 Recei ve Under si ze Count RUC ( 0x 040A4; RC)
8.2.3.23.51 Recei ve Fr agment Count RFC ( 0x 040A8; RC)
8.2.3.23.52 Recei ve Ov er si ze Count ROC ( 0x 040AC; RC)
8.2.3.23.53 Recei ve Jabber Count RJC ( 0x 040B0; RC)
8.2.3.23.54 Management Pack et s Recei v ed Count MNGPRC ( 0x 040B4; RO)
8.2.3.23.55 Management Pack et s Dr opped Count MNGPDC ( 0x 040B8; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RUC 31: 0 0x0
Receive Undersize Error. This regist er count s t he number of received frames t hat are
short er t han minimum size ( 64 byt es from < Dest inat ion Address> t hrough < CRC> ,
inclusively) , and had a valid CRC. This regist er count s packet s regardless of L2 filt ering
and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RFC 31: 0 0x0
Number of receive fragment errors ( frame short ed t han 64 byt es from < Dest inat ion
Address> t hrough < CRC> , inclusively) t hat have bad CRC ( t his is slight ly different from
t he Receive Undersize Count regist er) . This regist er count s packet s regardless of L2
filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
ROC 31: 0 0x0
Receive Oversize Error. This regist er count s t he number of received frames t hat are
longer t han maximum size as defined by MAXFRS. MFS ( from < Dest inat ion Address>
t hrough < CRC> , inclusively) and have valid CRC. This regist er count s packet s
regardless of L2 filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RJC 31: 0 0x0
Number of receive j abber errors. This regist er count s t he number of received packet s
t hat are great er t han maximum size and have bad CRC ( t his is slight ly different from
t he Receive Oversize Count regist er) . The packet s lengt h is count ed from < Dest inat ion
Address> t hrough < CRC> , inclusively. This regist er count s packet s regardless of L2
filt ering and receive enablement .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MNGPRC 31: 0 0x0
Number of management packet s received. This regist er count s t he t ot al number of
packet s received t hat pass t he management filt ers. Management packet s include RMCP
and ARP packet s. Any packet s wit h errors are not count ed, except for t he packet s t hat
are dropped because t he management receive FI FO is full are count ed.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MPDC 31: 0 0
Number of management packet s dropped. This regist er count s t he t ot al number of
packet s received t hat pass t he management filt ers and t hen are dropped because t he
management receive FI FO is full. Management packet s include any packet direct ed t o
t he manageabilit y console ( such as RMCP and ARP packet s) .
I nt el

570
8.2.3. 23.56 Management Pack et s Tr ansmi t t ed Count MNGPTC ( 0x 0CF90; RO)
8.2.3. 23.57 Tot al Oct et s Recei ved Low TORL ( 0x 040C0; RC)
8.2.3. 23.58 Tot al Oct et s Recei ved Hi gh TORH ( 0x 040C4; RC)
8.2.3. 23.59 Tot al Pack et s Recei ved TPR ( 0x 040D0; RC)
8.2.3. 23.60 Tot al Pack et s Tr ansmi t t ed TPT ( 0x 040D4; RC)
8.2.3. 23.61 Pack et s Tr ansmi t t ed ( 64 By t es) Count PTC64 ( 0x 040D8; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CNT_L 31: 0 0x0
Lower 32 bit s of t he t ot al oct et s received count er. See complet e descript ion in t he next
regist er TORH.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CNT_H 3: 0 0x0
Higher four bit s of t he t ot al oct et s received count er. The TORL and TORH regist ers make
up a logical 36- bit count er of t he t ot al received oct et s ( in t he packet s count ed by t he
TPR count er) . This regist er includes byt es received in a packet from t he < Dest inat ion
Address> field t hrough t he < CRC> field, inclusively.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TPR 31: 0 0x0
Number of all packet s received. This regist er count s t he t ot al number of all packet s
received. All packet s received are count ed in t his regist er, regardless of t heir lengt h,
whet her t hey are erred, regardless on L2 filt ering and receive enablement but
excluding flow cont rol packet s.
TPR can count packet s int errupt ed by link disconnect alt hough t hey have a CRC error.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TPT 31: 0 0x0
Number of all packet s t ransmit t ed. This regist er count s t he t ot al number of all packet s
t ransmit t ed. This regist er count s all packet s, including st andard packet s, secure
packet s, FC packet s, and manageabilit y packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC64 31: 0 0x0
Number of packet s t ransmit t ed t hat are 64 byt es in lengt h ( from < Dest inat ion Address>
t hrough < CRC> , inclusively) . This regist er count s all packet s, including st andard
packet s, secure packet s, FC packet s, and manageabilit y packet s.

571
8.2.3.23.62 Pack et s Tr ansmi t t ed [ 65127 By t es] Count PTC127 ( 0x 040DC; RC)
8.2.3.23.63 Pack et s Tr ansmi t t ed [ 128255 Byt es] Count PTC255 ( 0x 040E0; RC)
8.2.3.23.64 Pack et s Tr ansmi t t ed [ 256511 Byt es] Count PTC511 ( 0x 040E4; RC)
8.2.3.23.65 Pack et s Tr ansmi t t ed [ 5121023 By t es] Count PTC1023 ( 0x 040E8; RC)
8.2.3.23.66 Pack et s Tr ansmi t t ed [ Gr eat er Than 1024 By t es] Count PTC1522 ( 0x 040EC;
RC)
8.2.3.23.67 Mul t i cast Pack et s Tr ansmi t t ed Count MPTC ( 0x 040F0; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC127 31: 0 0x0
Number of packet s t ransmit t ed t hat are 65- 127 byt es in lengt h ( from < Dest inat ion
Address> t hrough < CRC> , inclusively) . This regist er count s all packet s, including
st andard packet s, secure packet s, and manageabilit y packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC255 31: 0 0x0
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC511 31: 0 0x0
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC1023 31: 0 0x0
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC1522 31: 0 0x0
Number of packet s t ransmit t ed t hat are 1024 or more byt es in lengt h ( from
< Dest inat ion Address> t hrough < CRC> , inclusively) . This regist er count s all packet s,
including st andard packet s, secure packet s, and manageabilit y packet s.
Due t o changes in t he st andard for maximum frame size for VLAN t agged frames in
802. 3, t his device t ransmit s packet s t hat have a maximum lengt h of 1522 byt es. The
RMON st at ist ics associat ed wit h t his range has been ext ended t o count 1522 byt e long
packet s. This regist er count s all packet s, including st andard and secure packet s.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MPTC 31: 0 0x0
Number of mult icast packet s t ransmit t ed. This regist er count s t he number of mult icast
packet s t ransmit t ed. This regist er count s all packet s, including st andard packet s, secure
packet s, FC packet s and manageabilit y packet s.
I nt el

572
8.2.3. 23.68 Br oadcast Pack et s Tr ansmi t t ed Count BPTC ( 0x 040F4; RC)
f
8.2.3. 23.69 MAC Shor t Pack et Di scar d Count MSPDC ( 0x 04010; RC)
8.2.3. 23.70 XSUM Er r or Count XEC ( 0x 04120; RC)
XSUM errors are not count ed when a packet has any MAC error ( CRC, lengt h, undersize, oversize,
byt e error or symbol error) .
8.2.3. 23.71 Recei ve Queue St at i st i c Mappi ng Regi st er s RQSMR[ n] ( 0x 02300 + 4* n,
n= 0...31; RW)
These regist ers define t he mapping of t he receive queues t o t he per queue st at ist ics. Several queues
can be mapped t o a single st at ist ic regist er. Each st at ist ic regist er count s t he number of packet s and
byt es of all t he queues t hat are mapped t o t hat st at ist ics. The regist ers count ing Rx queue st at ist ics
are: QPRC, QBRC, and QPRDC.
For example, set t ing RQSMR[ 0] . Q_MAP[ 0] t o 3 maps Rx queue 0 t o t he count ers QPRC[ 3] , QBRC[ 3] ,
and QPRDC[ 3] . Set t ing RQSMR[ 2] . Q_MAP[ 1] t o 5 maps Rx queue 9 t o t he QPRC[ 5] , QBRC[ 5] , and
QPRDC[ 5] .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BPTC 31: 0 0x0
Number of broadcast packet s t ransmit t ed count . This regist er count s all packet s,
including st andard packet s, secure packet s, FC packet s and manageabilit y packet s
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MSPDC 31: 0 0x0 Number of MAC short packet discard packet s received.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
XEC 31: 0 0x0 Number of receive I Pv4, TCP, UDP or SCTP XSUM errors.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Q_MAP[ 0] 3: 0 0x0
For each regist er n, Q_MAP[ 0] defines t he per queue st at ist ic regist ers t hat are
mapped t o Rx queue 4* n+ 0. ( see examples t hat follow) .
Q_MAP[ 1] 11: 8 0x0
Q_MAP[ 2] 19: 16 0x0
Q_MAP[ 3] 27: 24 0x0

573
8.2.3.23.72 Rx DMA St at i st i c Count er Cont r ol RXDSTATCTRL ( 0x 02F40; RW)
8.2.3.23.73 Tr ansmi t Queue St at i st i c Mappi ng Regi st er s TQSM[ n] ( 0x 08600 + 4* n,
n= 0...31; RW)
These regist ers define t he mapping of t he t ransmit queues t o t he per queue st at ist ics. Several queues
can be mapped t o a single st at ist ic regist er. Each st at ist ic regist er count s t he number of packet s and
byt es of all t he queues t hat are mapped t o t hat st at ist ics. The regist ers count ing Tx queue st at ist ics
are: QPTC and QBTC.
8.2.3.23.74 Queue Pack et s Recei ved Count QPRC[ n] ( 0x 01030 + 0x 40* n, n= 0. ..15; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
QSEL 4: 0 0x0
The Queue Select field cont rols which Rx queues are considered for t he DMA good Rx
and DMA duplicat ed count ers as follows:
0x00000 . . . 01111 - The count ers relat es t o t he same queues t hat are direct ed t o t he
QPRC[ QSEL] count er as defined by t he RQSMR[ n] regist ers.
10000 - The count ers relat es t o all Rx queues.
Else - Reserved.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Q_MAP[ 0] 3: 0 0x0
mapped t o Tx queue 4* n+ 0.
Q_MAP[ 1] 11: 8 0x0
Q_MAP[ 2] 19: 16 0x0
Q_MAP[ 3] 27: 24 0x0
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC 31: 0 0x0
Number of packet s received for t he queue. FCoE packet s are count ed in QRPC even if
t hey are post ed only t o t he DDP queue ( wit h no t races in t he legacy queue) .
I nt el

574
8.2.3. 23.75 Queue Pack et s Recei ved Dr op Count QPRDC[ n] ( 0x 01430 + 0x 40* n,
n= 0...15; RC)
8.2.3. 23.76 Queue Byt es Recei ved Count Low QBRC_L[ n] ( 0x 01034 + 0x 40* n, n= 0...15;
RC)
8.2.3. 23.77 Queue Byt es Recei ved Count Hi gh QBRC_H[ n] ( 0x 01038 + 0x 40* n, n= 0...15;
RC)
8.2.3. 23.78 Queue Pack et s Tr ansmi t t ed Count QPTC[ n] ( 0x 08680 + 0x 4* n, n= 0... 15 /
0x 06030 + 0x 40* n, n= 0...15; RC)
These regist ers are also mapped t o 0x06030 t o maint ain compat ibilit y wit h t he 82598.
8.2.3. 23.79 Queue Byt es Tr ansmi t t ed Count Low QBTC_L[ n] ( 0x 08700 + 0x 8* n, n= 0...15;
RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRDC 31: 0 0x0
Tot al number of receive packet s dropped for t he queue. Packet s can be dropped for t he
following reasons:
1. Rx queue is disabled in t he RXDCTL[ n] regist er.
2. No free descript ors in t he Rx queue while hardware is set t o Drop En in t he
SRRCTL[ n] regist er or in t he PFQDE regist er.
3.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BRC_L 31: 0 0x0
Lower 32 bit s of t he st at ist ic count er. The QBRC_L[ n] and QBRC_H[ n] regist ers make
up a logical 36- bit count er of received byt es t hat were post ed t o t he programmed Rx
queues of t he packet s count ed by QPRC[ n] .
The count er count s all byt es post ed t o t he host before VLAN st rip. Furt hermore, byt es
of RSC and FCoE are count ed before coalescing or DDP.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BRC_H 3: 0 0x0 Higher four bit s of t he st at ist ic count er described in QBRC_L.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC 31: 0 0x0
Number of packet s t ransmit t ed for t he queue. A packet is considered as t ransmit t ed if it
is was forwarded t o t he MAC unit for t ransmission t o t he net work and/ or is accept ed by
t he int ernal Tx t o Rx swit ch enablement logic. Packet s dropped due t o ant i- spoofing
filt ering or VLAN t ag validat ion ( as described in Sect ion 7. 10. 3. 9. 2) are not count ed.

575
8. 2.3. 23. 80 Queue By t es Tr ansmi t t ed Count Hi gh QBTC_H[ n] ( 0x 08704 + 0x 8* n,
n= 0...15; RC)
8.2.3.23.81 FC CRC Er r or Count FCCRC ( 0x 05118; RC)
8. 2.3. 23. 82 FCoE Rx Pack et s Dr opped Count FCOERPDC ( 0x 0241C; RC)
8. 2.3. 23. 83 FC Last Er r or Count FCLAST ( 0x 02424; RC)
8. 2.3. 23. 84 FCoE Pack et s Recei v ed Count FCOEPRC ( 0x 02428; RC)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BTC_L 31: 0 0x0
Lower 32 bit s of t he st at ist ic count er. The QBTC_L and QBTC_H regist ers make up a
logical 36- bit count er of t ransmit t ed byt es of t he packet s count ed by t he mat ched QPTC
count er. These regist ers count all byt es in t he packet s from t he < Dest inat ion Address>
field t hrough t he < CRC> field, inclusively. These regist ers must be accessed as t wo
consecut ive 32- bit ent it ies while t he QBTC_L regist er is read first , or a single 64- bit
read cycle. Each regist er is read cleared. I n addit ion, it st icks at 0xFF. . . F t o avoid
overflow.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
BTC_H 3: 0 0x0 Higher four bit s of t he st at ist ic count er described in QBTC_L.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CRC_CNT 15: 0 0x0 FC CRC Count . Count t he number of packet s wit h good Et hernet CRC and bad FC CRC.
Reserve 31: 16 N/ A Reserved.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RPDC 31: 0 0x0 Number of Rx packet s dropped due t o lack of descript ors.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Last _CNT 15: 0 0x0
Number of packet s received t o valid FCoE cont ext s while t heir user buffers are
exhaust ed.
Reserve 31: 16 N/ A Reserved.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PRC 31: 0 0x0
Number of FCoE packet s post ed t o t he host . I n normal operat ion ( no save bad frames)
it equals t o t he number of good packet s.
I nt el

576
8.2. 3. 23. 85 FCOE DWor d Recei ved Count FCOEDWRC ( 0x 0242C; RC)
8.2.3. 23.86 FCoE Pack et s Tr ansmi t t ed Count FCOEPTC ( 0x 08784; RC)
8.2.3. 23.87 FCoE DWor d Tr ansmi t t ed Count FCOEDWTC ( 0x 08788; RC)
8. 2.3. 24 Wak e Up Cont r ol Regi st er s
8.2.3. 24.1 Wak e Up Cont r ol Regi st er WUC ( 0x 05800; RW)
The PME_En and PME_St at us bit s are reset when LAN_PWR_GOOD is 0b. When AUX_PWR= 0b t hese
bit s are also reset by t he assert ion of PE_RST_N.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
DWRC 31: 0 0x0
Number of DWords count in good received packet s wit h no Et hernet CRC or FC CRC
errors. The count er relat es t o FCoE packet s st art ing at t he FC header up t o and
including t he FC CRC ( it excludes Et hernet encapsulat ion) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PTC 31: 0 0x0
Number of FCoE packet s t ransmit t ed. Not e t hat t he count er does not include packet s
dropped due t o ant i- spoofing filt ering or VLAN t ag validat ion as described in
Sect ion 7. 10. 3. 9. 2. This rule is applicable if FCoE t raffic is sent by a VF.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
DWTC 31: 0 0x0
Number of DWords count in t ransmit t ed packet s. The count er relat es t o FCoE packet s
st art ing at t he FC header up t o and including t he FC CRC ( it excludes Et hernet
encapsulat ion) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PME_En 1 0b
PME_En. This bit is used by t he driver t o enable wakeup capabilit ies as programmed by
t he WUFC regist er. Wakeup is furt her gat ed by t he PME_En bit of t he PMCS regist er.
Not e t hat set t ing t he PME_En bit in t he PMCSR regist er also set s t his bit .
PME_St at us ( RO) 2 0b
PME_St at us. This bit is set when t he 82599 receives a wakeup event . I t is t he same as
t he PME_St at us bit in t he PMCSR. Writ ing a 1b t o t his bit clears it . The PME_St at us bit in
t he PMCSR is also cleared.
WKEN 4 1b
WKEN
This bit can be cleared t o disable PE_WAKE_N pin deassert ion even if APM is enabled in
t he EEPROM. I n t his case, PMCSR wakeup st at us will be invalid. Refer t o Sect ion 5. 3 for
t he correct way t o enable APM wit h valid st at us.
Not e: This bit should not be cleared while in ACPI mode.

577
8.2.3.24.2 Wak e Up Fi l t er Cont r ol Regi st er WUFC ( 0x 05808; RW)
This regist er is used t o enable each of t he pre- defined and flexible filt ers for wake up support . A value
of one means t he filt er is t urned on, and a value of zero means t he filt er is t urned off.
I f t he NoTCO bit is set , t hen any packet t hat passes t he manageabilit y packet filt ering does not cause a
wake up event even if it passes one of t he wake up filt ers.
8.2.3.24.3 Wak e Up St at us Regi st er WUS ( 0x 05810; RW1C)
Not e: This regist er is de- feat ured and soft ware should not read it . To enable ACPI , t his regist er
must be cleared by writ ing 0x3F01FF.
8.2.3.24.4 I P Addr ess Val i d I PAV ( 0x 5838; RW)
The I P address valid indicat es whet her t he I P addresses in t he I P address t able are valid:
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LNKC 0 0b Link St at us Change Wake Up Enable.
MAG 1 0b Magic Packet Wake Up Enable.
EX 2 0b Direct ed Exact Wake Up Enable.
MC 3 0b
Direct ed Mult icast Wake Up Enable. Set t ing t his bit does not enable broadcast packet s
t hat are enabled by t he BC bit in t his regist er.
BC 4 0b Broadcast Wake Up Enable.
ARP 5 0b ARP/ I Pv4 Request Packet Wake Up Enable.
I PV4 6 0b Direct ed I Pv4 Packet Wake Up Enable.
I PV6 7 0b Direct ed I Pv6 Packet Wake Up Enable.
NoTCO 15 0b I gnore TCO Packet s for TCO.
FLX0 16 0b Flexible Filt er 0 Enable.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
V40 0 0b
1
I Pv4 Address 0 Valid.
V41 1 0b I Pv4 Address 1 Valid.
I nt el

578
8.2.3. 24.5 I Pv4 Addr ess Tabl e I P4AT[ n] ( 0x 05840 + 8* n, n = 0...3; RW)
4 x I Pv4 addresses for ARP/ I Pv4 request packet and direct ed I Pv4 packet wake up. I Pv4[ 0] is loaded
from MI PAF words in t he EEPROM.
8.2.3. 24.6 I Pv6 Addr ess Tabl e I P6AT[ n] ( 0x 05880 + 4* n, n = 0...3; RW)
1 x I Pv6 addresses for a neighbor discovery packet filt ering and direct ed I Pv6 packet wake up.
According t o t he power management sect ion; one I pv6 address is support ed and it is programmed in
t he I pv6 Address Table ( I P6AT)
8.2.3. 24.7 Wak e Up Pack et Lengt h WUPL ( 0x 05900; RO)
This regist er is de- feat ured and soft ware should not access it ( not read nor writ e)
8.2.3. 24.8 Wak e Up Pack et Memor y ( 128 Byt es) WUPM[ n] ( 0x 05A00 + 4* n, n= 0...31;
RO)
This regist er is de- feat ured and soft ware should not access it ( not read nor writ e)
8.2.3. 24.9 Fl ex i bl e Host Fi l t er Tabl e Regi st er s FHFT ( 0x 09000 0x 093FC and 0x 09800
0x 099FC; RW)
Each of t he six Flexible Host Filt ers Table ( FHFT) regist ers cont ains a 128- byt e pat t ern and a
corresponding 128- bit mask array. I f enabled, t he first 128 byt es of t he received packet are compared
against t he non- masked byt es in t he FHFT regist er.
Each 128- byt e filt er is composed of 32 Dword ent ries, where each t wo Dwords are accompanied by an
8- bit mask, one bit per filt er byt e.
Not e: The Lengt h field must be eight byt e- aligned. For filt ering packet s short er t han eight byt e-
aligned t he values should be rounded up t o t he next eight byt e- aligned value, hardware
implement at ion compares eight byt es at a t ime so it should get ext ra zero masks ( if needed)
unt il t he end of t he lengt h value.
I f t he act ual lengt h, which is defined by t he Lengt h Field regist er and t he mask bit s is not
eight byt e- aligned, t here might be a case t hat a packet , which is short er t hen t he act ual
1. Loaded from EEPROM
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PV4ADDR 31: 0 X I Pv4 Address n, n = 0. . . 3.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I PV6ADDR 31: 0 X
4 x Regist er I Pv6 filt er. Regist er n cont ains byt es 4* n up t o 4* n+ 3 of t he I Pv6
address. LS byt e of regist er 0 is first on t he wire.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

579
required lengt h pass t he flexible filt er. This can happen due t o a comparison of up t o seven
byt es t hat come aft er t he packet but are not a real part of t he packet .
The last Dword of each filt er cont ains a Lengt h field defining t he number of byt es from t he beginning of
t he packet compared by t his filt er, t he Lengt h field should be an eight byt e- aligned value. I f t he act ual
packet lengt h is less t han ( lengt h 8) ( lengt h is t he value specified by t he Lengt h field) , t he filt er fails.
Ot herwise, it depends on t he result of act ual byt e comparison. The value should not be great er t han
128.
. . .
Each of t he filt ers have allocat ed addresses as follows:
Filt er 0 0x09000 0x090FF
The following t able list s t he addresses used for filt er 0.
31 0 31 8 7 0 31 0 31 0
Reserved Reserved Mask [ 7: 0] Dword 1 Dword 0
31 7 6 0 31 8 7 0 31 0 31 0
Reserved Reserved Reserved Mask [ 127: 120] Dword 29 Dword 28
Reserved Lengt h Reserved Mask [ 127: 120] Dword 31 Dword 30
Fi el d Dw or d Addr ess Bi t ( s) I ni t i al Val ue
Filt er 0 DW0 0 0x09000 31: 0 X
Filt er 0 DW1 1 0x09004 31: 0 X
Filt er 0 Mask[ 7: 0] 2 0x09008 7: 0 X
Reserved 3 0x0900C X
Filt er 0 DW2 4 0x09010 31: 0 X
Filt er 0 DW30 60 0x090F0 31: 0 X

Filt er 0 DW31 61 0x090F4 31: 0 X
Filt er 0 Mask[ 127: 120] 62 0x090F8 7: 0 X
Lengt h 63 0x090FC 6: 0 X
I nt el

580
Accessing t he FHFT regist ers during filt er operat ion can result in a packet being mis- classified if t he
writ e operat ion collides wit h packet recept ion. As a result , it is recommended t hat t he flex filt ers be
disabled prior t o changing t heir set up.
8. 2.3. 25 Management Fi l t er s Regi st er s
The Management Filt ers regist ers are RO for t he host . These regist ers are init ialized at LAN Power Good
and can be loaded from t he EEPROM by t he manageabilit y firmware.
8.2.3. 25.1 Management VLAN TAG Val ue MAVTV[ n] ( 0x 5010 + 4* n, n= 0...7; RW)
8.2.3. 25.2 Management Fl ex UDP/ TCP Por t s MFUTP[ n] ( 0x 5030 + 4* n, n= 0...7; RW)
Each 32- bit regist er ( n= 0,,7) refers t o t wo port filt ers ( regist er 0 refers t o port s 0 and 1, regist er 2
refers t o port s 2 and 3, et c.) . Not e t hat SCTP packet s do not mat ch t he MFUTP filt ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VI D 11: 0 0x0
Cont ain t he VLAN I D t hat should be compared wit h t he incoming packet if t he
corresponding bit in MFVAL. VLAN is set .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MFUTP[ 2n] 15: 0 0x0 ( 2n) - t h Management Flex UDP/ TCP port .
MFUTP[ 2n+ 1] 31: 16 0x0 ( 2n+ 1) - t h Management Flex UDP/ TCP port .

581
8.2.3.25.3 Management Et her net Type Fi l t er s- METF[ n] ( 0x 05190 + 4* n, n= 0...3; RW)
8. 2.3. 25. 4 Management Cont r ol Regi st er MANC ( 0x 05820; RW)
8.2.3.25.5 Manageabi l i t y Fi l t er s Val i d MFVAL ( 0x 5824; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EType 15: 0 0x0
Et herType value t o be compared against t he L2 Et herType field in t he Rx packet .
Not e: Appears in lit t le endian order ( high byt e first on t he wire) .
Polarit y 30 0b
0b = Posit ive filt er. Filt er ent ers t he decision filt ers if a mat ch occurred.
1b = Negat ive filt er. Filt er ent ers t he decision filt ers if a mat ch did not occur.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RCV_TCO_EN 17 0b
Receive TCO Packet s Enabled. When t his bit is set it enables t he receive flow from t he
wire t o t he manageabilit y block.
RCV_ALL 19 0b
Receive All Enable. When set , all packet s are received from t he wire and passed t o t he
manageabilit y block.
MCST_PASS_L2 20 0b
Receive All Mult icast : When set , all received mult icast packet s pass L2 filt ering and can
be direct ed t o t he MNG or Host by a one of t he decision filt ers. Broadcast packet s are
not forwarded by t his bit .
EN_MNG2HOST 21 0b
Enable manageabilit y packet s t o host memory. This bit enables t he funct ionalit y of t he
MANC2H regist er. When set t he packet s t hat are specified in t he MANC2H regist ers are
also forwarded t o host memory, if t hey pass manageabilit y filt ers.
Bypass VLAN 22 0b When set , VLAN filt ering is bypassed for MNG packet s.
EN_XSUM_FI LTER 23 0b
When set , t his bit enables Xsum filt ering t o manageabilit y. Meaning, only packet s t hat
pass L3, L4 checksum are sent t o t he manageabilit y block. Not e t hat t his capabilit y is
not provided for t unneled packet s.
EN_I Pv4_FI LTER 24 0b
Enable I Pv4 address Filt ers. When set , t he last 128 bit s of t he MI PAF regist er are used t o
st ore four I Pv4 addresses for I Pv4 filt ering. When cleared, t hese bit s st ore a single I Pv6
filt er.
FI XED_NET_TYPE 25 0b
Fixed Next Type. I f set , only packet s mat ching t he net t ype defined by t he NET_TYPE
field pass t o manageabilit y. Ot herwise, bot h t agged and un- t agged packet s can be
forwarded t o t he manageabilit y engine.
NET_TYPE 26 0b
Net Type:
0b = Pass only un- t agged packet s.
1b = Pass only VLAN t agged packet s.
Valid only if FI XED_NET_TYPE is set .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MAC 3: 0 0x0
MAC. I ndicat es if t he MAC unicast filt er regist ers ( MMAH, MMAL) cont ain valid Et hernet
MAC Addresses. Bit 0 corresponds t o filt er 0, et c.
VLAN 15: 8 0x0
VLAN. I ndicat es if t he VLAN filt er regist ers ( MAVTV) cont ain valid VLAN t ags. Bit 8
corresponds t o filt er 0, et c.
I nt el

582
8.2.3. 25.6 Management Cont r ol To Host Regi st er MANC2H ( 0x 5860; RW)
8.2.3. 25.7 Manageabi l i t y Deci si on Fi l t er s- MDEF[ n] ( 0x 5890 + 4* n, n= 0...7; RW)
I Pv4 19: 16 0x0
I Pv4. I ndicat es if t he I Pv4 address filt ers ( MI PAF) cont ain valid I Pv4 addresses. Bit 16
corresponds t o I Pv4 address 0. These bit s apply only when I Pv4 address filt ers are
enabled ( MANC. EN_I Pv4_FI LTER= 1) .
I Pv6 27: 24 0x0
I Pv6. I ndicat es if t he I Pv6 address filt er regist ers ( MI PAF) cont ain valid I Pv6 addresses.
Bit 24 corresponds t o address 0, et c. Bit 27 ( filt er 3) , applies only when I Pv4 address
filt ers are not enabled. ( MANC. EN_I Pv4_FI LTER= 0) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Host Enable 7: 0 0x0
Host Enable. When set , indicat es t hat packet s rout ed by t he manageabilit y filt ers t o
manageabilit y are also sent t o t he host . Bit 0 corresponds t o decision filt er ( MDEF[ 0]
and MDEF_EXT[ 0] ) , bit 1 corresponds t o decision filt er ( MDEF[ 1] and MDEF_EXT[ 1] ) ,
et c. The MANC2H rout ing is furt her enabled by a global MANC. EN_MNG2HOST bit .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Unicast ( AND) 0 0b
Unicast . Cont rols t he inclusion of unicast address filt ering in t he manageabilit y filt er
decision ( AND sect ion) .
Broadcast ( AND) 1 0b
Broadcast . Cont rols t he inclusion of broadcast address filt ering in t he manageabilit y
filt er decision ( AND sect ion) .
VLAN ( AND) 2 0b
VLAN. Cont rols t he inclusion of VLAN addr ess filt ering in t he manageabilit y filt er
I P Address ( AND) 3 0b
I P Address. Cont rols t he inclusion of I P address filt ering in t he manageabilit y filt er
Unicast ( OR) 4 0b
Unicast . Cont rols t he inclusion of unicast address filt ering in t he manageabilit y filt er
decision ( OR sect ion) .
Broadcast ( OR) 5 0b
Broadcast . Cont rols t he inclusion of broadcast address filt ering in t he manageabilit y
filt er decision ( OR sect ion) .
Mult icast ( AND) 6 0b
Mult icast . Cont rols t he inclusion of mult icast address filt ering in t he manageabilit y filt er
decision ( AND sect ion) . Broadcast packet s are not included by t his bit . The packet must
pass some L2 filt ering t o be included by t his bit eit her by t he MANC. MCST_PASS_L2 or
by some dedicat ed Et hernet MAC Address.
ARP Request ( OR) 7 0b
ARP Request . Cont rols t he inclusion of ARP request filt ering in t he manageabilit y filt er
ARP Response ( OR) 8 0b
ARP Response. Cont rols t he inclusion of ARP response filt ering in t he manageabilit y
filt er decision ( OR sect ion) .
Neighbor Discovery
( OR)
9 0b
Neighbor Discovery. Cont rols t he inclusion of neighbor discovery filt ering in t he
manageabilit y filt er decision ( OR sect ion) . The neighbor t ypes accept ed by t his filt er are
t ypes 0x86, 0x87, 0x88 and 0x89.
Port 0x298 ( OR) 10 0b
Port 0x298. Cont rols t he inclusion of port 0x298 filt ering in t he manageabilit y filt er
Port 0x26F ( OR) 11 0b
Port 0x26F. Cont rols t he inclusion of port 0x26F filt ering in t he manageabilit y filt er
Flex port ( OR) 27: 12 0x0
Flex Port . Cont rols t he inclusion of flex port filt ering in t he manageabilit y filt er decision
( OR sect ion) . Bit 12 corresponds t o flex port 0, et c.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

583
8.2.3.25.8 Manageabi l i t y Deci si on Fi l t er s- MDEF_EXT[ n] ( 0x 05160 + 4* n, n= 0...7; RW)
8.2.3.25.9 Manageabi l i t y I P Addr ess Fi l t er MI PAF[ m,n] ( 0x 58B0 + 0x 10* m + 4* n,
m= 0.. .3, n= 0. ..3; RW)
8.2.3.25.10 Manageabi l i t y Et her net MAC Addr ess Low MMAL[ n] ( 0x 5910 + 8* n, n= 0...3;
RW)
8.2.3.25.11 Manageabi l i t y Et her net MAC Addr ess Hi gh MMAH[ n] ( 0x 5914 + 8* n, n= 0...3;
RW)
Flex TCO ( OR) 31: 28 0x0
Flex TCO. Cont rols t he inclusion of Flex TCO filt ering in t he manageabilit y filt er decision
( OR sect ion) . Bit 28 corresponds t o Flex TCO filt er 0, et c.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
L2 Et herType ( AND) 3: 0 0x0
L2 Et herType. Cont rols t he inclusion of L2 Et herType filt ering in t he manageabilit y filt er
Reserved 7: 4 0x0 Reserved for addit ional L2 Et herType AND filt ers.
L2 Et herType ( OR) 11: 8 0x0
L2 Et herType. Cont rols t he inclusion of L2 Et herType filt ering in t he manageabilit y filt er
Reserved 15: 12 0x0 Reserved for addit ional L2 Et herType OR filt ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I P_ADDR 31: 0 X
Manageabilit y I P Address Filt ers.
For each n, m, m= 0. . . 3, n= 0. . . 3 while MANC. EN_I Pv4_FI LTER = 0, MI PAF[ m, n] regist er
holds Dword n of I Pv6 filt er m ( 4 x I Pv6 filt ers) .
For each n, m, m= 0. . . 3, n= 0. . . 3 while MANC. EN_I Pv4_FI LTER = 1, MI PAF[ m, n]
regist ers for m= 0, 1, 2 is t he same as t he previous case ( 3 x I Pv6 filt ers) . And
MI PAF[ 3, n] regist ers holds I Pv4 filt er n ( 4 x I Pv4 filt ers) .
Not e: These regist ers appear in big endian order ( LS byt e, LS address is first on t he
wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MMAL 31: 0 X
Manageabilit y Et hernet MAC Address Low. The lower 32 bit s of t he 48- bit Et hernet MAC
address.
Not e: Appears in big endian order ( LS byt e of MMAL is first on t he wire) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MMAH 15: 0 X
Manageabilit y Et hernet MAC Address High. The upper 16 bit s of t he 48- bit Et hernet MAC
address.
Not e: Appears in big endian order ( MS byt e of MMAH is last on t he wire) .
Reserved 31: 16 0x0 Reserved. Reads as 0x0. I gnored on writ e.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

584
8.2. 3. 25. 12 Fl ex i bl e TCO Fi l t er Tabl e Regi st er s FTFT ( 0x 09400- 0x 097FC; RW)
Each of t he four Flexible TCO Filt ers Table ( FTFT) regist ers cont ains a 128- byt e pat t ern and a
corresponding 128- bit mask array. I f enabled, t he first 128 byt es of t he received packet are compared
against t he non- masked byt es in t he FTFT regist er.
Not e: FTFT regist ers are configured by firmware. Host writ e/ read access t o t hese regist ers should
be avoided.
Each 128- byt e filt er is composed of 32 Dword ent ries, where each t wo Dwords are accompanied by an
8- bit mask, one bit per filt er byt e. 15: 8] et c. The Mask field is set so t hat bit 0 in t he mask masks byt e
0, bit 1 masks byt e 1 et c. A value of one in t he Mask field means t hat t he appropriat e byt e in t he filt er
should be compared t o t he appropriat e byt e in t he incoming packet .
Not es: The Mask field must be eight byt e- aligned even if t he Lengt h field is not eight byt e- aligned as
t he hardware implement at ion compares eight byt es at a t ime so it should get ext ra masks
unt il t he end of t he next Qword. Any Mask bit t hat is locat ed aft er t he lengt h should be set t o
zero indicat ing no comparison should be done.
I f t he act ual lengt h, which is defined by t he Lengt h Field regist er and t he mask bit s is not
eight byt e- aligned, t here might be a case where a packet , which is short er t hen t he act ual
required lengt h passes t he flexible filt er. This can happen due t o a comparison of up t o seven
byt es t hat come aft er t he packet but are not a real part of t he packet .
The last Dword of each filt er cont ains a Lengt h field defining t he number of byt es from t he beginning of
t he packet compared by t his filt er. I f act ual packet lengt h is less t han t he lengt h specified by t his field,
t he filt er fails. Ot herwise, it depends on t he result of act ual byt e comparison. The value should not be
great er t han 128.
. . .
31 0 31 8 7 0 31 0 31 0
31 0 31 8 7 0 31 0 31 0
Lengt h Reserved Mask [ 127: 120] Dword 31 Dword 30

585
8.2.3.25.13 Li nk Sec Sof t w ar e/ Fi r mw ar e I nt er f ace LSWFW ( 0x 015F14; RO)
Not e: The access rules on t his regist er are for t he driver soft ware.
Fi el d Dw or d Addr ess Bi t ( s) I ni t i al Val ue
Filt er 0 DW0 0 0x09400 31: 0 X
Filt er 0 DW1 1 0x09404 31: 0 X
Filt er 0 Mask[ 7: 0] 2 0x09408 7: 0 X
Reserved 3 0x0940C X
Filt er 0 DW2 4 0x09410 31: 0 X
Filt er 0 DW30 60 0x094F0 31: 0 X

Filt er 0 DW31 61 0x094F4 31: 0 X
Filt er 0 Mask[ 127: 120] 62 0x094F8 7: 0 X
Lengt h 63 0x094FC 6: 0 X
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Lock LinkSec Logic 0 0b
Block LinkSec
0b = Host can access LinkSec regist ers.
1b = Host cannot access LinkSec regist ers.
Block host t raffic 1 0b When set , all host t raffic ( Tx and Rx) is blocked.
Request LinkSec ( SC) 2 0b When set , a message is sent t o t he MC, request ing access t o t he LinkSec regist ers.
Release LinkSec ( SC) 3 0b When set , a message is sent t o t he MC, releasing ownership of t he LinkSec regist ers.
LinkSec Ownership 8 0b
Set by firmware t o indicat e t he st at us of t he LinkSec ownership:
0b = LinkSec owned by host ( default ) .
1b = LinkSec owned by MC.
I nt el

586
8. 2. 3. 26 Ti me Sy nc ( I EEE 1588) Regi st er s
8.2.3. 26.1 Rx Ti me Sync Cont r ol Regi st er TSYNCRXCTL ( 0x 05188; RW)
8.2.3. 26.2 Rx Ti me St amp Low RXSTMPL ( 0x 051E8; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RXTT( RO/ V) 0 0b
Rx Time St amp Valid. Equals 1b when a valid value for Rx t ime st amp is capt ured in t he Rx
Time St amp regist er. Cleared by read of Rx Time St amp ( RXSTMPH) regist er.
Type 3: 1 0x0
Type of packet s t o t ime st amp:
000b = Time st amp L2 ( V2) packet s only ( sync or Delay_req depends on message t ype in
Sect ion 8. 2. 3. 26. 6 and packet s wit h message I D 2 and 3) .
001b = Time st amp L4 ( V1) packet s only ( sync or Delay_req depends on message t ype in
Sect ion 8. 2. 3. 26. 6) .
010b = Time st amp V2 ( L2 and L4) packet s ( sync or Delay_req depends on message t ype
in Sect ion 8. 2. 3. 26. 6 and packet s wit h message I D 2 and 3) .
101b = Time st amp all packet s in which message I D bit 3 is zero, which means t ime st amp
all event packet s. This is applicable for V2 packet s only.
011b, 100b, 110b and 111b = Reserved
En 4 0b
Enable Rx Time St amp.
0x0 = Time st amping disabled.
0x1 = Time st amping enabled.
RSV 31: 5 0x0 Reserved
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RXSTMPL 31: 0 0x0 Rx t ime st amp LSB value.

587
8.2.3.26.3 Rx Ti me St amp Hi gh RXSTMPH ( 0x 051A4; RO)
8.2.3.26.4 Rx Ti me St amp At t r i but es Low RXSATRL ( 0x 051A0; RO)
8.2.3.26.5 Rx Ti me St amp At t r i but es Hi gh- RXSATRH ( 0x 051A8; RO)
8.2.3.26.6 Rx Message Type Regi st er Low RXMTRL ( 0x 05120; RW)
8.2.3.26.7 Tx Ti me Sy nc Cont r ol Regi st er TSYNCTXCTL ( 0x 08C00; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RXSTMPH 31: 0 0x0 Rx t ime st amp MSB value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SourceI DL 31: 0 0x0
Sourceuuid Low. Capt ured byt es 24- 27 in t he PTP message as list ed in Sect ion 7. 9. 5 while
t he MS byt e is last on t he wire. I n a V1 PTP packet it is t he 4 LS byt es of t he Sourceuuid
field and in V2 PTP packet it is part of t he Source Port I D field.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
SourceI DH 15: 0 0x0
Sourceuuid High. Capt ured byt es 22- 23 in t he PTP message as list ed in Sect ion 7. 9. 5
while t he LS byt e is first on t he wire. I n a V1 PTP packet it is t he 2 MS byt es of t he
Sourceuuid field and in V2 PTP packet it is part of t he Source Port I D field.
SequenceI D 31: 16 0x0
Sequence I d. Capt ured value of t he SequenceI D field in t he PTP Rx packet while LS byt e
first on t he wire.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
CTRLT 7: 0 0x0 V1 cont rol t o t ime st amp.
MSGT 15: 8 0x0 V2 message I D t o t ime st amp.
UDPT 31: 16 0x319 UDP port number t o t ime st amp.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TXTT( RO/ V) 0 0b
Tx Time St amp Valid. Equals 1b when a valid value for Tx t ime st amp is capt ured in t he
Tx Time St amp regist er. Cleared by read of Tx Time St amp ( TXSTMPH) regist er.
EN 4 0x0
Enable Tx Time St amp.
0x0 = Time st amping disabled.
0x1 = Time st amping enabled.
I nt el

588
8.2.3. 26.8 Tx Ti me St amp Val ue Low TXSTMPL ( 0x 08C04; RO)
8.2.3. 26.9 Tx Ti me St amp Val ue Hi gh TXSTMPH ( 0x 08C08; RO)
8.2.3. 26.10 Syst em Ti me Regi st er Low SYSTI ML ( 0x 08C0C; RW)
8.2.3. 26.11 Syst em Ti me Regi st er Hi gh SYSTI MH ( 0x 08C10; RW)
8.2.3. 26.12 I ncr ement At t r i but es Regi st er TI MI NCA ( 0x 08C14; RW)
8.2.3. 26.13 Ti me Adj ust ment Of f set Regi st er Low TI MADJL ( 0x 08C18; RW)
8.2. 3. 26. 14 Ti me Adj ust ment Of f set Regi st er Hi gh TI MADJH ( 0x 08C1C; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TXSTMPL 31: 0 0x0 Tx t ime st amp LSB value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TXSTMPH 31: 0 0x0 Tx t ime st amp MSB value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
STL 31: 0 0x0 Syst em t ime LSB regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
STH 31: 0 0x0 Syst em t ime MSB regist er.
I V 23: 0 0x0 I ncrement Value ( incvalue) .
I P 31: 24 0x0
I ncrement Per iod ( incperiod) .
Not e t hat t he minimum permit t ed funct ional value is t wo.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TADJL 31: 0 0x0 Time Adj ust ment Value Low.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TADJH 30: 0 0x0 Time Adj ust ment Value High.
Sign 31 0x0 Sign ( 0 = + , 1 = - ) .

589
8.2.3.26.15 Ti meSync Aux i l i ar y Cont r ol Regi st er TSAUXC ( 0x 08C20; RW)
8.2.3.26.16 Tar get Ti me Regi st er 0 Low TRGTTI ML0 ( 0x 08C24; RW)
8.2.3.26.17 Tar get Ti me Regi st er 0 Hi gh TRGTTI MH0 ( 0x 08C28; RW)
8.2.3.26.18 Tar get Ti me Regi st er 1 Low TRGTTI ML1 ( 0x 08C2C; RW)
8.2.3.26.19 Tar get Ti me Regi st er 1 Hi gh TRGTTI MH1 ( 0x 08C30; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
EN_TT0 0 0b Enable Tar get Time 0.
EN_TT1 1 0b Enable Tar get Time 1.
UTT0 3 0b Use t arget t ime 0 t o clear clk_out 0 down count er.
ST0 4 0b St art clock out t oggle only if t arget of clock out occurs.
UTT1 6 0b Use t arget t ime 1 t o clear clk_out 1 down count er.
ST1 7 0b
St art clock out t oggle only on t arget t ime 1, at t his point a rising edge of clock out
occurs.
EN_TS0 8 0b Enable Hardware Time St amp 0.
AUTT0 9 0b
Auxiliary Time St amp Taken. Cleared when read aft er an auxiliary t ime st amp 0
occurred.
EN_TS1 10 0b Enable Hardware Time St amp 1.
AUTT1 11 0b Auxiliary Time St amp Taken. Cleared when read aft er auxiliary t ime st amp 1 occurred.
Mask 16: 12 0b
Masking Value for Tar get Time. The value in t his field det ermines t he masked bit s in t he
comparison of t he syst em t ime and t arget t ime ( where 0 = no masking, 1 = bit 0 is
masked, 2 = bit 0 and 1 are masked and so on up t o 24 in which bit s 0 t hrough bit 23
are masked. Any value higher t han 24 are reserved) .
RSV 31: 17 0b Reserved
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TTL 31: 0 0x0 Target t ime 0 LSB regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TTH 31: 0 0x0 Target t ime 0 MSB regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TTL 31: 0 0x0 Target t ime 1 LSB regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TTH 31: 0 0x0 Target t ime 1 MSB regist er.
I nt el

590
8.2.3. 26.20 Fr equency Out 0 Cont r ol Regi st er FREQOUT0 ( 0x 08C34; RW) SEC- Tx
8.2.3. 26.21 Fr equency Out 1 Cont r ol Regi st er FREQOUT1 ( 0x 08C38; RW) SEC- Tx
8.2.3. 26.22 Aux i l i ar y Ti me St amp 0 Regi st er Low AUXSTMPL0 ( 0x 08C3C; RO)
8.2.3. 26.23 Aux i l i ar y Ti me St amp 0 Regi st er Hi gh AUXSTMPH0 ( 0x 08C40; RO)
8.2.3. 26.24 Aux i l i ar y Ti me St amp 1 Regi st er Low AUXSTMPL1 ( 0x 08C44; RO)
8.2.3. 26.25 Aux i l i ar y Ti me St amp 1 Regi st er Hi gh AUXSTMPH1 ( 0x 08C48; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RLV 31: 0 0x0 Reload value for frequency out zero down count er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
RLV 31: 0 0x0 Reload value for frequency out one down count er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TST_Low 31: 0 0x0 Auxiliary t ime st amp 0 LSB value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TST_Hi 31: 0 0x0 Auxiliary t ime st amp 0 MSB value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TST_Low 31: 0 0x0 Auxiliary t ime st amp 1 LSB value.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
TST_Hi 31: 0 0x0 Auxiliary t ime st amp 1 MSB value.

591
8. 2. 3. 27 Vi r t ual i zat i on PF Regi st er s
8.2.3.27.1 VT Cont r ol Regi st er PFVTCTL ( 0x 051B0; RW)
8.2.3.27.2 PF Mai l box PFMai l box [ n] ( 0x 04B00 + 4* n, n= 0...63; RW)
8.2.3.27.3 PF Mai l box I nt er r upt Causes Regi st er PFMBI CR[ n] ( 0x 00710 + 4* n, n= 0...3;
RW1C)
Each regist er handles 16 VFs and are defined as follows.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VT_Ena 0 0b
Virt ualizat ion Enabled Mode. When set , t he 82599 support s eit her 16, 32, or 64 pools.
When cleared, Rx t raffic is handled int ernally as if it belongs t o VF zero while VF zero is
enabled.
This bit should be set t he same as MTQC. VT_Ena.
DEF_PL 12: 7 0x0
Default Pool. Pool assignment for packet s t hat do not pass any pool queuing decision.
Enabled by t he Dis_Def_Pool bit .
Dis_Def_Pool 29 0b
Disable Default Pool. Det ermines t he behavior of an Rx packet t hat does not mat ch any
Rx filt er and is t herefore not allocat ed a dest inat ion pool.
0b = Packet is assigned t o t he default pool ( see DEF_PL) .
1b = Packet is dropped.
Rpl_En 30 0b Replicat ion Enable, when set t o 1b.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
St s ( WO) 0 0b
St at us/ Command from PF ready. Set t ing t his bit causes an int errupt t o t he relevant VF.
This bit always read as zero. Set t ing t his bit set s t he PFSTS bit in VFMailbox.
Ack ( WO) 1 0b
VF message received. Set t ing t his bit , causes an int errupt t o t he relevant VF. This bit
always read as zero. Set t ing t his bit set s t he PFACK bit in VFMailbox.
VFU 2 0b
Buffer is t aken by VF. This bit is RO for t he PF and is a mirror of t he VFU bit in t he
VFMailbox regist er.
PFU 3 0b
Buffer is t aken by PF. This bit can be set only if t he VFU bit is cleared and is mirrored in
t he PFU bit of t he VFMailbox regist er.
RVFU ( WO) 4 0b
Reset VFU. Set t ing t his bit clears t he VFU bit in t he corresponding VFMailbox regist er.
This bit should be used only if t he VF driver is not operat ional. Set t ing t his bit also reset s
t he corresponding bit s in t he PFMBI CR VFREQ and VFACK fields.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VFREQ 15: 0 0x0
Each bit in t he VFREQ field is set when VF number ( 16* n+ j ) wrot e a message in it s
mailbox. While n is t he regist er index, n= 0. . . 3 and j is t he index of t he bit s in t he
VFREQ, j = 0. . . 15.
VFACK 31: 16 0x0
Each bit in t he VFACK field is set when VF number ( 16* n+ j ) acknowledged a PF
message. While n is t he regist er index, n= 0. . . 3 and 16+ j is t he index of t he bit s in t he
VFACK, j = 0. . . 15.
I nt el

592
8.2.3. 27.4 PF Mai l box I nt er r upt Mask Regi st er PFMBI MR[ n] ( 0x 00720 + 4* n, n= 0... 1;
RW)
8.2.3. 27.5 PF VFLR Ev ent s I ndi cat i on PFVFLRE[ n] ( 0x00600, 0x001C0; RO)
8.2.3. 27.6 PF VFLR Event s Cl ear PFVFLREC[ n] ( 0x 00700 + 4* n, n= 0...1; W1C)
8.2.3. 27.7 PF VF Recei ve Enabl e PFVFRE[ n] ( 0x 051E0 + 4* n, n= 0.. .1; RW)
This regist er is reset on common reset cases and on per- funct ion reset cases. Respect ive bit s per VF
are reset on VFLR and on VF soft ware reset . See Sect ion 4. 2.2.2 for more det ails.
8.2.3. 27.8 PF VF Tr ansmi t Enabl e PFVFTE[ n] ( 0x 08110 + 4* n, n= 0...1; RW)
This regist er is reset on common reset cases and on per- funct ion reset cases. Respect ive bit s per VF
are reset on VFLR and on VF soft ware reset . See Sect ion 4. 2.2.2 for more det ails.
8.2.3. 27.9 PF PF Queue Dr op Enabl e Regi st er PFQDE ( 0x 02F04; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VFI M 31: 0 0xFF
Mailbox int errupt enable from VF # 32* n+ j , while n is t he regist er index and j is t he
bit number.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VFLE 31: 0 0x0
When set , bit i in regist er n reflect s an FLR event on VF# 32* n+ i. These bit s are
accessible only t o t he PF and are cleared by writ ing 0x1 t o t he mat ched bit in t he
PFVFLREC regist ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Clear VFLE 31: 0 X
Writ ing a 0x1 t o bit ' i' in regist er ' n' clears t he FLR event on VF# 32* n+ i indicat ed in t he
PFVFLRE[ n] regist ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VFRE 31: 0 0x0
Bit j . Enables receiving packet s t o VF# ( 32* n+ j ) .
Each bit is cleared by t he relevant VFLR.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VFTE 31: 0 0x0
Bit j . Enables t ransmit t ing packet s from VF# ( 32* n+ j ) .
Each bit is cleared by t he relevant VFLR.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
QDE 0 0b
Enable drop of packet s from Rx queue Queue_I ndex. This bit overrides t he
SRRCTL. drop_en bit of each queue. For example, if eit her of t he bit s is set , a packet
received when no descript or is available is dropped.
Reserved 3: 1 0x0 Reserved ( see WE and RE bit descript ions) .

593
8.2.3.27.10 PF VM Tx Sw i t ch Loopback Enabl e PFVMTXSW[ n] ( 0x 05180 + 4* n, n= 0...1;
RW)
8.2.3.27.11 PF VF Ant i Spoof Cont r ol PFVFSPOOF[ n] ( 0x 08200 + 4* n, n= 0...7; RW)
8. 2.3. 27. 12 PFDMA Tx Gener al Sw i t ch Cont r ol PFDTXGSWC ( 0x 08220; RW)
8.2.3.27.13 PF VM VLAN I nser t Regi st er PFVMVI R[ n] ( 0x 08000 + 4* n, n= 0...63; RW)
Queue I ndex 14: 8 0x0 I ndicat es t he queue referenced upon WE/ RE commands.
WE 16 0b
Writ e Enable. When t his bit is set , t he cont ent of bit s 3: 0 are writ t en int o t he relevant
queue cont ext . Bit s 3: 1 are reserved.
This bit should never be set t oget her wit h t he RE bit in t his regist er.
RE 17 0b
Read Enable. When t his bit is set , t he cont ent of bit s 3: 0 are read from t he relevant
queue cont ext . Bit s 3: 1 are reserved.
This bit should never be set t oget her wit h t he WE bit in t his regist er.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LLE 31: 0 0x0
Local Loopback Enable. For each regist er n, and bit i, i= 0. . 31, enables Local loopback
for pool 32* n+ 1.
When set , a packet originat ing from a specific pool and dest ined t o t he same pool is
allowed t o be looped back. I f cleared, t he packet is dropped.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MACAS 7: 0 0x0
For each regist er n, and bit i, i= 0. . 7, enables ant i- spoofing filt er on Et hernet MAC
addresses for VF( 8* n+ 1) .
VLANAS 15: 8 0x0
For each regist er n, and bit 8+ i, i= 0. . 7, enables ant i- spoofing filt er on VLAN t ag for
VF( 8* n+ i) .
Not e: I f VLANAS is set for a specific pool, t hen t he respect ive MACAS bit must be set as
well.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
LBE 0 0b Enables VMDQ loopback.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Port VLAN I D 15: 0 0x0 Port VLAN t ag t o insert if t he VLANA field = 01b.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I nt el

594
8.2.3. 27.14 PF VM L2 Cont r ol Regi st er PFVML2FLT[ n] ( 0x 0F000 + 4* n, n= 0...63; RW)
This regist er cont rols per VM I nexact L2 Filt ering.
8.2.3. 27.15 PF VM VLAN Pool Fi l t er PFVLVF[ n] ( 0x 0F100 + 4* n, n= 0...63; RW)
8.2.3. 27.16 PF VM VLAN Pool Fi l t er Bi t map PFVLVFB[ n] ( 0x 0F200 + 4* n, n= 0...127; RW)
VLANA 31: 30 0x0
VLAN act ion:
00b = Use descript or command.
01b = Always insert default VLAN.
10b = Never insert VLAN.
11b = Reserved.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
AUPE 24 0b
Accept Unt agged Packet s Enable. When set , packet s wit hout a VLAN t ag can be
forwarded t o t his queue, assuming t hey pass t he Et hernet MAC address queuing
mechanism.
ROMPE 25 0b Receive Overflow Mult icast Packet s. Accept packet s t hat mat ch t he MTA t able.
ROPE 26 0b Receive MAC Filt ers Overflow. Accept packet s t hat mat ch t he PFUTA t able.
BAM 27 0b Broadcast Accept .
MPE 28 0b Mult icast Promiscuous.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VLAN_I d 11: 0 X
Defines a VLAN t ag for pool VLAN filt er n. The bit map defines which pools belong t o t his
VLAN.
Not e: Appears in lit t le endian order ( LS byt e last on t he wire) .
VI _En 31 X VLAN I d Enable t his filt er is valid.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
POOL_ENA 31: 0 x
Pool Enable Bit Array. Each couple of regist ers ' 2* n' and ' 2* n+ 1' enables rout ing of
packet s t hat mat ch a PFVLVF[ n] filt er t o a pool list . Each bit when set , enables packet
recept ion wit h t he associat ed pools as follows:
Bit ' i' in regist er ' 2* n' is associat ed wit h POOL ' i' .
Bit ' i' in regist er ' 2* n+ 1' is associat ed wit h POOL ' 32+ i' .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on

595
8.2.3.27.17 PF Uni cast Tabl e Ar r ay PFUTA[ n] ( 0x 0F400 + 4* n, n= 0... 127; RW)
There is one regist er per 32 bit s of t he unicast address t able for a t ot al of 128 regist ers ( t he
PFUTA[ 127: 0] designat ion) . Soft ware must mask t o t he desired bit on reads and supply a 32- bit word
on writ es. The first bit of t he address used t o access t he t able is set according t o t he MCSTCTRL.MO
field.
The seven MS bit s of t he Et hernet MAC address ( out of t he 12 bit s) select s t he regist er index while t he
five LS bit s ( out of t he 12 bit s) select s t he bit wit hin a regist er.
Not e: All accesses t o t his t able must be 32 bit .
The lookup algorit hm is t he same one used for t he MTA t able.
This t able should be zeroed by soft ware before st art of operat ion.

8.2.3.27.18 PF Mi r r or Rul e Cont r ol PFMRCTL[ n] ( 0x 0F600 + 4* n, n= 0. ..3; RW)
This regist er defines mirroring rules for each of four dest inat ion pools.
8.2.3.27.19 PF Mi r r or Rul e VLAN PFMRVLAN[ n] ( 0x 0F610 + 4* n, n= 0. ..7; RW)
This regist er defines t he VLAN values as list ed in t he PFVLVF t able t aking part in t he VLAN mirror rule.
Regist ers 0, 4 correspond t o rule 0, regist ers 1, 5 correspond t o rule 1, et c. Regist ers 0- 3 correspond t o
t he LSB in t he PFVLVF t able. For example, regist er 0 corresponds t o VLAN filt ers 31: 0, while regist er 4
corresponds t o VLAN filt ers 63: 32.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Bit Vect or 31: 0 X Word wide bit vect or specifying 32 bit s in t he unicast dest inat ion address filt er t able.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VPME 0 0b
Virt ual Pool Mirroring Enable. Enables mirroring of cert ain pools as defined in t he
PFMRVM regist ers.
UPME 1 0b Uplink Port Mirroring Enable. Enables mirroring of all t raffic received from t he net work.
DPME 2 0b
Downlink Port Mirroring Enable. Enables mirroring of all t raffic t ransmit t ed t o t he
net work.
VLME 3 0b
VLAN Mirroring Enable. Enables mirroring of a set of given VLANs as defined in t he
PFMRVLAN regist ers.
MP 13: 8 0x0 Mirror Pool. Defines t he dest inat ion pool for t his mirror rule.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
VLAN 31: 0 0x0 Bit map list ing which VLANs part icipat e in t he mirror rule.
I nt el

596
8.2.3. 27.20 PF Mi r r or Rul e Pool PFMRVM[ n] ( 0x 0F630 + 4* n, n= 0. ..7; RW)
This regist er defines which pools are being mirrored t o t he dest inat ion pool.
Regist ers 0, 4 correspond t o rule 0, regist ers 1, 5 correspond t o rule 1, et c. Regist ers 0- 3 correspond t o
t he LSB in t he pool list . For example, regist er 0 corresponds t o pools 31: 0, while regist er 4 corresponds
t o pools 63: 32.
8.3 Devi ce Regi st er s VF
8. 3. 1 Regi st er s Al l ocat ed Per Queue
Depending on configurat ion, each pool has 2, 4, or 8 queues allocat ed t o it . Not e t hat in I OV mode, any
queues not allocat ed t o a VF are allocat ed t o t he PF. The regist ers assigned t o a queue are accessible
bot h in it s VF address space and in t he PF address space. This sect ion describes t he address mapping of
regist ers t hat belong t o queues.
Sect ion 7. 10. 2. 7. 2 defines t he correspondence of queue indices bet ween t he PF and t he VFs. For
example, when in configurat ion for 32 VFs, queues 124- 127 in t he PF correspond t o queues [ 3: 0] of
VF# 31.
The queues are enumerat ed in each VF from 0 ( such as [ 1: 0] , [ 3: 0] , or [ 7: 0] ) . I f a queue is allocat ed
t o a VF, t hen it s corresponding regist ers are accessible in t he VF CSR space. Each regist er is allocat ed
an address in t he VF ( relat ive t o it s base) according t o it s index in t he VF space. Therefore, t he
regist ers of queue 0 in each VF are allocat ed t he same addresses, which equal t he addresses of t he
same regist ers for queue 0 in t he PF. For example, RDH[ 0] in t he VF space has t he same relat ive
address in each VF and in t he PF ( address 0x01010) .
8.3.2 Non- Queue Regi st er s
Regist ers t hat do not correspond t o a specific queue are allocat ed addresses in t he VF space according
t o t hese rules:
Regist ers t hat are read only by t he VF ( like STATUS) have t he same address in t he VF space as in
t he PF space.
Regist ers allocat ed per pool are accessed in t he VF in t he same locat ion as pool [ 0] in t he PF
address space.
Regist ers t hat are read/ writ e by t he VF ( like CTRL) are replicat ed in t he PF, one per VF, in adj acent
addresses.
Not e: Since t he VF address space is limit ed t o 16 KB, any regist er t hat resides above t hat address in
t he PF space cannot reside in t he same address in t he VF space and is t herefore allocat ed in
anot her locat ion in t he VF.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Pool 31: 0 0x0 Bit map list ing which pools part icipat e in t he mirror rule.

597
8. 3. 3 MSI X Regi st er Summar y VF BAR 3
8.3. 3.1 MSI X Tabl e Ent r y Low er Addr ess MSI XTADD ( BAR3: 0x 0000 +
n* 0x 10, n= 0. . . 2; RW)
See Sect ion 9. 3. 8. 2 for det ails of t his regist er.
8.3.3.2 MSI X Tabl e Ent r y Upper Addr ess MSI XTUADD ( BAR3: 0x 0004 +
n* 0x 10, n= 0. . . 2; RW)
8.3.3.3 MSI X Tabl e Ent r y Message MSI XTMSG ( BAR3: 0x 0008 + n* 0x 10,
n= 0. . . 2; RW)
8.3. 3.4 MSI X Tabl e Ent r y Vect or Cont r ol MSI XVCTRL ( BAR3: 0x 000C +
n* 0x 10, n= 0. . . 2; RW)
8.3.3.5 MSI XPBA ( BAR3: 0x 02000; RO) MSI XPBA Bi t Descr i pt i on
Not e: I f a page size larger t han 8 KB is programmed in t he I OV st ruct ure, t he address of t he MSI X
PBA t able moves t o be page aligned.
Vi r t ual Addr ess
Phy si cal Addr ess
Base ( + VFn * 0x 30)
Abbr ev i at i on Name
0x0000 + n* 0x10,
n= 0. . . 2
0x00010 MSI XTADD MSI X Table Ent ry Lower Address
0x0004 + n* 0x10,
n= 0. . . 2
0x00018 MSI XTUADD MSI X Table Ent ry upper Address
0x0008 + n* 0x10,
n= 0. . . 2
0x00028 MSI XTMSG MSI X Table Ent ry Message
0x000C + n* 0x10,
n= 0. . . 2
N/ A MSI XTVCTRL MSI X Table Vect or Cont rol
Max( Page Size, 0x2000) N/ A MSI XPBA MSI -X Pending Bit Array
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Pending Bit s 2: 0 0x0
For each pending bit t hat is set , t he funct ion has a pending message for t he associat ed MSI -X
t able ent ry.
Pending bit s t hat have no associat ed MSI -X t able ent ry are reserved.
I nt el

598
8.3.4 Regi st er s Summar y VF BAR 0
8. 3.4. 1 VF Regi st er s Tabl e
Vi r t ual Addr ess Abbr ev i at i on Name Bl ock
Reset
Sour ce
RW
Gener al Cont r ol
Regi st er s
0x00000 VFCTRL VF Cont rol Regist er Target WO
0x00008 VFSTATUS VF St at us Regist er Target RO
0x00010 VFLI NKS VF Link St at us Regist er MAC RO
0x00048 VFFRTI MER VF Free Running Timer Rx- Filt er RO
0x002FC VFMailbox VF Mailbox Target RW
0x00200 + 4* n, n= 0. . . 15 VFMBMEM[ n] VF Mailbox Memory Target RW
0x03190 VFRXMEMWRAP VF Rx Packet Buffer Flush Det ect DBU- Rx RO
I nt er r upt Regi st er s
0x00100 VFEI CR VF Ext ended I nt errupt Cause I nt errupt RC/ W1C
0x00104 VFEI CS VF Ext ended I nt errupt Cause Set I nt errupt WO
0x00108 VFEI MS VF Ext ended I nt errupt Mask Set / Read I nt errupt RWS
0x0010C VFEI MC VF Ext ended I nt errupt Mask Clear I nt errupt WO
0x00110 VFEI AC VF Ext ended I nt errupt Aut o Clear I nt errupt RW
0x00114 VFEI AM VF Ext ended I nt errupt Aut o Mask Enable I nt errupt RW
0x00820 + 4* n, n= 0. . . 1 VFEI TR VF Ext ended I nt errupt Mask Set / Read I nt errupt RWS
0x00120 + 4* n, n= 0. . . 3 VFI VAR VF I nt errupt Vect or Allocat ion Regist ers I nt errupt RW
0x00140 VFI VAR_MI SC VF I nt errupt Vect or Allocat ion Regist ers I nt errupt RW
0x00180 + 4* n, n= 0, 1 VFRSCI NT VF RSC Enable I nt errupt I nt errupt RW
0x00148 VFPBACL VF MSI X PBA Clear PCI e RW1C
Recei ve DMA Regi st er s
0x01000 + 0x40* n,
n= 0. . . 7
VFRDBAL VF Receive Descript or Base Address Low DMA- Rx RW
0x01004 + 0x40* n,
n= 0. . . 7
VFRDBAH VF Receive Descript or Base Address High DMA- Rx RW
0x01008 + 0x40* n,
n= 0. . . 7
VFRDLEN VF Receive Descript or Ring Lengt h DMA- Rx RW
0x01010 + 0x40* n,
n= 0. . . 7
VFRDH VF Receive Descript or Head DMA- Rx RO
0x01018 + 0x40* n,
n= 0. . . 7
VFRDT VF Receive Descript or Tail DMA- Rx RW
0x01028 + 0x40* n,
n= 0. . . 7
VFRXDCTL VF Receive Descript or Cont rol DMA- Rx RW
0x01014 + 0x40* n,
n= 0. . . 7
VFSRRCTL
VF Split and Replicat ion Receive Cont rol
Regist er queue
DMA- Rx RW
0x00300 VFPSRTYPE VF Replicat ion Packet Split Receive Type DBU- Rx RW

599
8. 3. 5 Det ai l ed Regi st er Descr i pt i ons VF
All t he regist ers in t his sect ion are replicat ed per VF. The addresses are relat ive t o t he beginning of each
VF address space. The address relat ive t o BAR0 as programmed in t he I OV st ruct ure in t he PF
configurat ion space ( offset 0x180- 0x184) can be found by t he following formula:
VF BAR0 + Max( 16K, syst em page si ze) * VF# + CSR of f set .
0x0102C + 0x40* n,
n= 0. . . 7
VFRSCCTL VF RSC Cont rol DMA- Rx RW
Tr ansmi t DMA Regi st er s
0x02000 + 0x40* n,
n= 0. . . 7
VFTDBAL VF Transmit Descript or Base Address Low DMA-Tx RW
0x02004 + 0x40* n,
n= 0. . . 7
VFTDBAH VF Transmit Descript or Base Address High DMA-Tx RW
0x02008 + 0x40* n,
n= 0. . . 7
VFTDLEN VF Transmit Descript or Ring Lengt h DMA-Tx RW
0x02010 + 0x40* n,
n= 0. . . 7
VFTDH VF Transmit Descript or Head DMA-Tx RO
0x02018 + 0x40* n,
n= 0. . . 7
VFTDT VF Transmit Descript or Tail DMA-Tx RW
0x02028 + 0x40* n,
n= 0. . . 7
VFTXDCTL VF Transmit Descript or Cont rol DMA-Tx RW
0x02038 + 0x40* n,
n= 0. . . 7
VFTDWBAL
VF Tx Descript or Complet ion Writ e- Back
Address Low
DMA-Tx RW
0x0203C + 0x40* n,
n= 0. . . 7
VFTDWBAH
VF Tx Descript or Complet ion Writ e- Back
Address High
DMA-Tx RW
DCA Regi st er s
0x0100C + 0x40* n,
n= 0. . . 7
VFDCA_RXCTRL VF Rx DCA Cont rol Regist ers DMA- Rx RW
0x0200C + 0x40* n,
n= 0. . . 7
VFDCA_TXCTRL VF Tx DCA Cont rol Regist ers DMA-Tx RW
St at i st i c Regi st er
0x0101C VFGPRC VF Good Packet s Received Count DMA- Rx RO
0x0201C VFGPTC VF Good Packet s Transmit t ed Count STAT RO
0x01020 VFGORC_LSB VF Good Oct et s Received Count Low DMA- Rx RO
0x01024 VFGORC_MSB VF Good Oct et s Received Count High DMA- Rx RO
0x02020 VFGOTC_LSB VF Good Oct et s Transmit t ed Count Low STAT RO
0x02024 VFGOTC_MSB VF Good Oct et s Transmit t ed Count High STAT RO
0x01034 VFMPRC VF Mult icast Packet s Received Count DMA- Rx RO
Vi r t ual Addr ess Abbr evi at i on Name Bl ock
Reset
Sour ce
RW
I nt el

600
8. 3. 5. 1 Gener al Cont r ol Regi st er s VF
8.3. 5. 1.1 VF Cont r ol Regi st er VFCTRL ( 0x 00000; WO)
O
8.3.5. 1.2 VF St at us Regi st er VFSTATUS ( 0x 00008; R)
This regist er is a mirror of t he PF st at us regist er. See Sect ion 8.2. 3. 1. 1 for det ails of t his regist er.
8.3.5. 1.3 VF Li nk St at us Regi st er VFLI NKS ( 0x 00010; RO)
This regist er is a mirror of t he PF LI NKS regist er. See Sect ion 8. 2. 3. 22. 20 for det ails of t his regist er.
8.3.5. 1.4 VF Fr ee Runni ng Ti mer VFFRTI MER ( 0x 00048; RO)
This regist er mirrors t he value of a free running t imer regist er in t he PF RTFRTI MER. The regist er is
reset by a PCI reset and/ or soft ware reset . This regist er is a mirror of t he PF regist er.
8.3.5. 1.5 VF Mai l box VFMai l box ( 0x002FC; RW)
Not e: VFLR wont clear t he VFMAI LBOX.VFU bit . This bit should be cleared by a direct writ e access
or by set t ing PFMailbox.RVFU bit .
8.3.5. 1.6 VF Mai l box Memor y VFMBMEM ( 0x 00200 + 4* n, n= 0.. .15; RW)
Mailbox memory for PF and VF drivers communicat ion. The mailbox size for each VM is 64 byt es
accessed by32- bit regist ers. Locat ions can be accessed as 32- bit or 64- bit words.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Reser ved 25: 0 0x0 Reserved.
RST 26 0b VF Reset . This bit performs a reset of t he queue enable and t he int errupt regist ers of t he VF.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Req ( WO) 0 0b
Request for PF ready. Set t ing t his bit , causes an int errupt t o t he PF. This bit always reads as
zero. Set t ing t his bit set s t he corresponding bit in VFREQ field in PFMBI CR regist er.
Ack ( WO) 1 0b
PF message received. Set t ing t his bit , causes an int errupt t o t he PF. This bit always reads as
zero. Set t ing t his bit set s t he corresponding bit in VFACK field in PFMBI CR regist er.
VFU 2 0b
Buffer is t aken by VF. This bit can be set only if t he PFU bit is cleared and is mirrored in t he
VFU bit of t he PFMailbox regist er.
PFU 3 0b
Buffer is t aken by PF. This bit is RO for t he VF and is a mirror of t he PFU bit of t he PFMailbox
regist er.
PFSTS ( RC) 4 0b PF wrot e a message in t he mailbox.
PFACK ( RC) 5 0b PF acknowledged t he VF previous message.
RSTI ( RO) 6 1b I ndicat es t hat t he PF had reset t he shared resources and t he reset sequence is in progress.
RSTD ( RC) 7 0b I ndicat es t hat a PF soft ware reset complet ed. This bit is cleared on read.

601
8.3.5.1.7 VF Rx Pack et Buf f er Fl ush Det ect VFRXMEMWRAP ( 0x 03190; RO)
This regist er mirrors t he PF RXMEMWRAP described in Sect ion 8. 2. 3.8.11.
8.3.5.2 I nt er r upt Regi st er s VF
8.3.5.2.1 VF Ex t ended I nt er r upt Cause VFEI CR ( 0x 00100; RC/ W1C)
8.3.5.2.2 VF Ex t ended I nt er r upt Cause Set VFEI CS ( 0x 00104; WO)
8.3.5.2.3 VF Ex t ended I nt er r upt Mask Set / Read VFEI MS ( 0x 00108; RWS)
8. 3.5. 2.4 VF Ex t ended I nt er r upt Mask Cl ear VFEI MC ( 0x 0010C; WO)
8. 3.5. 2.5 VF Ex t ended I nt er r upt Aut o Mask Enabl e VFEI AM ( 0x 00114; RW)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
Mailbox Dat a 31: 0 X Mailbox Dat a field composed of 16 x 4 byt e regist ers.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MSI X 2: 0 0x0 I ndicat es an int errupt cause mapped t o MSI -X vect ors 2: 0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MSI X 2: 0 0x0 Set s t o corresponding EI CR bit of MSI -X vect ors 2: 0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MSI X 2: 0 0x0 Set Mask bit for t he corresponding EI CR bit of MSI -X vect ors 2: 0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MSI X 2: 0 0x0 Clear Mask bit for t he corresponding EI CR bit of MSI -X vect ors 2: 0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MSI X 2: 0 0x0 Aut o Mask bit for t he corresponding EI CR bit of MSI -X vect ors 2: 0.
I nt el

602
8.3.5. 2.6 VF Ex t ended I nt er r upt Mask Set / Read VFEI TR[ n] ( 0x 00820 + 4* n, n= 0...1;
RWS)
See regist er descript ion in Sect ion 8.2.3.5. 12.
8.3.5. 2.7 VF I nt er r upt Vect or Al l ocat i on Regi st er s VFI VAR[ n] ( 0x 00120 + 4* n, n= 0...3;
RW)
These regist ers map int errupt causes int o MSI -X vect ors. See addit ional det ails in Sect ion 7.3.4.
Transmit and receive queues mapping t o VFI VAR regist ers is as follows:
8.3.5. 2.8 VF I nt er r upt Vect or Al l ocat i on Regi st er s VFI VAR_MI SC ( 0x 00140; RW)
This regist er maps t he mailbox int errupt int o an MSI -X vect or. See addit ional det ails in Sect ion 7.3. 4.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I NT_Alloc[ 0] 0 X Defines t he MSI -X vect or ( 0 or 1) assigned t o Rx queue 2* N for I VAR N regist er ( N= 0. . . 3) .
reserved 6: 1 0x0 Reserved
I NT_Alloc[ 1] 8 X Defines t he MSI -X vect or ( 0 or 1) assigned t o Tx queue 2* N for I VAR N regist er ( N= 0. . . 3) .
I NT_Alloc[ 2] 16 X
Defines t he MSI -X vect or ( 0 or 1) assigned t o Rx queue 2* N+ 1 for I VAR N regist er
( N= 0. . . 3) .
I NT_Alloc[ 3] 24 X Defines t he MSI -X vect or ( 0 or 1) assigned t o Tx queue 2* N+ 1 for I VAR N regist er ( N= 0. . . 3) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
I NT_Alloc[ 0] 1: 0 X Defines t he MSI -X vect or assigned t o t he mailbox int errupt .
Rx 0
Tx 0
Rx 1
Tx 1
VTIVAR 0
Rx 2
Tx 2
Rx 3
Tx 3
VTIVAR 1
Rx 4
Tx 4
Rx 5
Tx 5
VTIVAR 2
Rx 6
Tx 6
Rx 7
Tx 7
VTIVAR 3

603
8. 3.5. 2.9 VF RSC Enabl e I nt er r upt VFRSCI NT[ n] ( 0x 00180 + 4* n, n= 0, 1; RW)
See regist er descript ion in Sect ion 8. 2. 3.5.12.
8.3.5.2.10 VF MSI X PBA Cl ear VFPBACL ( 0x 00148; RW1C)
8.3.5.3 Recei v e DMA Regi st er s VF
8.3.5.3.1 VF Recei ve Descr i pt or Base Addr ess Low VFRDBAL[ n] ( 0x 01000 + 0x 40* n,
n= 0...7; RW)
See RDBAL descript ion in Sect ion 8.2. 3. 8. 1.
8.3.5.3.2 VF Recei ve Descr i pt or Base Addr ess Hi gh VFRDBAH[ n] ( 0x 01004 + 0x 40* n,
n= 0...7; RW)
See RDBAH descript ion in Sect ion 8.2. 3. 8. 2.
8.3.5.3.3 VF Recei ve Descr i pt or Ri ng Lengt h VFRDLEN[ n] ( 0x 01008 + 0x 40* n, n= 0...7;
RW)
See RDLEN descript ion in Sect ion 8. 2.3.8.3.
8.3.5.3.4 VF Recei ve Descr i pt or Head VFRDH[ n] ( 0x 01010 + 0x 40* n, n= 0...7; RO)
See RDH descript ion in Sect ion 8. 2. 3. 8.4.
8.3.5.3.5 VF Recei ve Descr i pt or Tai l VFRDT[ n] ( 0x 01018 + 0x 40* n, n= 0...7; RW)
See RDT descript ion in Sect ion 8.2. 3. 8. 5.
8.3.5.3.6 VF Recei ve Descr i pt or Cont r ol VFRXDCTL[ n] ( 0x 01028 + 0x 40* n, n= 0...7;
RW)
See RXDCTL descript ion in Sect ion 8.2.3. 8. 6.
8.3.5.3.7 VF Spl i t and Repl i cat i on Recei v e Cont r ol Regi st er queue VFSRRCTL ( 0x 01014
+ 0x 40* n, n= 0...7; RW)
See SRRCTL descript ion in Sect ion 8. 2. 3.8.7.
8.3.5.3.8 VF Repl i cat i on Pack et Spl i t Recei ve Type VFPSRTYPE ( 0x 00300 ; RW)
See PSRTYPE descript ion in Sect ion 8. 2. 3.7.4.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
PENBI T 2: 0 000b
MSI -X Pending Bit s Clear. Writ ing a 1b t o any bit clears t he corresponding MSI XPBA bit ; writ ing
a 0x0 has no effect .
Reading t his regist er ret urns t he PBA vect or.
I nt el

604
8.3.5. 3.9 VF RSC Cont r ol VFRSCCTL[ n] ( 0x 0102C + 0x 40* n, n= 0...7; RW)
See RSCCTL descript ion in Sect ion 8. 2. 3. 8.13.
8. 3.5. 4 Tr ansmi t Regi st er s VF
8.3.5. 4.1 VF Tr ansmi t Descr i pt or Base Addr ess Low VFTDBAL[ n] ( 0x 02000 + n* 0x 40,
n= 0...3; RW)
See TDBAL descript ion in Sect ion 8. 2. 3. 9.5.
8.3.5. 4.2 VF Tr ansmi t Descr i pt or Base Addr ess Hi gh VFTDBAH[ n] ( 0x 02004 + n* 0x 40,
n= 0...3; RW)
See TDBAH descript ion in Sect ion 8.2. 3. 9.6.
8.3.5. 4.3 VF Tr ansmi t Descr i pt or Ri ng Lengt h VFTDLEN[ n] ( 0x 02008 + n* 0x 40,
n= 0...3; RW)
See TDLEN descript ion in Sect ion 8.2.3.9. 7.
8.3.5. 4.4 VF Tr ansmi t Descr i pt or Head VFTDH[ n] ( 0x 02010 + n* 0x 40, n= 0.. . 3; RO)
See TDH descript ion in Sect ion 8. 2. 3.9.8.
8.3.5. 4.5 VF Tr ansmi t Descr i pt or Tai l VFTDT[ n] ( 0x 02018 + n* 0x 40, n= 0...3; RW)
See TDT descript ion in Sect ion 8. 2. 3. 9.9.
8.3.5. 4.6 VF Tr ansmi t Descr i pt or Cont r ol VFTXDCTL[ n] ( 0x 02028 + n* 0x 40, n= 0...3;
RW)
8.3.5. 4.7 VF Tx Descr i pt or Compl et i on Wr i t e- Back Addr ess Low VFTDWBAL[ n]
( 0x 02038 + n* 0x 40, n= 0... 3; RW)
8.3.5. 4.8 VF Tx Descr i pt or Compl et i on Wr i t e- Back Addr ess Hi gh VFTDWBAH[ n]
( 0x 0203C + n* 0x 40, n= 0...3; RW)
8. 3.5. 5 DCA Regi st er s VF
8.3.5. 5.1 Rx DCA Cont r ol Regi st er s VFDCA_RXCTRL[ n] ( 0x 0100C + 0x 40* n, n= 0...7;
RW)
See DCA_RXCTRL descript ion in Sect ion 8. 2.3.11.1.

605
8.3.5.5.2 Tx DCA Cont r ol Regi st er s VFDCA_TXCTRL[ n] ( 0x 0200C + 0x 40* n, n= 0...7;
RW)
See DCA_TXCTRL descript ion in Sect ion 8.2. 3. 11. 2.
8. 3. 5. 6 St at i st i c Regi st er Descr i pt i ons VF
8.3.5.6.1 VF Good Pack et s Recei v ed Count VFGPRC ( 0x 0101C; RO)
8.3.5.6.2 VF Good Pack et s Tr ansmi t t ed Count VFGPTC ( 0x 0201C; RO)
8. 3.5. 6.3 VF Good Oct et s Recei ved Count Low VFGORC_LSB ( 0x 01020; RO)
8. 3.5. 6.4 VF Good Oct et s Recei ved Count Hi gh VFGORC_MSB ( 0x 01024; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPRC 31: 0 0x0
Number of good packet s received for t his VF ( of any lengt h) . This count er includes loopback
packet s or replicat ions of mult icast packet s.
The count er is not cleared on read. Furt hermore, t he regist er is a cyclic count er increment ing
from 0xFFFF t o 0x0000.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GPTC 31: 0 0x0
Number of good packet s sent by t he queues allocat ed t o t his VF. This count er includes
loopback packet s or packet s lat t er dropped by t he swit ch or t he MAC but does not include
packet dropped by ant i spoofing or VLAN t ag filt ering ( as described in Sect ion 7. 10. 3. 9. 2) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GORC- LSB 31: 0 0x0
Number of good oct et s received ( 32 LS bit s of a 36- bit count er) by t he queues allocat ed t o
t his VF. The count er includes loopback packet s or replicat ions of mult icast packet s. This
regist er includes byt es received in a packet from t he < Dest inat ion Address> field t hrough t he
< CRC> field, inclusively. Oct et s are count ed on t he VF int erface rat her t han on t he net work
int erface ( such as LinkSec oct et s not being count ed) .
Byt es of RSC are count ed before coalescing.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GORC- MSB 3: 0 0x0
Number of good oct et s received ( 4 MS bit s of a 36- bit count er) by t he queues allocat ed t o t his
VF. See t he complet e explanat ion in t he descript ion of t he VFGORC_LSB regist er.
from 0xF t o 0x0.
I nt el

606
8.3.5. 6.5 VF Good Oct et s Tr ansmi t t ed Count VFGOTC_LSB ( 0x 02020; RO)
8.3.5. 6.6 VF Good Oct et s Tr ansmi t t ed Count VFGOTC_MSB ( 0x 02024; RO)
8.3.5. 6.7 VF Mul t i cast Pack et s Recei ved Count VFMPRC ( 0x 01034; RO)
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GOTC- LSB 31: 0 0x0
Number of good oct et s t ransmit t ed ( 32 LS bit s of a 36- bit count er) by t he queues allocat ed t o
t his VF. This regist er includes byt es t ransmit t ed in a packet from t he < Dest inat ion Address>
field t hrough t he < CRC> field, inclusively. This regist er count s oct et s of t he packet s count ed
by t he VFGPTC regist er. Oct et s are count ed on t he VF int erface rat her t han on t he net work
int erface ( such as LinkSec oct et s not being count ed) .
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
GOTC- MSB 3: 0 0x0
Number of good oct et s t ransmit t ed ( 4 MS bit s of a 36- bit count er) by t he queues allocat ed t o
t his VF. See t he complet e explanat ion in t he descript ion of t he VFGOTC- LSB regist er.
from 0xF t o 0x0.
Fi el d Bi t ( s)
I ni t
Val .
Descr i pt i on
MPRC 31: 0 0x0
Number of mult icast good packet s received by t his VF ( of any lengt h) t hat pass Et hernet MAC
address filt ering ( excluding broadcast packet s) . The count er does not count received flow
cont rol packet s. This regist er increment s only if receives are enabled. This regist er does not
count packet s count ed by t he Missed Packet Count ( MPC) regist er.
This count er includes loopback packet s or replicat ions of mult icast packet s.
PCI e Pr ogr ammi ng I nt er f ace I nt el

607
9. 0 PCI e Pr ogr ammi ng I nt er f ace
9.1 PCI Compat i bi l i t y
PCI e is fully compat ible wit h exist ing deployed PCI soft ware. To achieve t his, PCI e hardware
implement at ions conform t o t he following requirement s:
All devices are required t o be support ed by deployed PCI soft ware and must be enumerable as part
of a t ree- t hrough PCI device enumerat ion mechanisms.
Devices must not require any resources such as address decode ranges and int errupt s beyond
t hose claimed by PCI resources for operat ion of soft ware compat ible and soft ware t ransparent
feat ures wit h respect t o exist ing deployed PCI soft ware.
Devices in t heir default operat ing st at e must confirm t o PCI ordering and cache coherency rules
from a soft ware viewpoint .
PCI e devices must conform t o t he PCI power management specificat ion and must not require any
regist er programming for PCI - compat ible power management beyond t hose available t hrough PCI
power management capabilit y regist ers. Power management is expect ed t o conform t o a st andard
PCI power management by exist ing PCI bus drivers.
PCI e devices implement all regist ers required by t he PCI specificat ion as well as t he power
management regist ers and capabilit y point ers specified by t he PCI power management specificat ion. I n
addit ion, PCI e defines a PCI e capabilit y point er t o indicat e support for PCI e ext ensions and associat ed
capabilit ies.
The 82599 is a mult i- funct ion device wit h t he following funct ions:
LAN 0
LAN 1
Different paramet ers affect how LAN funct ions are exposed on PCI e.
Bot h funct ions cont ain t he following regions of t he PCI configurat ion space ( some of t hem are enabled
by EEPROM set t ings as det ailed in t he following sect ions) :
Mandat ory PCI configurat ion regist ers
Power management capabilit ies
MSI / MSI -X capabilit ies
Vit al Product Dat a ( VPD) capabilit y
PCI e ext ended capabilit ies:
Advanced Error Report ing ( AER)
Serial I D
Alt ernat e request er I D.
Single root I OV
I nt el
82599 10 GbE Cont r ol l er PCI e Pr ogr ammi ng I nt er f ace

608
9.2 Conf i gur at i on Shar i ng Among PCI Funct i ons
The 82599 cont ains a single physical PCI e core int erface. I t is designed so t hat each of t he logical LAN
devices ( LAN 0, LAN 1) appears as a dist inct funct ion implement ing it s own PCI e device header space.
Many of t he fields of t he PCI e header space cont ain hardware default values t hat are eit her fixed or can
be overridden using an EEPROM, but might not be independent ly specified for each logical LAN device.
The following fields are considered t o be common t o bot h LAN funct ions:
The following fields are implement ed as unique t o each LAN funct ions:
Vendor I D
The Vendor I D of t he 82599 is specified t o a single value 0x8086.
The value is reflect ed ident ically for bot h LAN devices.
Revision The revision number of t he 82599 is reflect ed ident ically for bot h LAN devices.
Header Type
This field indicat es if a device is single funct ion or mult i- funct ion. The value reflect ed in t his field
is reflect ed ident ically for bot h LAN devices, but t he act ual value reflect ed depends on LAN
disable configurat ion.
When bot h t he 82599 LAN port s are enabled, bot h PCI e headers ret urn 0x80 in t his field,
acknowledging being part of a mult i- funct ion device. LAN 0 exist s as device funct ion 0, while
LAN 1 exist s as device funct ion 1.
I f funct ion 1 is disabled, t hen only a single- funct ion device is indicat ed ( t his field ret urns a value
of 0x00) and t he LAN exist s as device funct ion 0.
Subsyst em I D
The Subsyst em I D of t he 82599 can be specified via an EEPROM, but only a single value can be
specified. The value is reflect ed ident ically for bot h LAN devices.
Subsyst em Vendor I D
The Subsyst em Vendor I D of t he 82599 can be specified via an EEPROM, but only a single value
can be specified. The value is reflect ed ident ically for bot h LAN devices.
Cap_Pt r
Max Lat ency
Min Grant
These fields reflect fixed values t hat are const ant values reflect ed for bot h LAN devices.
Device I D The Device I D reflect ed for each LAN funct ion can be independent ly specified via an EEPROM.
Command
St at us
Each LAN funct ion implement s it s own Command/ St at us regist ers.
Lat ency Timer
Cache Line Size
Each LAN funct ion implement s t hese regist ers independent ly. The syst em should program t hese
fields ident ically for each LAN t o ensure consist ent behavior and performance of each device.
Memory BAR, I O BAR
Expansion ROM BAR
MSI X BAR
Each LAN funct ion implement s it s own Base Address regist ers, enabling each device t o claim it s
own address region( s) . The I / O BAR is enabled by t he I O_Sup bit in t he EEPROM.
I nt errupt Pin
Each LAN funct ion independent ly indicat es which int errupt pin ( I NTA# . . . I NTD# ) is used by t hat
devices MAC t o signal syst em int errupt s. The value for each LAN device can be independent ly
specified via an EEPROM, but only if bot h LAN devices are enabled.
Class Code
Each funct ion can have it s own device class. Funct ion 0 can be dummy funct ion, LAN or st orage
and Funct ion 1 can be eit her LAN or st orage. Bot h are enabled by t he EEPROM.

609
9.3 PCI e Regi st er Map
Configurat ion regist ers are assigned one of t he at t ribut es described in t he t able t hat follows.
9. 3. 1 Regi st er At t r i but es
The following t able list s t he regist er at t ribut es used in t his sect ion.
9.3.2 PCI e Conf i gur at i on Space Summar y
Table 9.1list s t he PCI e configurat ion regist ers while t heir det ailed descript ion is given in t he sect ions
t hat follow. PCI configurat ion fields in t he summary t able are present ed by t he following marking:
Fields t hat have meaningful default values are indicat ed in parent hesis ( val ue) .
Dot t ed fields indicat es t he same value for bot h LAN funct ions
Light - blue fields indicat e read- only fields ( loaded from t he EEPROM)
Magent a fields indicat e hard- coded values.
Ot her fields cont ain RW at t ribut es.
RD/ WR Descr i pt i on
RO Read- only regist er: Regist er bit s are read- only and cannot be alt ered by soft ware.
RW Read- writ e regist er: Regist er bit s are read- writ e and can be eit her set or reset .
RW1C Read- only st at us, Writ e- 1b- t o- clear st at us regist er, Writ ing a 0b t o RW1C bit s has no effect .
ROS
Read- only regist er wit h st icky bit s: Regist er bit s are read- only and cannot be alt ered by soft ware. Bit s are not
cleared by reset and can only be reset wit h t he PWRGOOD signal. Devices t hat consume AUX power are not
allowed t o reset st icky bit s when AUX power consumpt ion ( eit her via AUX power or PME Enable) is enabled.
RWS
Read- writ e regist er: Regist er bit s are read- writ e and can be eit her set or reset by soft ware t o t he desired st at e.
Bit s are not cleared by reset and can only be reset wit h t he PWRGOOD signal. Devices t hat consume AUX power
are not allowed t o reset st icky bit s when AUX power consumpt ion ( eit her via AUX power or PME Enable) is
enabled.
RW1CS
Read- only st at us, Writ e- 1b- t o- clear st at us regist er: Regist er bit s indicat e st at us when read, a set bit , indicat ing a
st at us event , can be cleared by writ ing a 1b t o it . Writ ing a 0b t o RW1C bit s has no effect . Bit s are not cleared by
reset and can only be reset wit h t he PWRGOOD signal. Devices t hat consume AUX power are not allowed t o reset
st icky bit s when AUX power consumpt ion ( eit her via AUX power or PME Enable) is enabled.
HwI nit
Hardware init ialized: Regist er bit s are init ialized by firmware or hardware mechanisms such as pin st rapping or
serial EEPROM. Bit s are read- only aft er init ializat ion and can only be reset ( for writ e- once by firmware) wit h t he
PWRGOOD signal.
RsvdP
Reserved and preserved: Reserved for fut ure read/ writ e implement at ions; soft ware must preserve value read for
writ es t o t hese bit s.
RsvdZ Reserved and zero: Reserved for fut ure RW1C implement at ions; soft ware must use 0b for writ es t o t hese bit s.
I nt el

610
9.3.3 Mandat or y PCI Conf i gur at i on Regi st er s Ex cept BARs
9. 3.3. 1 Vendor I D Regi st er ( 0x 0; RO)
This is a read- only regist er t hat has t he same value for all PCI funct ions. I t ident ifies unique I nt el
product s.
9. 3. 3. 2 Dev i ce I D Regi st er ( 0x 2; RO)
This is a read- only regist er t hat ident ifies individual t he 82599 PCI funct ions. Bot h port s have t he same
default value equals t o 0x10D8, and can be aut o- loaded from t he EEPROM during init ializat ion wit h
different values for each port as well as t he dummy funct ion ( See Sect ion 4. 4 for dummy funct ion
relevance) .
Tabl e 9.1. PCI Conf i gur at i on Space
Sect i on By t e Of f set By t e 3 By t e 2 Byt e 1 By t e 0
Mandat ory PCI
Regist er
0x0 Device I D Vendor I D
0x4 St at us Regist er Cont rol Regist er
0x8 Class Code ( 0x020000/ 0x010000) Revision I D
0xC Reserved
Header Type ( 0x0/
0x80)
Lat ency Timer
Cache Line Size
( 0x10)
0x10 Base Address Regist er 0
0x1C Base Address Regist er 3
0x28 CardBus CI S point er ( 0x0000)
0x2C Subsyst em I D Subsyst em Vendor I D
0x30 Expansion ROM Base Address
0x34 Reserved Cap Pt r ( 0x40)
0x38 Reserved
0x3C Max Lat ency ( 0x00) Min Grant ( 0x00)
I nt errupt Pin
( 0x01. . . 0x04)
I nt errupt Line ( 0x00)
PCI / PCI e
Capabilit ies
0x40. . . 0x47 Power management capabilit y
0x50. . . 0x67 MSI Capabilit y
0x70. . . 0x7B MSI -X Capabilit y
0xA0. . . 0xDB PCI e Capabilit y
0xE0. . . 0xE7 VPD Capabilit y
Ext ended PCI e
Configurat ion
0x100. . . 0x12B AER Capabilit y
0z140. . . 0x14B Serial I D Capabilit y
0x150. . . 0x157 ARI Capabilit y
0x160. . . 0x19C SR- I OV Capabilit y

611
9.3.3.3 Command Regi st er ( 0x 4; RW)
Shaded bit s are not used by t his implement at ion and are hardwired t o 0b. Each funct ion has it s own
Command regist er. Unless explicit ly specified, funct ionalit y is t he same in bot h funct ions.
9.3.3.4 St at us Regi st er ( 0x 6; RO)
Shaded bit s are not used by t his implement at ion and are hardwired t o 0b. Each funct ion has it s own
St at us regist er. Unless explicit ly specified, funct ionalit y is t he same in bot h funct ions.
Bi t ( s) I ni t i al Val ue Descr i pt i on
0 0b I / O Access Enable.
1 0b Memory Access Enable.
2 0b
Enable Mast ering, also named Bus Mast er Enable ( BME) ) .
LAN funct ions RW field
Dummy funct ion RO as zero field
3 0b Special Cycle Monit oring Hardwire t o 0b.
4 0b MWI Enable Hardwire t o 0b.
5 0b Palet t e Snoop Enable Hardwire t o 0b.
6 0b Parit y Error Response.
7 0b Wait Cycle Enable Hardwired t o 0b.
8 0b SERR# Enable.
9 0b Fast Back- t o- Back Enable Hardwire t o 0b.
10 1b
I nt errupt Disable. When set , devices are prevent ed from generat ing legacy
int errupt messages.
15: 11 0b Reserved.
Bi t s
I ni t i al
Val ue
RW Descr i pt i on
2: 0 0b Reserved.
3 0b RO I nt errupt St at us.
1
1. The I nt errupt St at us field is a RO field t hat indicat es t hat an int errupt message is pending int ernally t o t he device.
4 1b RO
New Capabilit ies: I ndicat es t hat a device implement s ext ended capabilit ies. The 82599
set s t his bit and implement s a capabilit ies list t o indicat e t hat it support s PCI Power
Management , Message Signaled I nt errupt s ( MSI ) , Enhanced Message Signaled I nt errupt s
( MSI -X) , VPD and t he PCI e ext ensions.
5 0b 66 MHz Capable Hard wire t o 0b.
6 0b Reserved.
7 0b Fast Back- t o- Back Capable Hard wire t o 0b.
8 0b RW1C Dat a Parit y Report ed.
10: 9 00b DEVSEL Timing Hard wire t o 0b.
11 0b RW1C Signaled Target Abort .
12 0b RW1C Received Target Abort .
13 0b RW1C Received Mast er Abort .
14 0b RW1C Signaled Syst em Error.
15 0b RW1C Det ect ed Parit y Error.
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9. 3.3. 5 Rev i si on Regi st er ( 0x 8; RO)
The default revision I D of t his device is 0x00. The value of t he rev I D is a logic XOR bet ween t he default
value and t he value in EEPROM word 0x1D. Not e t hat LAN 0 and LAN 1 funct ions have t he same
revision I D.
9. 3.3. 6 Cl ass Code Regi st er ( 0x 9; RO)
The class code is a read- only value t hat ident ifies t he device funct ionalit y according t o t he value of t he
St orage Class bit in t he EEPROM PCI e Configurat ion ( Offset 0x01) .
Class Code = 0x020000 ( Et hernet Adapt er) if EEPROM- > St orage Class = 0b
Class Code = 0x010000 ( SCSI St orage device) if EEPROM- > St orage Class = 1b
I n t he dummy funct ion t he class code equals t o 0xFF0000.
9. 3.3. 7 Cache Li ne Si ze Regi st er ( 0x C; RW)
This field is implement ed by PCI e devices as a read/ writ e field for legacy compat ibilit y purposes but has
no impact on any PCI e device funct ionalit y. Loaded from t he EEPROM. All funct ions are init ialized t o t he
same value.
9. 3.3. 8 Lat ency Ti mer ( 0x D; RO) , Not Suppor t ed
Not used. Hard wire t o 0b.
9.3.3. 9 Header Ty pe Regi st er ( 0x E; RO)
This indicat es if a device is single- or mult i- funct ion. I f a single LAN funct ion is t he only act ive one t hen
t his field has a value of 0x00 t o indicat e a single funct ion device. I f ot her funct ions are enabled t hen
t his field has a value of 0x80 t o indicat e a mult i- funct ion device. Table 9.2 list s t he different opt ions t o
set t he header t ype field.
:
9. 3.3. 10 Subsy st em Vendor I D Regi st er ( 0x 2C; RO)
This value can be loaded aut omat ically from t he EEPROM at power up or reset . A value of 0x8086 is t he
default for t his field at power up if t he EEPROM does not respond or is not programmed. All funct ions
are init ialized t o t he same value.
Tabl e 9.2. Header Ty pe Set t i ngs
Lan 0 Enabl e Lan 1 Enabl e Cr oss- Mode Enabl e Dummy Funct i on Enabl e
Header Ty pe Ex pect ed
Val ue
0 0 X X N/ A ( no funct ion)
1 0 0 X 0x00
0 1 0 0 0x00
0 1 0 1 0x80 ( dummy exist )
1 1 X X 0x80 ( dual funct ion)
1 0 1 0 0x00
1 0 1 1 0x80 ( dummy exist )
0 1 1 X 0x00

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9.3.4 Subsy st em I D Regi st er ( 0x 2E; RO)
This value can be loaded aut omat ically from t he EEPROM at power up wit h a default value of 0x0000.
9.3.5 Cap_Pt r Regi st er ( 0x 34; RO)
The Capabilit ies Point er field ( Cap_Pt r) is an 8- bit field t hat provides an offset in t he 82599' s PCI
configurat ion space for t he locat ion of t he first it em in t he capabilit ies linked list . The 82599 set s t his bit
and implement s a capabilit ies list t o indicat e t hat it support s PCI power management , MSI s, and PCI e
ext ended capabilit ies. I t s value is 0x40, which is t he address of t he first ent ry: PCI power management .
9.3.5.1 I nt er r upt Li ne Regi st er ( 0x 3C; RO)
Read/ writ e regist er programmed by soft ware t o indicat e which of t he syst em int errupt request lines t he
82599' s int errupt pin is bound t o. Refer t o t he PCI definit ion for more det ails. Each PCI funct ion has it s
own regist er.
Max_Lat / Min_Gnt not used. Hard wired t o 0b.
9.3.5.2 I nt er r upt Pi n Regi st er ( 0x 3D; RO)
Read- only regist er. LAN 0 / LAN 1
1
A value of 0x1...0x4 indicat es t hat t his funct ion implement s a
legacy int errupt on I NTA# . ..I NTD# respect ively. Loaded from t he EEPROM word offset 0x01 in t he
EEPROM PCI e Configurat ion Space per funct ion. Refer t o t he following det ailed explanat ion for cases in
which any of t he LAN port ( s) are disabled.
9.3.6 Mandat or y PCI Conf i gur at i on Regi st er s BARs
9.3. 6.1 Memor y and I O Base Addr ess Regi st er s ( 0x 10. . . 0x 27; RW)
Base Address Regist ers ( BARs) are used t o map t he 82599 regist er space of t he device funct ions. The
82599 has a memory BAR, I / O BAR and MSI -X BAR described in Table 9.3. The BARs locat ion and sizes
are described in t he Table 9.3 and Table 9.4. The fields wit hin each BAR are t hen described in Table 9.4.
PCI Funct i on Def aul t Val ue EEPROM Addr ess
LAN Funct ions 0x0000 0x0B
1. I f only a single device/ funct ion of t he 82599 component is enabled, t his value is ignored and t he
I nt errupt Pin field of t he enabled device report s I NTA# usage.
Tabl e 9. 3. t he 82599 Base Addr ess Regi st er s Descr i pt i on LAN 0 / LAN 1
Mappi ng Wi ndow s Mappi ng Descr i pt i on
Memory BAR
The int ernal regist ers memories and ext ernal Flash device are accessed as direct memory mapped
offset s from t he BAR. Soft ware can access a Dword or 64 bit s.
I / O BAR
All int ernal regist ers and memories can be accessed using I / O operat ions. There are t wo 4- byt e
regist ers in t he I / O mapping window: Addr Reg and Dat a Reg accessible as Dword ent it ies. The I / O
BAR is support ed depending on t he I O_Sup bit in t he EEPROM at word PCI e Cont rol 3 Offset 0x07.
MSI -X BAR
The MSI -X vect ors and Pending Bit Array ( PBA) st ruct ures are accessed as direct memory mapped
offset s from t he MSI -X BAR. Soft ware can access Dword ent it ies.
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9. 3.6. 2 Ex pansi on ROM Base Addr ess Regi st er ( 0x 30; RW)
This regist er is used t o define t he address and size informat ion for boot - t ime access t o t he opt ional
Flash memory. I t is enabled by EEPROM words 0x24 and 0x14 for LAN 0 and LAN 1, respect ively. This
regist er ret urns a zero value for funct ions wit hout an expansion ROM window.
9. 3. 7 PCI e Capabi l i t i es
The first ent ry of t he PCI capabilit ies link list is point ed t o by t he Cap_Pt r regist er. Table 9.5 list s t he
capabilit ies support ed by t he 82599.
Tabl e 9.4. Base Addr ess Regi st er s' Fi el ds
Fi el d bi t s RW Descr i pt i on
Memory and I / O Space
I ndicat ion
0 RO
0b = I ndicat es memory space.
1b = I ndicat es I / O.
Memory Type 2: 1 RO 10b = 64- bit BAR
Prefet ch Memory 3 R
0b = Non- prefet chable space.
1b = Prefet chable space.
The 82599 implement s non- prefet chable space since it has read- side effect s.
This bit is loaded from t he PREFBAR bit in t he NVM.
Address Space ( low regist er
for 64- bit memory BARs)
31: 4 RW
The lengt h of t he RW bit s and RO 0b bit s depend on t he mapping window sizes.
I nit ial value of t he RW fields is 0x0.
Mapping Window RO bit s
MSI -X space is 16 KB. 13: 4
I / O space size is 32 byt es ( 32- bit BAR) . 4: 0
Memory CSR + Flash BAR size depends on EEPROM PCI e
Cont rol 3 word, Flash_Size and CSR_Size fields.
16: 4 for 128 KB
17: 4 for 256 KB
and so on. . .
Fi el d Bi t ( s) RW I ni t i al Val ue Descr i pt i on
En 0 RW 0b
1b = Enables expansion ROM access.
0b = Disables expansion ROM access.
Reserved 10: 1 R 0b Always read as 0b. Writ es are ignored.
Address 31: 11 RW 0b
Read- writ e bit s are hard wired t o 0b and dependent on t he memory
mapping window size. The LAN Expansion ROM spaces can be eit her
64 KB or up t o 8 MB in powers of 2. Mapping window size is set by
EEPROM word 0x0F.
Tabl e 9.5. PCI Capabi l i t i es Li st
Addr ess I t em Nex t Poi nt er
0x40- 4F PCI Power Management 0x50 / 0xA0
1
1. I n t he dummy funct ion, t he power management capabilit y point s t o t he PCI e capabilit ies.
0x50- 6F MSI 0x70
0x70- 8F MSI -X 0xA0
0xA0- DF PCI e Capabilit ies 0xE0 / 0x00
0xE0- 0xEF VPD Capabilit y 0x00

615
9. 3. 7. 1 PCI Pow er Management Capabi l i t y
All fields are reset at full power up. All fields except PME_En and PME_St at us are reset aft er exit ing
from t he D3cold st at e. I f AUX power is not supplied, t he PME_En and PME_St at us fields also reset aft er
exit ing from t he D3cold st at e. Refer t o t he det ailed descript ion for regist ers loaded from t he EEPROM at
init ializat ion.
9.3.7.1.1 Capabi l i t y I D Regi st er ( 0x 40; RO)
This field equals 0x01 indicat ing t he linked list it em as being t he PCI Power Management regist ers.
9. 3.7. 1.2 Nex t Poi nt er Regi st er ( 0x 41; RO)
This field provides an offset t o t he next capabilit y it em in t he capabilit y list . This field equals for bot h
LAN port s t o 0x50 point ing t o t he MSI capabilit y. I n dummy funct ion, it equals t o 0xA0 point ing t o t he
PCI e Capabilit ies.
9.3.7.1.3 Pow er Management Capabi l i t i es PMC Regi st er ( 0x 42; RO)
This field describes t he device funct ionalit y during t he power management st at es as list ed in t he
following t able. Not e t hat each device funct ion has it s own regist er.
9.3.7.1.4 Pow er Management Cont r ol / St at us Regi st er PMCSR ( 0x 44; RW)
This regist er ( shown in t he following t able) is used t o cont rol and monit or power management event s in
t he device. Not e t hat each device funct ion has it s own PMCSR.
By t e Of f set By t e 3 By t e 2 By t e 1 By t e 0
0x40 Power Management Capabilit ies
Next Point er ( 0x50 /
0xA0)
Capabilit y I D ( 0x01)
0x44 Dat a
Bridge Support
Ext ensions
Power Management Cont rol & St at us
Bi t s Def aul t RW Descr i pt i on
15: 11 01001b RO
PME_Support . This 5- bit field indicat es t he power st at es in which t he funct ion can assert
PME# .
Condit ion Funct ionalit y Values:
No AUX Pwr PME at D0 and D3hot = 01001b
AUX Pwr PME at D0, D3hot , and D3cold = 11001b
10 0b RO D2_Support The 82599 does not support t he D2 st at e.
9 0b RO D1_Support The 82599 does not support t he D1 st at e.
8: 6 000b RO AUX Current Required current defined in t he Dat a regist er.
5 1b RO
DSI t he 82599 requires it s device driver t o be execut ed following a t ransit ion t o t he D0 un-
init ialized st at e.
4 0b RO Reserved.
3 0b RO PME_Clock Disabled. Hard wire t o 0b.
2: 0 011b RO Version The 82599 complies wit h t he PCI PM specificat ion revision 1. 2.
15
0b at power
up
RW1CS
PME_St at us. This bit is set t o 1b when t he funct ion det ect s a wakeup event independent
of t he st at e of t he PME_En bit . Writ ing a 1b clears t his bit .
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9.3.7. 1.5 PMCSR_BSE Br i dge Suppor t Ex t ensi ons Regi st er ( 0x 46; RO)
This regist er is not implement ed in t he 82599; values set t o 0x00.
9.3.7. 1.6 Dat a Regi st er ( 0x 47; RO)
This opt ional regist er is used t o report power consumpt ion and heat dissipat ion. The report ed regist er is
cont rolled by t he Dat a_Select field in t he PMCSR; t he power scale is report ed in t he Dat a_Scale field in
t he PMCSR. The dat a for t his field is loaded from t he EEPROM if power management is enabled in t he
EEPROM or wit h a default value of 0x00. The values for t he 82599s funct ions are as follows:
Not e: For ot her Dat a_Select values t he Dat a regist er out put is reserved ( 0b) .
9. 3. 7. 2 MSI Capabi l i t y
This st ruct ure is required for PCI e devices.
14: 13 01b RO
Dat a_Scale. This field indicat es t he scaling fact or t hat s used when int erpret ing t he value
of t he Dat a regist er.
This field equals 01b ( indicat ing 0. 1 wat t / unit s) and t he Dat a_Select field is set t o 0, 3, 4,
7, ( or 8 for funct ion 0) . Ot herwise, it equals 00b.
12: 9 0000b RW
Dat a_Select . This 4- bit field is used t o select which dat a is t o be report ed t hrough t he
Dat a regist er and Dat a_Scale field. These bit s are writ eable only when power
management is enabled via t he EEPROM.
8
0b at power
up
RWS PME_En. Writ ing a 1b t o t his regist er enables Wakeup.
7: 4 0000b RO Reserved.
3 0b RO
No_Soft _Reset . This bit is always set t o 0b t o indicat e t hat t he 82599 performs an int ernal
reset upon t ransit ioning from D3hot t o D0 via soft ware cont rol of t he PowerSt at e bit s.
Configurat ion cont ext is lost when performing t he soft reset . Upon t ransit ion from t he
D3hot t o t he D0 st at e, a full re- init ializat ion sequence is needed t o ret urn t he 82599 t o t he
D0 I nit ialized st at e.
2 0b RO Reser ved for PCI e.
1: 0 00b RW
PowerSt at e. This field is used t o set and report t he power st at e of a funct ion as follows:
00b = D0.
01b = D1 ( cycle ignored if writ t en wit h t his value) .
10b = D2 ( cycle ignored if writ t en wit h t his value) .
11b = D3
Funct i on
D0 ( Consume/
Di ssi pat e)
D3 ( Consume/
Di ssi pat e)
Common
Dat a_Scal e/
Dat a_Sel ect
( 0x0/ 0x4) ( 0x3/ 0x7) ( 0x8)
0
EEP PCI e Cont rol Word at
offset 0x06
offset 0x06
Mult i- funct ion opt ion:
offset 0x06
Single- funct ion opt ion:
0x00
01b
1
offset 0x06
offset 0x06
0x00 01b

617
This field equals 0x05 indicat ing t hat t he linked list it em as being t he MSI regist ers.
This field provides an offset t o t he next capabilit y it em in t he capabilit y list . I t s value of 0x70 and point s
t o MSI -X capabilit y.
9.3.7.2.3 Message Cont r ol Regi st er ( 0x 52; RW)
These regist er fields are list ed in t he following t able. Not e t hat t here is a dedicat ed regist er ( per PCI
funct ion) t o separat ely enable it s MSI .
9. 3.7. 2.4 Message Addr ess Low Regi st er ( 0x 54; RW)
Writ t en by t he syst em t o indicat e t he lower 32 bit s of t he address t o use for t he MSI memory writ e
t ransact ion. The lower t wo bit s always ret urn 0b regardless of t he writ e operat ion.
9.3.7.2.5 Message Addr ess Hi gh Regi st er ( 0x 58; RW)
Writ t en by t he syst em t o indicat e t he upper 32 bit s of t he address t o use for t he MSI memory writ e
t ransact ion.
0x50 Message Cont rol ( 0x0080) Next Point er ( 0x70) Capabilit y I D ( 0x05)
0x54 Message Address
0x58 Message Upper Address
0x5C Reserved Message Dat a
0x60 Mask Bit s
0x64 Pending Bit s
0 0b RW
MSI Enable. 1b = Message Signaled I nt errupt s. The 82599 generat es an MSI for
int errupt assert ion inst ead of I NTx signaling.
3: 1 000b RO
Mult iple Messages Capable. The 82599 indicat es a single request ed message per
funct ion.
6: 4 000b RO
Mult iple Message Enable. The 82599 ret urns 000b t o indicat e t hat it support s a
single message per funct ion.
7 1b RO
64- bit Capable. A value of 1b indicat es t hat t he 82599 is capable of generat ing 64-
bit message addresses.
8 1b* RO
MSI per-vect or masking. A value of 0b indicat es t hat t he 82599 is not capable of
per-vect or masking. A value of 1b indicat es t hat t he 82599 is capable of per-vect or
masking.
( * ) The value is loaded from t he MSI Mask bit in t he EEPROM.
15: 9 0b RO Reserved. Reads as 0b
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9.3.7. 2.6 Message Dat a Regi st er ( 0x 5C; RW)
Writ t en by t he syst em t o indicat e t he lower 16 bit s of t he dat a writ t en in t he MSI memory writ e Dword
t ransact ion. The upper 16 bit s of t he t ransact ion are writ t en as 0b.
9.3.7. 2.7 Mask Bi t s Regi st er ( 0x 60; RW)
The Mask Bit s and Pending Bit s regist ers enable soft ware t o disable or defer message sending on a per-
vect or basis. As t he 82599 support s only one message, only bit 0 of t hese regist ers are implement ed.
9.3.7. 2.8 Pendi ng Bi t s Regi st er ( 0x 64; RW)
9.3.8 MSI - X Capabi l i t y
More t han one MSI -X capabilit y st ruct ure per funct ion is prohibit ed while a funct ion is permit t ed t o have
bot h an MSI and an MSI -X capabilit y st ruct ure.
I n cont rast t o t he MSI capabilit y st ruct ure, which direct ly cont ains all of t he cont rol/ st at us informat ion
for t he funct ion' s vect ors, t he MSI -X capabilit y st ruct ure inst ead point s t o an MSI -X t able st ruct ure and
an MSI -X Pending Bit Array ( PBA) st ruct ure, each residing in memory space.
Each st ruct ure is mapped by a BAR belonging t o t he funct ion t hat begins at 0x10 in t he configurat ion
space. A BAR I ndicat or Regist er ( BI R) indicat es which BAR and a Qword- aligned offset indicat es where
t he st ruct ure begins relat ive t o t he base address associat ed wit h t he BAR. The BAR is 64- bit , but must
map t o t he memory space. A funct ion is permit t ed t o map bot h st ruct ures wit h t he same BAR or map
each st ruct ure wit h a different BAR.
The MSI -X t able st ruct ure ( Sect ion 9.3. 8. 2) t ypically cont ains mult iple ent ries, each consist ing of
several fields: Message Address, Message Upper Address, Message Dat a, and Vect or Cont rol. Each
ent ry is capable of specifying a unique vect or.
The PBA st ruct ure [ MSI -X PBA Regist er ( 0x78; RO) ] cont ains t he funct ion' s pending bit s, one per t able
ent ry, organized as a packed array of bit s wit hin Qwords. The last Qword is not necessarily fully
populat ed.
To request service using a given MSI -X t able ent ry, a funct ion performs a Dword memory writ e
t ransact ion using:
The cont ent s of t he Message Dat a field ent ry for dat a
The cont ent s of t he Message Upper Address field for t he upper 32 bit s of t he address
The cont ent s of t he Message Address field ent ry for t he lower 32 bit s of t he address
A memory read t ransact ion from t he address t arget ed by t he MSI -X message produces undefined
result s.
0 0b RW MSI Vect or 0 Mask. I f set , t he 82599 is prohibit ed from sending MSI messages.
31: 1 0x0 RO Reserved
0 0b RO I f set , t he 82599 has a pending MSI message.
31: 1 0x0 RO Reserved

619
The MSI -X t able and MSI -X PBA are permit t ed t o co- reside wit hin a nat urally aligned 4 KB address
range, t hough t hey must not overlap wit h each ot her.
MSI -X t able ent ries and Pending bit s are each numbered 0 t hrough N- 1, where N- 1 is indicat ed by t he
Table Size field in t he MSI -X Message Cont rol regist er. For a given arbit rary MSI -X t able ent ry K, it s
st art ing address can be calculat ed wit h t he formula:
Ent ry st art ing address = Table base + K* 16
For t he associat ed Pending bit K, it s address for Qword access and bit number wit hin t hat Qword can be
calculat ed wit h t he formulas:
Qword address = PBA base + ( K div 64) * 8
Qword bit # = K mod 64
Soft ware t hat chooses t o read Pending bit K wit h Dword accesses can use t hese formulas:
Dword address = PBA base + ( K div 32) * 4
Dword bit # = K mod 32
9. 3. 8. 1 MSI - X Capabi l i t y St r uct ur e
This field equals 0x11 indicat ing t hat t he linked list it em as being t he MSI -X regist ers.
This field provides an offset t o t he next capabilit y it em in t he capabilit y list . I t s value of 0xA0 point s t o
PCI e capabilit y.
9.3.8.1.3 Message Cont r ol Regi st er ( 0x 72; RW)
These regist er fields are list ed in t he following t able. Not e t hat t here is a dedicat ed regist er ( per PCI
funct ion) .
By t e Of f set By t e 3 Byt e 2 By t e 1 By t e 0
0x70 Message Cont rol ( 0x00090) Next Point er ( 0xA0) Capabilit y I D ( 0x11)
0x74 Table Offset
0x78 PBA Offset
10: 0 0x3F RO
Table Size. Syst em soft ware reads t his field t o det ermine t he MSI -X Table Size N,
which is encoded as N- 1. The 82599 support s up t o 64 different int errupt vect ors
per funct ion.
This field is loaded from t he EEPROM MSI _X _N field.
13: 11 0b RO Always ret urns 0b on a read. A writ e operat ion has no effect .
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9.3.8. 1.4 MSI - X Tabl e Of f set Regi st er ( 0x 74; RW)
These regist er fields are list ed in t he following t able.
9.3.8. 1.5 MSI - X Pendi ng Bi t Ar r ay PBA Of f set ( 0x 78; RW)
This regist er fields are list ed in t he following t able.
9. 3.8. 2 MSI - X Tabl e St r uct ur e
14 0b RW
Funct ion Mask. I f 1b, all of t he vect ors associat ed wit h t he funct ion are masked,
regardless of t heir per-vect or Mask bit st at es.
I f 0b, each vect or s Mask bit det ermines whet her t he vect or is masked or not .
Set t ing or clearing t he MSI -X Funct ion Mask bit has no effect on t he st at e of t he
per-vect or Mask bit s.
15 0b RW
MSI -X Enable. I f 1b and t he MSI Enable bit in t he MSI Message Cont rol regist er is
0b, t he funct ion is permit t ed t o use MSI -X t o request service and is prohibit ed from
using it s I NTx# pin.
Syst em configurat ion soft ware set s t his bit t o enable MSI -X. A device driver is
prohibit ed from writ ing t his bit t o mask a funct ions service request .
I f 0b, t he funct ion is prohibit ed from using MSI -X t o request service.
2: 0 0x3 RO
Table BI R. I ndicat es which one of a funct ions BARs, beginning at 0x10 in t he
configurat ion space, is used t o map t he funct ions MSI -X t able int o t he memory
space. while BI R values: 0. . . 5 correspond t o BARs 0x100x 24 respect ively.
31: 3 0x000 RO
Table Offset . Used as an offset from t he address cont ained in one of t he funct ions
BARs t o point t o t he base of t he MSI -X t able. The lower t hree Table BI R bit s are
masked off ( set t o 0b) by soft ware t o form a 32- bit Qword- aligned offset .
Not e t hat t his field is read only.
2: 0 0x4 RO
PBA BI R. I ndicat es which one of a funct ions BARs, beginning at 0x10 in t he
configurat ion space, is used t o map t he funct ions MSI -X PBA int o t he memory
space. while BI R values: 0. . . 5 correspond t o BARs 0x100x 24 respect ively.
31: 3 0x0400 RO
PBA Offset . Used as an offset from t he address cont ained in one of t he funct ions
BARs t o point t o t he base of t he MSI -X PBA. The lower t hree PBA BI R bit s are
masked off ( set t o 0b) by soft ware t o form a 32- bit Qword- aligned offset .
This field is read only.
Dw or d3
MSI XTVCTRL
Dw or d2
MSI XTMSG
Dw or d1
MSI XTUADD
Dw or d0
MSI XTADD
Ent r y
Number
BAR 3 Of f set
Vect or Cont rol Msg Dat a Msg Upper Addr Msg Lower Addr 0 Base ( 0x0000)
Vect or Cont rol Msg Dat a Msg Upper Addr Msg Lower Addr 1 Base + 1* 16



621
Not e: All MSI -X vect ors > MSI -X 63, are usable only by t he Virt ual Funct ions ( VFs) in I OV mode.
These vect ors are not exposed t o t he operat ing syst em by t he Table Size field in t he MSI -X
Message Cont rol word.
9.3.8.2.1 MSI X Message Addr ess Low MSI XTADD ( BAR3: 0x 0 + 0x 10* n, n= 0...255;
RW)
9.3.8.2.2 MSI X Message Addr ess Hi gh MSI XTUADD ( BAR3: 0x 4 + 0x 10* n, n= 0... 255;
RW)
9.3.8.2.3 MSI X Message Dat a MSI XTMSG ( BAR3: 0x 8 + 0x 10* n, n= 0...255; RW)
Bi t s Def aul t Ty pe Descr i pt i on
1: 0 0x00 RW
Message Address. For proper Dword alignment , soft ware must always writ e zeroes
t o t hese t wo bit s; ot herwise, t he result is undefined. The st at e of t hese bit s aft er
reset must be 0b. These bit s are permit t ed t o be read- only or read/ writ e.
31: 2 0x00 RW
Message Address. Syst em- specified message lower address.
For MSI -X messages, t he cont ent s of t his field from an MSI -X t able ent ry specifies
t he lower port ion of t he Dword- aligned address ( AD[ 31: 02] ) for t he memory writ e
t ransact ion. This field is read/ writ e.
31: 0 0x00 RW
Message Upper Address. Syst em- specified message upper address bit s. I f t his field
is zero, Single Address Cycle ( SAC) messages are used. I f t his field is non-zero,
Dual Address Cycle ( DAC) messages are used. This field is read/ writ e.
31: 0 0x00 RW
Message Dat a. Syst em- specified message dat a.
For MSI -X messages, t he cont ent s of t his field from an MSI -X t able ent ry specifies
t he dat a driven on AD[ 31: 0] during t he memory writ e t ransact ions dat a phase.
This field is read/ writ e.
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9.3.8. 2.4 MSI X Vect or Cont r ol MSI XTVCTRL ( BAR3: 0x C + 0x 10* n, n= 0...255; RW)
9. 3.8. 3 MSI - X PBA St r uct ur e ( BAR3: 0x 2000 + 4* n, n= 0. . . 7; RW)
Not e: Regist ers 2...7 are usable only by t he VFs in I OV mode. These regist ers are not exposed t o
t he operat ing syst em by t he Table Size field in t he MSI -X Message Cont rol word.
9.3.9 VPD Regi st er s
The 82599 support s access t o a VPD st ruct ure st ored in t he EEPROM using t he following set of
regist ers.
I nit ial values of t he configurat ion regist ers are marked in parent hesis.
Not e: The VPD st ruct ure is available t hrough bot h port s funct ions. As t he int erface is common t o t he
t wo funct ions, accessing t he VPD st ruct ure of one funct ion while an access t o t he EEPROM is
in process on t he ot her funct ion can yield t o unexpect ed result s.
9. 3. 9. 1 Capabi l i t y I D Regi st er ( 0x E0; RO)
This field equals 0x3 indicat ing t he linked list it em as being t he VPD regist ers.
9. 3.9. 2 Nex t Poi nt er Regi st er ( 0x E1; RO)
Offset t o t he next capabilit y it em in t he capabilit y list . A 0x00 value indicat es t hat it is t he last it em in
t he capabilit y- linked list .
9. 3. 9. 3 VPD Addr ess Regi st er ( 0x E2; RW)
word- aligned byt e address of t he VPD area in t he EEPROM t o be accessed. The regist er is read/ writ e,
and t he init ial value at power- up is indet erminat e.
0 1b RW
Mask Bit . When t his bit is set , t he funct ion is prohibit ed from sending a message
using t his MSI -X t able ent ry. However, any ot her MSI -X t able ent ries programmed
wit h t he same vect or are st ill capable of sending an equivalent message unless
t hey are also masked.
This bit s st at e aft er reset is 1b ( ent ry is masked) .
This bit is read/ writ e.
31: 1 0x00 RW
Reserved. Aft er reset , t he st at e of t hese bit s must be 0b.
However, for pot ent ial fut ure use, soft ware must preserve t he value of t hese
reserved bit s when modifying t he value of ot her Vect or Cont rol bit s. I f soft ware
modifies t he value of t hese reserved bit s, t he result is undefined.
PENBI T 31: 0 0x0
MSI -X Pending Bit s. Each bit is set t o 1b when t he appropriat e int errupt request is set
and cleared t o 0b when t he appropriat e int errupt request is cleared. Bit i in regist er N
is associat ed t o MSI -X vect or 32 * N + i, N = 0. . . 3.
Byt e Of f set By t e 3 By t e 2 By t e 1 By t e 0
0xE0 VPD Address Next Point er ( 0x00) Capabilit y I D ( 0x03)
0xE4 VPD Dat a

623
9.3.9.4 VPD Dat a Regi st er ( 0x E4; RW)
VPD read/ writ e dat a.
9.3.10 PCI e Conf i gur at i on Regi st er s
The 82599 implement s t he PCI e capabilit y st ruct ure linked t o t he legacy PCI capabilit y list for endpoint
devices as follows:
Bi t s Def aul t Rd/ Wr Descr i pt i on
14: 0 X RW
Address: Dword- aligned byt e address of t he VPD area in t he EEPROM t o be accessed. The
regist er is read/ writ e, and t he init ial value at power- up is indet erminat e. The t wo LSBs
are RO as zero.
15 0b RW
F: A flag used t o indicat e when t he t ransfer of dat a bet ween t he VPD Dat a regist er and
t he st orage component complet es. The Flag regist er is writ t en when t he VPD Address
regist er is writ t en.
0b = Read. Set by hardware when dat a is valid.
1b = Writ e. Cleared by hardware when dat a is writ t en t o t he EEPROM.
The VPD address and dat a should not be modified before t he act ion is done.
Bi t s Def aul t Rd/ Wr Descr i pt i on
31: 0 X RW
VPD Dat a: VPD dat a can be read or writ t en t hrough t his regist er. The LS byt e of t his
regist er ( at offset 4 in t his capabilit y st ruct ure) corresponds t o t he byt e of VPD at t he
address specified by t he VPD Address regist er. The dat a read from or writ t en t o t his
regist er uses t he normal PCI byt e t ransfer capabilit ies. Four byt es are always t ransferred
bet ween t his regist er and t he VPD st orage component . Reading or writ ing dat a out side of
t he VPD space in t he st orage component is not allowed.
I n a writ e access, t he dat a should be set before t he address and t he flag is set .
0xA0 PCI Express Capabilit y Regist er ( 0x0002) Next Point er ( 0xE0) Capabilit y I D ( 0x10)
0xA4 Device Capabilit y
0xA8 Device St at us Device Cont rol
0xAC Link Capabilit y
0xB0 Link St at us Link Cont rol
0xB4 Reserved
0xB8 Reserved Reserved
0xBC Reserved
0xC0 Reserved Reserved
0xC4 Device Capabilit y 2
0xC8 Reserved Device Cont rol 2
0xCC Reserved
0xD0 Link St at us 2 Link Cont rol 2
0xD4 Reserved
0xD8 Reserved Reserved
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9. 3. 10. 1 Capabi l i t y I D Regi st er ( 0x A0; RO)
This field equals 0x10 indicat ing t hat t he linked list it em as being t he PCI e Capabilit ies regist ers.
9. 3.10. 2 Nex t Poi nt er Regi st er ( 0x A1; RO)
Offset t o t he next capabilit y it em in t he capabilit y list . I t s value of 0xE0 point s t o t he VPD st ruct ure. I f
VPD is disabled, a value of 0x00 value indicat es t hat it is t he last it em in t he capabilit y- linked list .
9. 3. 10. 3 PCI e Capabi l i t i es Regi st er ( 0x A2; RO)
The PCI e Capabilit ies regist er ident ifies PCI e device t ype and associat ed capabilit ies. This is a read- only
regist er ident ical t o all funct ions.
9. 3. 10. 4 Dev i ce Capabi l i t i es Regi st er ( 0x A4; RO)
This regist er ident ifies t he PCI e device specific capabilit ies. I t is a read- only regist er wit h t he same
value for t he t wo LAN funct ions and for all ot her funct ions.
3: 0 0010b RO
Capabilit y Version. I ndicat es t he PCI e capabilit y st ruct ure version. The 82599
support s PCI e version 2 ( also loaded from t he PCI e Capabilit y Version bit in t he
EEPROM) .
7: 4 0000b RO
Device/ Port Type. I ndicat es t he t ype of PCI e funct ions. All funct ions are nat ive PCI
funct ions wit h a value of 0000b.
8 0b RO
Slot I mplement ed. The 82599 does not implement slot opt ions. Therefore, t his
field is hard wired t o 0b.
13: 9 00000b RO
I nt errupt Message Number. The 82599 does not implement mult iple MSI per
funct ion. As a result , t his field is hard wired t o 0x0.
15: 14 00b RO Reserved.
Bi t s Rd/ Wr Def aul t Descr i pt i on
2: 0 RO 010b
Max Payload Size Support ed. This field indicat es t he maximum payload t hat The
82599 can support for TLPs. I t is loaded from t he EEPROM wit h a default value of
512 byt es.
4: 3 RO 00b Phant om Funct ion Support ed. Not support ed by t he 82599.
5 RO 0b
Ext ended Tag Field Support ed. Maximum support ed size of t he Tag field. The
82599 support s a 5- bit Tag field for all funct ions.
8: 6 RO 011b
Endpoint L0s Accept able Lat ency. This field indicat es t he accept able lat ency t hat
t he 82599 can wit hst and due t o t he t ransit ion from L0s st at e t o t he L0 st at e. All
funct ions share t he same value loaded from t he EEPROM PCI e I nit Configurat ion 1
bit s [ 8: 6] .
A value of 011b equals 512 ns.
11: 9 RO 110b
Endpoint L1 Accept able Lat ency. This field indicat es t he accept able lat ency t hat t he
82599 can wit hst and due t o t he t ransit ion from L1 st at e t o t he L0 st at e.
A value of 110b equals 32 s- 64 s.
All funct ions share t he same value loaded from t he EEPROM.
12 RO 0b At t ent ion But t on Present . Hard wired in t he 82599 t o 0b for all funct ions.
13 RO 0b At t ent ion I ndicat or Present . Hard wired in t he 82599 t o 0b for all funct ions.
14 RO 0b Power I ndicat or Present . Hard wired in t he 82599 t o 0b for all funct ions.
15 RO 1b Role Based Error Report ing. Hard wired in t he 82599 t o 1b for all funct ions.
17: 16 RO 000b Reserved 0b.

625
9.3.10.5 Dev i ce Cont r ol Regi st er ( 0x A8; RW)
This regist er cont rols t he PCI e specific paramet ers. Not e t hat t here is a dedicat ed regist er per each
funct ion.
25: 18 RO 0x00
Slot Power Limit Value. Used in upst ream port s only. Hard wired in t he 82599 t o
0x00 for all funct ions.
27: 26 RO 00b
Slot Power Limit Scale. Used in upst ream port s only. Hard wired in t he 82599 t o 0b
for all funct ions.
28 RO 1b
Funct ion Level Reset Capabilit y A value of 1b indicat es t he
Funct ion support s t he opt ional Funct ion Level Reset ( FLR) mechanism.
31: 29 RO 0000b Reserved.
Bi t s RW Def aul t Descr i pt i on
0 RW 0b Correct able Error Report ing Enable. Enable error report .
1 RW 0b Non- Fat al Error Report ing Enable. Enable error report .
2 RW 0b Fat al Error Report ing Enable. Enable error report .
3 RW 0b Unsupport ed Request Report ing Enable. Enable error report .
4 RW 1b
Enable Relaxed Ordering. I f t his bit is set , t he 82599 is permit t ed t o set t he
Relaxed Ordering bit in t he At t ribut e field of writ e t ransact ions t hat do not need
st rong ordering. Refer t o t he CTRL_EXT regist er bit RO_DI S for more det ails.
7: 5 RW 000b ( 128 byt es)
Max Payload Size. This field set s t he maximum TLP payload size for t he 82599
funct ions. As a receiver, t he 82599 must handle TLPs as large as t he set value. As a
t ransmit t er, t he 82599 must not generat e TLPs exceeding t he set value.
The Max Payload Size field support ed in t he Device Capabilit ies regist er indicat es
permissible values t hat can be programmed.
I n ARI mode, Max Payload Size is det ermined solely by t he field in funct ion 0 while
it is meaningless in t he ot her funct ion( s) .
8 RW 0b Ext ended Tag field Enable. Not implement ed in t he 82599.
9 RW 0b Phant om Funct ions Enable. Not implement ed in t he 82599.
10 RWS 0b
Auxiliary Power PM Enable. When set , enables t he 82599 t o draw AUX power
independent of PME AUX power. The 82599 is a mult i- funct ion device, t herefore
allowed t o draw AUX power if at least one of t he funct ions has t his bit set .
11 RW 1b Reserved
14: 12 RW 010b
Max Read Request Size. This field set s maximum read request size for t he 82599
as a request er.
000b = 128 byt es.
001b = 256 byt es.
010b = 512 byt es.
011b = 1024 byt es.
100b = 2048 byt es.
101b = 4096 byt es ( unsupport ed by 82599) .
110b = Reserved.
111b = Reserved.
15 RW 0b
I nit iat e FLR A writ e of 1b init iat es FLR t o t he funct ion. The value read by soft ware
from t his bit is always 0b.
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9. 3.10. 6 Dev i ce St at us Regi st er ( 0x AA; RW1C)
This regist er provides informat ion about PCI e device specific paramet ers. Not e t hat t here is a dedicat ed
regist er per each funct ion.
9. 3. 10. 7 Li nk Capabi l i t i es Regi st er ( 0x AC; RO)
This regist er ident ifies PCI e link- specific capabilit ies. This is a read- only regist er ident ical t o all
funct ions.
0 RW1C 0b Correct able Det ect ed. I ndicat es st at us of correct able error det ect ion.
1 RW1C 0b Non- Fat al Error Det ect ed. I ndicat es st at us of non- fat al error det ect ion.
2 RW1C 0b Fat al Error Det ect ed. I ndicat es st at us of fat al error det ect ion.
3 RW1C 0b
Unsupport ed Request Det ect ed. I ndicat es t hat t he 82599 received an unsupport ed
request . This field is ident ical in all funct ions. The 82599 can t dist inguish which
funct ion causes t he error.
4 RO 0b
Aux Power Det ect ed. I f Aux Power is det ect ed, t his field is set t o 1b. I t is a
st rapping signal from t he periphery and is ident ical for all funct ions. Reset s on LAN
Power Good and PE_RST_N only.
5 RO 0b
Transact ion Pending. I ndicat es whet her t he 82599 has ANY t ransact ions pending.
( t ransact ions include complet ions for any out st anding non- post ed request for all
used t raffic classes) .
15: 6 RO 0x00 Reserved.
3: 0 RO 0010b
Support ed Link Speeds. This field indicat es t he support ed Link speed( s) of t he
associat ed link port .
Defined encodings are:
0001b = 2. 5 GbE link speed support ed.
0010b = 5 GbE and 2. 5 GbE link speeds support ed.
9: 4 RO 0x08
Max Link Widt h. I ndicat es t he maximum link widt h. The 82599 support s a x1, x2,
x4 and x8- link widt h wit h a default value of eight lanes.
Defined encoding:
000000b = Reserved
000001b = x1
000010b = x2
000100b = x4
001000b = x8
11: 10 RO 11b
Act ive St at e Link PM Support . I ndicat es t he level of t he act ive st at e of power
management support ed in t he 82599. Defined encodings are:
00b = Reserved.
01b = L0s Ent ry Support ed.
10b = Reserved.
11b = L0s and L1 Support ed.
All funct ions share t he same value loaded from t he EEPROM Act _St at _PM_Sup field
in t he EEPROM PCI e I nit Configurat ion 3 word at offset 0x3.

627
9.3.10.8 Li nk Cont r ol Regi st er ( 0x B0; RO)
This regist er cont rols PCI e link specific paramet ers. There is a dedicat ed regist er per each funct ion.
14: 12 RO
001b
( 64- 128 ns)
L0s Exit Lat ency. I ndicat es t he exit lat ency from L0s t o L0 st at e. 000b = Less t han
64 ns.
001b = 64 ns 128 ns.
010b = 128ns 256 ns.
011b = 256 ns 512 ns.
100b = 512 ns 1 s.
101b = 1 s 2 s.
110b = 2 s 4 s.
111b = Reserved.
17: 15 RO 111b
L1 Exit Lat ency. I ndicat es t he exit lat ency from L1 t o L0 st at e.
000b = Less t han 1 s.
001b = 1 s 2 s.
010b = 2 s 4 s.
011b = 4 s 8 s.
100b = 8 s 16 s.
101b = 16 s 32 s.
110b = 32 s 64 s.
111b = L1 t ransit ion not support ed.
18 RO 0 Clock Power Management
19 RO 0
Surprise Down Error Report ing Capable.
Hard wired t o 0b.
20 RO 0 Dat a Link Layer Link Act ive Report ing Capable.
21 RO 0
Link Bandwidt h Not ificat ion Capabilit y.
Hard wired t o 0b.
23: 22 RO 00b Reserved
31: 24 HwI nit 0x0
Port Number. The PCI e port number for t he given PCI e link. This field is set in t he
link t raining phase.
1: 0 RW 00b
Act ive St at e Link PM Cont rol. This field cont rols t he act ive st at e PM support ed on
t he link. Link PM funct ionalit y is det ermined by t he lowest common denominat or of
all funct ions. Defined encodings are:
00b = PM Disabled.
01b = L0s Ent ry Support ed.
10b = Reserved.
11b = L0s and L1 Support ed.
I n ARI mode, t he ASPM is det ermined solely by t he field in funct ion 0 while it is
meaningless in t he ot her funct ion( s) .
2 RO 0b Reser ved
3 RW 0b Read Complet ion Boundary.
4 RO 0b Link Disable. Reserved for endpoint devices. Hard wired t o 0b.
5 RO 0b Ret rain Clock. Not applicable for endpoint devices. Hard wire t o 0b.
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9. 3.10. 9 Li nk St at us Regi st er ( 0x B2; RO)
This regist er provides informat ion about PCI e Link specific paramet ers. This is a read only regist er
ident ical t o all funct ions.
The following regist ers are support ed only if t he capabilit y version is t wo and above.
6 RW 0b
Common Clock Configurat ion. When set , indicat es t hat t he 82599 and t he
component at t he ot her end of t he link are operat ing wit h a common reference
clock. A value of 0b indicat es t hat t hey are operat ing wit h an asynchronous clock.
This paramet er affect s t he L0s exit lat encies.
I n ARI mode, t he common clock configurat ion is det ermined solely by t he field in
funct ion 0 while it is meaningless in t he ot her funct ion( s) .
7 RW 0b
Ext ended Sync. When set , t his bit forces an ext ended Tx of t he FTS ordered set in
FTS and an ext ra TS1 at t he exit from L0s prior t o ent ering L0.
8 RO 0b Reserved.
9 WR 0b
Hardware Aut onomous Widt h Disable. When set t o 1b, t his bit disables hardware
from changing t he link widt h for reasons ot her t han at t empt ing t o correct an
unreliable link operat ion by reducing link widt h.
This bit can be writ t en only by funct ion 0.
10 RO 0b
Link Bandwidt h Management I nt errupt Enable. Not support ed in t he 82599. Hard
wired t o 0b.
11 RO 0b
Link Aut onomous Bandwidt h I nt errupt Enable. Not support ed in t he 82599. Hard
wired t o 0b.
15: 12 RO 0x0 Reserved
3: 0 RO 0001b
Current Link Speed. This field indicat es t he negot iat ed link speed of t he given PCI e
link.
0001b = 2. 5 GbE PCI e link.
0010b = 5 GbE PCI e link.
All ot her encodings are reserved.
9: 4 RO 000001b
Negot iat ed Link Widt h. I ndicat es t he negot iat ed widt h of t he link.
Relevant encodings for t he 82599 are:
000001b = x1.
000010b = X2.
000100b = x4.
001000b = x8.
10 RO 0b Undefined.
11 RO 0b
Link Training. I ndicat es t hat link t raining is in progress.
This field is not applicable and is reserved for endpoint devices, and is hard wired
t o 0b.
12 HwI nit 1b
Slot Clock Configurat ion. When set , indicat es t hat t he 82599 uses t he physical
reference clock t hat t he plat form provides at t he connect or. This bit must be
cleared if t he 82599 uses an independent clock. The Slot Clock Configurat ion bit is
loaded from t he Slot _Clock_Cfg EEPROM bit .
13 RO 0b
Dat a Link Layer Link Act ive.
Not support ed in t he 82599. Hard wire t o 0b.
14 RO 0b
Link Bandwidt h Management St at us.
Not support ed in t he 82599. Hard wire t o 0b.
15 RO 0b
Link Aut onomous Bandwidt h St at us.
This bit is not applicable and is reserved for endpoint s.

629
9. 3. 10. 10 Dev i ce Capabi l i t y 2 Regi st er ( 0x C4; RO)
This regist er ident ifies t he PCI e device- specific capabilit ies. I t is a read- only regist er wit h t he same
value for bot h LAN funct ions.
9.3. 10. 11 Dev i ce Cont r ol 2 Regi st er ( 0x C8; RW)
This regist er cont rols t he PCI e specific paramet ers. Not e t hat t here is a dedicat ed regist er per each
funct ion.
3: 0 RO 1111b
Complet ion Timeout Ranges Support ed. This field indicat es t he 82599s support for
t he opt ional complet ion t imeout programmabilit y mechanism.
Four t ime value ranges are defined:
Range A: 50 s t o 10 ms.
Range B: 10 ms t o 250 ms.
Range C: 250 ms t o 4 s.
Range D: 4 s t o 64 s.
Bit s are set according t o t he following values t o show t he t imeout value ranges
t hat t he 82599 support s.
0000b = Complet ion t imeout programming not support ed. The 82599 must
implement a t imeout value in t he range of 50 s t o 50 ms.
0001b = Range A.
0010b = Range B.
0011b = Ranges A and B.
0110b = Ranges B and C.
0111b = Ranges A, B and C.
1110b = Ranges B, C and D.
1111b = Ranges A, B, C and D.
All ot her values are reserved.
4 RO 1b Complet ion Timeout Disable Support ed
5 RO 0b
ARI Forwarding Support ed. Applicable only t o Swit ch Downst ream.
Port s and Root Port s; must be 0b for ot her funct ion t ypes.
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9. 3.10. 12 Li nk Cont r ol 2 Regi st er ( 0x D0; RWS)
All RW fields in t his regist er affect t he device behavior only t hrough funct ion 0. I n funct ion 1 t hese
fields are reserved read as zeros.
3: 0 RW 0x0
Complet ion Timeout Value. For devices t hat support complet ion t imeout
programmabilit y, t his field enables syst em soft ware t o modify t he complet ion
t imeout value.
Defined encodings:
0000b = Default range: 50 s t o 50 ms.
Not e: I t is st rongly recommended t hat t he complet ion t imeout mechanism not
expire in less t han 10 ms.
Values available if Range A ( 50 s t o 10 ms) programmabilit y range is support ed:
0001b = 50 s t o 100 s.
0010b = 1 ms t o 10 ms.
Values available if Range B ( 10 ms t o 250 ms) programmabilit y range is
support ed:
0101b = 16 ms t o 55 ms.
0110b = 65 ms t o 210 ms.
Values available if Range C ( 250 ms t o 4 s) programmabilit y range is support ed:
1001b = 260 ms t o 900 ms.
1010b = 1 s t o 3. 5 s.
Values available if t he Range D ( 4 s t o 64 s) programmabilit y range is support ed:
1101b = 4 s t o 13 s.
1110b = 17 s t o 64 s.
Values not defined are reserved.
Soft ware is permit t ed t o change t he value of t his field at any t ime. For request s
already pending when t he complet ion t imeout value is changed, hardware is
permit t ed t o use eit her t he new or t he old value for t he out st anding request s and
is permit t ed t o base t he st art t ime for each request eit her on when t his value was
changed or on when each request was issued.
4 RW 0b
Complet ion Timeout Disable. When set t o 1b, t his bit disables t he complet ion
t imeout mechanism.
Soft ware is permit t ed t o set or clear t his bit at any t ime. When set , t he complet ion
t imeout det ect ion mechanism is disabled. I f t here are out st anding request s when
t he bit is cleared, it is permit t ed but not required for hardware t o apply t he
complet ion t imeout mechanism t o t he out st anding request s. I f t his is done, it is
permit t ed t o base t he st art t ime for each request on eit her t he t ime t his bit was
cleared or t he t ime each request was issued.
5 RO 0b ARI Forwarding Enable. Applicable only t o swit ch devices.
15: 6 RO 0b Reserved.
3: 0 RWS 0010b
Target Link Speed. This field is used t o set t he t arget compliance mode speed when
soft ware is using t he Ent er Compliance bit t o force a link int o compliance mode.
0001b = 2. 5 GbE t arget link speed.
0010b = 5 GbE t arget link speed.
All ot her encodings are reserved.
I f a value is writ t en t o t his field t hat does not correspond t o a speed included in t he
Support ed Link Speeds field, t he result is undefined.
The default value of t his field is t he highest link speed support ed by t he 82599 ( as
report ed in t he Support ed Link Speeds field of t he Link Capabilit ies regist er) .
4 RWS 0b
Ent er Compliance. Soft ware is permit t ed t o force a link t o ent er compliance mode
at t he speed indicat ed in t he Target Link Speed field by set t ing t his bit t o 1b in bot h
component s on a link and t hen init iat ing a hot reset on t he link.
The default value of t his field following a fundament al reset is 0b.

631
9.3.10.13 Li nk St at us 2 Regi st er ( 0x D2; RO)
9.4 PCI e Ex t ended Conf i gur at i on Space
PCI e configurat ion space is locat ed in a flat memory- mapped address space. PCI e ext ends t he
configurat ion space beyond t he 256 byt es available for PCI t o 4096 byt es. The 82599 decodes an
addit ional four bit s ( bit s 27: 24) t o provide t he addit ional configurat ion space as shown. PCI e reserves
t he remaining four bit s ( bit s 31: 28) for fut ure expansion of t he configurat ion space beyond 4096 byt es.
The configurat ion address for a PCI e device is comput ed using a PCI - compat ible bus, device, and
funct ion numbers as follows:
PCI e ext ended configurat ion space is allocat ed using a linked list of opt ional or required PCI e ext ended
capabilit ies following a format resembling PCI capabilit y st ruct ures. The first PCI e ext ended capabilit y is
locat ed at offset 0x100 in t he device configurat ion space. The first Dword of t he capabilit y st ruct ure
ident ifies t he capabilit y/ version and point s t o t he next capabilit y.
The 82599 support s t he following PCI e ext ended capabilit ies:
5 RWS 0b
Hardware Aut onomous Speed Disable. When set t o 1b, t his bit disables hardware
from changing t he link speed for reasons ot her t han at t empt ing t o correct
unreliable link operat ion by reducing link speed.
6 RO 0b
Select able De- Emphasis.
This bit is not applicable and reserved for endpoint s.
9: 7 RWS 000b
Transmit Margin. This field cont rols t he value of t he non de emphasized volt age
level at t he Transmit t er pins.
Encodings:
000b = Normal operat ing range.
001b = 800- 1200 mV for full swing and 400- 700 mV for half- swing.
010b = ( n- 1) Values must be monot onic wit h a non- zero slope. The value of n
must be great er t han 3 and less t han 7. At least t wo of t hese must be below t he
normal operat ing range of n: 200- 400 mV for full- swing and 100- 200 mV for half-
swing.
111b= ( n) reserved.
10 RWS 0b
Ent er Modified Compliance. When t his bit is set t o 1b, t he device t ransmit s
modified compliance pat t ern if t he LTSSM ent ers Polling. Compliance st at e.
11 RWS 0b
Compliance SOS. When set t o 1b, t he LTSSM is required t o send SOS periodically in
bet ween t he ( modified) compliance pat t erns.
0 RO 0b
Current De- emphasis Level. When t he link is operat ing at 5 GT/ s speed, t his bit
reflect s t he level of de- emphasis. it is undefined when t he Link is operat ing at 2. 5
GT/ s speed
Encodings:
1b - 3. 5 dB.
0b - 6 dB.
31 28 27 20 19 15 14 12 11 2 1 0
0000b Bus # Device # Fun # Regist er Address ( offset ) 00b
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632
9.4.1 Adv anced Er r or Repor t i ng Capabi l i t y ( AER)
The PCI e advanced error report ing capabilit y is an opt ional ext ended capabilit y t o support advanced
error report ing. The t ables t hat follow list t he PCI e advanced error report ing ext ended capabilit y
st ruct ure for PCI e devices.
9. 4. 1. 1 Adv anced Er r or Repor t i ng Enhanced Capabi l i t y Header Regi st er ( 0x 100;
RO)
9.4.1. 2 Uncor r ect abl e Er r or St at us Regi st er ( 0x 104; RW1CS)
The Uncorrect able Error St at us regist er report s error st at us of individual uncorrect able error sources on
a PCI e device. An individual error st at us bit t hat is set t o 1b indicat es t hat a part icular error occurred;
soft ware can clear an error st at us by writ ing a 1b t o t he respect ive bit . Regist er is cleared by
LAN_PWR_GOOD.
Tabl e 9.6. Ex t ended Capabi l i t i es l i st
Capabi l i t y Of f set Nex t Header
Advanced Error Report ing Capabilit y 0x100 0x140/ 0x150/ 0x000
1
1. Depends on EEPROM set t ings enabling t he serial numbers and ARI / I OV st ruct ures.
Serial Number 0x140 0x150/ 0x000
1
Alt ernat ive RI D I nt erpret at ion ( ARI ) 0x150 0x160
I OV support 0x160 0x000
0x100
Next Capabilit y Pt r.
( 0x140)
Version ( 0x1) AER Capabilit y I D ( 0x0001)
0x104 Uncorrect able Error St at us
0x108 Uncorrect able Error Mask
0x10C Uncorrect able Error Severit y
0x110 Correct able Error St at us
0x114 Correct able Error Mask
0x118 Advanced Error Capabilit ies and Cont rol Regist er
0x11C. . . 0x128 Header Log
Bi t
Locat i on
At t r i but e Def aul t Val ue Descr i pt i on
15: 0 RO 0x0001
Ext ended Capabilit y I D. PCI e ext ended capabilit y I D indicat ing advanced error
report ing capabilit y.
19: 16 RO 0x1
Version Number. PCI e advanced error report ing ext ended capabilit y version
number.
31: 20 RO
0x0140/ 0x0150/
0x0000
Next Capabilit y Point er. Next PCI e ext ended capabilit y point er.
See Table 9. 6 for possible values of t he next capabilit y point er.

633
9. 4. 1. 3 Uncor r ect abl e Er r or Mask Regi st er ( 0x 108; RWS)
The Uncorrect able Error Mask regist er cont rols report ing of individual uncorrect able errors by device t o
t he host bridge via a PCI e error message. A masked error ( respect ive bit set in mask regist er) is not
report ed t o t he host bridge by an individual device. Not e t hat t here is a mask bit per bit of t he
Uncorrect able Error St at us regist er.
9. 4. 1. 4 Uncor r ect abl e Er r or Sev er i t y Regi st er ( 0x 10C; RWS)
The Uncorrect able Error Severit y regist er cont rols whet her an individual uncorrect able error is report ed
as a fat al error. An uncorrect able error is report ed as fat al when t he corresponding error bit in t he
severit y regist er is set . I f t he bit is cleared, t he corresponding error is considered non- fat al.
Bi t
Locat i on
3: 0 RO 0b Reser ved
4 RW1CS 0b Dat a Link Prot ocol Error St at us.
11: 5 RO 0b Reser ved
12 RW1CS 0b Poisoned TLP St at us.
13 RW1CS 0b Flow Cont rol Prot ocol Error St at us.
14 RW1CS 0b Complet ion Timeout St at us.
15 RW1CS 0b Complet er Abort St at us.
16 RW1CS 0b Unexpect ed Complet ion St at us.
17 RW1CS 0b Receiver Over flow St at us.
18 RW1CS 0b Malformed TLP St at us.
19 RW1CS 0b ECRC Error St at us.
20 RW1CS 0b Unsupport ed Request Error St at us.
21 RO 0b ACS Violat ion St at us.
Bi t
Locat i on
3: 0 RO 0b Reserved
4 RWS 0b Dat a Link Prot ocol Error Mask.
12 RWS 0b Poisoned TLP Mask.
13 RWS 0b Flow Cont rol Prot ocol Error Mask.
14 RWS 0b Complet ion Timeout Mask.
15 RWS 0b Complet er Abort Mask.
16 RWS 0b Unexpect ed Complet ion Mask.
17 RWS 0b Receiver Overflow Mask.
18 RWS 0b Malformed TLP Mask.
19 RWS 0b ECRC Error Mask.
20 RWS 0b Unsupport ed Request Error Mask.
21 RO 0b ACS Violat ion Mask.
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634
9. 4. 1. 5 Cor r ect abl e Er r or St at us Regi st er ( 0x 110; RW1CS)
The Correct able Error St at us regist er report s error st at us of individual correct able error sources on a
PCI e device. When an individual error st at us bit is set t o 1b it indicat es t hat a part icular error occurred;
soft ware can clear an error st at us by writ ing a 1b t o t he respect ive bit . Regist er is cleared by
LAN_PWR_GOOD.
9. 4. 1. 6 Cor r ect abl e Er r or Mask Regi st er ( 0x 114; RWS)
The Correct able Error Mask regist er cont rols report ing of individual correct able errors by device t o t he
host bridge via a PCI e error message. A masked error ( respect ive bit set in mask regist er) is not
report ed t o t he host bridge by an individual device. There is a mask bit per bit in t he Correct able Error
St at us regist er.
Bi t
Locat i on
3: 0 RO 0b Reserved
4 RWS 1b Dat a Link Prot ocol Error Severit y.
12 RWS 0b Poisoned TLP Severit y.
13 RWS 1b Flow Cont rol Prot ocol Error Severit y.
14 RWS 0b Complet ion Timeout Severit y.
15 RWS 0b Complet er Abort Severit y.
16 RWS 0b Unexpect ed Complet ion Severit y.
17 RWS 1b Receiver Overflow Severit y.
18 RWS 1b Malformed TLP Severit y.
19 RWS 0b ECRC Error Severit y.
20 RWS 1b Unsupport ed Request Error Severit y.
21 RO 0b ACS Violat ion Severit y.
Bi t
Locat i on
0 RW1CS 0b Receiver Error St at us.
5: 1 RO 0b Reserved
6 RW1CS 0b Bad TLP St at us.
7 RW1CS 0b Bad DLLP St at us.
8 RW1CS 0b REPLAY_NUM Rollover St at us.
12 RW1CS 0b Replay Timer Timeout St at us.
13 RW1CS 0b Advisory Non- Fat al Error St at us.
Bi t
Locat i on
0 RWS 0b Receiver Error Mask.

635
9. 4. 1. 7 Adv anced Er r or Capabi l i t i es and Cont r ol Regi st er ( 0x 118; RO)
9.4.1.8 Header Log Regi st er ( 0x 11C: 128; RO)
The header log regist er capt ures t he header for t he t ransact ion t hat generat ed an error. This regist er is
16 byt es.
9. 4. 2 Ser i al Number
The PCI e device serial number capabilit y is an opt ional ext ended capabilit y t hat can be implement ed by
any PCI e device. The device serial number is a read- only 64- bit value t hat is unique for a given PCI e
device.
All mult i- funct ion devices t hat implement t his capabilit y must implement it for funct ion 0; ot her
funct ions t hat implement t his capabilit y must ret urn t he same device serial number value as t hat
report ed by funct ion 0.
5: 1 RO 0b Reserved
6 RWS 0b Bad TLP Mask.
7 RWS 0b Bad DLLP Mask.
8 RWS 0b REPLAY_NUM Rollover Mask.
12 RWS 0b Replay Timer Timeout Mask.
13 RWS 1b Advisory Non- Fat al Error Mask.
Bi t
Locat i on
4: 0 ROS 0b
Vect or point ing t o t he first recorded error in t he Uncorrect able Error St at us
regist er. This is a read- only field t hat ident ifies t he bit posit ion of t he first
uncorrect able error report ed in t he Uncorrect able Error St at us regist er.
5 RO 0b
ECRC Generat ion Capable. I f set , t his bit indicat es t hat t he funct ion is capable of
generat ing ECRC.
This bit is loaded from EEPROM.
6 RWS 0b ECRC Generat ion Enable. When set , ECRC generat ion is enabled.
7 RO 0b
ECRC Check Capable. I f set , t his bit indicat es t hat t he funct ion is capable of
checking ECRC.
This bit is loaded from EEPROM.
8 RWS 0b ECRC Check Enable. When set Set , ECRC checking is enabled.
Bi t
Locat i on
127: 0 ROS 0b Header of t he packet in error ( TLP or DLLP) .
Bi t
Locat i on
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636
9. 4. 2. 1 Dev i ce Ser i al Number Enhanced Capabi l i t y Header Regi st er ( 0x 140; RO)
9. 4.2. 2 Ser i al Number Regi st er s ( 0x 144: 0x 148; RO)
The Serial Number regist er is a 64- bit field t hat cont ains t he I EEE defined 64- bit Ext ended Unique
I dent ifier ( EUI - 64* ) . The regist er at offset 0x144 holds t he lower 32 bit s and t he regist er at offset
0x148 holds t he higher 32 bit s. The following figure det ails t he allocat ion of regist er fields in t he Serial
Number regist er. The t able t hat follows provides t he respect ive bit definit ions.
The serial number uses t he Et hernet MAC address according t o t he following definit ion:
The serial number can be const ruct ed from t he 48- bit Et hernet MAC address in t he following form:
0x140
( 0x150)
Version ( 0x1) Serial I D Capabilit y I D ( 0x0003)
0x144 Serial Number Regist er ( Lower Dword)
0x148 Serial Number Regist er ( Upper Dword)
Bi t ( s) At t r i but es Descr i pt i on
15: 0 RO
PCI e Ext ended Capabilit y I D. This field is a PCI - SI G defined I D number t hat indicat es t he nat ure and
format of t he ext ended capabilit y.
The ext ended capabilit y I D for t he device serial number capabilit y is 0x0003.
19: 16 RO
Capabilit y Version. This field is a PCI - SI G defined version number t hat indicat es t he version of t he
capabilit y st ruct ure present .
Not e: Must be set t o 0x1 for t his version of t he specificat ion.
31: 20 RO
Next Capabilit y Offset . This field cont ains t he offset t o t he next PCI e capabilit y st ruct ure or 0x000 if
no ot her it ems exist in t he linked list of capabilit ies.
The value of t his field is 0x150 t o point t o t he ARI capabilit y st ruct ure.
I f ARI / I OV and Serial I D are disabled in EEPROM t his field is zero. See Table 9. 6.
Bi t ( s)
Locat i on
At t r i but es Descr i pt i on
63: 0 RO
PCI e Device Serial Number. This field cont ains t he I EEE defined 64- bit EUI -
64* . This ident ifier includes a 24- bit company I D value assigned by I EEE
regist rat ion aut horit y and a 40- bit ext ension ident ifier assigned by t he
manufact urer.
Fi el d Company I D Ex t ensi on I dent i f i er
Order Addr+ 0 Addr+ 1 Addr+ 2 Addr+ 3 Addr+ 4 Addr+ 5 Addr+ 6 Addr+ 7
Most Significant Byt e Least Significant Byt e
Most Significant Bit Least Significant Bit

637
I n t his case, t he MAC label is 0xFFFF.
For example, assume t hat t he company I D is ( I nt el) 00-A0- C9 and t he ext ension ident ifier is 23- 45- 67.
I n t his case, t he 64- bit serial number is:
The Et hernet MAC address for t he serial number capabilit y is loaded from t he Serial Number Et hernet
MAC Address EEPROM field ( not t he same field t hat is loaded from EEPROM int o t he RAL and RAH
regist ers) .
Not e: The official document t hat defines EUI - 64* is: ht t p: / / st andards.ieee.org/ regaut h/ oui/
t ut orials/ EUI 64.ht ml
9.4.3 Al t er nat e Rout i ng I D I nt er pr et at i on ( ARI ) Capabi l i t y St r uct ur e
I n order t o allow more t han eight funct ions per endpoint wit hout request ing an int ernal swit ch, as is
usually needed in virt ualizat ion scenarios, t he PCI - SI G defines a new capabilit y t hat allows a different
int erpret at ion of t he Bus, Device, and Funct ion fields. The ARI capabilit y st ruct ure is as follows:
9. 4. 3. 1 PCI e ARI Header Regi st er ( 0x 150; RO)
Fi el d Company I D MAC Label Ex t ensi on i dent i f i er
Order Addr+ 0 Addr+ 1 Addr+ 2 Addr+ 3 Addr+ 4 Addr+ 5 Addr+ 6 Addr+ 7
Most Significant Byt es Least Significant Byt e
Fi el d Company I D MAC Label Ex t ensi on I dent i f i er
Order Addr + 0 Addr + 1 Addr+ 2 Addr+ 3 Addr+ 4 Addr+ 5 Addr+ 6 Addr+ 7
00 A0 C9 FF FF 23 45 67
Most Significant Byt e Least Significant Byt e
By t e Of f set By t e 3 Byt e 2 Byt e 1 By t e 0
0x150
( 0x160)
Version ( 0x1) ARI Capabilit y I D ( 0x000E)
0x154 ARI Cont rol Regist er ARI Capabilit ies
Fi el d Bi t ( s)
I ni t i al
Val ue
Access Descr i pt i on
I D 15: 0 0x000E RO
PCI e Ext ended Capabilit y I D. PCI e ext ended capabilit y I D for t he
alt ernat ive RI D int erpret at ion.
Version 19: 16 1b RO
Capabilit y Version. This field is a PCI - SI G defined version number
t hat indicat es t he version of t he capabilit y st ruct ure present .
Must be 0x1 for t his version of t he specificat ion.
Next Capabilit y
Pt r.
31: 20 0x160 RO
Next Capabilit y Offset . This field cont ains t he offset t o t he next
PCI e ext ended capabilit y st ruct ure. The value of t he 0x160 point s
t o t he I OV st ruct ure.
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638
9. 4. 3. 2 PCI e ARI Capabi l i t i es and Cont r ol Regi st er ( 0x 154; RO)
9.4.4 I OV Capabi l i t y St r uct ur e
This is t he new st ruct ure used t o support t he I OV capabilit ies report ing and cont rol. The following t ables
shows t he possible implement at ions of t his st ruct ure in t he 82599.
Fi el d Bi t ( s)
I ni t i al
Val ue
Reserved 0 0b RO Not support ed in t he 82599.
Reserved 7: 2 0b RO Reserved
NFP 15: 8
0x1 ( func 0)
0x0 ( func
1)
1
1. Even if port 0 and port 1 are swit ched or funct ion zero is a dummy funct ion, t his regist er should keep it s at t ribut es according t o
t he funct ion number. I f LAN1 is disabled, t he value of t his field in funct ion zero should be zero.
RO
Next Funct ion Point er. This field cont ains t he point er t o t he next
physical funct ion configurat ion space or 0x0000 if no ot her it ems
exist in t he linked list of funct ions. Funct ion 0 is t he st art of t he
link list of funct ions.
Reserved 22: 20 0b RO Not support ed in t he 82599.
0x150
( 0x160)
Version ( 0x1) Capabilit y I D ( 0x000E)
0x154 Cont rol Regist er Capabilit ies
0x160
Next Capabilit y Offset
( 0x0)
Version ( 0x1) I OV Capabilit y I D ( 0x0010)
0x164 SR I OV Capabilit ies
0x168 SR I OV St at us SR I OV Cont rol
0x16C Tot al VFs ( RO) I nit ial VF ( RO)
0x170 Reserved
Funct ion Dependency
Link ( RO)
Num VF ( RW)
0x174 VF St ride ( RO) First VF Offset ( RO)
0x178 VF Device I D Reserved
0x17C Support ed Page Size ( 0x553)
0x180 syst em page Size ( RW)
0x184 VF BAR0 Low ( RW)
0x188 VF BAR0 High ( RW)
0x18C VF BAR2 ( RO)
0x190 VF BAR3 Low ( RW)
0x194 VF BAR3- High ( RW)
0x198 VF BAR5 ( RO)
0x19C VF Migrat ion St at e Array Offset ( RO)

639
9.4.4.1 PCI e SR- I OV Header Regi st er ( 0x 160; RO)
9. 4. 4. 2 PCI e SR- I OV Capabi l i t i es Regi st er ( 0x 164; RO)
9. 4. 4. 3 PCI e SR- I OV Cont r ol / St at us Regi st er ( 0x 168; RW)
Fi el d Bi t ( s)
I ni t i al
Val ue
I D 15: 0 0x0010 RO
PCI e Ext ended Capabilit y I D. PCI e ext ended capabilit y I D for t he
SR- I OV capabilit y.
Version 19: 16 0x1 RO
Capabilit y Version. This field is a PCI - SI G defined version number
t hat indicat es t he version of t he capabilit y st ruct ure present .
Must be 0x1 for t his version of t he specificat ion.
Next
point er
31: 20 0x0 RO
Next Capabilit y Offset . This field cont ains t he offset t o t he next
PCI e ext ended capabilit y st ruct ure or 0x000 if no ot her it ems
exist in t he linked list of capabilit ies.
Fi el d Bi t ( s)
I ni t i al
Val ue
Reserved 20: 1 0x0 RO Reserved
Reserved 31: 21 0x0 RO Not support ed in t he 82599.
Fi el d Bi t ( s)
I ni t i al
Val ue
VFE 0 0b RW
VF Enable/ Disable.
VF Enable manages t he assignment of VFs t o t he associat ed PF. I f
VF Enable is set t o 1b, VFs must be enabled, associat ed wit h t he
PF, and exist s in t he PCI e fabric. When enabled, VFs must
respond t o and can issue PCI e t ransact ions following all ot her
rules for PCI e funct ions.
I f set t o 0b, VFs must be disabled and not visible in t he PCI e
fabric; VFs cannot respond t o or issue PCI e t ransact ions.
I n addit ion, if VF Enable is cleared aft er having been set , all of t he
VFs must no longer:
I ssue PCI e t ransact ions
Respond t o configurat ion space or memory space accesses.
The behavior must be as if an FLR was issued t o each of t he VFs.
Specifically, VFs must not ret ain any cont ext aft er VF Enable has
been cleared. Any errors already logged via PF error report ing
regist ers, remain logged. However, no new VF errors must be
logged aft er VF Enable is cleared.
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640
9. 4.4. 4 PCI e SR- I OV Max / Tot al VFs Regi st er ( 0x 16C; RO)
9. 4.4. 5 PCI e SR- I OV Num VFs Regi st er ( 0x 170; RW)
VF MSE 3 0b RW
Memory Space Enable for Virt ual Funct ions.
VF MSE cont rols memory space enable for all VFs associat ed wit h
t his PF as wit h t he Memory Space Enable bit in a funct ions PCI
command regist er. The default value for t his bit is 0b.
When VF Enable is 1, virt ual funct ion memory space access is
permit t ed only when VF MSE is Set . VFs shall follow t he same
error report ing rules as defined in t he base specificat ion if an
at t empt is made t o access a virt ual funct ions memory space when
VF Enable is 1 and VF MSE is zero.
I mplement at ion Not e: Virt ual funct ions memory space cannot be
accessed when VF Enable is zero. Thus, VF MSE is " don' t care"
when VF Enable is zero, however, soft ware may choose t o set VF
MSE aft er programming t he VF BARn regist ers, prior t o set t ing VF
Enable t o 1.
VF ARI 4 0b
RW ( func 0)
RO ( func 1)
1
VF ARI Enable. Device can locat e VFs in funct ion numbers 8 t o
255 of t he capt ured bus number.
Reserved 16 0b RO Not implement ed in t he 82599.
1. Even if port 0 and port 1 are swit ched or funct ion zero is a dummy funct ion, t his field should keep it s at t ribut es according t o t he
funct ion number.
Fi el d Bi t ( s)
I ni t i al
Val ue
I nit ialVFs 15: 0 64 RO
I nit ialVFs indicat es t he number of VFs t hat are init ially associat ed wit h t he PF. I f
VF Migrat ion Capable is cleared, t his field must cont ain t he same value as
Tot alVFs.
I n t he 82599 t his paramet er is equal t o t he Tot alVFs in t his regist er.
Tot alVFs 31: 16 64 RO
Tot alVFs defines t he maximum number of VFs t hat can be associat ed wit h t he
PF. This field is loaded from t he Max VFs field in t he I OV Cont rol Word 1 in t he
EEPROM.
Fi el d Bi t ( s) I ni t i al Val ue Access Descr i pt i on
NumVFs 15: 0 0x0 RW
Num VFs defines t he number of VFs soft ware has assigned t o t he PF.
Soft ware set s NumVFs t o any value bet ween one and t he Tot alVFs as part
of t he process of creat ing VFs. NumVFs VFs must be visible in t he PCI e
fabric aft er bot h NumVFs is set t o a valid value and VF Enable is set t o 1b.
FDL 23: 16
0x0 ( func 0)
0x1 ( func 1)
1
1. Even if port 0 and port 1 are swit ched or funct ion zero is a dummy funct ion, t his regist er should keep it s at t ribut es according t o
t he funct ion number.
RO
Funct ion Dependency Link. Defines dependencies bet ween physical
funct ions allocat ion. I n t he 82599 t here are no const raint s.
Reserved 31: 24 0 RO Reserved
Fi el d Bi t ( s)
I ni t i al
Val ue

641
9.4.4.6 PCI e SR- I OV VF RI D Mappi ng Regi st er ( 0x 174; RO)
9. 4. 4. 7 PCI e SR- I OV VF Dev i ce I D Regi st er ( 0x 178; RO)
9.4. 4.8 PCI e SR- I OV Suppor t ed Page Si ze Regi st er ( 0x 17C; RO)
Fi el d Bi t ( s)
I ni t i al
Val ue
FVO 15: 0 0x180 RO
First VF offset defines t he request or I D ( RI D) offset of t he first VF t hat is
associat ed wit h t he PF t hat cont ains t his capabilit y st ruct ure. The first VFs 16-
bit RI D is calculat ed by adding t he cont ent s of t his field t o t he RI D of t he PF
cont aining t his field.
The cont ent of t his field is valid only when VF Enable is set . I f VF Enable is 0b,
t he cont ent s are undefined.
I f t he ARI Enable bit is set , t his field changes t o 0x80.
VFS 31: 16 0x2
1
1. See Sect ion 7. 10. 2. 6. 1.
RO
VF st ride defines t he request or I D ( RI D) offset from one VF t o t he next one for
all VFs associat ed wit h t he PF t hat cont ains t his capabilit y st ruct ure. The next
VFs 16- bit RI D is calculat ed by adding t he cont ent s of t his field t o t he RI D of
t he current VF.
The cont ent s of t his field is valid only when VF Enable is set and NumVFs is
non- zero. I f VF Enable is 0b or if NumVFs is zero, t he cont ent s are undefined.
Fi el d Bi t ( s)
I ni t i al
Val ue
DEVI D 31: 16 0x10ED RO
VF Device I D. This field cont ains t he device I D t hat should be present ed for
every VF t o t he Virt ual Machine ( VM) .
The value of t his field can be read from t he I OV Cont rol Word 2 in t he
EEPROM.
Fi el d Bi t ( s)
I ni t i al
Val ue
Support ed
page Size
31: 0 0x553 RO
For PFs t hat support s t he st ride- based BAR mechanism, t his field defines t he
support ed page sizes. This PF support s a page size of 2^ ( n+ 12) if bit n is set .
For example, if bit 0 is Set , t he Endpoint ( EP) support s 4KB page sizes.
Endpoint s are required t o support 4 KB, 8 KB, 64 KB, 256 KB, 1 MB and 4 MB
page sizes. All ot her page sizes are opt ional.
VF #1 VF #2 VF #3
First VF Offset VF Stride VF Stride VF Stride
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9. 4.4. 9 PCI e SR- I OV Sy st em Page Si ze Regi st er ( 0x 180; RW)
9. 4.4. 10 PCI e SR- I OV BAR 0 Low Regi st er ( 0x 184; RW)
Fi el d Bi t ( s)
I ni t i al
Val ue
Page size 31: 0 0x1 RW
This field defines t he page size t he syst em uses t o map t he PF' s and
associat ed VFs' memory addresses. Soft ware must set t he value of t he
Syst em Page Size t o one of t he page sizes set in t he Support ed Page Sizes
field. As wit h Support ed Page Sizes, if bit n is set in Syst em Page Size, t he PF
and it s associat ed VFs are required t o support a page size of 2^ ( n+ 12) . For
example, if bit 1 is set , t he syst em is using an 8 KB page size. The result s are
undefined if more t han one bit is set in Syst em Page Size. The result s are
undefined if a bit is set in Syst em Page Size t hat is not set in Support ed Page
Sizes.
When Syst em Page Size is set , t he PF and associat ed VFs are required t o align
all BAR resources on a Syst em Page Size boundary. Each BAR size, including
VF BARn Size ( described lat er) must be aligned on a Syst em Page Size
boundary. Each BAR size, including VF BARn Size must be sized t o consume a
mult iple of Syst em Page Size byt es. All fields requiring page size alignment
wit hin a funct ion must be aligned on a Syst em Page Size boundary. VF Enable
must be zero when Syst em Page Size is set . The result s are undefined if
Syst em Page Size is set when VF Enable is set .
Fi el d Bi t ( s)
I ni t i al
Val ue
Mem 0 0b RO 0b indicat es memory space.
Mem Type 2: 1 10b RO
I ndicat es t he address space size.
10b = 64- bit .
This bit is loaded from t he I OV Cont rol word in t he EEPROM.
Prefet ch Mem 3 0b* RO
0b = Non- prefet chable space.
1b = Prefet chable space.
Memory
Address
Space
31: 4 0x0 RW
Which bit s are RW bit s and which are RO t o 0x0 depend on t he memory
mapping window size. The size is a maximum bet ween 16 KB and t he page
size.

643
9.4. 4.11 PCI e SR- I OV BAR 0 Hi gh Regi st er ( 0x 188; RW)
9.4.4.12 PCI e SR- I OV BAR 2 Regi st er ( 0x 18C; RO)
9.4.4.13 PCI e SR- I OV BAR 3 Low Regi st er ( 0x 190; RW)
9.4. 4.14 PCI e SR- I OV BAR 3 Hi gh Regi st er ( 0x 194; RW)
9.4.4.15 PCI e SR- I OV BAR 5 Regi st er ( 0x 198; RO)
9. 4. 4. 16 PCI e SR- I OV VF Mi gr at i on St at e Ar r ay Of f set Regi st er ( 0x 19C; RO)
Fi el d Bi t ( s)
I ni t i al
Val ue
BAR0 MSB 31: 0 0x0 RW MSB part of BAR0.
Fi el d Bi t ( s)
I ni t i al
Val ue
BAR2 31: 0 0x0 RO This BAR is not used.
Fi el d Bi t ( s)
I ni t i al
Val ue
Mem 0 0b RO 0b indicat es memory space.
Mem Type 2: 1 10b RO
I ndicat es t he address space size.
10b = 64- bit .
Prefet ch Mem 3 0b* RO
0b = Non- prefet chable space
1b = Prefet chable space
Memory
Address
Space
31: 4 0x0 RW
Which bit s are RW bit s and which are RO t o 0x0 depend on t he memory
mapping window size. The size is a maximum bet ween 16 KB and page size.
Fi el d Bi t ( s)
I ni t i al
Val ue
BAR3 MSB 31: 0 0x0 RW MSB part of BAR3.
Fi el d Bi t ( s)
I ni t i al
Val ue
BAR5 31: 0 0x0 RO This BAR is not used.
Fi el d Bi t ( s)
I ni t i al
Val ue
Reserved 2: 0 0x0 RO Not implement ed in t he 82599.
Reserved 31: 0 0x0 RO Not implement ed in t he 82599.
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9.5 Vi r t ual Funct i ons Conf i gur at i on Space
The configurat ion space reflect ed t o each of t he VF is a sparse version of t he physical funct ion
configurat ion space. The following t able describes t he behavior of each regist er in t he VF configurat ion
space.
Tabl e 9.7. VF PCI e Conf i gur at i on Space
Sect i on Of f set Name VF behav i or Not es
PCI Mandat ory
Regist ers
0 Vendor I D RO 0xFFFF
2 Device I D RO 0xFFFF
4 Command RW See Sect ion 9. 5. 1. 1.
6 St at us Per VF See Sect ion 9. 5. 1. 2.
8 RevisionI D RO as PF
9 Class Code RO as PF
C Cache Line Size RO 0x0
D Lat ency Timer RO 0x0
E Header Type RO 0x0
F Reserved RO 0x0
10 27 BARs RO 0x0 Emulat ed by VMM.
28 CardBus CI S RO 0x0 Not used.
2C Sub Vendor I D RO as PF
2E Sub Syst em RO as PF
30 Expansion ROM RO 0x0 Emulat ed by VMM.
34 Cap Point er RO 0x70 Next = MSI -X capabilit y.
3C I nt Line RO 0x0
3D I nt Pin RO 0x0
3E Max Lat / Min Gnt RO 0x0
MSI -X
Capabilit y
70 MSI -X Header RO 0xA011 Next = PCI e capabilit y.
72 MSI -x Message Cont rol per VF See Sect ion 9. 5. 2. 1.
74 MSI -X t able Address RO as PF
78 MSI -X PBA Address RO
PCI e Capabilit y
A0 PCI e Header RO 0x0010 Next = Last capabilit y.
A2 PCI e Capabilit ies RO 0x0
A4 PCI e Dev Cap RO 0x0
A8 PCI e Dev Ct rl RW
As PF apart from FLR See
Table 9. 5. 2. 2. 1.
AA PCI e Dev St at us per VF See Table 9. 5. 2. 2. 2.
AC PCI e Link Cap RO 0x0
B0 PCI e Link Ct rl RO 0x0
B2 PCI e Link St at us RO 0x0
C4 PCI e Dev Cap 2 RO 0x0
C8 PCI e Dev Ct rl 2 RO 0x0
D0 PCI e Link Ct rl 2 RO 0x0
D2 PCI e Link St at us 2 RO 0x0

645
AER Capabilit y
100 AER Header RO 0x15010001 Next = ARI st ruct ure.
104 AER Uncorr St at us per VF See Sect ion 9. 5. 2. 3.
108 AER Uncorr Mask RO 0x0
10C AER Uncorr Severit y RO 0x0
110 AER Corr St at us Per PF
114 AER Corr Mask RO 0x0
118 AER Cap/ Ct rl RO as PF
11C 128 AER Error Log Shared t wo logs for all VFs
Same st ruct ure as in PF. I n case of
overflow, t he header log is filled wit h
ones.
ARI Capabilit y
150 ARI Header 0x0001000E Next = Last ext ended Capabilit y.
154 ARI Cap/ Ct rl RO 0X0
Tabl e 9. 7. VF PCI e Conf i gur at i on Space ( Cont i nued)
Sect i on Of f set Name VF behav i or Not es
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9. 5. 1 Mandat or y Conf i gur at i on Space
9. 5.1. 1 VF Command Regi st er ( 0x 4; RW)
9. 5.1. 2 VF St at us Regi st er ( 0x 6; RW)
Bi t ( s)
I ni t i al
Val ue
Rd/ Wr Descr i pt i on
0 0b RO I OAE. I / O Access Enable. RO as zero field.
1 0b RO MAE. Memory Access Enable. RO as zero field.
2 0b RW
BME. Bus Mast er Enable. Disabling t his bit prevent s t he associat ed VF from issuing any
memory or I / O request s. Not e t hat as MSI / MSI -X int errupt messages are in- band
memory writ es, disabling t he bus mast er enable bit disables MSI / MSI -X int errupt
messages as well.
Request s ot her t han memory or I / O request s are not cont rolled by t his bit .
Not e: The st at e of act ive t ransact ions is not specified when t his bit is disabled aft er
being enabled. The device can choose how it behaves when t his condit ion occurs.
Soft ware cannot count on t he device ret aining st at e and resuming wit hout loss of dat a
when t he bit is re- enabled.
Transact ions for a VF t hat has it s Bus Mast er Enable set must not be blocked by
t ransact ions for VFs t hat have t heir Bus Mast er Enable cleared.
3 0b RO SCM. Special Cycle Enable. Hard wired t o 0b
4 0b RO MWI E. MWI Enable. Hard wired t o 0b.
5 0b RO PSE. Palet t e Snoop Enable. Hard wired t o 0b.
6 0b RO PER. Parit y Error Response. Zero for VFs.
7 0b RO WCE. Wait Cycle Enable. Hard wired t o 0b.
8 0b RO SERRE. SERR# Enable. Zero for VFs.
9 0b RO FB2BE. Fast Back- t o- Back Enable. Hard wired t o 0b.
10 0b RO I NTD. I nt errupt Disable. Hard wired t o 0b.
15: 11 0b RO RSV. Reserved
Bi t s
I ni t i al
Val ue
2: 0 0x0 RO RSV. Reserved
3 0b RO I S. I nt errupt St at us. Hard wired t o 0b.
4 1b RO
NC. New Capabilit ies. I ndicat es t hat t he 82599 VFs implement ext ended capabilit ies. The
82599 VFs implement a capabilit ies list , t o indicat e t hat it support s MSI -X and PCI e
ext ensions.
5 0b RO 66E. 66 MHz Capable. Hard wired t o 0b.
6 0b RO RSV. Reserved
7 0b RO FB2BC. Fast Back- t o- Back Capable. Hard wired t o 0b.
8 0b RW1C MPERR. Dat a Parit y Report ed.
10: 9 00b RO DEVSEL. DEVSEL Timing. Hard wired t o 0b.
11 0b RW1C STA. Signaled Target Abort .
12 0b RW1C RTA. Received Target Abort .
13 0b RW1C RMA. Received Mast er Abort .
14 0b RW1C SSERR. Signaled Syst em Error.
15 0b RW1C DSERR. Det ect ed Parit y Error.

647
9.5.2 PCI Capabi l i t i es
9. 5. 2. 1 MSI - X Capabi l i t y
The only regist ers wit h a different layout t han t he PF for MSI -X, is t he cont rol regist er.
Not e: The message address and dat a regist ers in enhanced mode use t he first MSI -X ent ry of each
VF in t he regular MSI -X t able.
9.5.2.1.1 VF MSI - X Cont r ol Regi st er ( 0x 72; RW) .
9.5.2.1.2 MSI - X PBA Regi st er ( 0x 78; RO)
Bi t s
I ni t i al
Val ue
10: 0 0x002
1
1. Default value is read from t he EEPROM.
RO TS. Table Size.
13: 11 0x0 RO RSV. Reserved.
14 0b RW Mask. Funct ion Mask.
15 0b RW En. MSI -X Enable.
31: 3 0x400 RO
PBA Offset . Used as an offset from t he address cont ained by one of t he funct ions BARs
t o point t o t he base of t he MSI -X PBA. The lower t hree PBA BI R bit s are masked off ( set
t o zero) by soft ware t o form a 32- bit Qword- aligned offset .
This value is changed by hardware t o be half of t he value programmed t o t he I OV
Syst em Page Size regist er.
2: 0 0x3 RO
PBA BI R. I ndicat es which one of a funct ions BARs, locat ed beginning at 0x10 in
configurat ion space, is used t o map t he funct ions MSI -X PBA int o memory space.
A BI R value of t hree indicat es t hat t he PBA is mapped in BAR 3.
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648
9. 5. 2. 2 PCI e Capabi l i t y Regi st er s
The device cont rol and device st at us regist ers have some fields which are specific per VF.
9.5.2. 2.1 VF Devi ce Cont r ol Regi st er ( 0x A8; RW)
9.5.2. 2.2 VF Devi ce St at us Regi st er ( 0x AA; RO)
0 RO 0b Correct able Error Report ing Enable. Zero for VFs.
1 RO 0b Non- Fat al Error Report ing Enable. Zero for VFs.
2 RO 0b Fat al Error Report ing Enable. Zero for VFs.
3 RO 0b Unsupport ed Request Report ing Enable. Zero for VFs.
4 RO 0b Enable Relaxed Ordering. Zero for VFs.
7: 5 RO 0b Max Payload Size. Zero for VFs.
8 RO 0b Not implement ed in t he 82599.
9 RO 0b Not implement ed in t he 82599.
10 RO 0b Auxiliary Power PM Enable. Zero for VFs.
11 RO 0b Reserved
14: 12 RO 000b Max Read Request Size. Zero for VFs.
15 RW 0b I nit iat e Funct ion Level Reset . Specific t o each VF.
0 RO 0b Correct able Det ect ed. I ndicat es st at us of correct able error det ect ion. Zero for VF.
1 RO 0b Non- Fat al Error Det ect ed. I ndicat es st at us of non- fat al error det ect ion. Zero for VF.
2 RO 0b Fat al Error Det ect ed. I ndicat es st at us of fat al error det ect ion. Zero for VF.
3 RO 0b
Unsupport ed Request Det ect ed. I ndicat es t hat t he 82599 received an unsupport ed
request . This field is ident ical in all funct ions. The 82599 can t dist inguish which funct ion
caused an error. Zero for VF.
4 RO 0b Aux Power Det ect ed. Zero for VFs.
5 RO 0b
Transact ion Pending. Specific per VF. When set , indicat es t hat a part icular funct ion ( PF
or VF) has issued non- post ed request s t hat have not been complet ed. A funct ion report s
t his bit cleared only when all complet ions for any out st anding non- post ed request s have
been received.

649
9.5.2.3 AER Regi st er s
The following regist ers in t he AER capabilit y have a different behavior in a VF funct ion.
9. 5.2. 3.1 Uncor r ect abl e Er r or St at us Regi st er ( 0x 104; RW1C)
Bi t
Locat i on
At t r i but e
Def aul t
Val ue
Descr i pt i on
4 RO 0b Dat a Link Prot ocol Error St at us
5 RO 0b Surprise Down Error St at us ( Opt ional)
12 RW1C 0b Poisoned TLP St at us
13 RO 0b Flow Cont rol Prot ocol Error St at us
14 RW1C 0b Complet ion Timeout St at us.
15 RW1C 0b Complet er Abort St at us.
16 RW1C 0b Unexpect ed Complet ion St at us.
17 RO 0b Receiver Overflow St at us.
18 RO 0b Malformed TLP St at us.
19 RO 0b ECRC Error St at us.
20 RW1C 0b Unsupport ed Request Error St at us when caused by a funct ion t hat claims a TLP.
21 RO 0b ACS Violat ion St at us.
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650
9.5.2. 3.2 Cor r ect abl e Er r or St at us Regi st er ( 0x 110; RW1C)
The Correct able Error St at us regist er report s error st at us of individual correct able error sources on a
PCI e device. When an individual error st at us bit is set t o 1b it indicat es t hat a part icular error occurred;
soft ware can clear an error st at us by writ ing a 1b t o t he respect ive bit .
Bi t
Locat i on
At t r i but e
Def aul t
Val ue
Descr i pt i on
0 RW1C 0b Receiver Error St at us.
6 RW1C 0b Bad TLP St at us.
7 RW1C 0b Bad DLLP St at us.
8 RW1C 0b REPLAY_NUM Rollover St at us.
12 RW1C 0b Replay Timer Timeout St at us.
13 RW1C 0b Advisory Non- Fat al Error St at us.
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10. 0 Manageabi l i t y
Net work management is an import ant requirement in t oday' s net worked comput er environment .
Soft ware- based management applicat ions provide t he abilit y t o administ er syst ems while t he operat ing
syst em is funct ioning in a normal power st at e ( not in a pre- boot st at e or powered- down st at e) . The
I nt el Syst em Management Bus ( SMBus) I nt erface and t he Net work Cont roller Sideband I nt erface
( NC- SI ) fill t he management void t hat exist s when t he operat ing syst em is not running or fully
funct ional. This is accomplished by providing mechanisms by which manageabilit y net work t raffic can
be rout ed t o and from a Baseboard Management Cont roller ( BMC) , or simply MC.
This sect ion describes t he support ed management int erfaces and hardware configurat ions for plat form
syst em management . I t describes t he int erfaces t o an ext ernal BMC, t he part it ioning of plat form
manageabilit y among syst em component s, and t he funct ionalit y provided by t he 82599 in each
plat form configurat ion.
10. 1 Pl at f or m Conf i gur at i ons
This sect ion describes t he hardware configurat ions for plat form management . I t describes t he
part it ioning of plat form manageabilit y among syst em component s and t he funct ionalit y provided by t he
82599 in each of t he plat form configurat ions.
The 82599 support s pass- t hrough manageabilit y t o an on- board BMC. The link bet ween t he 82599 and
t he BMC is eit her SMBus or t he DMTF NC- SI .
10.1.1 On- Boar d BMC Conf i gur at i ons
Figure 10.1 ( left opt ion) depict s an SMBus- only connect ion bet ween t he 82599 and t he BMC. The
SMBus is used for all communicat ion bet ween t he 82599 and t he BMC ( pass- t hrough t raffic,
configurat ion, and st at us) . The prot ocol det ails for t his configurat ion follow t he SMBus commands
described in Sect ion 10.2.2. Figure 10.1 ( right opt ion) depict s an NC- SI - only connect ion bet ween t he
82599 and t he BMC. The NC- SI is used for all communicat ion bet ween t he 82599 and t he BMC ( pass-
t hrough t raffic, configurat ion, and st at us) . The prot ocol det ails for t his configurat ion follow t he DMTF
NC- SI prot ocol.
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652
Fi gur e 10.1. t he 82599 t o BMC Connect i vi t y Thr ough SMBus Li nk or NC- SI Li nk
Refer t o t he sect ions t hat follow for a descript ion of t he t raffic t ypes t hat use t he NC- SI and/ or SMBus
int erfaces.
10.1. 2 t he 82599 NI C
BMC connect ion t o a NI C is not expect ed.
10.2 Pass Thr ough ( PT) Funct i onal i t y
The 82599 support s t raffic pass t hrough t o an ext ernal BMC. The pass- t hrough t raffic is carried t hrough
an NC- SI int erface or SMBus ( legacy devices) based on t he Redirect ion Sideband I nt erface set t ing in
t he EEPROM ( loaded on power up) . The usable bandwidt h for eit her direct ion is up t o 100 Mb/ s in NC- SI
mode and up t o 400 Kb/ s in SMBus mode. Supplement al descript ions on SMBus and NC- SI int erfaces
can be found in Sect ion 3. 2 and in Sect ion 3.3. The following list describes usage models for t he pass
t hrough t raffic:
BMC management t raffic
Keyboard or mouse t raffic for KVM ( low dat a rat e)
Video t raffic for KVM ( low average rat e of 150 Kb/ s t o 200 Kb/ s) t ransmit only
USB 2.0 redirect ( up t o 50 Mb/ s)
I DE redirect for remot e CD/ floppy ( rat e priorit y 1 CDx7 = 1.05 Mb/ s. Priorit y 2 CDx24 = 64
Mb/ s
Serial Over LAN ( SoL) 300 Kb/ s
10. 2. 1 DMTF NC- SI Mode
The 82599 support s all t he mandat ory feat ures of t he DMTF NC- SI spec rev1.0. 0a.
BMC 82599
IOH
PCIe*
SMBus
BMC 82599
IOH
PCIe*
NC-SI

653
10. 2. 1. 1 Suppor t ed Feat ur es
Table 10.1 list s t he commands support ed by t he 82599.
Table 10.2 list s t he NC- SI feat ures support ed by t he 82599:
Tabl e 10.1. Suppor t ed NC- SI Commands
Command Suppor t ed
Clear I nit ial St at e Yes
Get Version I D Yes
Get Paramet ers Yes
Get Cont roller Packet St at ist ics No
Get Link St at us Yes
Enable Channel Yes
Disable Channel Yes
Reset Channel Yes
Enable VLAN Yes ( filt ering only by t he VLAN I D. No filt ering by t he User priorit y)
Disable VLAN Yes
Enable BCast Yes
Disable BCast Yes
Set Et hernet MAC Address Yes
Clear Et her net MAC Address Yes
Get NC- SI St at ist ics Yes, part ially
Set NC- SI Flow Cont rol No
Set Link Command Yes ( support for 10 GbE is not fully defined in t he specificat ion)
Enable Global MCast Filt er Yes
Disable Global MCast Filt er Yes
Get Capabilit ies Yes
Set VLAN Filt ers Yes
AEN Enable Yes
Get Pass-Through St at ist ics Yes, part ially
Select Package Yes
Deselect Package Yes
Enable Channel Net work Tx Yes
Disable Channel Net work Tx Yes
OEM Command Yes
Tabl e 10.2. Opt i onal NC- SI Feat ur es Suppor t
Feat ur e Suppor t ed Det ai l s
AENs Yes.
Not e: The driver st at e AEN might be emit t ed up t o 15
seconds aft er act ual driver change.
Get NC- SI st at ist ics command Yes, part ially Support s t he following count ers: 1- 4, 7
Get NC- SI pass- t hrough st at ist ics
command
Yes, part ially
Support s t he following count ers: 2
Support s t he following count ers only when t he
operat ing syst em is down:
1, 6, 7
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10.2. 2 SMBus Pass Thr ough ( PT) Funct i onal i t y
When operat ing in SMBus mode, t he 82599 provides t he following manageabilit y services t o t he BMC
on t op of t he pass t hrough t raffic funct ionalit y:
ARP handling The 82599 can be programmed t o aut o-ARP replying for ARP request packet s and
sending grat uit ous ARP t o reduce t he t raffic over t he SMBus.
Teaming and failover The 82599 can be configured t o eit her t eaming or non- t eaming modes.
When operat ed in t eaming mode t he 82599 can also provide aut o failover configurat ions as
det ailed in t he following subsect ions.
Default configurat ion of filt ers by EEPROM When working in SMBus mode, t he default values of
t he manageabilit y receive filt ers can be set according t o t he PT LAN ( Sect ion 6. 4. 3) and flex TCO
EEPROM st ruct ure ( Sect ion 6.4.5) .
10. 2. 2. 1 Pass Thr ough ( PT) Modes
PT configurat ion depends on how t he LAN port s are configured. I f t he LAN port s are configured as t wo
different channels ( non- t eaming mode) t hen t he 82599 is present ed on t he manageabilit y link as t wo
different devices ( via t wo different SMBus addresses) on which each device is connect ed t o a different
LAN port . I n t his mode ( t he same as in t he LAN channels) , t here is no logical connect ion bet ween t he
t wo devices. I n t his mode, t he failover bet ween t he t wo LAN port s are done by t he ext ernal BMC ( by
sending/ receiving packet s t hrough different devices) . The st at us report s t o t he BMC, ARP handling,
DHCP and ot her pass t hrough funct ionalit y are unique for each port .
When t he 82599 operat es in t eaming mode, it present s it self on t he SMBus as a single device. I n t his
mode, t he ext ernal BMC is not aware t hat t here are t wo LAN port s. The 82599 det ermines how t o rout e
t he packet s t hat it receives on t he manageabilit y channel according t o t he failover algorit hm. The
st at us report s t o t he BMC and ot her pass t hrough configurat ions are common t o bot h port s.
I n pass t hrough mode most of t he manageabilit y t raffic is handled by t he BMC. However, port ion of t he
net work t raffic can be offloaded and by t he 82599 as described in t he following subsect ions. This
configurat ion can be done by issuing configurat ion commands over t he SMBus channel or t he 82599
can load it from it s EEPROM at power up ( or bot h) .
VLAN modes Yes, part ially Support s only modes 1, 3
Buffering capabilit ies Yes 8 K
Et hernet MAC address filt ers Yes Support s 2 Et hernet MAC addresses as mixed per port
Channel count Yes Support s 2 channels
VLAN filt ers Yes Support s 8 VLAN filt ers per port
Broadcast filt ers Yes
Support s t he following filt ers:
ARP
DHCP
Net BI OS
Mult icast filt ers Yes
Support s t he following filt er s ( support ed only when all
t hree are enabled) :
I Pv6 neighbor advert isement
I Pv6 rout er advert isement
DHCPv6 relay and server mult icast
NC- SI flow cont rol command No
Hardware arbit rat ion No
Tabl e 10.2. Opt i onal NC- SI Feat ur es Suppor t
Feat ur e Suppor t ed Det ai l s

655
10. 2. 2. 2 LAN Fai l - Ov er i n LAN Teami ng Mode
Manageabilit y failover is t he abilit y t o det ect t hat t he LAN connect ion on one port is lost , and enable
t he ot her port for manageabilit y t raffic. When t he 82599 operat es in t eaming mode, t he operat ing
syst em and t he ext ernal BMC consider it as one logical net work device. The decision on which of t he
82599 port s are used is done int ernally by t he 82599 ( or by t he ANS driver in case of t he regular
receive/ t ransmit t raffic) . This sect ion deals wit h failover in t eaming mode only. I n non- t eaming mode,
t he ext ernal BMC should consider t he 82599' s net work port s as t wo different net work devices, and t he
BMC is solely responsible for t he failover mechanism.
I n t eaming mode, t he 82599 maps bot h net work port s int o a single SMBus slave device. The 82599
aut omat ically handles t he configurat ions of bot h net work port s. Thus, for configurat ions, receiving and
t ransmit t ing t he BMC should consider bot h port s as a single ent it y.
When t he current ly act ive t ransmission port becomes unavailable ( such as t he link is down) , t he 82599
aut omat ically swit ches t ransmission t o t he ot her port . Thus, as long as one of t he port s is valid, t he
BMC will have a valid link indicat ion for t he SMBus slave.
Not e: As bot h port s might be act ive ( such as wit h a valid link) packet s might be received on t he
current ly non- act ive port . To avoid packet duplicat ion, failover should not be enabled when
connect ed t o a hub.
Not e: Fail over and t eaming are not support ed in NC- SI mode.
10.2.2.2.1 Por t Sw i t chi ng ( Fai l - Over )
While in t eaming mode, t ransmit t raffic is always t ransmit t ed by t he 82599 t hrough only one of t he
port s at any given t ime. The 82599 might swit ch t he t raffic t ransmission bet ween port s under any of
t he following condit ions:
1. The current t ransmit t ing port link is not available
2. The preferred primary port is enabled and becomes available for t ransmission.
10.2.2.2.2 Dr i ver I nt er act i ons
When t he LAN driver is present , t he decision t o swit ch bet ween t he t wo port s is done by t he driver.
When t he driver is absent , t his decision is done int ernally by t he 82599.
Not e: When t he driver releases t eaming mode ( such as, when t he syst em st at e changes) , t he
82599 reconfigures t he LAN port s t o t eaming mode. The 82599 accomplishes t his by re-
set t ing t he Et hernet MAC address of t he t wo port s t o be t he t eaming address in order t o re-
st art t eaming. This is followed by t ransmission of grat uit ous ARP packet s t o not ify t he
net work of t eaming mode reset t ing.
10.2.2.2.3 Fai l - Over Conf i gur at i on
Fail- over operat ion is configured t hrough t he failover configurat ion st ruct ure ( see Sect ion 10. 2.2.2.4) .
The BMC should configure t his regist er aft er a t he 82599 init ializat ion indicat ion ( following a firmware
reset ) . The different configurat ions available t o t he BMC are det ailed in t his sect ion.
Not e: I n t eaming mode bot h port s should be configured wit h t he same receive manageabilit y filt ers
paramet ers ( EEPROM sect ions for port 0 and port 1 should be ident ical) .
Pr ef er r ed Pr i mar y Por t The BMC might choose one of t he net work port s ( LAN0 or LAN1) as a
preferred primary port for packet t ransmission. The 82599 always swit ches t o t he preferred primary
port when it is available.
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Gr at ui t ous ARPs I n order t o not ify t he link part ner t hat a port swit ching has occurred, t he 82599
can be configured t o aut omat ically send grat uit ous ARPs. These grat uit ous ARPs cause t he link part ner
t o updat e it s ARP t ables t o reflect t he change. The BMC might enable/ disable grat uit ous ARPs, configure
t he number of grat uit ous ARPs or t he int erval bet ween t hem by modifying t he Fail Over configurat ion
regist er.
Li nk Dow n Ti meout The BMC can cont rol t he t imeout for a link t o be considered invalid. The 82599
wait s t his t imeout before at t empt ing t o swit ch from an inact ive port .
10.2.2.2.4 Fai l - Over St r uct ur e
The failover st ruct ure ( list ed in t he following t able) is loaded on power up from t he EEPROM ( see
Sect ion 6. 4. 4. 5) , or t hrough t he Set Fail- Over Configurat ion host command by t he LAN driver ( see
Sect ion 10.5. 3. 8) . The bit s in t his regist er can also be modified by t he 82599 hardware reflect ing it s
current st at e.
Bi t ( s) Fi el d
I ni t i al
Val ue
Read/
Wr i t e
Descr i pt i on
0 RMP0EN 0x1 RO
RCV MNG port 0 Enable. When t his bit is set , it report s t hat MNG t raffic is
received from port 0.
1 RMP1EN 0x1 RO
RCV MNG port 1 Enable. When t his bit is set , it report s t hat MNG t raffic is
received from port 1.
2 MXP 0x0 RO
MNG XMT Port .
0b = MNG t raffic should be t ransmit t ed t hrough port 0.
1b = MNG t raffic should be t ransmit t ed t hrough port 1.
3 PRPP 0x0 RW
Preferred Primary Port .
0b = Port 0 is t he preferred primary port .
1b = Port 1 is t he preferred primary port .
4 PRPPE 0x0 RW Preferred Primary Port enables.
5 Reserved 0x0 RO Reserved
6 RGAEN 0x0 RW
Repeat ed Grat uit ous ARP Enable. I f t his bit is set , t he 82599 sends a
configurable number of grat uit ous ARP packet s ( GAC bit s of t his regist er) using
configurable int erval ( GATI bit s of t his regist er) aft er t he following event s:
Syst em move t o Dx, or failover event init iat ed t he 82599.
9 TFOENODX 0x0 RW
Teaming Fail Over Enable on Dx. Enable failover mechanism. Bit s 3- 8 are valid
only if t his bit is set .
10- 11 Reserved 0x0 RO Reserved
12- 15 GAC 0x0 RW
Grat uit ous ARP count er. Count s t he number of grat uit ous ARP t hat should be
done aft er a failover event and aft er a move t o Dx. When it is set t o zero,
t here is no limit on t he grat uit ous ARP packet s.
16- 23 LDFOT 0x0 RW
Link Down Fail- Over Time. Defines t he t ime in seconds t he link should be down
before doing a fail over t o t he ot her port .
This is also t he t ime t hat t he primary link should be up ( aft er it was down)
before t he 82599 swit ches back t o t he primary port .
24- 31 GATI 0x0 RW
Grat uit ous ARP Transmission I nt erval. Defines t he GAP in seconds before
ret ransmission of grat uit ous ARP packet s.

657
10.2.2.3 ARP Handl i ng
I ndependent of t he management int erface, t he 82599 can be programmed by t he BMC t o provide ARP
services. The 82599 support s aut o-ARP replying for ARP request packet s and sending Grat uit ous ARP.
Aut o-ARP is done in bot h port s in eit her modes: dual- channel and one- channel. I n dual- channel mode,
each channel uses it s own I P and Et hernet MAC address ( eit her t he operat ing syst em Et hernet MAC
address or independent addresses) . I n one- channel mode, bot h port s use t he same I P and Et hernet
MAC address and t he ARP is responded t o t hrough t he port it was received.
The following ARP paramet ers are loaded from t he EEPROM on power up or configured t hrough t he
management int erface:
ARP aut o- reply enabled
ARP I P address ( t o filt er ARP packet s)
ARP Et hernet MAC Addresses ( for ARP response)
When an ARP request packet is received on t he wire and ARP aut o- reply is enabled, t he 82599 checks
t he t arget ed I P address ( aft er t he packet has passed L2 checks and ARP checks) . I f t he t arget ed I P
mat ches t he 82599 I P configurat ion, t hen it replies wit h an ARP response. The 82599 responds t o t he
ARP request t arget ed t o t he ARP I P address wit h it s ARP Et hernet MAC address. I n a case where t here
is no mat ch, t he 82599 silent ly discards t he packet s. I f t he 82599 is not configured t o do aut o-ARP
response, it forwards t he ARP packet s t o t he BMC. See Sect ion 18.1.1 for ARP request and ARP
response packet format s.
When t he ext ernal BMC uses t he same I P and MAC of t he operat ing syst em, t he ARP operat ion should
be coordinat ed wit h t he operat ing syst em operat ion. I n t his mode, t he ext ernal BMC has t he
responsibilit y and ARP aut o- reply should be disabled.
Not e: When configured in NC- SI mode, t he 82599 does not provide ARP services. All ARP handling
is done by t he BMC.
10. 3 Manageabi l i t y Recei v e Fi l t er i ng
10.3.1 Ov er v i ew and Gener al St r uct ur e
For complet eness, t his sect ion summarizes t he MAC and VLAN filt ers described in Sect ion 7. 1. 1. 1 and
Sect ion 7.1.1. 2. I n addit ion, t his sect ion describes t he manageabilit y receive packet filt ering flow. The
descript ion applies t o any of t he 82599 LAN port s. Receive packet filt ering can have one of t he following
rout ing result s:
Discard packet s ( packet s t hat do not pass t he host nor manageabilit y filt ering)
Send packet s t o host memory ( default hardware set t ing)
Send packet s t o t he ext ernal BMC ( t wo modes) :
Receive All All received packet s are rout ed t o t he BMC in t his mode. I t is enabled by set t ing
t he RCV_TCO_EN bit ( which enables packet s t o be rout ed t o t he BMC) and RCV_ALL bit ( which
rout es all packet s t o t he BMC) in t he MANC regist er.
Receive Filt ering I n t his mode only some of t he packet t ypes are direct ed t o t he
manageabilit y block. The BMC should set t he RCV_TCO_EN bit t oget her wit h t he required
packet t ypes bit s in t he manageabilit y filt ering regist ers. Not e t hat t he RCV_ALL bit must be
cleared) .
Send packet s t o bot h t he ext ernal BMC and host memory:
The BMC can enable t his mode by set t ing t he EN_MNG2HOST bit in t he MANC regist er and
enable specific packet t ypes in t he MANC2H regist er.
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The BMC cont rols it s packet filt ering by programming t he receive manageabilit y filt ers list ed in t he
following t able. These regist ers are not writ e- accessible by t he host ( prot ect ing t he BMC from
erroneous/ malicious host soft ware) .
Manageabilit y filt ering follows t hese st eps and are det ailed in t he following sect ions:
1. L2 Et hernet MAC address and VLAN filt ering
2. L3/ L4 manageabilit y filt ers Port , I P, flex filt ers ( packet s must also mat ch t he above L2 filt ering) .
Filt ering except ions:
Fragment ed packet s can be rout ed t o manageabilit y but not parsed beyond t he I P header.
Packet s wit h L2 errors ( CRC, alignment , et c.) are never forwarded t o manageabilit y.
Not e: Jumbo packet s above 2 KB are not expect ed t o be received by t he manageabilit y dat a pat h. I f
t he manageabilit y unit uses a dedicat ed Et hernet MAC address/ VLAN t ag, it should not use
furt her L3/ L4 filt ers on t op of it . Ot herwise, packet s t hat mat ch t he L2 filt ers but fail t he L3/
L4 filt ers are rout ed t o t he host .
Fi l t er s Funct i onal i t y When Reset ?
Filt ers enable General configurat ion of t he manageabilit y filt ers. I nt ernal Power On Reset
Manageabilit y t o host Enables rout ing of manageabilit y packet s t o host . I nt ernal Power On Reset
Manageabilit y decision filt ers
[ 7: 0]
Configurat ion of manageabilit y decision filt ers. I nt ernal Power On Reset
MAC address [ 3: 0] Four unicast MAC manageabilit y addresses. I nt ernal Power On Reset
VLAN filt ers [ 7: 0] Eight VLAN t ag values. I nt ernal Power On Reset
UDP/ TCP port filt ers [ 15: 0] 16 dest inat ion port values. I nt ernal Power On Reset
Flexible 128- byt e TCO filt ers Lengt h values for four flex TCO filt ers. I nt ernal Power On Reset
I Pv4 and I Pv6 address
filt ers[ 3: 0]
I P address for manageabilit y filt ering. I nt ernal Power On Reset
L2 Et herType filt ers [ 3: 0] Four L2 Et herType values. I nt ernal Power On Reset

659
The complet e filt ering flow is described in t he following flow diagram:
Not e: L2 MAC address and VLAN filt ering are described in Sect ion 7. 1. 1.1 and Sect ion 7.1.1. 2.
10.3.2 L2 Et her Ty pe Fi l t er s
Packet s are compared against t he Et herType filt ers programmed in t he METF. EType ( up t o 4 filt ers) and
t he result is incorporat ed t o t he decision filt ers.
Each of t he manageabilit y Et herType filt ers can be configured as pass ( posit ive) or rej ect ( negat ive)
polarit y. When negat ive polarit y filt ers are used, all negat ive filt ers should be included in all enabled
decision filt ers.
Examples for usages of t he L2 Et herType filt ers are:
Block rout ing of packet s wit h t he NC- SI Et herType from being rout ed t o t he BMC. The NC- SI
Et herType is used for communicat ions bet ween t he BMC on t he NC- SI link and t he 82599. Packet s
coming from t he net work are not expect ed t o carry t his Et herType and such packet s are blocked t o
prevent at t acks on t he BMC.
Det ermine t he dest inat ion of 802.1X cont rol packet s. The 802.1X prot ocol is execut ed at different
t imes in eit her t he BMC or by t he host . The L2 Et herType filt ers are used t o rout e t hese packet s t o
t he proper agent .
RCV_TCO_EN
No
RCV_ALL
FIXED_NET_TYPE
& NET_TYPE
EN_XSUM_FILTER
Packet Pass L2 (MAC and
VLAN) Filtering (see note)
Yes
No
Yes
Unmatched Tag/Untaged VLAN packet
Matched Tag/Untaged VLAN packet
Yes
No
Send Packet to
Manageability
Manageability
Decision Filters
Pass
Fail
L3 & L4 XSUM
Pass
Fail
Candidate packet
for the Host
MANC
flags
MANC2H check or
MTQF + MTQS filters
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10.3. 3 VLAN Fi l t er s - Si ngl e and Doubl e VLAN Cases
The 82599 support s eight VLAN filt ers per port defined by t he MAVTV[ n] and cont rolled by t he MANC
regist er as described in t he t ext t hat follows.
When MANC.NET_TYPE = 1b and MANC.FI XED_NET_TYPE = 1b ( pass only VLAN t agged packet s)
A packet wit hout any VLAN or a single VLAN header is not rout ed t o manageabilit y
A packet wit h 2 VLANs is a candidat e for manageabilit y
When MANC.NET_TYPE = 0b and MANC.FI XED_NET_TYPE = 1b ( pass only un- t agged packet s)
A packet wit hout any VLAN or a single VLAN header is a candidat e for manageabilit y
A packet wit h 2 VLANs is not rout ed t o manageabilit y
When MANC.FI XED_NET_TYPE = 0b ( bot h t agged and unt agged packet s are candidat es for
manageabilit y)
A packet wit h no VLAN header skips successfully t o t he next filt ering level
A packet wit h a single VLAN or 2 VLANs are filt ered by it s VLAN header as described in
Sect ion 7. 1. 1. 2
10.3. 4 L3 and L4 Fi l t er s
ARP Fi l t er i ng: The 82599 support s filt ering of bot h ARP request packet s ( init iat ed ext ernally) and ARP
responses ( t o request s init iat ed by t he BMC or t he 82599) .
Nei ghbor Di scover y Fi l t er i ng: The 82599 support s filt ering of neighbor discovery packet s. Neighbor
discovery filt ers use t he I PV6 dest inat ion address filt ers defined in t he MI PAF regist ers ( such as mat ch
t o any of t he enabled I Pv6 addresses) .
Por t 0x 298/ 0x 26F Fi l t er i ng: The 82599 support s filt ering by fixed dest inat ion port s numbers: 0x26F
and 0x298.
Fl ex Por t Fi l t er i ng: The 82599 implement s 16 flex dest inat ion port filt ers. The 82599 direct s packet s
whose L4 dest inat ion port mat ches t he value of t he respect ive word in t he MFUTP regist ers. The BMC
must ensure t hat only valid ent ries are enabled in t he decision filt ers t hat follow.
Fl ex TCO Fi l t er s: See Sect ion 10. 3. 4. 1.
I P Addr ess Fi l t er i ng: The 82599 support s filt ering by I P address t hrough dedicat ed I Pv4 and I Pv6
address filt ers t o manageabilit y. Two modes are possible, depending on t he value of t he
MANC. EN_I Pv4_FI LTER bit :
EN_I Pv4_FI LTER = 0b: The 82599 provides four I Pv6 address filt ers.
EN_I Pv4_FI LTER = 1b: The 82599 provides t hree I Pv6 address filt ers and four I Pv4 address filt ers.
The MFVAL regist er indicat es which of t he I P address filt ers are valid ( cont ains a valid ent ry and
should be used for comparison) .
Check sum Fi l t er : I f bit MANC.EN_XSUM_FI LTER is set , t he 82599 direct s packet s t o t he BMC only if
t hey mat ch all ot her filt ers previously described as well as pass L3/ L4 checksum ( if it exist s) .

661
10. 3. 4. 1 Fl ex i bl e 128 By t es Fi l t er ( TCO Fi l t er s)
10.3.4.1.1 Over vi ew
The flexible 128 filt ers are a set of filt ers designed t o enable dynamic filt ering of received packet s.
These filt ers are part of t he manageabilit y receive filt ers. The filt ers do not make a decision on t he
packet s dest inat ion. They part icipat e in t he decision mechanism for each received packet
( Sect ion 10. 3.5) .
Each filt er enables a flexible t est ing of t he first 128 byt es of t he packet against a given value. The filt er
also enables t est ing of specific byt es by defining a byt e- wise mask on t he filt er.
The 82599 provides four flex TCO filt ers. Each filt er looks for a pat t ern mat ch wit hin t he 1st 128 byt es
of t he packet . The BMC must ensure t hat only valid ent ries are enabled in t he decision filt ers.
Not e: The flex filt ers are t emporarily disabled when read or writ t en by t he host . Any packet received
during a read or writ e operat ion is dropped. Filt er operat ion resumes once t he read or writ e
access complet es.
10.3.4.1.2 St r uct ur e
Each filt er is composed of t he following fields:
1. Flexible Filt er Lengt h: This field indicat es t he number of byt es in t he packet header t hat should be
inspect ed. This field also indicat es t he minimal lengt h of packet s in order t o be inspect ed by t he
filt er. A packet below t hat lengt h is not inspect ed by t he filt er. Valid values for t his field are: 8* n,
where n= 18.
2. Dat a: This is a set of up t o 128 byt es comprising t he values t hat t he header byt es of each packet
are t est ed against .
3. Mask: This is a set of 128 bit s corresponding t o t he 128 dat a byt es t hat indicat e for each
corresponding byt e if is t est ed against it s corresponding byt e.
Overall, each filt er t est s t he first 128 byt es ( or less) of a packet , where not necessarily all byt es must
be t est ed.
10.3.4.1.3 Pr ogr ammi ng
Programming each filt er is done using t he following t wo commands ( NC- SI or SMBus) in a sequent ial
manner:
1. Filt er Mask and Lengt h. This command configures t he following fields.
a. Mask: A set of 16 byt es cont aining t he 128 bit s of t he mask. Bit 0 of t he first byt e corresponds
t o t he first byt e on t he wire.
b. Lengt h: A 1- byt e field indicat ing t he lengt h.
2. Filt er Dat a.
The filt er dat a is divided int o groups of byt es. as follows:
Gr oup Test By t es
0x0 0- 29
0x1 30- 59
0x2 60- 89
0x3 90- 119
0x4 120- 127
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Each group of byt es needs t o be configured using a separat e command, where t he group number is
given as a paramet er.
The command has t he following paramet ers:
a. Group number. A 1- byt e field indicat ing t he current group addressed.
b. Dat a byt es. Up t o 30 byt es of t est - byt es for t he current group.
10.3. 5 Manageabi l i t y Deci si on Fi l t er s
The manageabilit y decision filt ers are a set of eight filt ers wit h t he same st ruct ure ( MDEF[ 7: 0] and
MDEF_EXT[ 7: 0] ) . The filt ering rule for each decision filt er is programmed by t he BMC and defines which
of t he L2, VLAN, and manageabilit y filt ers part icipat e in t he decision ( host soft ware cant modify t heir
set t ing) . A packet t hat passes at least one set of decision filt ers is direct ed t o manageabilit y and
possibly t o t he host as well. The input s t o each decision filt er are:
Packet passed a valid management L2 unicast address filt er.
Packet is a broadcast packet .
Packet has a VLAN header and it passed a valid manageabilit y VLAN filt er.
Packet mat ched one of t he valid I Pv4 or I Pv6 manageabilit y address filt ers.
Packet is a mult icast packet .
Packet passed ARP filt ering ( request or response) .
Packet passed neighbor discovery filt ering.
Packet passed 0x298/ 0x26F port filt er.
Packet passed a valid flex port filt er.
Packet passed a valid flex TCO filt er.
Packet passed or failed an L2 Et herType filt er.
The st ruct ure of each of t he decision filt ers is shown in Figure 10. 2 . A boxed x.y number indicat es
t hat t he input is condit ioned on a mask bit y defined in regist er index x, while x= 0 denot es MDEF
and x= 1 denot es MDEF_EXT. The decision filt er rules are as follows:
Any bit set in t he MDEF and MDEF_EXT regist ers enables it s corresponding filt er. Any filt er t hat is
not enabled in t he MDEF and MDEF_EXT regist ers is ignored. I f all bit s in t he MDEF and MDEF_EXT
regist ers of a specific decision filt er are cleared, it is disabled and ignored.
All enabled AND filt ers must pass for t he decision filt er t o mat ch.
I f at least one OR filt er is enabled, t hen at least one of t he enabled OR filt ers must pass for t he
decision filt er t o mat ch.

663
Fi gur e 10.2. Manageabi l i t y Deci si on Fi l t er s
10.3.6 Possi bl e Conf i gur at i ons
This sect ion describes possible ways of using t he management filt ers. Act ual usage might vary.
Dedi cat ed MAC pack et f i l t er i ng
Select one of t he eight rules for broadcast filt ering
Set bit 0 of t he decision rule t o enforce Et hernet MAC address filt ering
Set ot her bit s t o qualify which packet s are allowed t o pass t hrough. For example:
Set bit 2 t o qualify wit h manageabilit y VLAN
Set bit 3 t o qualify wit h a mat ch t o an I P address
Set any L3/ L4 bit s ( 30: 7) t o qualify wit h any of a set of L3/ L4 filt ers
Manageability L2 unicast
address
0.0
0.1 Broadcast
0.2 VLAN
0.3 IP address
Manageability L2 unicast
address
0.4
0.5 Broadcast
0.6 Multicast
0.7 ARP Request
0.10 Port 0x298
0.11 Port 0x26F
0.12 Flex Port 0
0.27 Flex Port 15
0.28 Flex TCO 0
0.31 Flex TCO 3
0.9 Neighbor Discovery
0.8 ARP Response
1.0 L2 EtherType
1.3 L2 EtherType
1.4
1.7
L2 EtherType
L2 EtherType
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Br oadcast pack et f i l t er i ng
Select one of t he eight rules for broadcast filt ering
Set bit 1 of t he decision rule t o enforce broadcast filt ering
Set ot her bit s t o qualify which broadcast packet s are allowed t o pass t hrough. For example:
Set bit 2 t o qualify wit h manageabilit y VLAN
Set bit 3 t o qualify wit h a mat ch t o an I P address
VLAN pack et f i l t er i ng
Select one of t he eight rules for VLAN filt ering
Set bit 2 of t he decision rule t o enforce VLAN filt ering
Set ot her bit s t o qualify which VLAN packet s are allowed t o pass t hrough. For example:
I Pv6 filt ering is done via t he following I Pv6- specific filt ers:
I P unicast filt ering requires filt ering for link local address and a global address. Filt ering set up
might depend on whet her an Et hernet MAC address is shared wit h t he host or dedicat ed t o
manageabilit y:
Dedicat ed Et hernet MAC address ( such as dynamic address allocat ion wit h DHCP does not
support mult iple I P addresses for one Et hernet MAC address) . I n t his case, filt ering can be done
at L2 using t wo dedicat ed unicast MAC filt ers.
Shared Et hernet MAC address ( such as st at ic address allocat ion sharing addresses wit h t he
host ) . I n t his case, filt ering needs t o be done at L3, requiring t wo I Pv6 address filt ers, one per
address.
A Neighbor discovery filt er The 82599 support s I Pv6 neighbor discovery prot ocol. Since t he
prot ocol relies on mult icast packet s, t he 82599 support s filt ering of t hese packet s. I Pv6 mult icast
addresses are t ranslat ed int o corresponding Et hernet mult icast addresses in t he form of 33- 33-xx-
xx-xx-xx, where t he last 32 bit s of t he address are t aken from t he last 32 bit s of t he I Pv6 mult icast
address. Therefore, t wo direct MAC filt ers can be used t o filt er I Pv6 solicit ed- node mult icast packet s
as well as I Pv6 all node mult icast packet s.
Recei v e f i l t er i ng w i t h shar ed I P CPMP
When t he BMC shares t he MAC and I P address wit h t he host , receive filt ering is based mainly on
ident ifying specific flows t hrough port allocat ion. The following set t ing can be used:
Select one of t he eight rules:
Set a manageabilit y dedicat ed MAC filt er t o t he host Et hernet MAC address and set bit 0 in t he
MNG_ FI LTER_RULE regist er.
I f VLAN is used for management , load one of more management VLAN filt ers and set bit 2 in t he
MNG_ FI LTER_RULE regist er
ARP filt er / neighbor discovery filt er is enabled when t he BMC is responsible t o handle t he ARP
prot ocol. Set bit 7 or bit 8 in t he MNG_ FI LTER_RULE regist er for t his funct ionalit y.
Program flex port filt ers wit h t he port values for management flows such as DHCP, HTTP, HTTPS,
SMWG, SoL/ I DER/ KVM, WS- MAN, Telnet , USB redirect ion, SSH, DNS, and more. Set t he respect ive
bit s 26: 11 in t he MNG_ FI LTER_RULE regist er.
An I P address filt er can be loaded as well by set t ing bit 3 in t he MNG_ FI LTER_RULE regist er.
Management flex filt ers are programmed t o correspond t o remaining flows such as DNS updat e
response packet s. Set appropriat e bit s 30: 27 in t he MNG_ FI LTER_RULE regist er.

665
10. 4 Li nk Sec and Manageabi l i t y
For det ails on LinkSec and t he role of manageabilit y in it , see Sect ion 7. 8.
Pass- t hrough mode is support ed in a LinkSec environment in one of t he following modes of operat ions:
Management t raffic not prot ect ed by LinkSec The management t raffic from and t o t he BMC is
carried over a separat e Et hernet MAC address and/ or a separat e VLAN and t he net work swit ch is
configured t o enable such t raffic t o pass unprot ect ed.
Management t raffic is prot ect ed by LinkSec The 82599 support s a single secure channel for bot h
host and BMC. At a given t ime, t he host and BMC can be act ive or inact ive. When only BMC is
act ive, it act s as t he KaY cont rolling t he secured channel. The host can act as t he KaY when it is
funct ional and aft er it acquires cont rol over LinkSec. I n t his case, t he BMC uses t he secured channel
set by t he host . Even when operat ing in t his mode, t he BMC can t ransmit packet s on t he clear ( as
required for 802.1x cont rol packet s) . The BMC must disable MACsec operat ion before sending such
packet s and re- enable MACsec operat ion aft erwards. The messages t hat cont rol MACsec operat ion
are described in Sect ion 10.5.1.16.
The 82599 provides t he following funct ionalit y t hat enables management t raffic over t he same secure
channel wit h t he host :
Handover of LinkSec ownership bet ween t he BMC and t he host . Several t ransit ions in ownership are
possible:
Power- on The 82599 powers up wit h LinkSec not being owned by t he BMC. I f t he BMC is
configured for LinkSec, it t akes ownership over LinkSec as follows. I f t he BMC is not configured
for LinkSec, t he host t akes ownership when it boot s. I f LinkSec is not owned by t he BMC, t he
host is not required for any handshake wit h t he BMC as t here are cases where t he BMC is not
connect ed t o t he 82599. I f t here is a race bet ween t he BMC and t he host , t he BMC wins over
LinkSec, and t he host is t hen int errupt ed so t hat t he LinkSec resources are not accessible.
Handover of LinkSec responsibilit y from BMC t o host The host can init iat e a t ransfer of
ownership from t he BMC ( such as on operat ing syst em boot ) .
Handover of LinkSec responsibilit y from host t o BMC The host can init iat e a t ransfer of
ownership t o t he BMC ( such as on ent ry t o low power st at e) . This is done t hrough t he host
slave command int erface.
Forced handover of LinkSec responsibilit y from host t o BMC The BMC can acquire ownership
of LinkSec on it s own, for example when t he host fails t o acquire a secure channel. See
Sect ion 10. 4.1 for t he different t ransit ion sequences.
Configurat ion of LinkSec resources by t he BMC When t he BMC owns t he secure channel, it
configures LinkSec operat ion t hrough t he SMBus or NC- SI vendor- specific commands ( see
Sect ion 10. 5.1.16) .
Alert s The 82599 init iat es an SMBus or NC- SI alert t o t he BMC on several LinkSec event s as
follows ( see alert s message format in Sect ion 10.5. 1. 17, Sect ion 10. 5. 2. 2.3, and
Sect ion 10. 5.2.2. 8) .
Packet arrived wit h a LinkSec error ( no SA mat ch, replay det ect ion, or a bad LinkSec
signat ure) .
Key- exchange event relevant on Tx when t he packet number count er reaches t he exhaust ion
t hreshold as described in Sect ion 7. 8. 5. 1.
Host request for LinkSec ownership.
Host request t o relinquish LinkSec ownership.
I nt el

666
I nt errupt causes The 82599 issues a management int errupt t o t he host on t he following LinkSec
event s:
Acknowledge of handover of LinkSec responsibilit y from BMC t o host .
Forced handover of LinkSec responsibilit y from host t o BMC.
The host might ident ify t he ownership st at us by reading t he Operat ing Syst em St at us field in t he
LSWFW regist er.
10.4. 1 Handov er of Li nk Sec Responsi bi l i t y Bet w een BMC and Host
10. 4. 1. 1 KaY Ow ner shi p Rel ease by t he Host
The following procedure is used by t he host in order t o release ownership of t he LinkSec capabilit y. This
procedure is usually done before an ordered shut down of t he host .
The host should st op accessing t he LinkSec regist ers and set t he Release LinkSec bit in t he LSWFW
regist er.
Set t ing t he Release LinkSec bit causes an int errupt t o t he firmware t hat is forwarded t o t he BMC.
The BMC t hen t akes ownership as described in Sect ion 10. 4. 1.2.
The host can t hen wait for an int errupt from t he firmware indicat ing t hat t he BMC t ook t he KaY
ownership.
10. 4. 1. 2 KaY Ow ner shi p Tak eov er by BMC
As previously ment ioned, t he BMC can acquire ownership over LinkSec eit her by ownership relinquish
by t he host or wit hout any negot iat ion ( such as on power- up and on a forced t ransit ion when t he host
failed t o bring up a LinkSec connect ion) . The BMC acquires ownership of LinkSec by t aking t he following
act ions:
Locking access t o LinkSec resources t o t he host by set t ing t he Lock LinkSec Logic bit in t he LSWFW
regist er.
Blocking host packet s t ransmission from t he wire by set t ing t he Block Host Traffic bit in t he LSWFW
regist er.
Set t he OS St at us field in t he LSWFW regist er t o 1b indicat ing a BMC t akeover of t he LinkSec logic.
I ssue a manageabilit y event int errupt t o t he host .
10. 4. 1. 3 KaY Ow ner shi p Request by t he Host
The following procedure is used by t he host in order t o request ownership of t he LinkSec capabilit y:
The host should read t he LSWFW.OS st at us field t o check if t he KaY is current ly owned by t he BMC.
if KaY is owned by t he BMC, t hen t he host should set t he Request LinkSec bit in t he LSWFW regist er
prior t o assuming responsibilit y over LinkSec connect ion.
Set t ing t he Request LinkSec bit causes an int errupt t o t he firmware t hat is forwarded t o t he BMC.
The host should t hen wait for an int errupt from t he firmware indicat ing t hat t he BMC released t he
KaY ownership.
Following t he manageabilit y int errupt , t he host should check t he OS St at us and Lock LinkSec Logic
fields in t he LSWFW regist er t o make sure t he BMC released t he KaY ownership.

667
10. 4. 1. 4 KaY Ow ner shi p Rel ease by BMC
I n order t o release ownership of LinkSec, t he BMC should t ake t he following act ions:
Disconnect t he LinkSec connect ion wit h t he swit ch ( such as EAP logoff ) .
Clear t he Lock LinkSec Logic bit in t he LSWFS regist er enabling t he host set t ing of t he LinkSec
regist ers.
Clear t he OS St at us bit t o 0b in t he LSWFS regist er indicat e a LinkSec release.
I ssue a manageabilit y event int errupt t o t he host .
Poll t he connect ion st at e t o check if t he LinkSec channel was set by t he host .
I f t he BMC decides t o deny t he release request , it silent ly ignores t he request .
10. 4. 1. 5 Cont r ol Regi st er s
The complet e set of manageabilit y regist ers are described in Sect ion 8.2.3. 26 and Sect ion 8.2. 3. 26.
The following configurat ion fields are dedicat ed for manageabilit y cont rol over LinkSec:
LSWFW Fi el d LSWFW Fi el d Funct i onal i t y
Block Host Traffic Enables or disables host t ransmit t raffic for t his PCI funct ion from going t o t he wire. Default is t o enable.
OS St at us
Set by firmware t o indicat e t he st at us of t he LinkSec ownership:
0b = LinkSec owned by host ( default ) .
1b = LinkSec owned by BMC.
LinkSec Request Bit used by host t o request KaY ownership.
LinkSec Release Bit used by host t o release KaY ownership.
Lock LinkSec Logic
Serves t wo purposes. I t indicat es who owns LinkSec ( default value is host ownership) . Second, it enables
or disables host accesses t o t he LinkSec regist ers. Default is t o enable. The following regist ers are
blocked:
LSECTXCAP; LSECRXCAP; LSECTXCTRL; LSECRXCTRL; LSECTXSCL; LSECTXSCH; LSECTXSA;
LSECTXPN0; LSECTXPN1; LSECTXKEY0 ( 4 regist ers) ; LSECTXKEY1 ( 4 regist ers) ; LSECRXSCL;
LSECRXSCH; LSECRXSA ( 0 and 1) ; LSECRXSAPN ( 0 and 1) ; LSECRXKEY ( 4 regist ers / SA) ; LSECTXUT;
LSECTXPKTE; LSECTXPKTP; LSECTXOCTE; LSECTXOCTP; LSECRXUTnS; LSECRXUTyS; LSECRXOCTE;
LSECRXOCTP; LSECRXBAD; LSECRXNOSCI nS; LSECRXNOSCI yS; LSECRXNOSCI ; LSECRXDELAY;
LSECRXLATE; LSECRXOK; LSECRXI NVCK; LSECRXI NVST; LSECRXNSAST; LSECRXNSA
I nt el

668
10. 5 Manageabi l i t y Pr ogr ammi ng I nt er f aces
10.5. 1 NC- SI Pr ogr ammi ng
The 82599 support s t he mandat ory NC- SI commands as list ed in Table 10. 1. On t op of t hese
commands, t he 82599 also support s I nt el vendor specific commands. The vendor specific commands
are based on t he NC- SI OEM Command. These commands are list ed in t he following subsect ions
and are used t o enable t he BMC t o cont rol t he 82599 specific feat ures:
Rx filt ers:
Packet addit ion decision filt ers 0x00x4
Packet reduct ion decision filt ers 0x50x7
MNG2HOST regist er ( cont rols t he forwarding of manageabilit y packet s t o t he host )
Flex 128 filt ers 0x00x3
Flex TCP/ UDP port filt ers 0..0xA
I Pv4/ I Pv6 filt ers
Et her t ype filt ers
Get Syst em Et hernet MAC Address This command enables t he BMC t o ret rieve t he syst em
Et hernet MAC address used by t he NC. This Et hernet MAC address can be used for shared Et hernet
MAC address mode.
Keep PHY Link Up ( Vet o bit ) Enable/ Disable This feat ure enables t he BMC t o block PHY reset ,
which might cause session loss.
TCO Reset Enables t he MC t o reset t he net work adapt er.
Checksum Offloading Offloads I P/ UDP/ TCP checksum checking from t he MC.
LinkSec logic programming
These commands are designed t o be compliant wit h t heir corresponding SMBus commands ( if exist ing) .
All of t he commands are based on a single DMTF defined NC- SI command, known as OEM Command
described in Sect ion 10.5. 1. 1.
10.5.1.1 OEM Command ( 0x 50)
The OEM command can be used by t he MC t o request t he sideband int erface t o provide vendor- specific
informat ion. The Vendor Ent erprise Number ( VEN) is t he unique MI B/ SNMP privat e ent erprise number
assigned by I ANA per organizat ion. Vendors are free t o define t heir own int ernal dat a st ruct ures in t he
vendor dat a fields.
10.5.1.2 OEM Response ( 0x D0)
The sideband int erface must ret urn an Unknown Command Type reason code for any unrecognized
ent erprise number using t he following frame format . I f t he command is valid, t he response, if any, is
allowed t o be vendor- specific. I t is recommended t o use t he 0x8000 range for vendor- specific code.
Bits
Bytes 31..24 23..16 15..08 07..00
00..15 NC-SI Header
16..19 Manufacturer ID (Intel 0x157)
20.. Intel Command Number Optional Data

669
Bits
Bytes 31..24 23..16 15..08 07..00
00..15 NC-SI Header
16..19 Response Code Reason Code
20..23 Manufacturer ID (Intel 0x157)
24..27 Intel Command Number Optional Return Data
Tabl e 10.3. OEM Speci f i c Command Response and Reason Codes
Response Code Reason Code
Val ue Descr i pt i on Val ue Descr i pt i on
0x1 Command Failed
0x5081 I nvalid I nt el Command Number
0x5082 I nvalid I nt el Command Paramet er Number
I nt el

670
10. 5. 1. 3 I nt el Commands
Table 10. 4 list s t he I nt el commands and t heir associat ed I nt el Command Number values. For det ailed
descript ion of t he commands and t heir paramet ers refer t o t he following sect ions.
Tabl e 10.4. I nt el Command Summar y
I nt el Command Par amet er Command Name
0x00 0x00 Set I P Filt ers Cont rol
0x01 0x00 Get I P Filt ers Cont rol
0x02
0x0A Set Manageabilit y t o Host
0x10 Set Flexible 128 Filt er 0 Mask and Lengt h
0x11 Set Flexible 128 Filt er 0 Dat a
0x61 Set Packet Addit ion Filt ers
0x63 Set Flex TCP/ UDP Port Filt ers
0x64 Set Flex I Pv4 Address Filt ers
0x65 Set Flex I Pv6 Address Filt ers
0x67 Set Et herType Filt er
0x68 Set Packet Addit ion Ext ended Decision Filt er
0x3
0x0A Get Manageabilit y t o Host
0x10 Get Flexible 128 Filt er 0 Mask and Lengt h
0x11 Get Flexible 128 Filt er 0 Dat a
0x61 Get Packet Addit ion Filt ers
0x63 Get Flex TCP/ UDP Port Filt ers
0x64 Get Flex I Pv4 Address Filt ers
0x65 Get Flex I Pv6 Address Filt ers
0x67 Get Et herType Filt er
0x68 Get Packet Addit ion Ext ended Decision Filt er

671
I nt el Command Par amet er Command Name
0x04
0x00 Set Unicast Packet Reduct ion
0x01 Set Mult icast Packet Reduct ion
0x02 Set Broadcast Packet Reduct ion
0x10 Set Unicast Ext ended Packet Reduct ion
0x11 Set Mult icast Ext ended Packet Reduct ion
0x12 Set Broadcast Ext ended Packet Reduct ion
0x05
0x00 Get Unicast Packet Reduct ion
0x01 Get Mult icast Packet Reduct ion
0x02 Get Broadcast Packet Reduct ion
0x10 Get Unicast Ext ended Packet Reduct ion
0x11 Get Mult icast Ext ended Packet Reduct ion
0x12 Get Broadcast Ext ended Packet Reduct ion
0x06 N/ A Get Syst em Et hernet MAC Address
0x20 N/ A Set I nt el Management Cont rol
0x21 N/ A Get I nt el Management Cont rol
0x22 N/ A Perform TCO Reset
0x23 N/ A Enable I P/ UDP/ TCP Checksum Offloading
0x24 N/ A Disable I P/ UDP/ TCP Checksum Offloading
0x30
0x10 Transfer LinkSec Ownership t o BMC
0x11 Transfer LinkSec Ownership t o Host
0x12 I nit ialize LinkSec Rx
0x13 I nit ialize LinkSec Tx
0x14 Set LinkSec Rx Key
0x15 Set LinkSec Tx Key
0x16 Enable Net work Tx Encrypt ion
0x17 Disable Net work Tx Encrypt ion
0x18 Enable Net work Rx Decrypt ion
0x19 Disable Net work Rx Decrypt ion
0x31
0x01 Get LinkSec Rx Paramet ers
0x02 Get LinkSec Tx Paramet ers
0xF0 N/ A Writ e Configurat ion
0xF1 N/ A Read Configurat ion
Tabl e 10.4. I nt el Command Summar y ( Cont i nued)
I nt el

672
10. 5. 1. 4 Set I nt el Fi l t er s Cont r ol Command ( I nt el Command 0x 00)
10.5.1.4.1 Set I nt el Fi l t er s Cont r ol I P Fi l t er s Cont r ol Command ( I nt el Command 0x 00)
While I P Filt ers Cont rol has t he following format :
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
00. . 15 NC- SI Header
16. . 19 Manufact urer I D ( I nt el 0x157)
20. . 23 0x00 0x00 I P Filt ers cont rol ( 3- 2)
24. . 27 I P Filt ers Cont rol ( 1- 0)
Tabl e 10.5. I P Fi l t er For mat s
Bi t # Name Descr i pt i on
Def aul t
Val ue
0 I Pv4/ I Pv6 Mode
I Pv6 ( 0b) : There are 0 I Pv4 filt ers and 4 I Pv6 filt ers
I Pv4 ( 1b) : There are 4 I Pv4 filt ers and 3 I Pv6 filt ers
See Sect ion 8. 2. 3. 25. 2 or Sect ion 10. 3. 4 for det ails.
1b
1. . 15 Reserved
16 I Pv4 Filt er 0 Valid
I ndicat es if t he I Pv4 address configured in I Pv4 address 0 is valid.
Not e: The net work cont roller must aut omat ically set t his bit t o 1b if t he Set
I nt el Filt er I Pv4 Filt er Command is used for filt er 0.
0b
0b
0b
0b
20. . 23 Reserved
0b
0b
0b
0b
28. . 31 Reserved Reserved

673
10.5.1.4.2 Set I nt el Fi l t er s Cont r ol I P Fi l t er s Cont r ol Response ( I nt el Command 0x 00,
Fi l t er Cont r ol I ndex 0x 00)
10. 5. 1. 5 Get I nt el Fi l t er s Cont r ol Command ( I nt el Command 0x 01)
10.5.1.5.1 Get I nt el Fi l t er s Cont r ol I P Fi l t er s Cont r ol Command ( I nt el Command 0x 01,
This command cont rols different aspect s of t he I nt el filt ers.
10.5.1.5.2 Get I nt el Fi l t er s Cont r ol I P Fi l t er s Cont r ol Response ( I nt el Command 0x 01,
I P Filt er Cont rol: See Table 10.5.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
16. . 19 Response Code Reason Code
24. . 27 0x00 0x00
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x01 0x00
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x01 0x00 I P Filt ers Cont rol ( 3- 2)
28. . 29 I P Filt ers Cont rol ( 1- 0)
I nt el

674
10. 5. 1. 6 Set I nt el Fi l t er s For mat s
10.5.1.6.1 Set I nt el Fi l t er s Command ( I nt el Command 0x 02)
10.5.1.6.2 Set I nt el Fi l t er s Response ( I nt el Command 0x 02)
10.5.1.6.3 Set I nt el Fi l t er s Manageabi l i t y t o Host Command ( I nt el Command 0x 02, Fi l t er
Par amet er 0x 0A)
This command set s t he Mng2Host regist er. The Mng2Host regist er cont rols whet her pass- t hrough
packet s dest ined t o t he BMC are also forwarded t o t he host operat ing syst em.
The Mng2Host regist er has t he following st ruct ure:
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x02 Filt er Paramet er Filt ers Dat a ( opt ional)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 0x02 Filt er Paramet er Ret urn Dat a ( Opt ional)
Bi t s
By t es 31. . 24 23. . 16 15..08 07. .00
20. . 23 0x02 0x0A Manageabilit y t o Host ( 3- 2)
24. . 25 Manageabilit y t o Host ( 1- 0)
Tabl e 10- 6. Manageabi l i t y t o Host Fi el d
Bi t s Name Descr i pt i on Def aul t
0 Decision Filt er 0
Det ermines if packet s t hat have passed Decision Filt er 0 are also
forwarded t o t he host operat ing syst em.
0b
0b

675
10.5.1.6.4 Set I nt el Fi l t er s Manageabi l i t y t o Host Response ( I nt el Command 0x 02, Fi l t er
Par amet er 0x 0A)
10.5.1.6.5 Set I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3 Enabl e Mask and Lengt h Command ( I nt el
Command 0x 02, Fi l t er Par amet er 0x 10/ 0x 20/ 0x 30/ 0x 40)
The following command set s t he I nt el flex filt ers mask and lengt h. Use filt er paramet ers 0x10/ 0x20/
0x30/ 0x40 for flexible filt ers 0/ 1/ 2/ 3 accordingly. See Sect ion 10. 3. 4.1 for det ails of t he programming.
0b
0b
0b
5 Unicast & Mixed
Det ermines if unicast and mixed packet s are also forwarded t o t he
host operat ing syst em.
0b
6 Global Mult icast
Det ermines if global mult icast packet s are also forwarded t o t he host
operat ing syst em.
1b
7 Broadcast
Det ermines if broadcast packet s are also forwarded t o t he host
operat ing syst em.
1b
31: 8 Reserved Reserved N/ A
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 0x02 0x0A
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20..23 0x02
0x10/
0x20/
0x30/
0x40
Mask Byt e 1 Mask Byt e 2
24. . 27 . . . . . . . .
28. . . 31 . . . . . . . .
32. . . 35 . . . . . . . .
35. . . 37 . . Mask Byt e 16 Reserved Reserved
38
Flexible Filt er Lengt h
( 8- 128 byt es)
Tabl e 10- 6. Manageabi l i t y t o Host Fi el d
I nt el

676
10.5.1.6.6 Set I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3 Dat a Command ( I nt el Command 0x 02,
Fi l t er Par amet er 0x 11/ 0x 21/ 0x 31/ 0x 41)
10.5.1.6.7 Set I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3 Dat a Command ( I nt el Command 0x 02,
The following command set s t he I nt el flex filt ers dat a. Use filt er paramet ers 0x11/ 0x21/ 0x31/ 0x41 for
flexible filt ers 0/ 1/ 2/ 3 accordingly.
The filt er dat a group paramet er defines which byt es of t he flex filt er are set by t his command:
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02
0x10/
0x20/
0x30/
0x40
Bi t s
By t es 31. . 24 23. . 16 15..08 07. .00
20. . 0x02
0x11/
0x21/
0x31/
0x41
Filt er Dat a Group Filt er Dat a 1
. . Filt er Dat a N
Tabl e 10- 7. Fi l t er Dat a Gr oup
Code
By t es
Pr ogr ammed
Fi l t er Dat a
Lengt h
0x0 Byt es 0- 29 1 - 30
0x1 Byt es 30- 59 1 - 30
0x2 Byt es 60- 89 1 - 30
0x3 Byt es 90- 119 1 - 30
0x4 Byt es 120- 127 1 - 8

677
10.5.1.6.8 Set I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3 Dat a Response ( I nt el Command 0x 02,
Not e: I f filt er dat a lengt h is larger t han specified in Table 10- 7 an out of range reason code is
ret urned.
10.5.1.6.9 Set I nt el Fi l t er s Pack et Addi t i on Deci si on Fi l t er Command ( I nt el Command
0x 02, Fi l t er Par amet er 0x 61)
Filt er index range: 0x0.. 0x4
I f t he filt er index is bigger t han four, a command failed response code is ret urned wit h no reason.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02
0x11/
0x21/
0x31/
0x41
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x02 0x61 Filt er index Decision Filt er ( MSB)
24. . 26 . . . . . Decision Filt er ( LSB)
I nt el

678
The filt ering is divided int o 2 decisions:
Bit s 0,1,2,3,6 works in an AND manner.As a result , t hey all must be t rue in order for a packet t o pass ( if
any were set ) .
Tabl e 10- 8. Fi l t er Val ues
0 Unicast ( AND) I f set , packet s must mat ch a unicast filt er.
1 Broadcast ( AND) I f set , packet s must mat ch t he broadcast filt er.
2 VLAN ( AND) I f set , packet s must mat ch a VLAN filt er.
3 I P Address ( AND) I f set , packet s must mat ch an I P filt er.
4 Unicast ( OR) I f set , packet s must mat ch a unicast filt er or a different OR filt er.
5 Broadcast
I f set , packet s must mat ch t he broadcast filt er or a different OR
filt er.
6 Mult icast ( AND) I f set , packet s must mat ch t he mult icast filt er.
7 ARP Request ( OR)
I f set , packet s must mat ch t he ARP request filt er or a different OR
filt er.
8
ARP
Response ( OR)
I f set , packet s can pass if mat ch t he ARP response filt er.
9
Neighbor
Discovery ( OR)
I f set , packet s can pass if mat ch t he neighbor discovery filt er.
10 Port 0x298 ( OR) I f set , packet s can pass if mat ch a fixed TCP/ UDP port 0x298 filt er.
11 Port 0x26F ( OR) I f set , packet s can pass if mat ch a fixed TCP/ UDP port 0x26F filt er.
12 Flex port 0 ( OR) I f set , packet s can pass if mat ch t he TCP/ UDP port filt er 0.
23 DHCPv6 ( OR) I f set , packet s can pass if mat ch t he DHCPv6 port ( 0x0223) .
24 DHCP Client ( OR) I f set , packet s can pass if mat ch t he DHCP server port ( 0x0043) .
25 DHCP Server ( OR) I f set , packet s can pass if mat ch t he DHCP client port ( 0x0044) .
26 Net BI OS Name Service ( OR)
I f set , packet s can pass if mat ch t he Net BI OS name service port
( 0x0089) .
27
Net BI OS Dat agram Service
( OR)
I f set , packet s can pass if mat ch t he Net BI OS dat agram service
port ( 0x008A) .
28 Flex TCO 0 ( OR) I f set , packet s can pass if mat ch t he flex 128 TCO filt er 0.

679
Bit s 5, 7- 31 operat e in an OR manner. Thus, at least one of t hem must be t rue for a packet t o pass ( if
any were set ) .
See Sect ion 10.3.5 for descript ion of t he decision filt ers.
Not e: These filt er set t ings operat e according t o t he VLAN mode, as configured according t o t he
DMTF NC- SI specificat ion. Aft er disabling packet reduct ion filt ers, t he BMC must reset t he
VLAN mode using t he Set VLAN command.
10.5.1.6.10 Set I nt el Fi l t er s Pack et Addi t i on Deci si on Fi l t er Response ( I nt el Command
10.5.1.6.11 Set I nt el Fi l t er s Fl ex TCP/ UDP Por t Fi l t er Command ( I nt el Command 0x 02,
Fi l t er Par amet er 0x 63)
Filt er index range: 0x0.. 0xA.
I f t he filt er index is bigger t han 10, a command failed response code is ret urned wit h no reason.
10.5.1.6.12 Set I nt el Fi l t er s Fl ex TCP/ UDP Por t Fi l t er Response ( I nt el Command 0x 02,
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02 0x61
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x02 0x63 Port filt er index TCP/ UDP Port MSB
24 TCP/ UDP Port LSB
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02 0x63
I nt el

680
10.5.1.6.13 Set I nt el Fi l t er s I Pv4 Fi l t er Command ( I nt el Command 0x 02, Fi l t er Par amet er
0x 64)
Not e: The filt ers index range can vary according t o t he I Pv4/ I Pv6 mode set t ing in t he Filt ers Cont rol
command
I Pv4 Mode: Filt er index range: 0x0. .0x3.
I Pv6 Mode: This command should not be used in I Pv6 mode.
10.5.1.6.14 Set I nt el Fi l t er s I Pv4 Fi l t er Response ( I nt el Command 0x 02, Fi l t er Par amet er
0x 64)
I f t he I P filt er index is bigger t han t hree, a command failed response code is ret urned wit h no reason.
Bi t s
By t es 31..24 23.. 16 15. .08 07..00
20. . 23 0x02 0x64 I P filt er index I Pv4 Address ( MSB)
24. . 26 . . . I Pv4 Address ( LSB)
Bi t s
By t es 31..24 23.. 16 15. .08 07..00
24. . 25 0x02 0x64

681
10.5.1.6.15 Set I nt el Fi l t er s I Pv 6 Fi l t er Command ( I nt el Command 0x 02, Fi l t er Par amet er
0x 65)
command
I Pv4 Mode: Filt er index range: 0x1.. 0x3.
10.5.1.6.16 Set I nt el Fi l t er s I Pv6 Fi l t er Response ( I nt el Command 0x 02, Fi l t er Par amet er
0x 65)
I f t he I P filt er index is bigger t han t hree, a command failed response code is ret urned wit h no reason.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x02 0x65 I P filt er index
I Pv6 Address ( MSB,
byt e 15)
24. . 27 . . . . . . . .
28. . 31 . . . . . . . .
32. . 35 . . . . . . . .
36. . 38 . . . .
I Pv6 Address ( LSB,
byt e 0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02 0x65
I nt el

682
10.5.1.6.17 Set I nt el Fi l t er s Et her Ty pe Fi l t er Command ( I nt el Command 0x 02, Fi l t er
Par amet er 0x 67)
Where t he Et herType filt er has t he format as described in Sect ion 8. 2.3.25.3.
10.5.1.6.18 Set I nt el Fi l t er s - Et her Ty pe Fi l t er Response ( I nt el Command 0x 02, Fi l t er
Par amet er 0x 67)
I f t he Et hert ype filt er index is different t han t wo or t hree, a command failed response code is ret urned
wit h no reason.
10.5.1.6.19 Set I nt el Fi l t er s Pack et Addi t i on Ex t ended Deci si on Fi l t er Command ( I nt el
Command 0x 02, Fi l t er Par amet er 0x 68)
DecisionFilt er0 Bit s 5,7- 31 and DecisionFilt er1 bit s 8. .10 work in an OR manner. Thus, at least one of
t hem must be t rue for a packet t o pass ( if any were set ) .
See Figure 10. 2 for descript ion of t he decision filt ers st ruct ure.
Not e: The command must overwrit e any previously st ored value.
Not e: Previous Set I nt el Filt ers Packet Addit ion Decision Filt er command ( 0x61) should be kept
and support ed. For legacy reasons, if previous Decision Filt er command is called, it should set
t he Decision Filt er 0 as provided and set t he ext ended Decision Filt er t o 0x0.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x02 0x67
Et herType Filt er
I ndex
Et herType Filt er
MSB
24. . 27 . . . . Et herType Filt er LSB
Tabl e 10- 9. Et her t y pe Usage
Fi l t er # Usage Not e
2 User defined
3 User defined
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02 0x67

683
Ext ended decision filt er index range: 0..4.
Filt er 0: See Table 10- 8.
Filt er 1: See t he following t able:
10.5.1.6.20 Set I nt el Fi l t er s Pack et Addi t i on Ex t ended Deci si on Fi l t er Response ( I nt el
I f t he ext ended decision filt er index is bigger t han five, a command failed response code is ret urned
wit h no reason.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x02 0x68
Ext ended Decision
filt er I ndex
Ext ended Decision
filt er 1 MSB
24. . 27 . . . .
Ext ended Decision
filt er 1 LSB
Ext ended Decision
filt er 0 MSB
28. . 30 . . . .
Ext ended Decision
filt er 0 LSB
Tabl e 10- 10. Ex t ended Fi l t er 1 Val ues
0 Et hert ype 0x88F8 AND filt er
1 Et hert ype 0x8808 AND filt er
3: 2 Et hert ype 2 - 3 AND filt ers
8 Et hert ype 0x88F8 OR filt er
9 Et hert ype 0x8808 OR filt er
11: 10 Et hert ype 2 - 3 OR filt ers
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x02 0x68
I nt el

684
10. 5. 1. 7 Get I nt el Fi l t er s For mat s
10.5.1.7.1 Get I nt el Fi l t er s Command ( I nt el Command 0x 03)
10.5.1.7.2 Get I nt el Fi l t er s Response ( I nt el Command 0x 03)
10.5.1.7.3 Get I nt el Fi l t er s Manageabi l i t y t o Host Command ( I nt el Command 0x 03, Fi l t er
Par amet er 0x 0A)
This command ret rieves t he Mng2Host regist er. The Mng2Host regist er cont rols whet her pass- t hrough
packet s dest ined t o t he BMC are also forwarded t o t he host operat ing syst em.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x03 Filt er Paramet er
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x03 Filt er Paramet er Opt ional Ret urn Dat a
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x03 0x0A

685
10.5.1.7.4 Get I nt el Fi l t er s Manageabi l i t y t o Host Response ( I nt el Command 0x 03, Fi l t er
Par amet er 0x 0A)
The Mng2Host regist er has t he following st ruct ure:
10.5.1.7.5 Get I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3 Enabl e Mask and Lengt h Command ( I nt el
The following command ret rieves t he I nt el flex filt ers mask and lengt h. Use filt er paramet ers 0x10/
0x20/ 0x30/ 0x40 for flexible filt ers 0/ 1/ 2/ 3 accordingly. See Sect ion 10.3.4. 1 for det ails of t he values
ret urned by t his command.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x03 0x0A Manageabilit y t o Host ( MSB)
28. . 29 Manageabilit y t o Host ( LSB)
Tabl e 10- 11. Mng2Host St r uct ur e
Bi t s Descr i pt i on Def aul t
5 Unicast & Mixed
Det ermines if unicast and mixed packet s are also forwarded t o t he
host operat ing syst em.
6 Global Mult icast
Det ermines if global mult icast packet s are also forwarded t o t he host
operat ing syst em.
7 Broadcast
Det ermines if broadcast packet s are also forwarded t o t he host
operat ing syst em.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
I nt el

686
10.5.1.7.6 Get I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3 Enabl e Mask and Lengt h Response ( I nt el
10.5.1.7.7 Get I nt el Fi l t er s Fl ex Fi l t er 0/ 1/ 2/ 3/ 4 Dat a Command ( I nt el Command 0x 03,
The following command ret rieves t he I nt el flex filt ers dat a. Use filt er paramet ers 0x11/ 0x21/ 0x31/ 0x41
for flexible filt ers 0/ 1/ 2/ 3 accordingly.
20. . 21 0x03
0x10/
0x20/
0x30/
0x40
Bi t s
By t es 31. .24 23.. 16 15..08 07..00
24. . 27 0x03
0x10/
0x20/
0x30/
0x40
Mask Byt e 1 Mask Byt e 2
28. . 31 . . . . . . . .
32. . 35 . . . . . . . .
36. . 39 . . . . . . . .
40. . 43 . . Mask Byt e 16 Reserved Reserved
44 Flexible Filt er Lengt h
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x03
0x11/
0x21/
0x31/
0x41
Filt er Dat a Group
0. . 4

687
The filt er dat a group paramet er defines which byt es of t he flex filt er are ret urned by t his command:
10.5.1.7.8 Get I nt el Fi l t er s Fl ex Fi l t er Dat a Response ( I nt el Command 0x 03, Fi l t er
Par amet er 0x 11)
I f t he filt er group number is bigger t han four, a command failed response code is ret urned wit h no
reason.
10.5.1.7.9 Get I nt el Fi l t er s Pack et Addi t i on Deci si on Fi l t er Command ( I nt el Command
Filt er index range: 0x0.. 0x4.
Tabl e 10- 12. Fi l t er Dat a Gr oup
Code By t es Ret ur ned
0x0 Byt es 0- 29
0x1 Byt es 30- 59
0x2 Byt es 60- 89
0x3 Byt es 90- 119
0x4 Byt es 120- 127
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 0x03
0x11/
0x21/
0x31/
0x41
Filt er Dat a Group Filt er Dat a 1
. . Filt er Dat a N
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x03 0x61 Decision filt er index
I nt el

688
10.5.1.7.10 Get I nt el Fi l t er s Pack et Addi t i on Deci si on Fi l t er Response ( I nt el Command
0x 03, Fi l t er Par amet er 0x 0A)
The decision filt er st ruct ure ret urned is list ed in Table 10- 8.
I f t he decision filt er index is bigger t han four, a command failed response code is ret urned wit h no
reason.
10.5.1.7.11 Get I nt el Fi l t er s Fl ex TCP/ UDP Por t Fi l t er Command ( I nt el Command 0x 03,
10.5.1.7.12 Get I nt el Fi l t er s Fl ex TCP/ UDP Por t Fi l t er Response ( I nt el Command 0x 03,
I f t he TCP/ UDP filt er index is bigger t han 10, a command failed response code is ret urned wit h no
reason.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x03 0x61 Decision Filt er ( MSB)
28. . 29 Decision Filt er ( LSB)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x03 0x63 TCP/ UDP Filt er I ndex
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x03 0x63 TCP/ UDP Filt er I ndex TCP/ UDP Port ( 1)
28 TCP/ UDP Port ( 0)

689
10.5.1.7.13 Get I nt el Fi l t er s I Pv 4 Fi l t er Command ( I nt el Command 0x 03, Fi l t er Par amet er
0x 64)
command
I Pv6 Mode: This command should not be used in I Pv6 mode.
10.5.1.7.14 Get I nt el Fi l t er s I Pv4 Fi l t er Response ( I nt el Command 0x 03, Fi l t er Par amet er
0x 64)
I f t he I Pv4 filt er index is bigger t han t hree, a command failed response code is ret urned wit h no reason.
10.5.1.7.15 Get I nt el Fi l t er s I Pv 6 Fi l t er Command ( I nt el Command 0x 03, Fi l t er Par amet er
0x 65)
command.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x03 0x64 I Pv4 Filt er I ndex
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x03 0x64 I Pv4 Filt er I ndex I Pv4 Address ( 3)
28. . 29 I Pv4 Address ( 2- 0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
I nt el

690
10.5.1.7.16 Get I nt el Fi l t er s I Pv6 Fi l t er Response ( I nt el Command 0x 03, Fi l t er Par amet er
0x 65)
I f t he I Pv6 filt er index is bigger t han t hree, a command failed response code is ret urned wit h no reason.
10.5.1.7.17 Get I nt el Fi l t er s Et her Type Fi l t er Command ( I nt el Command 0x 03, Fi l t er
Par amet er 0x 67)
Valid indices: 2..3.
See Table 10- 9 for a list of t he various Et hert ype filt ers usage.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
I Pv6 Address ( MSB,
Byt e 16)
28. . 31 . . . . . . . .
32. . 35 . . . . . . . .
36. . 39 . . . . . . . .
40. . 42 . . . .
I Pv6 Address ( LSB,
Byt e 0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x03 0x67
Et herType Filt er
I ndex

691
10.5.1.7.18 Get I nt el Fi l t er s - Et her Type Fi l t er Response ( I nt el Command 0x 03, Fi l t er
Par amet er 0x 67)
I f t he Et hert ype filt er index is different t han t wo or t hree, a command failed response code is ret urned
wit h no reason.
10.5.1.7.19 Get I nt el Fi l t er s Pack et Addi t i on Ex t ended Deci si on Fi l t er Command ( I nt el
This command enables t he BMC t o ret rieve t he ext ended decision filt er.
10.5.1.7.20 Get I nt el Fi l t er s Pack et Addi t i on Ex t ended Deci si on Fi l t er Response ( I nt el
Where Decision Filt er 0 and Decision Filt er 1 have t he st ruct ure as det ailed in t he respect ive Set
commands.
I f t he ext ended decision filt er index is bigger t han four, a command failed response code is ret urned
wit h no reason.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x03 0x67
Et herType Filt er
I ndex
Et herType Filt er MSB
28. . 30 . . . . Et herType Filt er LSB
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x03 0x68
Ext ended Decision
Filt er I ndex
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x03 0x68 Decision Filt er I ndex Decision Filt er 1 MSB
28. . 31 . . . . Decision Filt er 1 LSB Decision Filt er 0 MSB
32. . 34 . . . . Decision Filt er 0 LSB
I nt el

692
10. 5. 1. 8 Set I nt el Pack et Reduct i on Fi l t er s For mat s
10.5.1.8.1 Set I nt el Pack et Reduct i on Fi l t er s Command ( I nt el Command 0x 04)
Not e: I t is recommended t hat t he BMC only uses t he Ext ended Packet Reduct ion commands.
The Packet Reduct ion Dat a field has t he following st ruct ure:
Fort he Ext ended Packet Reduct ion command, t he following fields should also be programmed.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x04 Filt er Paramet er Opt ional Dat a
Tabl e 10- 13. Pack et Reduct i on Dat a
2: 0 Reser ved
3 I P Address I f set , all packet s must also mat ch an I P filt er.
9: 4 Reser ved
10 Port 0x298 I f set , all packet s can pass if mat ch a fixed TCP/ UDP port 0x298 filt er.
11 Port 0x26F I f set , all packet s can pass if mat ch a fixed TCP/ UDP port 0x26F filt er.
12 Flex port 0 I f set , all packet s can pass if mat ch t he TCP/ UDP port filt er 0.
27: 23 Reserved
28 Flex TCO 0 I f set , all packet s can pass if mat ch t he Flex 128 TCO filt er 0.

693
The filt ering is divided int o t wo decisions:
Unicast Reduct ion Filt er Bit 3 and Ext ended Unicast Reduct ion Filt er bit s 0.. 2 work in an AND manner.
Thus, t hey all must be t rue in order for a packet t o pass ( if any were set ) .
Unicast Reduct ion Filt er bit s 5, 7- 31 and Ext ended Unicast Reduct ion Filt er bit s 8. .10 work in an OR
manner, Thus, at least one of t hem must be t rue for a packet t o pass ( if any were set ) .
See Sect ion 10.3.5 for descript ion of t he decision filt ers.
10.5.1.8.2 Set I nt el Pack et Reduct i on Fi l t er s Response ( I nt el Command 0x 04)
10.5.1.8.3 Set Uni cast / Mul t i cast / Br oadcast pack et Reduct i on Command ( I nt el Command
0x 04, Fi l t er Par amet er 0x 00/ 0x 01/ 0x 02)
This command must cause t he net work cont roller t o filt er packet s t hat have passed due t o t he unicast /
mult icast / broadcast filt er. Not e t hat unicast filt ering might be affect ed by ot her filt ers, as specified in
t he DMTF NC- SI .
Tabl e 10- 14. Ex t ended Pack et Reduct i on For mat
0. . 1 Reser ved Used by t he regular NC- SI commands.
2 Et herType2 ( AND) I f set , packet s must also mat ch t he Et herType filt er 2.
3 Et herType3 ( AND) I f set , packet s must also mat ch t he Et herType filt er 3.
4. . 7 Reserved
8. . 9 Reser ved Used by t he regular NC- SI commands
10 Et herType2 ( OR) I f set , packet s can pass if it mat ch t he Et herType filt er 2.
11 Et herType3 ( OR) I f set , packet s can pass if it mat ch t he Et herType filt er 2.
12. . 31 Reserved
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 0x04 Filt er Paramet er Opt ional Ret urn Dat a
Bi t s
By t es 31. . 24 23. . 16 15..08 07. .00
20. . 23 0x04 0x00 / 0x01 / 0x02 Packet Reduct ion Table ( MSB)
24. . 25 Packet Reduct ion Table ( LSB)
I nt el

694
The filt ering of t hese packet s are done such t hat t he BMC might add a logical condit ion t hat a packet
must mat ch, or it must be discarded.
Not e: Packet s t hat might have been blocked can st ill pass due t o ot her decision filt ers.
I n order t o disable unicast / mult icast / broadcast packet reduct ion, t he BMC should set all reduct ions
filt ers t o 0b. Following such a set t ing, t he net work cont roller forwards t o t he BMC all packet s t hat have
passed t he unicast Et hernet MAC address/ global mult icast / broadcast filt ers as specified in t he DMTF
NC- SI .
10.5.1.8.4 Set Uni cast / Mul t i cast / Br oadcast Pack et Reduct i on Response ( I nt el Command
0x 04, Reduct i on Fi l t er Par amet er 0x 00/ 0x 01/ 0x 02)
10.5.1.8.5 Set Uni cast / Mul t i cast / Br oadcast Ex t ended Pack et Reduct i on Command ( I nt el
Command 0x 04, Fi l t er Par amet er 0x 10/ 0x 11/ 0x 12)
I n Set I nt el Reduct ion Filt ers, add anot her paramet er Unicast Ext ended Packet Reduct ion ( I nt el
Command 0x04, Filt er paramet er 0x10) such t hat t he byt e count is 0xE. The command must have t he
following format :
The command must overwrit e any previously st ored value.
Not e: See Table 10- 13 and Table 10- 14 for a list of t he unicast ext ended packet reduct ion format .
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x04 0x00 / 0x01 / 0x02
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x04 0x10 / 0x11 / 0x12
Ext ended Reduct ion
Filt er MSB
. .
24. . 27 . .
Ext ended Reduct ion
Filt er LSB
Reduct ion Filt er
Table ( MSB)
. .
28. . 29 . .
Reduct ion Filt er
Table ( LSB)

695
10.5.1.8.6 Set Uni cast / Mul t i cast / Br oadcast Ex t ended Pack et Reduct i on Response ( I nt el
Command 0x 04, Reduct i on Fi l t er I ndex 0x 10 / 0x 11 / 0x 12)
10. 5. 1. 9 Get I nt el Pack et Reduct i on Fi l t er s For mat s
10.5.1.9.1 Get I nt el Pack et Reduct i on Fi l t er s Command ( I nt el Command 0x 05)
10.5.1.9.2 Get I nt el Pack et Reduct i on Fi l t er s Response ( I nt el Command 0x 05)
10.5.1.9.3 Get Uni cast / Mul t i cast / Br oadcast Pack et Reduct i on Command & Response
( I nt el Command 0x 05, Fi l t er Par amet er 0x 00/ 0x 01/ 0x 02)
This command ret rieves t he request ed packet reduct ion filt er. The format of t he opt ional ret urn dat a
follows t he st ruct ure of t he Unicast Packet Reduct ion command described in Sect ion 10. 5.1.8. 3.
10.5.1.9.4 Get Uni cast / Mul t i cast / Br oadcast Ex t ended Pack et Reduct i on Command &
Response ( I nt el Command 0x 05, Fi l t er Par amet er 0x 00/ 0x 01/ 0x 02)
This command ret rieves t he request ed ext ended packet reduct ion filt er. The format of t he opt ional
ret urn dat a follows t he st ruct ure of t he Unicast Ext ended Packet Reduct ion command described in
Sect ion 10. 5.1.8. 5.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x04 0x10 / 0x11 / 0x12
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x05 Filt er Paramet er
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 0x05 Filt er Paramet er Opt ional Ret urn Dat a
I nt el

696
10. 5. 1. 10 Sy st em Et her net MAC Addr ess
10.5.1.10.1 Get Syst em Et her net MAC Addr ess Command ( I nt el Command 0x 06)
I n order t o support a syst em configurat ion t hat requires t he net work cont roller t o hold t he Et hernet
MAC address for t he BMC ( such as shared Et hernet MAC address mode) , t he following command is
provided t o enable t he BMC t o query t he net work cont roller for a valid Et hernet MAC address.
The net work cont roller must ret urn t he syst em Et hernet MAC addresses. The BMC should use t he
ret urned Et hernet MAC addressing as a shared Et hernet MAC address by set t ing it using t he Set
Et hernet MAC Address command as defined in NC- SI 1.0.
I t is also recommended t hat t he BMC uses t he Packet Reduct ion and Manageabilit y- t o- Host command
t o set t he proper filt ering met hod.
10.5.1.10.2 Get Syst em Et her net MAC Addr ess Response ( I nt el Command 0x 06)
The MAC address is ret urned in net work order.
10. 5. 1. 11 Set I nt el Management Cont r ol For mat s
10.5.1.11.1 Set I nt el Management Cont r ol Command ( I nt el Command 0x 20)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20 0x06
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x06 Et hernet MAC Address
28. . 30 Et hernet MAC Address
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x20 0x00
I nt el Management
Cont rol

697
The I nt el management cont rol byt e is defined in t he following t able:
10.5.1.11.2 Set I nt el Management Cont r ol Response ( I nt el Command 0x 20)
10. 5. 1. 12 Get I nt el Management Cont r ol For mat s
10.5.1.12.1 Get I nt el Management Cont r ol Command ( I nt el Command 0x 21)
Bi t # Def aul t Descr i pt i on
0 0b
Enable Crit ical Session Mode ( t he Keep PHY Link Up and Vet o bit s)
0b = Disabled
1b = Enabled
When crit ical session mode is enabled, t he PHY is not reset on PE_RST# nor PCI e reset s ( in- band and link
drop) . Ot her reset event s are not affect ed LAN Power Good reset , Device Disable, Force TCO, and PHY
reset by soft ware.
The PHY does not change it s power st at e. As a result , link speed does not change.
The device does not init iat e configurat ion of t he PHY t o avoid losing link.
17 0x0 Reserved
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x20 0x00
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x20 0x00
I nt el

698
10.5.1.12.2 Get I nt el Management Cont r ol Response ( I nt el Command 0x 21)
I nt el Management Cont rol 1 byt e is described in Sect ion 10. 5. 1. 11. 1.
10. 5. 1. 13 TCO Reset
This command causes t he net work cont roller t o perform TCO Reset , if Force TCO reset is enabled in t he
EEPROM.
I f t he BMC has det ect ed t hat t he operat ing syst em is hung and has blocked t he Rx/ Tx pat h t he Force
TCO reset clears t he dat a pat h ( Rx/ Tx) of t he net work cont roller t o enable t he BMC t o t ransmit / receive
packet s t hrough t he net work cont roller.
When t his command is issued t o a channel in a package, it applies only t o t he specific channel.
Aft er successfully performing t he command t he net work cont roller considers Force TCO command as an
indicat ion t hat t he operat ing syst em is hung and clears t he DRV_LOAD flag ( disable t he driver) .
10.5.1.13.1 Per f or m I nt el TCO Reset Command ( I nt el Command 0x 22)
10.5.1.13.2 Per f or m I nt el TCO Reset Response ( I nt el Command 0x 22)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 26 0x21 0x00
I nt el Management
Cont r ol 1
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20 0x22 TCO Mode
1
1. See Sect ion 10. 5. 2. 1. 4.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 26 0x22

699
10. 5. 1. 14 Check sum Of f l oadi ng
This command enables t he checksum offloading filt ers in t he net work cont roller.
When enabled, t hese filt ers block any packet s t hat did not pass I P, UDP and TCP checksums from being
forwarded t o t he BMC. This feat ure does not support t unneled I Pv4/ I Pv6 packet inspect ion.
10.5.1.14.1 Enabl e Check sum Of f l oadi ng Command ( I nt el Command 0x 23)
10.5.1.14.2 Enabl e Check sum Of f l oadi ng Response ( I nt el Command 0x 23)
10.5.1.14.3 Di sabl e Check sum Of f l oadi ng Command ( I nt el Command 0x 24)
This command causes t he net work cont roller t o st op verifying t he I P/ UDP/ TCP checksums.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20 0x23
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 26 0x23
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20 0x24
I nt el

700
10.5.1.14.4 Di sabl e Check sum Of f l oadi ng Response ( I nt el Command 0x 24)
10. 5. 1. 15 Read / Wr i t e Conf i gur at i on
The following command set enables t he BMC t o read and writ e specific MAC CSRs.
10.5.1.15.1 Wr i t e Conf i gur at i on Command ( I nt el Command 0x F0)
This command enables t he BMC t o writ e one MAC CSR at a defined offset .
10.5.1.15.2 Wr i t e Conf i gur at i on Response ( I nt el Command 0x F0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 26 0x24
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20 0xF0 MAC CSR offset ( 3- 1)
24. . 27 MAC CSR offset ( 0) MAC CSR Value ( 3- 1)
28 MAC CSR Value ( 0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24 0xF0

701
10.5.1.15.3 Read Conf i gur at i on Command ( I nt el Command 0x F1)
This command enables t he BMC t o read one MAC CSR at a defined offset .
10.5.1.15.4 Read Conf i gur at i on Response ( I nt el Command 0x F1)
10. 5. 1. 16 Li nk Sec Suppor t Commands
The following commands can be used by t he BMC t o cont rol t he different aspect s of t he LinkSec engine.
10.5.1.16.1 Tr ansf er Li nk Sec Ow ner shi p t o BMC Command ( I nt el Command 0x 30,
Par amet er 0x 10)
This command causes t he 82599 t o clear all LinkSec paramet ers, forcefully release host ownership and
grant t he ownership t o t he BMC. The BMC might allow t he host t o use t he BMCs key for t raffic by
set t ing t he Host Cont rol Allow Host Traffic bit . Act ivat ing t his command clears all t he LinkSec
paramet ers.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20 0xF1 MAC CSR offset ( 3- 1)
24 MAC CSR offset ( 0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0xF1 MAC CSR offset ( 3- 1)
28. . 31 MAC CSR offset ( 0) MAC CSR Value ( 3- 1)
32 MAC CSR Value ( 0)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x30 0x10 Host Cont rol
I nt el

702
10.5.1.16.2 Tr ansf er Li nk Sec Ow ner shi p t o BMC Response ( I nt el Command 0x 30, Par amet er
0x 10)
10.5.1.16.3 Tr ansf er Li nk Sec Ow ner shi p t o Host Command ( I nt el Command 0x 30,
Par amet er 0x 11)
This command causes t he 82599 t o clear all LinkSec paramet ers, release BMC ownership and grant
ownership t o t he host .
I n t his scenario t raffic from/ t o t he MC must be validat ed by t he host s programmed keys. I t is
recommended t hat t he MC t ry t o est ablish net work communicat ion wit h a remot e st at ion t o verify t hat
t he host was successful in programming t he keys.
Act ivat ing t his command clears all t he LinkSec paramet ers.
Tabl e 10.15. Li nk Sec Host Cont r ol
Bi t Descr i pt i on
0 Reserved
1
Allow Host Traffic:
0b = Host t raffic is blocked.
1b = Host t raffic is allowed.
2. . 7 Reserved
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x10
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x30 0x11

703
10.5.1.16.4 Tr ansf er Li nk Sec Ow ner shi p t o Host Response ( I nt el Command 0x 30,
Par amet er 0x 11)
10.5.1.16.5 I ni t i al i ze Li nk Sec Rx Command ( I nt el Command 0x 30, Par amet er 0x 12)
This command can be used by t he MC t o init ialize t he LinkSec Rx engine. This command should be
followed by a Set LinkSec Rx Key command t o est ablish a LinkSec environment .
Where:
Rx Por t I dent i f i er t he port number by which t he NC ident ifies Rx packet s. I t is recommended
t hat t he MC use 0x0 as t he port ident ifier. Not e t hat t he MC should use t he same port ident ifier
when performing t he key- exchange.
Rx SCI A 6- byt e unique ident ifier for t he LinkSec Tx CA. I t is recommended t hat t he MC use it s
Et hernet MAC address value for t his field.
10.5.1.16.6 I ni t i al i ze Li nk Sec Rx Response ( I nt el Command 0x 30, Par amet er 0x 12)
Bi t s
By t es 31..24 23.. 16 15. .08 07..00
24. . 25 0x30 0x11
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x30 0x12 Rx Port I dent ifier
24. . 27 Rx SCI [ 0. . 3]
28. . 29 Rx SCI [ 4. . 5]
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x12
I nt el

704
10.5.1.16.7 I ni t i al i ze Li nk Sec Tx Command ( I nt el Command 0x 30, Par amet er 0x 13)
This command can be used by t he MC t o init ialize t he LinkSec Tx engine. This command should be
followed by a Set LinkSec Tx Key command t o est ablish a LinkSec environment .
Tx Por t I dent i f i er For t his implement at ion t his field is a dont care and is aut omat ically set t o
0x0.
Tx SCI A 6- byt e unique ident ifier for t he LinkSec Tx CA. I t is recommended t hat t he MC use it s
PN Thr eshol d When a new key is programmed, t he packet number is reset t o 0x1. Wit h each Tx
packet , The packet number increment s by one and is insert ed t o t he packet ( t o avoid replay
at t acks) . The PN t hreshold value is t he 3 MSByt es of t he Tx packet number aft er which a Key
Exchange Required AEN is sent t o t he MC. Example: a PN t hreshold of 0x123456 means t hat when
t he PN reaches 0x123456FF a not ificat ion is sent . The fourt h byt e of t he PN t hreshold can be seen
as a reserved bit , because it is always t reat ed as 0xFF by t he NC.
Tx Cont r ol :
10.5.1.16.8 I ni t i al i ze Li nk Sec Tx Response ( I nt el Command 0x 30, Par amet er 0x 13)
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x30 0x13 Tx Port I dent ifier
24. . 27 Tx SCI [ 0. . 3]
28. . 31 Tx SCI [ 4. . 5] Reserved
32. . 35 Packet Number Threshold
36 Tx Cont rol
0. . 4 Reserved
5
Always I nclude SCI in Tx:
0b = Do not include SCI in Tx packet s.
1b = I nclude SCI in Tx packet s.
6. . 7 Reserved
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x13

705
10.5.1.16.9 Set Li nk Sec Rx Key Command ( I nt el Command 0x 30, Par amet er 0x 14)
This command can be used by t he MC t o set a new LinkSec Rx key. Upon receiving t his command t he
NC must swit ch t o t he new Rx key and send t he response.
Where:
Rx SA AN The associat ion number t o be used wit h t his key.
Rx Li nk Sec Key t he 128 bit s ( 16 byt es) key t o be used for Rx
10.5.1.16.10 Set Li nk Sec Rx Key Response ( I nt el Command 0x 30, Par amet er 0x 14)
Bi t s
By t es 31..24 23.. 16 15. .08 07..00
20. . 23 0x30 0x14 Reserved Rx SA AN
24. . 27 Rx LinkSec Key MSB . . . . . .
28. . 31 . . . . . . . .
32. . 35 . . . . . . . .
36. . 39 . . . . . . Rx LinkSec Key LSB
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x14
I nt el

706
10.5.1.16.11 Set Li nk Sec Tx Key Command ( I nt el Command 0x 30, Par amet er 0x 15)
This command can be used by t he MC t o set a new LinkSec Tx key. Upon receiving t his command t he
NC must swit ch t o t he new Tx key and send t he response.
Where:
Tx SA AN The associat ion number t o be used wit h t his key.
Tx Li nk Sec Key t he 128 bit s ( 16 byt es) key t o be used for Tx
10.5.1.16.12 Set Li nk Sec Tx Key Response ( I nt el Command 0x 30, Par amet er 0x 15)
10.5.1.16.13 Enabl e Net w or k Tx Encr y pt i on Command ( I nt el Command 0x 30, Par amet er
0x 16)
This command can be used by t he MC t o re- enable encrypt ion of out going pass- t hrough packet s.
Aft er t his command is issued and unt il a response is received, t he st at e of any out going packet s is
undet ermined.
By default net work Tx encrypt ion is enabled.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 23 0x30 0x15 Reserved Tx SA AN
24. . 27 Tx LinkSec Key MSB . . . . . .
28. . 31 . . . . . . . .
32. . 35 . . . . . . . .
36. . 39 . . . . . . Tx LinkSec Key LSB
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x15
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x30 0x16

707
10.5.1.16.14 Enabl e Net w or k Tx Encr y pt i on Response ( I nt el Command 0x 30, Par amet er
0x 16)
Following sending t his response t he NC must st op encrypt ing out going pass- t hrough packet s.
10.5.1.16.15 Di sabl e Net w or k Tx Encr ypt i on Command ( I nt el Command 0x 30, Par amet er
0x 17)
This command can be used by t he MC t o disable encrypt ion of out going pass- t hrough packet s.
Aft er t his command is issued and unt il a response is received, t he st at e of any out going packet s is
undet ermined.
10.5.1.16.16 Di sabl e Net w or k Tx Encr y pt i on Response ( I nt el Command 0x 30, Par amet er
0x 17)
Following sending t his response t he NC must st art encrypt ing out going pass- t hrough packet s.
10.5.1.16.17 Enabl e Net w or k Rx Decr y pt i on Command ( I nt el Command 0x 30, Par amet er
0x 18)
This command can be used by t he MC t o re- enable decrypt ion of incoming pass- t hrough packet s. This
causes t he NC t o execut e LinkSec offload and t o post t he frames t o t he MC ( or host ) only if t he LinkSec
operat ion succeeds.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x16
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x30 0x17
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x17
I nt el

708
Aft er t his command is issued and unt il a response is received, t he st at e of any incoming packet s is
undet ermined.
By default net work Rx decrypt ion is disabled.
10.5.1.16.18 Enabl e Net w or k Rx Decr y pt i on Response ( I nt el Command 0x 30, Par amet er
0x 18)
Following sending t his response t he NC must begin decrypt ing incoming pass- t hrough packet s.
10.5.1.16.19 Di sabl e Net w or k Rx Decr ypt i on Command ( I nt el Command 0x 30, Par amet er
0x 19)
This command can be used by t he MC t o disable decrypt ion of incoming pass- t hrough packet s.
Aft er t his command is issued and unt il a response is received, t he st at e of any incoming packet s is
undet ermined.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x30 0x18
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x18
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 21 0x30 0x19

709
10.5.1.16.20 Di sabl e Net w or k Rx Decr ypt i on Response ( I nt el Command 0x 30, Par amet er
0x 19)
Following sending t his response t he NC must st op decrypt ing incoming pass- t hrough packet s.
10.5.1.16.21 Get Li nk Sec Par amet er s f or mat ( I nt el Command 0x 31)
The following commands can be used by t he MC t o ret rieve t he different LinkSec paramet ers.
These commands responses are valid only if t he BMC owns t he LinkSec.
10.5.1.16.22 Get Li nk Sec Rx Par amet er s Command ( I nt el Command 0x 31, Par amet er 0x 01)
10.5.1.16.23 Get Li nk Sec Rx Par amet er s Response ( I nt el Command 0x 31, Par amet er 0x 01)
This command enables t he MC t o ret rieve t he current ly configured set of Rx LinkSec paramet ers.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 25 0x30 0x19
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x31 0x01
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x31 0x01 Reserved
28. . 31 LinkSec Owner St at us
LinkSec Host Cont rol
St at us
Rx Port I dent ifier
32. . 35 SCI [ 0. . 3]
36. . 39 SCI [ 4. . 5] Reserved Rx SA AN
40. . 43 Rx SA Packet Number
I nt el

710
Where:
Rx Por t I dent i f i er The Rx Port ident ifier
Rx SCI The Rx SCI ident ifier.
Rx SA AN The associat ion number associat ed wit h t he act ive SA ( for which t he last valid Rx
LinkSec packet was received) .
Rx SA Pack et Number I s t he last packet number, as read from t he last valid Rx LinkSec packet .
10.5.1.16.24 Get Li nk Sec Tx Par amet er s Command ( I nt el Command 0x 31, Par amet er 0x 02)
This command enables t he MC t o ret rieve t he current ly configured set of Tx LinkSec paramet er.
Tabl e 10.16. Li nk Sec Ow ner St at us
Val ue Descr i pt i on
0x0 Host is LinkSec owner.
0x1 BMC is LinkSec owner.
Tabl e 10.17. Li nk Sec Host Cont r ol St at us
0 Reserved
1
Allow Host Traffic:
0b= Host t raffic is blocked.
2. . 7 Reserved
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
20. . 22 0x31 0x02

711
10.5.1.16.25 Get Li nk Sec Tx Par amet er s Response ( I nt el Command 0x 31, Par amet er 0x 02)
Where:
Tx Por t I dent i f i er Reserved t o 0x0 for t his implement at ion.
Tx SCI The Rx SCI ident ifier.
Tx SA AN The associat ion number current ly used for t he act ive SA.
Tx SA Pack et Number I s t he last packet number, as read from t he last valid Rx LinkSec packet .
Pack et Number Thr eshol d.
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
24. . 27 0x31 0x2 Reserved
28. . 31 LinkSec Owner St at us
LinkSec Host Cont rol
St at us
Tx Port I dent ifier
32. . 35 SCI [ 0. . 3]
36. . 39 SCI [ 4. . 5] Reserved Tx SA AN
40. . 43 Tx SA Packet Number
44. 47 Packet Number Threshold
48 Tx Cont rol St at us
Tabl e 10. 19. Li nk Sec Host Cont r ol St at us
0 Reserved
1
Allow Host Traffic:
0b= Host t raffic is blocked.
2. . 7 Reserved
I nt el

712
10. 5. 1. 17 Li nk Sec AEN ( I nt el AEN 0x 80)
The following is t he AEN t hat can be sent by t he NC following a LinkSec event .
This AEN must be enabled using t he NC- SI AEN Enable command, using bit 16 ( 0x10000) of t he AEN
enable mask.
Where:
LinkSec Event Cause has t he following format :
Tabl e 10.20. Tx Cont r ol St at us:
0. . 4 Reserved
5
I nclude SCI :
6. . 7 Reserved
Bi t s
By t es 31. . 24 23. . 16 15. . 08 07. . 00
00. . 15 NC- SI AEN Header
20. . 23 Reserved 0x80
24. . 27 Reserved LinkSec Event Cause
Bi t # Descr i pt i on
0 Host request ed ownership.
1 Host released ownership.
2 Tx Key Packet Number ( PN) t hreshold met .
3. . 7 Reserved

713
10.5.2 SMBus Pr ogr ammi ng
This sect ion describes t he SMBus t ransact ions support ed in Advanced Pass Through ( APT) mode.
10. 5. 2. 1 Wr i t e SMBus Tr ansact i ons ( BMC t he 82599)
The following t able list s t he different SMBus writ e t ransact ions support ed by t he 82599.
10.5.2.1.1 Tr ansmi t Pack et Command
The Transmit Packet command behavior is det ailed in sect ion 3. 2.5. The Transmit Packet fragment s
have t he following format :
The payload lengt h is limit ed t o t he maximum payload lengt h set in t he EEPROM.
I f t he overall packet lengt h is bigger t han 1536 byt es, t he packet is silent ly discarded by t he 82599.
10.5.2.1.2 Request St at us Command
The BMC can init iat e a request t o read t he 82599 manageabilit y st at us by sending t his command.
When it receives t his command, t he 82599 init iat es a not ificat ion t o t he BMC ( when it is ready wit h t he
st at us) , and t hen t he BMC is able t o read t he st at us, by issuing a Read St at us command ( see sect ion
10.5. 2. 2. 3) . Request St at us Command format :
TCO Command Tr ansact i on Command Fr agment at i on Sect i on
Transmit Packet Block Writ e
First :
Middle:
Last :
0x84
0x04
0x44
Mult iple 10. 5. 2. 1. 1
Transmit Packet Block Writ e Single: 0xC4 Single 10. 5. 2. 1. 1
Receive Enable Block Writ e Single: 0xCA Single 10. 5. 2. 1. 3
Management Cont rol Block Writ e Single: 0xC1 Single 10. 5. 2. 1. 5
Updat e MNG RCV filt er paramet ers Block Writ e Single: 0xCC Single 10. 5. 2. 1. 6
Force TCO Block Writ e Single: 0xCF Single 10. 5. 2. 1. 4
Request St at us Block Writ e Single: 0xDD Single 10. 5. 2. 1. 2
Updat e LinkSec paramet ers Block Writ e Single: 0xC9 Single 10. 5. 2. 1. 7
Funct i on Command By t e Count Dat a 1 Dat a N
Transmit first fragment 0x84 N
Packet dat a
MSB
Packet dat a LSB
Transmit middle fragment 0x04
Transmit last fragment 0x44
Transmit single fragment 0xC4
Funct i on Command Byt e Count Dat a 1
Request
st at us
0xDD 1 0
I nt el

714
10.5.2.1.3 Recei ve Enabl e Command
The Receive Enable command is a single fragment command t hat is used t o configure t he 82599.
This command has t wo format s: short , 1- byt e legacy format ( providing backward compat ibilit y wit h
previous component s) and long, 14- byt e advanced format ( allowing great er configurat ion capabilit ies) .
Not e: I f t he Receive Enable command is short and t hus does not include all t he paramet ers, t hen
t he paramet ers are t aken from most recent previous configurat ion ( eit her t he most recent
long Receive Enable command in which t he part icular value was set , or t he EEPROM if t here
was no such previous long Receive Enable command) .
While...
Receive cont rol byt e ( dat a byt e 1) has t he following format
Func. Cmd
By t e
Count
Dat a 1 Dat a 2 Dat a 7 Dat a 8 Dat a 11 Dat a 12 Dat a 13 Dat a 14
Legacy
receive
enable
0xCA
1
Receive
cont rol
byt e
-
- -
- - - -
Advanced
receive
enable
14
0x0E
MAC
addr.
MSB
MAC
addr.
LSB
I P addr.
MSB
I P addr.
LSB
BMC
SMBus
addr.
I nt erf.
dat a
byt e
Alert
value
byt e
Fi el d Bi t ( s) Descr i pt i on
RCV_EN 0
Receive TCO Enable.
0b = Disable Receive TCO packet s. Rx Packet s are not direct ed t o BMC and Aut o ARP response is not
enabled.
1b = Enable Receive TCO packet s. Set t ing t his bit enables all manageabilit y receive filt ering
operat ion. The enable of t he specific filt ering is done t hrough loading t he Receive Enable 1 word in t he
EEPROM, or t hrough special configurat ion command ( see Sect ion 10. 5. 2. 1. 6) .
RCV_ALL 1
Receive All Enable. When set t o 1b, all LAN packet s received over t he wire t hat passed L2 filt ering are
forwarded t o t he BMC. This flag is meaningful only if t he RCV_EN bit is set as well.
EN_STA 2 Enable St at us report ing when set t o 1b.
EN_ARP_RES 3
Enable ARP Response.
0b = Disable. The 82599 t reat s ARP packet s as any ot her packet . These packet s are forwarded t o
BMC if it passes ot her ( non-ARP) filt ering.
1b = Enable. The 82599 aut omat ically responds t o all received ARP request s t hat mat ch it s I P
address. Not e t hat set t ing t his bit doesn t change t he Rx filt ering set t ings. Appropriat e Rx filt ering t o
enable ARP request packet s t o reach t he manageabilit y unit should be set by t he BMC or by t he
EEPROM.
The BMC I P address is provided as part of t he Receive Enable message ( byt es 8- 11) . I f short version
of t he command is used t he 82599 uses I P address configured in t he most recent long version of t he
command in which t he EN_ARP_RES bit was set . I f no such previous long command exist s, t hen t he
82599 uses t he I P address configured in t he EEPROM as ARP response I Pv4 address in pass- t hrough
LAN configurat ion st ruct ure. I f CBDM bit is set t he 82599 uses t he BMC dedicat ed Et hernet MAC
address in ARP response packet s. I f t he CBDM bit is not set , BMC uses t he host Et hernet MAC
address.
Set t ing t his bit requires appropriat e assert ion of bit s RCV_EN and RCV_ALL. Ot herwise, t he command
abort s wit h no processing.

715
MNG Et hernet MAC address ( dat a byt es 2- 7)
I gnored if CBDM bit is not set . This Et hernet MAC address is used for configurat ion of t he dedicat ed
Et hernet MAC address. I n addit ion, it is used in t he ARP response packet , when EN_ARP_RES bit is set .
This Et hernet MAC address cont inues t o be used when t he CBDM bit is set in subsequent short versions
of t his command.
MNG I P address ( dat a byt es 8- 11)
I gnored if EN_ARP_RES bit is not set . This I P address is used t o filt er ARP request packet s. This I P
address cont inues t o be used when EN_ARP_RES is set in subsequent short versions of t his command.
Asynchronous not ificat ion SMBus address ( dat a byt e 12)
This address is used for t he asynchronous not ificat ion SMBus t ransact ion and for direct receive.
NM 5: 4
Not ificat ion Met hod. Define t he not ificat ion met hod t hat t he 82599 uses.
00b = SMBus alert
01b = Asynchronous not ify
10b = Direct receive
11b = Not support ed.
Not e: I n dual SMBus address mode, bot h SMBus addresses must be configured t o t he same
not ificat ion met hod.
Reserved 6 Reserved
CBDM 7
Configure BMC dedicat ed Et hernet MAC address.
Not e: This bit should be 0b when t he RCV_EN bit ( bit 0) is not set .
0b = The 82599 shares t he same Et hernet MAC address for manageabilit y and host defined in t he
EEPROM LAN Core 0/ 1 Modules in t he EEPROM.
1b = The 82599 uses a dedicat ed Et hernet MAC address. The BMC Et hernet MAC address is set in
byt es 2- 7 in t his command.
I f short version of t he command is used, t he 82599 uses t he Et hernet MAC address configured in t he
most recent long version of t he command in which t he CBDM bit was set . I f no such previous long
command exist s, t hen t he 82599 uses t he Et hernet MAC address configured in t he MMAL and MMAH
fields in t he EEPROM.
When t he dedicat ed Et hernet MAC address feat ure is act ivat ed, t he 82599 uses t he following regist ers
for Rx filt ering. The BMC should not modify t he following regist ers:
MNG Decision Filt er MDEF7 ( and it s corresponding bit MANC2H[ 7] )
MNG Et hernet MAC Address 3 MMAL3 and MMAH3 ( and it s corresponding bit MFVAL[ 3] ) .
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716
I nt erface dat a ( dat a byt e 13)
I nt erface dat a byt e t o be used in asynchronous not ificat ion.
Alert dat a ( dat a byt e 14) .
Alert value dat a byt e t o be used in t he asynchronous not ificat ion.
10.5.2.1.4 For ce TCO Command
This command causes t he 82599 t o perform a TCO reset , if Force TCO reset is enabled in word Common
Firmware Paramet ers in t he EEPROM. The Force TCO reset clears t he dat a pat h ( Rx/ Tx) of t he 82599 t o
enable t he BMC t o t ransmit / receive packet s t hrough t he 82599.
Not e: I n single address mode, bot h port s are reset when t he command is issued. I n dual address
mode, Force TCO reset is assert ed only t o t he port relat ed t o t he SMB address t he command
was issued t o.
The 82599 considers t he Force TCO command as an indicat ion t hat t he operat ing syst em is hung and
clears t he DRV_LOAD flag.
Force TCO Reset command format :
TCO mode is list ed in t he following t able:
10.5.2.1.5 Management Cont r ol
This command is used t o set generic manageabilit y paramet ers. The paramet ers are list ed in t he
following t able. The command is 0xC1, which st at es t hat it is a management cont rol command. The
first dat a byt e is t he paramet er number and t he dat a aft erwards ( lengt h and cont ent ) are paramet er
specific as list ed in t he t able.
Funct i on Command Byt e Count Dat a 1
Force TCO reset 0xCF 1 TCO mode
DO_TCO_RST 0
Do TCO reset .
0b = Do not hing.
1b = Perform TCO reset .
Reserved 1 Reserved, set t o 0b.
Firmware Reset
1
1. Before init iat ing a Firmware Reset command, disable TCO receive via t he Receive Enable command, set
RCV_EN t o 0b, and t hen wait for 200 milliseconds before init iat ing t he Firmware Reset command. I n
addit ion, t he BMC should not t ransmit during t his period.
2
Reset manageabilit y and reload manageabilit y relat ed EEPROM
words
0b = Do not hing.
1b = I ssue firmware reset t o manageabilit y.
Not e: Set t ing t his bit generat es a one t ime firmware reset event .
Following a firmware reset , management relat ed dat a from t he
EEPROM is loaded.
Reserved 7: 3 Reserved, ( Set t o 0x00) .

717
Not e: I f in t he updat e configurat ion, t he paramet er t hat t he BMC set s is not support ed by t he
82599, t he 82599 does not NACK t he t ransact ion. Aft er t he t ransact ion ends, t he 82599
discards t he dat a and assert s a t ransact ion abort st at us ( see Sect ion 3. 2. 5.2) .
Following is t he format of t he Management Cont rol command:
This t able list s t he different paramet ers and t heir cont ent :
10.5.2.1.6 Updat e MNG RCV Fi l t er Par amet er s
This command is used t o set t he manageabilit y receive filt ers paramet ers. The paramet ers are list ed in
t he following t able. The command is 0xCC, which st at es t hat it is a paramet er updat e. The first dat a
byt e is t he paramet er number and t he dat a aft erwards ( lengt h and cont ent ) are paramet er specific as
list ed in t he t able.
Not e: I f in t he updat e configurat ion, t he paramet er t hat t he BMC set s is not support ed by t he
82599, t he 82599 does not NACK t he t ransact ion. Aft er t he t ransact ion ends, t he 82599
discards t he dat a and assert s a t ransact ion abort st at us ( see Sect ion 3. 2. 5.2) .
Det ailed descript ion of receive filt ering capabilit ies and configurat ion is described in Sect ion 10. 3.
The format of t he updat e MNG RCV filt er paramet ers is list ed in t he following t able:
The following t able list s t he different paramet ers and t heir cont ent s:
Funct i on Command By t e Count Dat a 1 Dat a 2 Dat a N
Management Cont rol 0xC1 N
Paramet er
Number ( PN# )
Paramet er Dependent
Par amet er PN# Par amet er Dat a
Keep PHY Link Up 0x00
A single byt e paramet er Dat a 2:
Bit 0 Programming of t he MMNGC. MNG_VETO bit .
Bit [ 7: 1] Reserved.
Updat e MNG RCV Filt er
Paramet ers
0xCC N
Paramet er
Number ( PN# )
Filt ers Enable 0x1
Defines generic filt ers configurat ion. The st ruct ure of t his paramet er is 4 byt es as t he MANC Value LSB
and MANC Value MSB loaded from t he EEPROM.
Not e t he general filt er enable is in t he Receive Enable command, which enable receive filt ering. This
paramet er specifies which filt ers should be enabled. ARP filt ering and dedicat ed Et hernet MAC address
can also be enabled t hrough t he Receive Enable command ( see Sect ion 10. 5. 2. 1. 3) .
MNG2HOST
configurat ion
0xA
This paramet er defines which manageabilit y packet s are direct ed t o t he host memory as well.
Dat a 2: 5: MNG2H regist er set t ing ( Dat a 2 is t he MSB) .
Fail- Over
configurat ion
0xB
Fail- Over St ruct ure Configurat ion ( see Sect ion 10. 2. 2. 2. 4) . The byt es of t his paramet er are loaded t o t he
failover configurat ion regist er.
Dat a 2: 5 Fail- over configurat ion regist er ( Dat a 2 is t he MSB) .
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718
Flex Filt er 0
Enable MASK
and Lengt h
0x10
Flex Filt er 0 Mask.
Dat a 2: 17 MASK. Bit 0 in dat a 2 is t he first bit of t he MASK
Dat a 18: 19 Reserved. Should be zero.
Dat a 20 Flexible Filt er lengt h ( must be > = 2) .
Flex Filt er 0
Dat a
0x11
Dat a 2 Group of flex filt er s byt es:
- 0x0 = byt es 0- 29.
- 0x1 = byt es 30- 59.
- 0x2 = byt es 60- 89.
- 0x3 = byt es 90- 119.
- 0x4 = byt es 120- 127.
Dat a 3: 32 Flex filt er dat a byt es. Dat a 3 is LSB.
Groups lengt h is not mandat ory 30 byt es; it can vary according t o filt er s lengt h and must NOT be padded
by zeros.
Flex Filt er 1
Enable MASK
and Lengt h
0x20 Same as paramet er 0x10 but for filt er 1.
Flex Filt er 1
Dat a
0x21 Same as paramet er 0x11 but for filt er 1
Flex Filt er 2
Enable MASK
and Lengt h
Flex Filt er 2
Dat a
Flex Filt er 3
Enable MASK
and Lengt h
Flex Filt er 3
Dat a
Filt ers Valid 0x60
4 byt es t o det ermine which of t he t he 82599 filt er regist ers cont ain valid dat a. Loaded int o t he MFVAL0
and MFVAL1 regist ers. Should be updat ed aft er t he cont ent s of a filt er regist er are updat ed.
Dat a 2 MSB of MFVAL . . . Dat a 5 is t he LSB
Decision Filt ers 0x61
5 byt es t o load t he Manageabilit y Decision Filt ers ( MDEF) .
Dat a 2 Decision filt er number.
Dat a 3 MSB of MDEF regist er for t his decision filt er . . . Dat a 6 is t he LSB.
VLAN Filt ers 0x62
3 byt es t o load t he VLAN t ag filt ers ( MAVTV) .
Dat a 2 VLAN filt er number.
Dat a 3 MSB of VLAN filt er.
Dat a 4 LSB of VLAN filt er.
Flex Port s
Filt ers
0x63
3 byt es t o load t he manageabilit y flex port filt ers ( MFUTP) .
Dat a 2 Flex port filt er number.
Dat a 3 MSB of flex port filt er.
Dat a 4 LSB of flex port filt er.
I Pv4 Filt ers 0x64
5 byt es t o load t he I Pv4 address filt er ( MI PAF, DW 15: 12) .
Dat a 2 I Pv4 address filt er number ( 0- 3) .
Dat a 3 MSB of I Pv4 address filt er Dat a 6 is t he LSB.
I Pv6 Filt ers 0x65 17 byt es t o load I Pv6 address filt er ( MI PAF) .
Dat a 2 I Pv6 address filt er number ( 0- 3) .
Dat a 3 MSB of I Pv6 address filt er Dat a 18 is t he LSB.

719
10.5.2.1.7 Updat e Li nk Sec Par amet er s
This command is used t o set t he manageabilit y LinkSec paramet ers. The paramet ers are list ed in t he
following t able. The first dat a byt e is t he paramet er number and t he dat a aft erwards ( lengt h and
cont ent ) are paramet er specific as list ed in t he t able.
This is t he format of t he Updat e LinkSec paramet ers command:
MAC Filt ers 0x66
7 byt es t o load Et hernet MAC address filt ers ( MMAL, MMAH) .
Dat a 2 Et hernet MAC address filt ers pair number ( 0- 3) .
Dat a 3 MSB of Et hernet MAC address Dat a 8 is t he LSB.
Et hert ype
Filt ers
0x67
6 byt es t o load Et hert ype filt ers ( MTQF) .
Dat a 2 METF filt er index ( valid values are 0. . 3) .
Dat a 3 MSB of METF . . . Dat a 6 is t he LSB.
Ext ended
Decision Filt er
0x68
10 byt es t o load t he ext ended decision filt ers ( MDEF_EXT & MDEF) .
Dat a 2 MDEF filt er index ( valid values are 0. . 6) .
Dat a 3 MSB of MDEF_EXT ( DecisionFilt er1) . . . Dat a 6 is t he LSB.
Dat a 7 MSB of MDEF ( DecisionFilt er0) . . . Dat a 10 is t he LSB.
The command must overwrit e any previously st ored value.
Not e: Previous Decision Filt er command ( 0x61) is st ill support ed. For legacy reasons I f previous
Decision Filt er command ( 0x61) is called it should set t he MDEF as provided and set t he ext ended
Decision Filt er ( MDEF_EXT) t o 0x0.
Updat e LinkSec Filt er
Paramet ers
0xC9 N
Paramet er
Number ( PN# )
Transfer LinkSec
ownership t o BMC
0x10
Dat a 2: Host Cont rol:
Bit 0 = Reserved.
Bit 1 = Allow host t raffic ( 0b blocked, 1b allowed) .
Bit 2. . . 31 = Reserved.
Transfer LinkSec
ownership t o Host
0x11 No dat a needed.
I nit ialize LinkSec
Rx
0x12
Dat a 2: Rx Port I dent ifier ( MSB) . . . Dat a 3: ( LSB) .
Rx Port I dent ifier t he port number by which t he 82599 ident ifies Rx packet s. I t is recommended
t hat t he BMC use 0x0 as t he port ident ifier.
Not e: The BMC should use t he same por t ident ifier when perfor ming t he key- exchange.
Dat a 4 : Rx MAC SecY ( MSB) Dat a 9: ( LSB) .
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720
I nit ialize LinkSec
Tx
0x13
Dat a 2: Tx Port I dent ifier ( MSB) . . . Dat a 3: ( LSB) must be set t o zero.
Dat a 4: Tx SCI ( MSB) Dat a 7: Tx SCI ( LSB) .
Tx SCI A 6- byt e unique ident ifier for t he LinkSec Tx CA. I t is recommended t hat t he BMC use it s
Dat a 8: Reserved.
Dat a 9: Reserved.
Dat a 10: Packet Number Threshold ( MSB) Dat a 12: ( LSB) .
PN Threshold When a new key is programmed, t he packet number is reset t o 0x1. Wit h each Tx
packet , The packet number is increment ed by one and insert ed t o t he packet ( t o avoid replay
at t acks) . The packet number t hreshold value is 3 MSByt es of t he Tx Packet number aft er which a
Key Exchange Required AEN is sent t o t he BMC. Example: a PN t hreshold of 0x123456 means t hat
when t he packet number reaches 0x12345600 a not ificat ion is sent .
Dat a 22: Tx Cont rol See Table 10. 21.
Set LinkSec Rx
Key
0x14
Dat a 2: Reserved.
Dat a 3: Rx SA AN ( The associat ion number t o be used wit h t his key) .
Dat a 4: Rx LinkSec Key ( MSB) Dat a 19: ( LSB) ( 16 byt es key t o be used) .
Set LinkSec Tx
Key
0x15
Dat a 3: Tx SA AN ( The associat ion number t o be used wit h t his key) .
Dat a 4: Tx LinkSec Key ( MSB) Dat a 19: ( LSB) ( 16 byt es key t o be used) .
Enable LinkSec
Net work Tx
encrypt ion
Disable LinkSec
Net work Tx
encrypt ion

721
10. 5. 2. 2 Read SMBus Tr ansact i ons ( t he 82599 t o BMC)
The following t able list s t he different SMBus read t ransact ions support ed by t he 82599. All t he read
t ransact ions are compat ible wit h SMBus Read Block Prot ocol format .
Not e: The 82599 responds t o one of t he commands 0xC0/ 0xD0 wit hin t he t ime defined in t he
SMBus not ificat ion t imeout and flags word in t he EEPROM ( see Sect ion 6.4. 4. 3. )
Not e: 0xC0/ 0xD0 commands are used for more t han one payload. I f t he BMC issues t hese read
commands, and t he 82599 has no pending dat a t o t ransfer, it always ret urns as default
opcode 0xDD wit h t he 82599 st at us, and does not NACK t he t ransact ion.
Not e: I f an SMBus Quick Read command is received, it is handled as a Read t he 82599 St at us
command ( See Sect ion 10. 5. 2. 2.3 for det ails) .
10.5.2.2.1 Recei ve TCO LAN Pack et Tr ansact i on
The BMC uses t his command t o read t he packet received on t he LAN and it s st at us. When t he 82599
has a packet t o deliver t o t he BMC, it assert s t he SMBus not ificat ion, for t he BMC t o read t he dat a ( or
direct receive) . Upon receiving not ificat ion of t he arrival of LAN receive packet , t he BMC should begin
issuing a Receive TCO packet command using t he block read prot ocol. The packet can be delivered in
more t han one SMBus fragment ( at least t wo one for t he packet , and t he ot her one for t he st at us) ,
and t he BMC should follow t he F and L bit .
Tabl e 10.21. Tx Cont r ol
0. . 4 Reserved
5
Always I nclude SCI in Tx:
6. . 7 Reserved
TCO Command Tr ansact i on Command Op- Code Fr agment at i on Sect i on
Receive TCO Packet Block Read 0xC0 or 0xD0
First :
Middle:
Last
1
1. Last fragment of t he receive TCO packet is t he packet st at us.
0x90
0x10
0x50
Mult iple 10. 5. 2. 2. 1
Read Receive Enable
configurat ion
Block Read 0xDA Single: 0xDA Single 10. 5. 2. 2. 7
Read t he 82599 St at us Block Read
0xC0 or 0xD0 or
0xDE
Single: 0xDD Single 10. 5. 2. 2. 3
Read Management
paramet ers
Block Read 0xD1 Single: 0xD1 Single 10. 5. 2. 2. 5
Read MNG RCV filt er
paramet ers
Block Read 0xCD Single: 0xCD Single 10. 5. 2. 2. 6
Get syst em Et hernet
MAC Address
Block Read 0xD4 Single 0xD4 Single 10. 5. 2. 2. 4
Read LinkSec
paramet ers
Block Read 0xD9 Single 0xD9 Single 10. 5. 2. 2. 8
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722
The opcode can have t hese values:
0x90 First fragment .
0x10 Middle fragment .
0x50 Packet st at us ( last fragment ) as described in Sect ion 10.5.2. 2. 2.
I f t he ext ernal BMC does not finish reading t he ent ire packet wit hin a t imeout period since t he packet
has arrived, t he packet is silent ly discarded. The t imeout period is set according t o t he SMBus
not ificat ion t imeout EEPROM paramet er ( see Sect ion 6.4.4. 3)
Dat a ret urned from t he 82599:
10.5.2.2.2 Recei ve TCO LAN St at us Payl oad Tr ansact i on
This t ransact ion is t he last t ransact ion t hat t he 82599 issues when a packet t hat was received from t he
LAN is t ransferred t o t he BMC. The t ransact ion cont ains t he st at us of t he received packet . The format of
t he st at us t ransact ion is as follows:
Funct i on Command
Receive TCO packet 0xC0 or 0xD0
Funct i on By t e Count
Dat a 1 ( Op-
Code)
Dat a 2 Dat a N
Receive TCO First Fragment
N
90
Packet Dat a
Byt e
Packet Dat a Byt e Receive TCO Middle Fragment 10
Receive TCO Last Fragment 50
Dat a 1 ( Op-
Code)
Dat a 2 Dat a 17 ( St at us dat a)
Receive TCO Long
St at us
17 ( 0x11) 0x50
See Table 10. 22. For more det ails on t he specific bit fields see
Sect ion 7. 1. 6.
Tabl e 10.22. Recei ve TCO Last Fr agment St at us Dat a Cont ent
Name Bi t ( s) Descr i pt i on
Packet Lengt h 13: 0 Packet lengt h including CRC, only 14 LSB bit s.
CRC 25 CRC st ripped indicat ion.
VEXT 29 Addit ional VLAN present in packet .
Reserved 34 Reserved
LAN 35 LAN number.

723
Name Bi t ( s) Descr i pt i on
St at us 79: 72 See Table 10. 23.
MNG st at us 127: 88 See Table 10. 24. This field should be ignored if Receive TCO is not enabled.
Tabl e 10.23. St at us I nf o
Reser ved 7: 4 Reserved
I PCS 3 I Pv4 Checksum Calculat ed on Packet .
L4CS 2 L4 Checksum Calculat ed on Packet .
UDPCS 1 UDP Checksum Calculat ed on Packet .
Reserved 0 Reserved
Tabl e 10.24. MNG St at us
Name Bi t s Descr i pt i on
Pass RMCP 0x026F 0 Set when t he UDP/ TCP port of t he MNG packet is 0x26F.
Pass RMCP 0x0298 1 Set when t he UDP/ TCP port of t he MNG packet is 0x298.
Pass MNG Broadcast 2 Set when t he MNG packet is a broadcast packet .
Pass MNG Neighbor 3 Set when t he MNG packet is a neighbor discovery packet .
Pass ARP req / ARP Response 4 Set when t he MNG packet is an ARP response/ request packet .
Pass MNG VLAN Filt er I ndex 10: 8
MNG VLAN Address Mat ch 11 Set when t he MNG packet mat ches one of t he MNG VLAN filt ers.
Unicast Address I ndex 14: 12
I ndicat es which of t he 4 unicast Et hernet MAC addresses mat ch t he
packet . Valid only if t he unicast address mat ch is set .
Unicast Address Mat ch 15
Set when t here is a mat ch t o any of t he 4 unicast Et hernet MAC
addresses.
L4 port Filt er I ndex 22: 16 I ndicat e t he flex filt er number.
L4 port Mat ch 23 Set when t here is a mat ch t o any of t he UDP / TCP port filt ers.
Flex TCO Filt er I ndex 26: 24
Flex TCO Filt er Mat ch 27
I P address I ndex 29: 28 Set when t here is a mat ch t o t he I P filt er number. ( I Pv4 or I Pv6) .
I P address Mat ch 30 Set when t here is a mat ch t o any of t he I P address filt ers.
I Pv4 Packet 31 Set t o 0b when packet is I Pv4 ( regardless of address mat ch) .
Decision Filt er Mat ch 39: 32 Set when t here is a mat ch t o one of t he decision filt ers.
Tabl e 10.22. Recei ve TCO Last Fr agment St at us Dat a Cont ent
I nt el

724
10.5.2.2.3 Read St at us Command
The BMC can read t he 82599 st at us. The 82599 assert s an alert prior t o t he BMC reading t he st at us
byt es. There can be t wo reasons for t he 82599 t o send st at us t o t he BMC ( described in Sect ion 3.2. 3) :
1. The ext ernal BMC assert s a request for reading t he 82599 st at us.
2. The 82599 det ect s a st at us change as described in Sect ion 3.2. 3.
Not e t hat commands 0xC0/ 0xD0 are for backward compat ibilit y. 0xD0/ 0xC0 can be used for ot her
payloads t he 82599 defines in t he opcode, which payload t his t ransact ion is. When 0xDE command is
set , t he 82599 always ret urns opcode 0sDD wit h t he 82599 st at us. The BMC reads t he event causing
t he not ificat ion, using t he Read St at us command as follows:
The following t able list s t he st at us dat a byt e 1:
St at us dat a byt e 2 is used for t he BMC for an indicat ion whet her t he LAN driver is alive and running.
Funct i on Command
Read St at us
0xC0 or 0xD0 or
0xDE
Dat a 1 ( Op-
Code)
Dat a 2
( St at us dat a 1)
Dat a 3
( St at us dat a 2)
Receive TCO Part ial St at us 3 0xDD See t he following t able
Bi t Name Descr i pt i on
7 LAN Port
0b = Alert came from LAN port 0.
1b = Alert came from LAN port 1
6 TCO Command Abort ed
0b = A TCO command abort event has not occurred since t he last read st at us cycle.
1b = A TCO command abort event has occurred since t he last read st at us cycle.
See Sect ion 3. 2. 5. 2 for command abort flow.
5 Link St at us I ndicat ion
1
1. When t he 82599 is working in t eaming mode, and present ed as one SMBus device, t he link indicat ion is 0b only when bot h links
( on bot h port s) are down. I f one of t he LANs is disabled, it s link is considered t o be down.
0b = LAN link down.
1b = LAN link is up.
4 PHY Link Forced Up Cont ains t he value of t he MMNGC. MNG_VETO bit .
3 I nit ializat ion I ndicat ion
2
2. This indicat ion is assert ed when t he 82599 manageabilit y block reloads t he EEPROM and it s int ernal dat abase is updat ed t o
EEPROM default values. This is an indicat ion t hat t he ext ernal BMC should reconfigure t he 82599, if ot her values besides t he
EEPROM default should be configured.
0b = An EEPROM reload event has not occurred since t he last read st at us cycle.
1b = An EEPROM reload event has occurred since t he last read st at us cycle.
2 Reserved Reserved as 0b.
1: 0 Power St at e
3
3. I n single address mode, t he 82599 report s t he highest powerst at e modes in bot h devices. The D st at e is marked in t his order:
D0, D0u, Dr, and D3.
00b = Dr st at e.
01b = D0u st at e.
10b = D0 st at e.
11b = D3 st at e.

725
The driver valid indicat ion is a bit t hat is set by t he driver when it is coming up, and cleared when it
goes down t o Dx st at e or cleared by t he hardware on PCI reset .
Bit s 2 and 1 indicat e t hat t he LAN driver is not st uck. Bit 2 indicat es whet her t he int errupt line of t he
LAN funct ion is assert ed, and bit 1 indicat es whet her t he driver bet ween t he last read st at us cycle dealt
t he int errupt line.
The following t able list s st at us dat a byt e 2:
Not e: When t he 82599 is in t eaming mode, t hese bit s represent bot h cores:
The driver alive indicat ion is set if 1b of t he driver is alive.
The LAN int errupt is considered t o be assert ed if one of t he int errupt lines is assert ed.
The I CR is considered t o read if one of t he I CRs was read ( LAN0 or LAN1) .
The following t able list s t he possible values of bit s 2, 1 and what t he BMC can assume according t o
t hat :
Not e: The BMC reads should consider t he t ime it t akes for t he driver t o deal wit h t he int errupt ( a
few microseconds) , t oo frequent reads give false indicat ions.
Bi t Name Descr i pt i on
7 Reserved Reserved
6 Reserved Reserved
5 Reserved Reserved
4 LinkSec I ndicat ion
I f set , indicat es t hat a LinkSec event has occurred. Use t he read LinkSec paramet ers
wit h t he LinkSec int errupt cause paramet er t o read t he int errupt cause
3 Driver Valid I ndicat ion
0b = LAN driver is not alive.
1b = LAN driver is alive.
2 I nt errupt Pending I ndicat ion
0b = LAN int errupt is not assert ed.
1b = LAN int errupt is assert ed.
1 I CR Regist er Read/ Writ e
0b = I CR regist er was not read since t he last read st at us cycle.
1b = I CR regist er was read since t he last read st at us cycle.
Reading t he I CR means t hat t he driver has dealt wit h t he int errupt t hat was assert ed.
0 Reserved Reserved
Pr evi ous Cur r ent
Don t care 00b I nt errupt is not pending OK.
00b 01b New int errupt is assert ed OK.
10b 01b New int errupt is assert ed OK.
11b 01b I nt errupt is wait ing for reading OK.
01b 01b
I nt errupt is wait ing for reading by t he driver more t han one read st at us cycle Not OK ( possible
driver hang st at e) .
Don t Care 11b Previous int errupt was read and current int errupt is pending OK.
Don t Care 10b I nt errupt is not pending OK.
I nt el

726
10.5.2.2.4 Get Syst em Et her net MAC Addr ess
The Get Syst em Et hernet MAC Address ret urns t he syst em Et hernet MAC Address ( RAL0, RAH0) over
t he SMBus. This command is a single fragment Read Block t ransact ion, wit h t he following format :
10.5.2.2.5 Read Management Par amet er s
I n order t o read t he management paramet ers t he BMC should execut e t wo SMBus t ransact ions. The
first t ransact ion is a block writ e t hat set s t he paramet er t hat t he BMC want s t o read. The second
t ransact ion is block read t hat reads t he paramet er.
This is t he block writ e t ransact ion:
Following t he block writ e t he BMC should issue a block read t hat reads t he paramet er t hat was set in
t he Block Writ e command:
Funct i on Command
MAC Address
0xD4
Dat a 1 ( Op-
Code)
Dat a 2 Dat a 7
MAC Address
7 0xD4
Et her net MAC Address
MSB
Et hernet MAC
Address LSB
Funct i on Command By t e Count Dat a 1
Management Cont rol Request 0xC1 1 Paramet er Number
Funct i on Command
Read Management Paramet er 0xD1
Dat a 1 ( Op-
Code)
Dat a 2 Dat a 3 Dat a N
Read Management Paramet er N 0xD1
Paramet er Number
( PN# )

727
The ret urned dat a is as follows:
Not e: I t might be t hat t he paramet er t hat is ret urned is not t he paramet er request ed by t he BMC.
The BMC should verify t he paramet er number ( default paramet er t o be ret urned is 0x1) .
Not e: I t is BMCs responsibilit y t o follow t he procedure Previously defined. I f t he BMC sends a Block
Read command ( as previously described) t hat is not preceded by a Block Writ e command
wit h byt ecount = 1b, t he 82599 set s t he paramet er number in t he read block t ransact ion t o be
0xFE.
10.5.2.2.6 Read MNG RCV Fi l t er Par amet er s
I n order t o read t he MNG RCV filt er paramet ers, t he BMC should execut e t wo SMBus t ransact ions. The
Keep PHY Link Up 0x00
A single byt e paramet er Dat a 2:
Bit 0 Reflect s t he set t ing of t he MMNGC. MNG_VETO bit .
Bit [ 7: 1] Reserved.
Wrong Paramet er
Request
0xFE
t he 82599 only: This paramet er is ret urned on a read t ransact ion, if in t he previous Read
command t he BMC set s a paramet er t hat is not support ed by t he 82599.
t he 82599 Not
Ready
0xFF
t he 82599 only: Ret urned on Read Paramet ers command when t he dat a t hat should have been
read is not ready. The BMC should ret ry t he read t ransact ion.
Funct i on Command By t e Count Dat a 1 Dat a 2
Updat e MNG RCV Filt er Paramet ers 0xCC 1 or 2
Paramet er Number
( PN# )
Paramet er Dat a
Filt ers Enable 0x1 None.
MNG2HOST Configurat ion 0xA None.
Fail- Over Configurat ion 0xB None.
Flex Filt er 0 Enable Mask and
Lengt h
0x10 None.
Flex Filt er 0 Dat a 0x11
Dat a 2 Group of Flex filt er s byt es:
0x0 = byt es 0- 29.
0x1 = byt es 30- 59.
0x2 = byt es 60- 89.
0x3 = byt es 90- 119.
0x4 = byt es 120- 127.
Lengt h
0x20 None.
Flex Filt er 1 Dat a 0x21 Same as paramet er 0x11 but for filt er 1.
Lengt h
0x30 None.
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728
Following t he block writ e t he BMC should issue a block read t hat readS t he paramet er t hat was set in
Flex Filt er 2 Dat a 0x31 Same as paramet er 0x11 but for filt er 2.
Lengt h
0x40 None.
Flex Filt er 3 Dat a9 0x41 Same as paramet er 0x11 but for filt er 3.
Filt ers Valid 0x60 None.
Decision Filt ers 0x61
1 byt e t o define t he accessed manageabilit y decision filt er ( MDEF) .
Dat a 2 Decision filt er number.
VLAN Filt ers 0x62
1 byt e t o define t he accessed VLAN t ag filt er ( MAVTV) .
Dat a 2 VLAN filt er number.
Flex Port s Filt ers 0x63
1 byt e t o define t he accessed manageabilit y flex port filt er ( MFUTP) .
Dat a 2 Flex port filt er number.
I Pv4 Filt er 0x64
1 byt e t o define t he accessed I Pv4 address filt er ( MI PAF) .
Dat a 2 I Pv4 address filt er number.
I Pv6 Filt ers 0x65
1 byt e t o define t he accessed I Pv6 address filt er ( MI PAF) .
Dat a 2 I Pv6 address filt er number.
MAC Filt ers 0x66
1 byt e t o define t he accessed Et hernet MAC address filt ers pair ( MMAL, MMAH) .
Dat a 2 Et hernet MAC address filt ers pair number ( 0- 3) .
Wrong Paramet er Request 0xFE
Ret urned by t he 82599 only. This paramet er is ret urned on read t ransact ion, if in t he
previous Read command t he BMC set s a paramet er t hat is not support ed by t he
82599.
t he 82599 Not Ready 0xFF
Ret urned by t he 82599 only, on Read Paramet ers command when t he dat a t hat
should have been read is not ready. This paramet er has no dat a.
Funct i on Command
Request MNG RCV Filt er
Paramet ers
0xCD

729
The ret urned dat a is in t he same format of t he Updat e command.
Not e: I f t he paramet er t hat is ret urned is not t he paramet er request ed by t he BMC, t he BMC should
verify t he paramet er number ( default paramet er t o be ret urned is 0x1) .
Not e: I f t he paramet er number is 0xFF, it means t hat t he dat a t hat t he 82599 should supply is not
ready yet . The BMC should ret ry t he read t ransact ion.
Not e: I t is BMCs responsibilit y t o follow t he procedure previously defined. I f t he BMC sends a Block
Read command ( as previously described) t hat is not preceded by a Block Writ e command
wit h byt ecount = 1b, t he 82599 set s t he paramet er number in t he read block t ransact ion t o be
0xFE.
10.5.2.2.7 Read Recei ve Enabl e Conf i gur at i on
The BMC uses t his command t o read t he receive configurat ion dat a. This dat a can be configured in t he
Receive Enable command or t hrough EEPROM loading at power up.
Read Receive Enable Configurat ion command format ( SMBus Read Block Prot ocol) :
The det ailed descript ion of each field is specified in t he Receive Enable command descript ion in
Sect ion 10. 5.2.1. 3.
10.5.2.2.8 Read Li nk Sec Par amet er s
I n order t o read t he MNG LinkSec paramet ers, t he BMC should execut e t wo SMBUS t ransact ions. The
Funct i on Byt e Count
Dat a 1 ( Op-
Code)
Dat a 2 Dat a 3 Dat a N
Read MNG RCV Filt er
Paramet ers
N 0xCD
Paramet er Number
( PN# )
Funct i on Command
Read Receive Enable 0xDA
Funct i on
By t e
Count
Dat a
1
( Op-
Code)
Dat a
2
Dat a
3
Dat a
8
Dat a
9
Dat a
12
Dat a
13
Dat a
14
Dat a
15
Read
Receive
Enable
15
( 0x0F)
0xDA
Receiv
e
Cont r ol
Byt e
Et hern
et MAC
Addres
s MSB
Et hern
et MAC
Addres
s LSB
I P
Addres
s MSB
I P
Address
LSB
BMC
SMBus
Address
I nt erfac
e Dat a
Byt e
Aler t
Value
Byt e
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730
Following t he block writ e t he BMC should issue a block read t hat reads t he paramet er t hat was set in
Funct i on Command Byt e Count Dat a 1 Dat a 2
Updat e MNG RCV Filt er Paramet ers 0xC9 1
Paramet er Number
( PN# )
Paramet er Dat a
LinkSec I nt errupt Cause 0x0 None.
LinkSec Rx Paramet ers 0x1 None.
LinkSec Tx Paramet ers 0x2 None.
Funct i on Command Byt e Count Dat a 1 Dat a 2 n
Read LinkSec Paramet ers 0xD9 2, 18 or 22
Paramet er Number
( PN# )
Paramet er Dat a

731
LinkSec I nt errupt Cause 0x0
This command must ret urn 1 byt e ( Dat a2) . This byt e cont ains t he LinkSec int errupt
cause, according t o t he following values:
Dat a2:
Bit 0 Tx key packet number t hreshold met .
Bit 1 Host request ed ownership.
Bit 2 Host released ownership.
Bit 3. . . 31 Reserved.
LinkSec Rx Paramet ers 0x1
Dat a 2: Reserved.
Dat a 3: LinkSec ownership st at us. See Table 10. 25.
Dat a 4: LinkSec host cont rol st at us. See Table 10. 26.
Dat a 5: Rx host ident ifier ( MSB) .
Dat a 6: Rx host ident ifier ( LSB) .
Dat a 7 : Rx SCI ( MSB) Dat a 12: ( LSB) .
Dat a 13: Reserved.
Dat a 14: Rx SA AN The associat ion number current ly used for t he act ive SA.
Dat a 15: Rx SA packet number ( MSB) Dat a 18: ( LSB) .
Rx SA packet number is t he last packet number, as read from t he last valid Rx LinkSec
packet .
LinkSec Tx Paramet ers 0x2
Dat a 2: Reserved
Dat a 3: LinkSec ownership st at us. See Table 10. 25.
Dat a 4: LinkSec host cont rol st at us. See Table 10. 26.
Dat a 5: Tx port ident ifier ( MSB) .
Dat a 6: Tx port ident ifier ( LSB) .
Not e: Tx port ident ifier is reserved t o 0x0 for t his implement at ion.
Dat a 7 : Tx SCI ( MSB) Dat a 12: ( LSB) .
Dat a 13: Reserved.
Dat a 14: Tx SA AN The associat ion number current ly used for t he act ive SA.
Dat a 15: Tx SA packet number ( MSB) Dat a 18: ( LSB) .
Dat a 19: packet number t hreshold ( MSB) Dat a 21: ( LSB) .
Tx SA packet number is t he last packet number, as read from t he last valid Tx LinkSec
packet .
Dat a 22: Tx Cont rol St at us. See Table 10. 27.
Tabl e 10. 26. Li nk Sec Host Cont r ol St at us
0 Reserved.
1
Allow host t raffic:
0b = Host t raffic is blocked.
2. . 7 Reserved.
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732
10. 5. 2. 3 SMBus ARP Tr ansact i ons
Not e: All SMBus-ARP t ransact ions include PEC byt e.
10.5.2.3.1 Pr epar e t o ARP
This command clears t he Address Resolved flag ( set t o false) . I t does not affect t he st at us or validit y of
t he dynamic SMBus address. I t is used t o signal all devices t hat t he ARP mast er is st art ing t he ARP
process:
10.5.2.3.2 Reset Dev i ce ( Gener al )
This command clears t he Address Resolved flag ( set t o false) . I t does not affect t he st at us or validit y of
t he dynamic SMBus address.
10.5.2.3.3 Reset Devi ce ( Di r ect ed)
The Command field is NACK- ed if t he bit s 7 t hrough 1 do not mat ch t he current t he 82599 SMBus
address.
I t clears t he Address Resolved flag ( set t o false) . I t does not affect t he st at us or validit y of t he dynamic
SMBus address.
Tabl e 10.27. Tx Cont r ol St at us
0..4 Reserved.
5
I nclude SCI :
6..7 Reserved
1 7 1 1 8 1 8 1 1
S Slave Address Wr A Command A PEC A P
1100 001 0 0 0000 0001 0 [ Dat a dependent value] 0
1 7 1 1 8 1 8 1 1
1100 001 0 0 0000 0010 0 [ Dat a dependent value] 0
1 7 1 1 8 1 8 1 1
1100 001 0 0 Target ed slave address | 0 0 [ Dat a dependent value] 0

733
10.5.2.3.4 Assi gn Addr ess
This command assigns t he 82599s SMBus address. The address and command byt es are always
acknowledged.
The t ransact ion is abort ed immediat ely ( NACK- ed- ) if any of t he UDI D byt es differ from t he 82599
UDI D byt es. I f successful, t he manageabilit y int erface updat es t he SMBus address int ernally. This
command also set s t he Address Resolved flag t o t rue.
1 7 1 1 8 1 8 1
Slave
Address
Wr A Command A
Byt e
Count
A - - -
1100 001 0 0
0000
0100
0
0001
0001
0
8 1 8 1 8 1 8 1
Dat a- 1 A Dat a- 2 A Dat a- 3 A Dat a- 4 A - - -
UDI D byt e 15
( MSB)
0 UDI D byt e 14 0 UDI D byt e 13 0 UDI D byt e 12 0
8 1 8 1 8 1 8 1
UDI D byt e 11 0 UDI D byt e 10 0 UDI D byt e 9 0 UDI D byt e 8 0
8 1 8 1 8 1
Dat a- 9 A Dat a- 10 A Dat a- 11 A - - -
UDI D byt e 7 0 UDI D byt e 6 0 UDI D byt e 5 0
8 1 8 1 8 1 8 1
8 1 8 1 8 1 1
Dat a- 16 A Dat a- 17 A PEC A P
UDI D byt e 0 ( LSB) 0 Assigned Address 0
[ Dat a dependent
value]
0
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734
10.5.2.3.5 Get UDI D ( Gener al and Di r ect ed)
The Get UDI D command depends on whet her t his is a direct ed or general command.
The General Get UDI D SMBus t ransact ion support s a const ant command value of 0x03.
The Direct ed Get UDI D SMBus t ransact ion support s a dynamic command value equal t o t he dynamic
SMBus address wit h t he LSB bit set .
Not e: Bit 0 ( LSB) of Dat a byt e 17 will always be 1b.
I f t he SMBus address has been resolved ( Address Resolved flag is t rue) ; for a general command t he
manageabilit y int erface does not acknowledge ( NACK) t his t ransact ion, for a direct ed command t he
manageabilit y always acknowledges ( ACK) t his t ransact ion.
This command does not affect t he st at us or validit y of t he dynamic SMBus address nor of t he Address
Resolved flag.
The command ret urns t he UDI D byt es as defined in Sect ion 3. 2. 7.
S Slave Address Wr A Command A S - - -
1100 001 0 0 See below 0
7 1 1 8 1
Slave Address Rd A Byt e Count A - - -
1100 001 1 0 0001 0001 0
8 1 8 1 8 1 8 1
UDI D byt e 15 ( MSB) 0 UDI D byt e 14 0 UDI D byt e 13 0 UDI D byt e 12 0
8 1 8 1 8 1 8 1
8 1 8 1 8 1
Dat a- 9 A Dat a- 10 A Dat a- 11 A - - -
UDI D byt e 7 0 UDI D byt e 6 0 UDI D byt e 5 0

735
10. 5. 2. 4 Ex ampl e Conf i gur at i on St eps
This sect ion provides an overview and sample configurat ion set t ings for commonly used filt ering
configurat ions. Three examples are present ed.
The examples are in pseudo code format , wit h t he name of t he SMBus command, followed by t he
paramet ers for t hat command and an explanat ion. Here is a sample:
Receive Enable[00]
Using t he simple form of t he Receive Enable command, t his prevent s any packet s from reaching t he
BMC by disabling filt ering.
10.5.2.4.1 Ex ampl e 1 - Shar ed MAC, RMCP Onl y Por t s
This example is t he most basic configurat ion. The MAC address filt ering are shared wit h t he host
operat ing syst em and only t raffic direct ed t he RMCP port s ( 0x26F and 0x298) are filt ered. For t his
simple example, t he BMC must issue grat uit ous ARPs because no filt er is enabled t o pass ARP request s
t o t he BMC.
10.5.2.4.1. 1 Ex ampl e 1 Pseudo Code
St ep 1: - Disable exist ing filt ering:
Receive Enable[00]
BMC by disabling filt ering:
Receive Enable Cont rol 0x00:
Bit 0 [ 0] Disable receiving of packet s
St ep 2: - Configure MDEF[ 0] :
Update Manageability Filter Parameters [61, 0, 00000C00]
Use t he Updat e Manageabilit y Filt er Paramet ers command t o updat e Decision Filt ers ( MDEF)
( paramet er 0x61) . This updat es MDEF[ 0] , as indicat ed by t he 2
nd
paramet er ( 0) .
8 1 8 1 8 1 8 1
8 1 8 1 8 1 1
Dat a- 16 A Dat a- 17 A PEC ~ P
UDI D byt e 0 ( LSB) 0 Device Slave Address 0 [ Dat a dependent value] 1
I nt el

736
MDEF[ 0] value of 0x00000C00:
Bit 10 [ 1] port 0x298
Bit 11 [ 1] port 0x26F
St ep 3: - Enable filt ering:
Receive Enable [05]
Using t he simple form of t he Receive Enable command:
Bit 0 [ 1] Enable receiving of packet s
Bit 2 [ 1] Enable st at us report ing ( such as link lost )
Bit 5: 4 [ 00] Not ificat ion met hod = SMBus Alert
Bit 7 [ 0] Use shared MAC

737
Tabl e 10.28. Ex ampl e 1 MDEF Resul t s
10.5.2.4.2 Ex ampl e 2 - Dedi cat ed MAC, Aut o ARP Response and RMCP por t f i l t er i ng
This example shows a common configurat ion; t he BMC has a dedicat ed MAC and I P address. Aut omat ic
ARP responses are enabled as well as RMCP port filt ering. By enabling aut omat ic ARP responses t he
BMC is not required t o send t he grat uit ous ARPs as it did in Example 1. Since ARP request s are now
filt ered, in order for t he host t o receive t he ARP request s, t he manageabilit y- t o- host filt er is configured
t o send t he ARP request s t o t he host as well.
For demonst rat ion purposes, t he dedicat ed MAC address is calculat ed by reading t he syst em MAC
address and adding one do it , assume t he syst em MAC is AABBCCDC. The I P address for t his example
is 1. 2. 3.4.
Addit ionally, t he XSUM filt ering is enabled.
Not e t hat not all I nt el Et hernet cont rollers support aut omat ic ARP responses, please refer t o product
specific document at ion.
Manageabi l i t y Deci si on Fi l t er ( MDEF)
Fi l t er 0 1 2 3 4 5 6 7
L2 Unicast Address AND
Broadcast AND
Manageabilit y VLAN AND
I P Address AND
L2 Unicast Address OR
Broadcast OR
Mult icast AND
ARP Request OR
ARP Response OR
Neighbor Discovery OR
Port 0x298 OR x
Port 0x26F OR x
Flex Port 15: 0 OR
Flex TCO 3: 0 OR
I nt el

738
10.5.2.4.2.1 Ex ampl e 2 - Pseudo Code
Receive Enable[00]
St ep 2: - Read Syst em MAC Address
Get System MAC Address []
Reads t he Syst em MAC address. Assume ret urned AABBCCDC for t his example.
St ep 3: - Configure XSUM Filt er
Update Manageability Filter Parameters [01, 00800000]
Use t he Updat e Manageabilit y Filt er Paramet ers command t o updat e Filt ers Enable set t ings ( paramet er
1) . This set t he Manageabilit y Cont rol ( MANC) regist er.
MANC Regist er 0x00800000:
Bit 23 [ 1] XSUM Filt er enable
Not e: Not e t hat some of t he following configurat ion st eps manipulat e t he MANC regist er indirect ly,
t his command set s all bit s except XSUM t o zero. I t is import ant t o eit her do t his st ep before
t he ot hers, or t o read t he value of t he MANC and t hen writ e it back wit h only bit 32 changed.
Also not e t hat t he XSUM enable bit might differ bet ween Et hernet cont rollers, refer t o product
specific document at ion.
St ep 4: - Configure MDEF[ 0]
Update Manageability Filter Parameters [61, 0, 00000C00]
nd
paramet er ( 0) .
MDEF value of 0x00000C00:
Bit 10 [ 1] port 0x298
Bit 11 [ 1] port 0x26F
Update Manageability Filter Parameters [61, 1, 00000080]
( paramet er 61h) . This updat es MDEF[ 1] , as indicat ed by t he 2
nd
paramet er ( 1) .

739
MDEF value of 0x00000080:
Bit 7 [ 7] ARP request s
When enabling aut omat ic ARP responses, t he ARP request s st ill go int o t he manageabilit y filt ering
syst em and as such need t o be designat ed as also needing t o be sent t o t he host . For t his reason a
separat e MDEF is creat ed wit h only ARP request filt ering enabled.
Refer t o t he next st ep for more det ails.
St ep 6: - Configure t he Management t o Host Filt er
Update Manageability Filter Parameters [0A, 00000002]
Use t he Updat e Manageabilit y Filt er Paramet ers command t o updat e t he Management Cont rol- t o- Host
( MANC2H) regist er.
MANC2H Regist er 0x00000002:
Bit 2 [ 1] Enable MDEF[ 1] t raffic t o go t o t he host as well
This enables ARP request s t o be passed t o bot h manageabilit y and t o t he host . Specified separat e MDEF
filt er for ARP request s. I f ARP request s had been added t o MDEF[ 0] and t hen MDEF[ 0] specified in
management - t o- host configurat ion t hen not only would ARP request s be sent t o t he BMC and host ,
RMCP t raffic ( port s 0x26F and 0x298) would have also been sent t o bot h places.
Receive Enable [8D, AABBCCDD, 01020304, 00, 00, 00]
Using t he advanced version Receive Enable command, t he first paramet er:
Receive Enable Cont rol 0x8D:
Bit 3 [ 1] Enable aut omat ic ARP responses
Bit 5: 4 [ 00] Not ificat ion met hod = SMBus alert
Bit 7 [ 1] Use dedicat ed MAC
Second paramet er is t he MAC address ( AABBCCDD) .
Third paramet er is t he I P address ( 01020304) .
The last t hree paramet ers are zero when t he not ificat ion met hod is SMBus Alert .
I nt el

740
10.5.2.4.3 Ex ampl e 3 - Dedi cat ed MAC and I P Addr ess
This example provides t he BMC wit h a dedicat ed MAC and I P address and allows it t o receive ARP
request s. The BMC is t hen responsible for responding t o ARP request s.
address and adding one t o it , assume t he syst em MAC is AABBCCDC. The I P address for t his example
is1. 2.3.4. For t his example, t he Receive Enable command is used t o configure t he MAC address filt er.
I n order for t he BMC t o be able t o receive ARP request s, it needs t o specify a filt er for t his, and t hat
filt er needs t o be included in t he manageabilit y- t o- host filt ering so t hat t he host operat ing syst em can
also receive ARP request s.
Receive Enable[00]
Fi l t er 0 1 2 3 4 5 6 7
L2 Unicast Address AND x
Broadcast AND
I P Address AND
Broadcast OR
Mult icast AND
ARP Request OR x
ARP Response OR
Port 0x298 OR x
Port 0x26F OR x
Flex Port 15: 0 OR
Flex TCO 3: 0 OR

741
St ep 2: - Read syst em MAC address:
Reads t he syst em MAC address. Assume ret urned AABBCCDC for t his example.
St ep 3: - Configure I P address filt er:
Use t he Updat e Manageabilit y Filt er Paramet ers t o configure an I Pv4 filt er.
The 1
st
paramet er ( 0x64) specifies t hat we are configuring an I Pv4 filt er.
The 2
nd
paramet er ( 0x00) indicat es which I Pv4 filt er is being configured, in t his case filt er 0.
The 3
rd
paramet er is t he I P address 1. 2. 3. 4.
St ep 4: - Configure MAC address filt er:
Update Manageability Filter Parameters [66, 00, AABBCCDD]
Use t he Updat e Manageabilit y Filt er Paramet ers t o configure a MAC Address filt er.
The 1
st
paramet er ( 0x66) specifies t hat we are configuring a MAC Address filt er.
The 2
nd
paramet er ( 0x00) indicat es which MAC address filt er is being configured, in t his case filt er 0.
The 3
rd
paramet er is t he MAC address - AABBCCDD
St ep 5: - Configure manageabilit y filt ers valid t o select t he I Pv4 [ 0] and MAC[ 0] filt ers:
St ep 3 configured one of possibly many I P address filt ers, t his st ep indicat es which of t hose filt ers
should be used when filt ering incoming t raffic.
Use t he Updat e Manageabilit y Filt er Paramet ers t o configure t he MVFAL regist er.
The 1
st
paramet er ( 0x60) specifies t hat we are configuring t he MFVAL regist er.
The 2
nd
paramet er ( 0x00010001) is t he new value of t he MFVAL regist er.
MFVAL value of 0x00010000:
Bit 1 [ 1] MAC Address Filt er 0
Bit 16 [ 1] I PV4 Filt er 0
For more informat ion regarding Manageabilit y Filt ers Valid, see sect ion Sect ion 8. 2. 3.25. 5.
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St ep 6: - Configure MDEF[ 0] for I P and MAC filt ering:
( paramet er 0x61) . This will updat e MDEF[ 0] , as indicat ed by t he 2
nd
paramet er ( 0) .
MDEF value of 0x00000040:
Bit 1 [ 1] - MAC Address Filt ering
Bit 3 [ 1] I P Address Filt ering
( paramet er 0x61) . This will updat e MDEF[ 1] , as indicat ed by t he 2
nd
paramet er ( 1) .
MDEF value of 00000080:
Bit 7 [ 7] ARP Request s
When filt ering ARP request s t he request s go int o t he manageabilit y filt ering syst em and as such need t o
be designat ed as also needing t o be sent t o t he host . For t his reason a separat e MDEF is creat ed wit h
only ARP request filt ering enabled.
St ep 8: - Configure t he management t o host filt er:
Update Manageability Filter Parameters [0A, 00000002]
Use t he Updat e Manageabilit y Filt er Paramet ers command t o updat e t he Management Cont rol- t o- Host
( MANC2H) regist er.
MANC2H Regist er 00000002:
Bit 2 [ 1] Enable MDEF[ 1] t raffic t o go t o t he host as well
Receive Enable [05]
Using t he simple form of t he Receive Enable command,:
Bit 5: 4 [ 00] Not ificat ion met hod = SMBus Alert
The result ing MDEF filt ers are as follows:

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10.5.2.4.4 Ex ampl e 4 - Dedi cat ed MAC and VLAN Tag
This example shows an alt ernat e configurat ion; t he BMC has a dedicat ed MAC and I P address, along
wit h a VLAN t ag of 0x32 is required for t raffic t o be sent t o t he BMC. This means t hat all t raffic wit h
VLAN a mat ching t ag is sent t o t he BMC.
address and adding one do it , assume t he syst em MAC is AABBCCDC. The I P address for t his example
is 1. 2. 3. 4 and t he VLAN t ag will be 0x0032.
I t is assumed t he host is not using t he same VLAN t ag as t he BMC. I f t hey were t o share t he same
VLAN t ag t hen addit ional filt ering would need t o be configured t o allow VLAN t agged non- unicast ( such
as ARP request s) t o be sent t o t he host as well as t he BMC using t he manageabilit y- t o - host filt er
capabilit y.
Addit ionally, t he XSUM filt ering is enabled.
Fi l t er 0 1 2 3 4 5 6 7
Broadcast AND
I P Address AND x
Broadcast OR
Mult icast AND
ARP Request OR x
ARP Response OR
Port 0x298 OR
Port 0x26F OR
Flex Port 15: 0 OR
Flex TCO 3: 0 OR
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Receive Enable[00]
St ep 2: - Read syst em MAC address:
Reads t he syst em MAC address. Assume ret urned AABBCCDC for t his example.
St ep 3: - Configure XSUM filt er:
Use t he Updat e Manageabilit y Filt er Paramet ers command t o updat e Filt ers Enable set t ings ( paramet er
1) . This set t he Manageabilit y Cont rol ( MANC) regist er.
MANC Regist er 0x00800000:
Bit 23 [ 1] XSUM Filt er enable
Not e t hat some of t he following configurat ion st eps manipulat e t he MANC regist er indirect ly, t his
command set s all bit s except XSUM t o zero. I t is import ant t o eit her do t his st ep before t he ot hers, or
t o read t he value of t he MANC and t hen writ e it back wit h only bit 32 changed. Also not e t hat t he XSUM
enable bit can differ bet ween Et hernet cont rollers, refer t o product specific document at ion.
St ep 4: - Configure VLAN 0 filt er:
Use t he Updat e Manageabilit y Filt er Paramet ers command t o configure VLAN filt ers. Paramet er 0x62
indicat es updat e t o VLAN Filt er, t he 2
nd
paramet er indicat es which VLAN filt er ( 0 in t his case) , t he last
paramet er is t he VLAN I D ( 0x0032) .
St ep 5: - Enable VLAN 0 filt er:
The previous st ep configured a VLAN filt er, t his st ep enables it .
Use t he Updat e Manageabilit y Filt er Paramet ers command t o enable t he VLAN filt er ( VLAN filt er 0)
configured in t he previous st ep, t his informat ion is writ t en t o t he Manageabilit y Filt ers Valid ( MFVAL)
regist er. See Sect ion 8. 2.3.25.5 for more det ails about MFVAL.

745
MFVAL value of 00000100:
Bit 8 [ 1] VLAN Filt er 0
nd
paramet er ( 0) .
MDEF value of 00000040:
Bit 2 [ 1] VLAN AND
Receive Enable [85, AABBCCDD, 01020304, 00, 00, 00]
Using t he advanced version Receive Enable command, t he first paramet er:
Bit 0 [ 1] b Enable receiving of packet s
Bit 2 [ 1] b Enable st at us report ing ( such as link lost )
Bit 5: 4 [ 00] b Not ificat ion met hod = SMBus Alert
Bit 7 [ 1] b Use dedicat ed MAC
Second paramet er is t he MAC address: AABBCCDD.
Third paramet er is t he I P address: 01020304.
The last t hree paramet ers are zero when t he not ificat ion met hod is SMBus Alert .
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10. 5. 2. 5 SMBus Tr oubl eshoot i ng and Recommendat i ons
This sect ion out lines t he most common issues found while working wit h pass- t hrough using t he SMBus
sideband int erface.
10.5.2.5.1 SMBus Commands Ar e Al w ays NACK' d
There are several reasons why all commands sent t o t he 82599 from a MC could be NACK' d. The
following are most common:
I nvalid NVM I mage The image it self might be invalid or it could be a valid image and is not a
pass- t hrough image, as such SMBus connect ivit y is disabled.
The MC is not using t he correct SMBus address Many MC vendors hard- code t he SMBus
address( es) int o t heir firmware. I f t he incorrect values are hard- coded, t he 82599 does not
respond.
The SMBus address( es) can be dynamically set using t he SMBus ARP mechanism.
Bus I nt erference t he bus connect ing t he MC and t he 82599 might be unst able, consult t he
reference schemat ics for correct pullup resist ers.
10.5.2.5.2 SMBus Cl ock Speed I s 16. 6666 KHz
This can happen when t he SMBus connect ing t he MC and t he 82599 is also t ied int o anot her device
( such as an I CH) t hat has a maximum clock speed of 16. 6666 KHz. The solut ion is t o not connect t he
SMBus bet ween t he 82599 and t he MC t o t his device.
Fi l t er 0 1 2 3 4 5 6 7
Broadcast AND
Manageabilit y VLAN AND x
I P Address AND
Broadcast OR
Mult icast AND
ARP Request OR
ARP Response OR
Port 0x298 OR
Port 0x26F OR
Flex Port 15: 0 OR
Flex TCO 3: 0 OR

747
10.5.2.5.3 A Net w or k Based Host Appl i cat i on I s Not Recei vi ng any Net w or k Pack et s
Report s have been received about an applicat ion not receiving any net work packet s. The applicat ion in
quest ion was NFS under Linux. The problem was t hat t he applicat ion was using t he RMPC/ RMCP+ I ANA
reserved port 0x26F ( 623) and t he syst em was also configured for a shared MAC and I P address wit h
t he operat ing syst em and MC.
The management cont rol t o host configurat ion, in t his sit uat ion, was set up not t o send RMCP t raffic t o
t he operat ing syst em ( t his is t ypically t he correct configurat ion) . This means t hat no t raffic sent t o port
623 was being rout ed.
The solut ion in t his case is t o configure t he problemat ic applicat ion NOT t o use t he reserved port 0x26F.
10.5.2.5.4 Unabl e t o Tr ansmi t Pack et s f r om t he MC
I f t he MC has been t ransmit t ing and receiving dat a wit hout issue for a period of t ime and t hen begins t o
receive NACKs from t he 82599 when it at t empt s t o writ e a packet , t he problem is most likely due t o t he
fact t hat t he buffers int ernal t o t he 82599 are full of dat a t hat has been received from t he net work but
has yet t o be read by t he MC.
Being an embedded device, t he 82599 has limit ed buffers t hat are shared for receiving and t ransmit t ing
dat a. I f a MC does not keep t he incoming dat a read, t he 82599 can be filled up This prevent s t he MC
form t ransmit t ing more dat a, result ing in NACKs.
I f t his sit uat ion occurs, t he recommended solut ion is t o have t he MC issue a Receive Enable command
t o disable more incoming dat a, read all t he dat a from t he 82599, and t hen use t he Receive Enable
command t o enable incoming dat a.
10.5.2.5.5 SMBus Fr agment Si ze
The SMBus specificat ion indicat es a maximum SMBus t ransact ion size of 32 byt es. Most of t he dat a
passed bet ween t he 82599 and t he MC over t he SMBus is RMCP/ RMCP+ t raffic, which by it s very nat ure
( UDP t raffic) is significant ly larger t han 32 byt es in lengt h. Mult iple SMBus t ransact ions may t herefore
be required t o move dat a from t he 82599 t o t he MC or t o send a dat a from t he MC t o t he 82599.
Recognizing t his bot t leneck, t he 82599 handles up t o 240 byt es of dat a in a single t ransact ion. This is a
configurable set t ing in t he NVM. The default value in t he NVM images is 32, per t he SMBus
specificat ion. I f performance is an issue, increase t his size.
10.5.2.5.6 Losi ng Li nk
Normal behavior for t he Et hernet cont roller when t he syst em powers down or performs a reset is for
t he link t o t emporarily go down and t hen back up again t o re- negot iat e t he link speed. This behavior
can have adverse affect s on manageabilit y.
For example if t here is an act ive FTP or Serial Over LAN ( SOL) session t o t he MC, t his connect ion may
be lost . I n order t o avoid t his possible sit uat ion, t he MC can use t he Management Cont rol command
det ailed in Sect ion 10.5. 2. 1. 5 t o ensure t he link st ays act ive at all t imes.
This command is available when using t he NC- SI sideband int erface as well.
Care should be t aken wit h t his command, if t he driver negot iat es t he maximum link speed, t he link
speed remains t he same when t he syst em powers down or reset s. This may have undesirable power
consumpt ion consequences. Current ly, when using NC- SI , t he MC can re- negot iat e t he link speed. That
funct ionalit y is not available when using t he SMBus int erface.
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10.5.2.5.7 Enabl e XSum Fi l t er i ng
I f XSum filt ering is enabled, t he MC does not need t o perform t he t ask of checking t his checksum for
incoming packet s. Only packet s t hat have a valid XSum is passed t o t he MC. All ot hers are silent ly
discarded.
This is a way t o offload some work from t he MC.
10.5.2.5.8 St i l l Hav i ng Pr obl ems?
I f problems st ill exist , cont act your field represent at ive. Be prepared t o provide t he following:
A SMBus t race if possible
A dump of t he NVM image. This should be t aken from t he act ual 82599, rat her t han t he NVM image
provided by I nt el. Part s of t he NVM image are changed aft er writ ing ( such as t he physical NVM
size) .
10.5. 3 Manageabi l i t y Host I nt er f ace
10. 5. 3. 1 HOST CSR I nt er f ace ( Funct i on 1/ 0)
The soft ware device driver of funct ion 0/ 1 communicat es wit h t he manageabilit y block t hrough CSR
access. The manageabilit y is mapped t o address space 0x15800 t o 0x15FFF on t he slave bus of each
funct ion.
Not e: Writ ing t o address 0x15800 from funct ion 0 or from funct ion 1 is t arget ed t o t he same
address in t he RAM.
10. 5. 3. 2 Host Sl av e Command I nt er f ace t o Manageabi l i t y
This int erface is used by t he soft ware device driver for several of t he commands and for delivering
various t ypes of dat a in bot h direct ions ( manageabilit y- t o- host and host - t o- manageabilit y) .
The address space is separat ed int o t wo areas:
Direct access t o t he int ernal ARC dat a RAM: The int ernal dat a RAM is mapped t o address space
0x15800 t o 0x15EFF. Writ ing/ reading t o t his address space goes direct ly t o t he RAM.
Cont rol regist ers are locat ed at address 0x15F00.
10. 5. 3. 3 Host Sl av e Command I nt er f ace Low Lev el Fl ow
This int erface is used for t he ext ernal host soft ware t o access t he manageabilit y subsyst em. Host
soft ware writ es a command block or read dat a st ruct ure direct ly from t he dat a RAM. Host soft ware
cont rols t hese t ransact ions t hrough a slave access t o t he cont rol regist er.
The following flow shows t he process of init iat ing a command t o t he manageabilit y block:
1. The soft ware device driver reads t he cont rol regist er and checks t hat t he Enable bit is set .
2. The soft ware device driver writ es t he relevant command block int o t he RAM area.
3. The soft ware device driver set s t he Command bit in t he cont rol regist er. Set t ing t his bit causes an
int errupt t o t he ARC ( can be masked) .
4. The soft ware device driver polls t he cont rol regist er for t he command bit t o be cleared by hardware.
5. When manageabilit y finishes wit h t he command, it clears t he command bit ( if t he manageabilit y
should reply wit h dat a, it should clear t he bit only aft er t he dat a is in t he RAM area where t he
soft ware device driver can read it ) .

749
I f t he soft ware device driver reads t he cont rol regist er and t he SV bit is set , t hen t here is a valid st at us
of t he last command in t he RAM. I f t he SV bit is not set , t hen t he command has failed wit h no st at us in
t he RAM.
10. 5. 3. 4 Host Sl av e Command Regi st er s
The Host Slave Command regist ers ( list ed below) are described in Sect ion 8.2. 3. 27. 1. These regist er
part icipat es in t he Host / Soft ware / Firmware int erface:
Host I nt erface Cont rol Regist er CSR Address 0x15F00; AUX 0x0700
Firmware St at us 0 ( FWS0R) Regist er CSR Address 0x15F0C; AUX 0x0702
Soft ware St at us Regist er CSR Address 0x15F10; AUX 0x0703
10. 5. 3. 5 Host I nt er f ace Command St r uct ur e
The following t able describes t he st ruct ure used by t he host driver t o send a command t o manageabilit y
firmware via t he host int erface slave command int erface:
# By t e Descr i pt i on Bi t Val ue Descr i pt i on
0 Command 7: 0
Command
Dependent
Specifies which host command t o process.
1 Buffer Lengt h 7: 0 Command Lengt h
Command Dat a Buffer lengt h: 0 t o 252, not including 32 bit s of
header.
2
Default / I mplicit
I nt erface
0
Command
Dependent
Used for commands might refer t o one of t wo int erfaces ( LAN or
SMBus) .
0b = Use default int erface.
1b = Use specific int erface.
I nt erface
Number
1
Command
Dependent
Used when bit 0 ( Default / I mplicit int erface) is set :
0b = Apply command for int erface 0.
1b = Apply command for int erface 1.
When bit 0 is set t o 0b, it is ignored.
3 Checksum 7: 0 Defined Below Checksum signat ure.
255: 4 Dat a Buffer 7: 0
Command
Dependent
Command Specific Dat a
Minimum buffer size: 0.
Maximum buffer size: 252.
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10. 5. 3. 6 Host I nt er f ace St at us St r uct ur e
The following t able list s t he st ruct ure used by manageabilit y firmware t o ret urn a st at us t o t he host
driver via t he host int erface slave command int erface. A st at us is ret urned aft er a command has been
execut ed.
10. 5. 3. 7 Check sum Cal cul at i on Al gor i t hm
The Host Command/ St at us st ruct ure is summed wit h t his field cleared t o 0b. The calculat ion is done
using 8- bit unsigned mat h wit h no carry. The inverse of t his sum is st ored in t his field ( 0b minus t he
result ) . Result : The current sum of t his buffer ( 8- bit unsigned mat h) is 0b.
10. 5. 3. 8 Host Sl av e I nt er f ace Commands
I n SMBus PT mode t he only host int erface command t hat is support ed is t he failover configurat ion
command ( besides debug commands t hat will not be described in t his document ) .
10.5.3.8.1 Fai l - Over Conf i gur at i on Host Command
This command is used t o updat e t he Fail- Over Configurat ion regist er:
Following is t he st at us ret urned on t his command:
# Byt e Descr i pt i on Bi t Val ue Descr i pt i on
0 Command 7: 0
Command
Dependent
Command I D.
1 Buffer Lengt h 7: 0 St at us Dependent St at us buffer lengt h: 252: 0
2 Ret urn St at us 7: 0
Depends on
Command Execut ing
Result s
Defined in commands descript ion.
3 Checksum 7: 0 Defined Below Checksum signat ure.
255: 4 Dat a Buffer St at us Dependent
St at us configurat ion paramet ers
Minimum Buffer Size: 0.
Maximal Buffer Size: 252.
By t e Descr i pt i on Bi t Val ue Descr i pt i on
0 Command 7: 0 0x26 Fail- over configurat ion command.
1 Buffer Lengt h 7: 0 0x4 Four byt es of t he failover configurat ion regist er.
2 7: 0 0x0
3 Checksum 7: 0 Checksum signat ure of t he Host command.
7: 4 Reserved 7: 0 Reserved Reserved.
0 Command 7: 0 0x26 Four byt es of t he fail over regist er value.
1 Buffer Lengt h 7: 0 0x0 No dat a in ret urn st at us.
2 Ret urn St at us 7: 0 0x1 0x1 for good st at us.
3 Checksum 7: 0 Checksum signat ure.

751
10.5.3.8.2 Read Fai l - Ov er Conf i gur at i on Host Command
This command is used t o read t he Fail- Over Configurat ion regist er:
Following is t he st at us ret urned on t his command:
10.5.4 Sof t w ar e and Fi r mw ar e Sy nchr oni zat i on
Soft ware and firmware synchronize accesses t o shared resources in t he 82599 t hrough a semaphore
mechanism and a shared configurat ion regist er bet ween t he host int erface of t he t wo port s and
firmware. This semaphore enables synchronized accesses t o t he following shared resources:
EEPROM
PHY 0 and PHY 1 regist ers
MAC ( LAN cont roller) shared regist ers ( reserved opt ion for fut ure use)
The SWSM.SWESMBI bit and t he FWSM.FWSMBI bit are used as a semaphore mechanism bet ween
soft ware and firmware. Once soft ware or firmware t akes cont rol over t hese semaphore flags, it can
access t he SW_FW_SYNC regist er and claim ownership of t he specific resources. The SW_FW_SYNC
includes pairs of bit s ( one owned by soft ware and t he ot her by firmware) , while each pair of bit s cont rol
a different resource. A resource is owned by soft ware or firmware when t he respect ive bit is set . I t is
illegal t o have bot h bit s in a pair set at t he same t ime. Following are t he required sequences for gaining
and releasing cont rol over t he shared resources:
0 Command 7: 0 0x27 Read Fail- Over Configurat ion command.
1 Buffer Lengt h 7: 0 0x0 No dat a at t ached t o t his command.
2 7: 0 0x0
3 Checksum 7: 0 Checksum signat ure of t he Host command.
0 Command 7: 0 0x27 Fail- over configurat ion command.
1 Buffer Lengt h 7: 0 0x4 I ndicat es four byt es of t he failover regist er ( 7: 4 below) .
2 Ret urn St at us 7: 0 0x1 I ndicat es good st at us.
3 Checksum 7: 0 Checksum signat ure.
7: 4 Dat a Buffer 7: 0
Fail- over
configurat ion
Dwords
Fail over regist er cont ent .
Byt e 4 is byt e 0 of t he configurat ion regist er.
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Gai ni ng Cont r ol of Shar ed Resour ce by Sof t w ar e
Soft ware checks t hat t he soft ware on t he ot her LAN funct ion does not use t he soft ware/ firmware
semaphore
Soft ware polls t he SWSM.SMBI bit unt il it is read as 0b or t ime expires ( recommended
expirat ion is ~ 10 ms+ expirat ion t ime used for t he SWSM. SWESMBI ) .
I f SWSM.SMBI is found at 0b, t he semaphore is t aken. Not e t hat following t his read cycle
hardware aut o set s t he bit t o 1b.
I f t ime expired, it is assumed t hat t he soft ware of t he ot her funct ion malfunct ions. Soft ware
proceeds t o t he next st eps checking SWESMBI for firmware use.
Soft ware checks t hat t he firmware does not use t he soft ware/ firmware semaphore and t hen t akes
it s cont rol
Soft ware writ es a 1b t o t he SWSM.SWESMBI bit
Soft ware polls t he SWSM.SWESMBI bit unt il it is read as 1b or t ime expires ( recommended
expirat ion is ~ 3 sec) . I f t ime has expired soft ware assumes t hat t he firmware malfunct ioned
and proceeds t o t he next st ep while ignoring t he firmware bit s in t he SW_FW_SYNC regist er.
Soft ware t akes cont rol of t he request ed resource( s)
Soft ware reads t he firmware and soft ware bit ( s) of t he request ed resource( s) in t he
SW_FW_SYNC regist er.
I f t ime has expired in t he previous st eps due t o a malfunct ion firmware, t he soft ware should
clear t he firmware bit s in t he SW_FW_SYNC regist er. I f t ime has expired in t he previous st eps
due t o malfunct ion soft ware of t he ot her LAN funct ion, soft ware should clear t he soft ware bit s
in t he SW_FW_SYNC regist er t hat it does not own.
I f t he soft ware and firmware bit ( s) of t he request ed resource( s) in t he SW_FW_SYNC regist er
are cleared, it means t hat t hese resources are accessible. I n t his case soft ware set s t he
soft ware bit ( s) of t he request ed resource( s) in t he SW_FW_SYNC regist er. Then t he SW clears
t he SWSM. SWESMBI and SWSM. SMBI bit s ( releasing t he SW/ FW semaphore regist er) and can
use t he specific resource( s) .
Ot herwise ( eit her firmware or soft ware of t he ot her LAN funct ion owns t he resource) , soft ware
clears t he SWSM. SWESMBI and SWSM. SMBI bit s and t hen repeat s t he ent ire process aft er
some delay ( recommended 5- 10 ms) . I f t he resources are not released by soft ware of t he ot her
LAN funct ion long enough ( recommended expirat ion t ime is ~ 1 sec) soft ware can assume t hat
t he ot her soft ware malfunct ioned. I n t hat case soft ware should clear all soft ware flags t hat it
does not own and t hen repeat t he ent ire process once again.
Not e t hat firmware init ializes it s semaphore flags as part of it s init ializat ion flow.
Rel easi ng a Shar ed Resour ce by Sof t w ar e
The soft ware t akes cont rol over t he soft ware/ firmware semaphore as previously described for
gaining shared resources.
Soft ware clears t he bit ( s) of t he released resource( s) in t he SW_FW_SYNC regist er.
Soft ware releases t he soft ware/ firmware semaphore by clearing t he SWSM. SWESMBI and
SWSM. SMBI bit s
Soft ware should wait a minimum delay ( recommended 5- 10 ms) before t rying t o gain t he
semaphore again

753
Gai ni ng Cont r ol of Shar ed Resour ce by Fi r mw ar e
Firmware t akes cont rol over t he soft ware/ firmware semaphore ( SW_FW_SYNC regist er)
Firmware writ es a 1b t o t he FWSM.FWSMBI bit
Firmware polls t he FWSM. FWSMBI bit unt il it is read as 1b or t ime is expired ( recommended
expirat ion t ime is ~ 10 ms) .
I f t ime has expired firmware ignores t he FWSM.FWSMBI bit and cont inues t o t he next st ep
( assuming soft ware does not funct ion well) .
Firmware t akes ownership of t he request ed resources
Firmware reads t he mat ched soft ware bit ( s) t o t he request ed resource( s) in t he SW_FW_SYNC
regist er.
I f t he soft ware bit ( s) are cleared ( such as soft ware does not own t he resource) , firmware set s
t he firmware bit ( s) of t he request ed resource( s) . Then firmware clears t he FWSM.FWSMBI bit
( releasing t he soft ware/ firmware semaphore) and can use t he specific resource( s) .
Ot herwise ( soft ware owns t he resource) , firmware clears t he FWSM.FWSMBI bit and t hen
repeat s t he previous process aft er some delay ( recommended delay of
5- 10 ms) . I f t he resources are not released long enough ( ~ 1 sec) firmware accesses by force
t he request ed resources. Firmware also clears t he soft ware flags of t he request ed resources in
t he SW_FW_SYNC regist er ( assuming soft ware t hat set t hose flags malfunct ioned) .
Rel easi ng a Shar ed Resour ce by Fi r mw ar e
Firmware t akes cont rol over t he soft ware/ firmware semaphore as previously described for gaining
shared resources.
Firmware clears t he bit ( s) of t he select ed resource( s) in t he SW_FW_SYNC regist er.
Firmware releases t he soft ware/ firmware semaphore by clearing t he FWSM. FWSMBI bit
Firmware should wait some delay before t rying t o gain t he semaphore once again ( recommended
5- 10 ms)
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El ect r i cal / Mechani cal Speci f i cat i on I nt el

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11. 0 El ect r i cal / Mechani cal Speci f i cat i on
11.1 I nt r oduct i on
This sect ion describes t he 82599 DC and AC ( t iming) elect rical charact erist ics and t he 82599 package
specificat ion. This includes absolut e maximum rat ing, recommended operat ing condit ions, power
sequencing requirement s, DC and AC t iming specificat ions. The DC and AC charact erist ics include
generic digit al I O specificat ion as well as ot her specificat ions of int erfaces support ed by t he 82599.
11. 2 Oper at i ng Condi t i ons
11.2.1 Absol ut e Max i mum Rat i ngs
Not e: St resses above t hose list ed in t he t able can cause permanent device damage. These values should not be used as limit s for
normal device operat ion. Exposure t o absolut e maximum rat ing condit ions for an ext ended period of t ime can affect device
reliabilit y.
Tabl e 11.1. Absol ut e Max i mum Rat i ngs
Sy mbol Par amet er Mi n Max Uni t s
T
case
Case Temperat ure Under Bias 0 120 C
T
st orage
St orage Temperat ure Range - 65 140 C
Vi 3. 3V I / O input Volt age Vss- 0. 5 4. 0 V
VCC3P3 3. 3V Periphery Supply Volt age Vss - 0. 5 4. 0 V
VCC1P2 1. 2V Core/ Periphery/ Analog Supply Volt age Vss- 0. 2 1. 68V V
I CC3P3 3. 3V Periphery Supply Current - 0. 25 A
I CC1P2 1. 2V Core/ Periphery/ Analog Supply Current - 5. 3 A
I nt el
82599 10 GbE Cont r ol l er El ect r i cal / Mechani cal Speci f i cat i on

756
11.2. 2 Recommended Oper at i ng Condi t i ons
Not es:
1. For normal device operat ion, adhere t o t he limit s in t his t able. Sust ained operat ion of a device at condit ions exceeding t hese
values, even if t hey are wit hin t he absolut e maximum rat ing limit s, can result in permanent device damage or impaired device
reliabilit y. Device funct ionalit y t o st at ed DC and AC limit s is not guarant eed if condit ions exceed recommended operat ing
condit ions.
2. Recommended operat ion condit ions require accuracy of power supply of 5% relat ive t o t he nominal volt age.
3. Ext ernal Heat Sink ( EHS) is needed.
4. Refer t o Sect ion 13. 0 for a descript ion of t he allowable t hermal environment .
11.3 Pow er Del i ver y
11.3. 1 Pow er Suppl y Speci f i cat i ons
Tabl e 11.3. VCC3P3 Ex t er nal Pow er Suppl y Speci f i cat i ons
Tabl e 11.2. Recommended Oper at i ng Condi t i ons
Sy mbol Par amet er Mi n Ty p Max Uni t s
Ta
Operat ing Temperat ure Range Commercial ( Ambient ;
0 CFS airflow)
0
See
Chapt er 13. 0
C
Tj Junct ion Temperat ure
Driven by
min Ta
123 C
VCC3P3 3. 3V Power Supply 3. 14 3. 3 3. 46 V
VCC1P2 1. 2V Power Supply 1. 14 1. 2 1. 26 V
Ti t l e Descr i pt i on Mi n Max Uni t s
Rise Time Time from 10% t o 90% mark 0. 1 100 ms
Monot onicit y Volt age dip allowed in ramp n/ a 0 mV
Slope
Ramp rat e at any given t ime bet ween 10% and 90%
Min: 0. 8* V( min) / rise t ime ( max)
Max: 0. 8* V( max) / rise t ime ( min)
24 28, 800 V/ S
Operat ional Range Volt age range for normal operat ing condit ions 3. 3 5% 3. 3 + 5% V
Ripple Maximum volt age ripple ( peak t o peak) n/ a 70 mV
Overshoot Maximum overshoot allowed n/ a 100 mV
Overshoot Set t ling Time
Maximum overshoot allowed durat ion.
( At t hat t ime delt a volt age should be lower t han 5 mV from
st eady st at e volt age)
n/ a 0. 05 ms

757
Tabl e 11.4. VCC1P2 Ex t er nal Pow er Suppl y Speci f i cat i on
11. 3. 1. 1 Pow er On/ Of f Sequence
The following relat ionships bet ween t he rise t ime of t he different power supplies should be maint ained
at all t imes when ext ernal power supplies are in use t o avoid risk of eit her lat ch- up or forward- biased
int ernal diodes:
T
3. 3
s T
1. 2
V
1. 2
s V
3. 3
At power- on and aft er 3.3V reaches 90% of it s final value, t he 1.2V volt age rail is allowed 100 ms t o
reach it s final operat ing volt age. Once t he 1.2V power supply reaches 80% of it s final value t he 3. 3V
power supply should always be above 80% of it s final value unt il power down.
For power down, it is recommended t o t urn off all rails at t he same t ime and allow volt age t o decay.
Ti t l e Descr i pt i on Mi n Max Uni t s
Rise Time Time from 10% t o 90% mark 0. 1 100 ms
Monot onicit y Volt age dip allowed in ramp n/ a 0 mV
Slope
Ramp rat e at any given t ime bet ween 10% and 90%
Min: 0. 8* V( min) / rise t ime ( max)
Max: 0. 8* V( max) / rise t ime ( min)
9. 1 10000 V/ S
Operat ional Range Volt age range for normal operat ing condit ions 1. 14 1. 26 V
Ripple Maximum volt age ripple ( peak t o peak) n/ a 40 mV
Overshoot Maximum overshoot allowed n/ a 60 mV
Overshoot Durat ion
Maximum overshoot allowed durat ion.
( At t hat t ime delt a volt age should be lower t han 5 mV from
st eady st at e volt age)
0. 0 0. 05 ms
Tabl e 11.5. Pow er Sequenci ng f or t he 82599
Sy mbol Par amet er Mi n Max uni t s
T
3_1
VCC3P3 ( 3. 3V) st able t o VCC1P2 ( 1. 2V) st able 0 100 ms
Tm- per, Tm- ppo 3. 3V core t o PE_RST_N and MAI N_PWR_OK on 0 ms
Tper- m, Tppo- m PE_RST_Nand MAI N_PWR_OK off before 3. 3V core down 0 ms
I nt el

758
11.3. 2 I n- Rush Cur r ent
Not e: NI Cs should limit in- rush current t o under 3A from 3. 3V power supply and 2. 1A from 12V
power supply
11.4 DC/ AC Speci f i cat i on
11.4. 1 DC Speci f i cat i ons
Tabl e 11.6. 82599 Pow er Summar y
Fi gur e 11.1. Pow er and Reset Sequenci ng
I nt er f ace
Typi cal [ W]
TTT, 60 C, Vnom, 512 B
Secur i t y On
1
1. The securit y engine in 10 GbE mode cont ribut es 200 mW maximum power ( 180 mW t ypical power) .
Max i mum [ W]
FFF, 125 C, Vnom, 512 B
Secur i t y On
1
Reser ved
SP
2
2. SP = Single port .
DP
3
3. DP = Dual port .
SP DP
KX 2. 3 2. 7 3. 1 3. 5
XAUI / KX4 3. 3 4. 5 4. 0 5. 2
SFI Opt ics 3. 4 4. 7 4. 2 5. 6
SFI Twinax 3. 6 5. 2 4. 5 6. 2
KR ( I EEE) 3. 3 4. 5 4. 1 5. 4
LAN_PWR_GOOD
VCC3P3 (3.3V)
Aux power stable
Main power stable
Tlpg
Tlpg-per
MAIN_PWR_OK
Tm-per
Tm-ppo
Main Power stable
Tper-m
Tppo-m
VCC1P2(1.2V)
PE_RST_N
T3_1
Tlpgw

759
11. 4. 1. 1 Cur r ent Consumpt i on
The 82599 priorit ies for power reduct ion are as follows ( in descending order) :
TDP: D0 act ive @ 10 GbE maximum load, fast silicon
D0 idle: 10 GbE/ 1 GbE link and no act ivit y
D0 idle: 10 GbE/ 1 GbE link wit h one port disabled
Syst em sleep: D3cold wit h wake ( link at 10 GbE or 1 GbE)
Syst em Sleep: D3cold wit hout wake and wit hout manageabilit y
Ot her st at es
The following t ables list t he t arget s for device power. The numbers list ed apply t o device current and
power and do not include power losses on ext ernal component s.
Tabl e 11.7. D0a Act i ve Li nk - Bot h Por t s Act i v e; L0s and L1 Di sabl ed
1000 Mb/ s
10 GbE ( KX4,
CX4, XAUI )
10 GbE KR I EEE SFI Opt i cs 10 GbE Tw i nax
Par amet er Ty p Max Ty p Max Ty p Max Ty p Max Ty p Max
3. 3v I dd [ mA] 42 42 42 42 62 64 126 126 126 126
1. 2v I dd [ mA] 2170 2810 3660 4380 3570 4330 3590 4350 4010 4790
Pow er [ mW] 2700 3500 4500 5400 4500 5400 4700 5600 5200 6200
Not es:
1. Typical condit ions: t ypical mat erial TJ = 60 C, nominal volt ages and cont inuous net work t raffic at link speed.
2. Maximum condit ions: fast mat erial maximum operat ing t emperat ure ( TJ) values, t ypical volt age values and cont inuous
net work t raffic at link speed.
3. Maximum power at 110 C is expect ed t o be ~ 0. 5 W less t han t he power at 123C ( max TJ) .
4. Power numbers are measured wit h securit y offload on. Disabling it reduces ~ 200 mW ( max) and 180 mW ( Typical) .
Tabl e 11.8. D0a Act i ve Li nk - Si ngl e Por t Act i v e; L0s and L1 Di sabl ed
1000 Mb/ s
10 GbE ( KX4,
CX4, XAUI )
3. 3v I dd [ mA] 42 42 42 42 53 53 84 84 84 84
1. 2v I dd [ mA] 1830 2460 2600 3240 2560 3260 2570 3270 2780 3490
Pow er [ mW] 2300 3100 3300 4000 3300 4100 3400 4200 3600 4500
Not es:
1. Typical condit ions: t ypical mat erial TJ = 60 C, nominal volt ages and cont inuous net work t raffic at link speed.
2. Maximum condit ions: fast mat erial maximum operat ing t emperat ure ( TJ) values, t ypical volt age values and cont inuous
net work t raffic at link speed.
3. Maximum power at 110 C is expect ed t o be ~ 0. 5 W less t han t he power at 123C ( max TJ) .
4. Power numbers are measured wit h securit y offload on. Disabling it reduces ~ 200 mW ( max) and 180 mW ( Typical) .
I nt el

760
Tabl e 11.9. D0a I dl e Li nk - Bot h Por t s Act i ve, L0s and L1 Di sabl ed, No Rx / Tx Tr af f i c
1000 Mb/ s
10 GbE ( KX4,
CX4, XAUI )
3. 3v I dd [ mA] 42 42 42 42 62 64 126 126 126 126
1. 2v I dd [ mA] 2110 2740 3070 3740 2930 3655 2950 3675 3770 4120
Pow er [ mW] 2700 3400 3800 4600 3700 4600 4000 4800 4500 5400
Not es:
1. Typical condit ions: t ypical mat erial TJ = 60 C, nominal volt ages and no net work t raffic.
2. Maximum condit ions: fast mat erial maximum operat ing t emperat ure ( TJ) values, nominal volt ages and no net work t raffic.
Tabl e 11.10. Typi cal D3col d Wak e Up Enabl e - One Por t Wi t h Wak eup Enabl ed; Second Por t
Wi t h Wak eup Di sabl ed
Par amet er
100 Mb/ s
Ty p . . . . Max
1000 Mb/ s
Ty p . . . . Max
10 GbE KX4
Ty p . . . . Max
10 GbE ( KX4, XAUI , CX4)
Typ . . . . Max
3. 3v I dd [ mA] 31 . . . . 31 31. 5 . . . . 31. 5 26. 8 . . . . 31. 5 4046. . . . 40
1. 2v I dd [ mA] 1365 . . . . 1420 1010. 1 . . . . 1010. 10 1291. 5 . . . . 1396. 5 1820. . . . 1970
Pow er [ mW] 1. 7 . . . . 1. 8 1316. 1 . . . . 1316. 1 1638. 2 . . . . 1779. 8 2. 3. . . . 2. 5
Not es:
1. I n t his measurement one port is set t o D3 wakeup enabled and one port at D3 no wake up.
2. Typical condit ions: t ypical mat erial TJ = 25, nominal volt ages and no net work t raffic.
3. TJ = 25, nominal volt ages and no net work t raffic.
Tabl e 11.11. Pow er Dow n
I DDq ( Tj = 123 C) I DDq ( Tj = 25 C) D3col d No Wak e Up
Par amet er Ty p Max Ty p Max Ty p Max
3. 3v I dd [ mA] 2 2 2 2 15. 8 15. 8
1. 2v I dd [ mA] 230 670 60 100 720. 3 805. 4
Pow er [ mW] 280 810 75 125 916. 3 1018. 4
Not es:
1. Typical condit ions: t ypical mat erial, nominal volt ages and no net work t raffic.
2. Maximum condit ions: fast mat erial, nominal volt ages and no net work t raffic.

761
11. 4. 1. 2 Di gi t al I / O DC Speci f i cat i ons
Not es:
1. Table 11. 12 applies t o PE_RST_N, LED0[ 3: 0] , LED1[ 3: 0] , LAN_PWR_GOOD, MAI N_PWR_OK, JTCK, JTDI , JTDO, JTMS,
SDP0[ 7: 0] , SDP1[ 7: 0] , FLSH_SI , FLSH_SO, FLSH_SCK, FLSH_CE_N, EE_DI , EE_DO, EE_SK, EE_CS_N, MDI O0, MDC1 and
MDI O1, LAN0_DI S_N, LAN1_DI S_N, AUX_PWR, OSC_SEL.
2. Charact erized not t est ed.
11. 4. 1. 3 Open Dr ai n I / O DC Speci f i cat i on
Not es:
1. Table 11. 13 applies t o SMBD, SMBCLK, SMBALRT _N, PE_WAKE_N, SCL0, SDA0, SCL1 and SDA1.
2. Device must meet t his specificat ion whet her powered or unpowered.
3. Charact erized, not t est ed.
4. The I PULLUP max specificat ion is det ermined primarily by t he need t o operat e at a cert ain frequency wit h a cert ain capacit ive
load.
5. OD no high out put drive. VOL max= 0. 4V at 8mA, VOL max= 0. 2V at 0. 1mA.
The buffer specificat ion meet s t he SMBus specificat ion requirement s defined at : www. smbus.org.
Tabl e 11.12. Di gi t al Funct i onal 3.3V I / O DC El ect r i cal Char act er i st i cs
Sy mbol Par amet er Condi t i ons Mi n Max Uni t s Not e
VOH Out put High Volt age I OH = - 8mA; VCC3P3 = Min 2. 4 V
VOL Out put Low Volt age I OL = 8mA; VCC3P3= Min 0. 4 V
VOH
led
LED Out put High Volt age I OL = 12mA; VCC3P3 = Min 2. 4 V
VOL
led
LED Out put Low Volt age I OL = 12mA; VCC3P3 = Min 0. 4 V
VI H I nput High Volt age 2. 0 VCC3P3 + 0. 3 V
VI L I nput Low Volt age - 0. 3 0. 8 V
I il I nput Current VCC3P3 = Max; VI n = 3. 6V/ GND 15 A
PU I nt ernal pullup 27 34 KO
Cin Pin capacit ance 7 pF [ 2]
Tabl e 11.13. Open Dr ai n I / O DC Char act er i st i cs
Symbol Par amet er Condi t i on Mi n Max Uni t s Not e
Vih I nput High Volt age VCC3P3 * 0. 7 VCC3P3 + 0. 5 V
Vil I nput Low Volt age - 0. 3 VCC3P3 * 0. 3 V
I leakage Out put Leakage Current 0 s Vin s VCC3P3 max - 10 10 A [ 2]
Vol Out put Low Volt age @ I pullup = 4 mA 0. 4 V [ 5]
I pullup Current Sink Vol = 0. 4V 4 mA [ 4]
Cin I nput Pin Capacit ance 7 pF [ 3]
I offsmb I nput leakage Current VCC3P3 off or float ing - 10 10 A [ 2]
I nt el

762
11. 4. 1. 4 NC- SI I / O DC Speci f i cat i on
Not es:
1. Vref = Bus high reference level. This paramet er replaces t he t erm ' supply volt age' since act ual devices may have int ernal
mechanisms t hat det ermine t he operat ing reference for t he sideband int erface t hat are different from t he devices overall power
supply input s. Vref is a reference point t hat is used for measuring paramet ers such as overshoot and undershoot and for
det ermining limit s on signal levels t hat are generat ed by a device. I n order t o facilit at e syst em implement at ions, a device must
provide a mechanism ( e. g. a power supply pin, int ernal programmable reference, or reference level pin) t o allow Vref t o be set
t o wit hin 20 mV of any point in t he specified Vref range. This is t o enable a syst em int egrat or t o est ablish an int eroperable Vref
level for devices on t he sideband int erface. Alt hough t he NC- SI spec define t he Vrefmax up t o 3. 6V, t he 82599 support s t he
Vrefmax up t o 3. 46V ( 3. 3V + 5%) .
2. Table 11. 14 applies t o NCSI _CLK_I N, NCSI _CRS_DV, NCSI _RXD[ 0: 0] , NCSI _TX_EN and NCSI _TXD[ 1: 0] .
3. Please refer also t o t he Net work Cont roller Sideband I nt erface ( NC- SI ) Specificat ion for more det ails.
11.4. 2 Di gi t al I / F AC Speci f i cat i ons
11. 4. 2. 1 Di gi t al I / O AC Speci f i cat i ons
Tabl e 11.14. NC- SI I / O DC Char act er i st i cs
Par amet er Symbol Condi t i ons Mi n. Ty p. Max Uni t s
Bus High Reference Vref
[ 1]
3. 0 3. 3 3. 46 V
Signal Volt age Range Vabs - 0. 300 3. 765 V
I nput Low Volt age Vil 0. 8 V
I nput High Volt age Vih 2. 0 V
Out put Low Volt age Vol
I ol = 4mA,
Vref= Vref
min
0 0. 4 V
Out put High Volt age Voh
I ol = - 4mA,
Vref= Vref
min
2. 4 Vref V
I nput High Current I ih
Vin

= 3. 6V,
Vref = 3. 6V
0 200 A
I nput Low Current I il
Vin = 0V,
Vref
min
t o Vref
max
- 20 0 A
Clock Midpoint Reference Level Vckm 1. 4 V
Leakage Current for Out put Signals
in High- I mpedance St at e
I z
0 s Vin s Vih
max
@Vr ef = Vref
max
- 20 20 A
Tabl e 11.15. Di gi t al Funct i onal 3.3V I / O AC El ect r i cal Char act er i st i cs
Par amet er s Descr i pt i on Mi n Max Condi t i on Not e
F
max
Maximum Operat ing
Frequency
50 MHz Cload 25 pF [ 2]
Tor Out put Rise Time 1 ns 5 ns Cload 25 pF
Tof Out put Fall Time 1 ns 5 ns Cload 25 pF
Todr
Core t o Out put Rise
Delay Time
1 ns 7 ns Cload 25 pF [ 2]
Todf
Core t o Out put Fall
Delay Time
1 ns 7 ns Cload 25 pF [ 2]
Ti dr
I nput t o Core Rise Delay
Time
0. 2ns 1. 3 ns I nt ernal Load 200 pF [ 2]

763
Not es:
1. The input delay t est condit ions: Maximum input level = VI N = 2.7V; I nput rise/ fall t ime ( 0. 2VI N t o 0. 8VI N) = 1 ns ( Slew Rat e ~
1. 5 ns) .
2. Charact erized but not t est ed.
MDI O1.
MDI O1, LAN0_DI S_N, LAN1_DI S_N, AUX_PWR, OSC_SEL.
Not es:
1. The input delay t est condit ions: Maximum input level = VI N = 2.7V; I nput rise/ fall t ime ( 0. 2VI N t o 0. 8VI N) = 1 ns ( Slew Rat e ~
1. 5 ns) .
2. Charact erized but not t est ed.
3. Table 11. 16 applies t o Digit al Test Pins and Pins used for Scan out during Scan operat ion.
Ti df
I nput t o Core Fall Delay
t ime
0. 2 ns 1. 3 ns I nt ernal Load 200 pF [ 2]
Ti r I nt ernal Core Rise Time 0. 03 ns 0.1 ns I nt ernal Load 200 pF [ 1] , [ 2]
Ti f I nt ernal Core Fall Time 0. 03 ns 0.1 ns I nt ernal Load 200 pF [ 1] , [ 2]
Tabl e 11.16. Di gi t al Test Por t 3.3V I / O AC El ect r i cal Char act er i st i cs
F
max
Maximum Operat ing
Frequency
312. 5 MHz Cload 16 pF [ 2]
Tor Out put Rise Time 0. 2 ns 1 ns Cload 16 pF
Tof Out put Fall Time 0. 2 ns 1 ns Cload 16 pF
Todr
Core t o Out put Rise
Delay Time
0. 2 ns 2 ns Cload 16 pF [ 2]
Todf
Core t o Out put Fall
Delay Time
0. 2 ns 2 ns Cload 16 pF [ 2]
Ti dr
I nput t o Core Rise Delay
Time
Ti df
I nput t o Core Fall Delay
Time
Ti r I nt ernal Core Rise Time 0. 03 ns 0.1 ns I nt ernal Load 200 pF [ 1] , [ 2]
Ti f I nt ernal Core Fall Time 0. 03 ns 0.1 ns I nt ernal Load 200 pF [ 1] , [ 2]
Tabl e 11.15. Di gi t al Funct i onal 3.3V I / O AC El ect r i cal Char act er i st i cs
I nt el

764
Fi gur e 11.2. Di gi t al 3.3V I / O Out put Ti mi ng Di agr am

765
11. 4. 2. 2 SMBus and I
2
C AC Speci f i cat i ons
The 82599 meet s t he SMBus AC specificat ion as defined in SMBus specificat ion version 2, sect ion 3. 1.1
( ht t p: / / www.smbus.org/ specs/ ) and t he I
2
C specificat ion.
The 82599 also support s a 400 KHz SMBus ( as a slave) and meet s t he specificat ions list ed in t he
following t able:
Not es:
1. Table 11. 17 applies t o SMBD, SMBCLK, SCL0, SDA0, SCL1 and SDA1.
Fi gur e 11.3. Di gi t al 3.3V I / O I nput Ti mi ng Di agr am
Tabl e 11.17. Suppor t f or 400 KHz SMBus
Symbol Par amet er Mi n Ty p Max Uni t s
F
SMB
SMBus Frequency 10 400 KHz
T
BUF
Time Bus Free Before New Transmission Can St art
( Bet ween St op and St art )
20 s
T
HD, STA
Hold Time Aft er St art Condit ion. Aft er This Period,
t he First Clock is Generat ed.
0. 6 s
T
SU, STA
St art Condit ion Set up Time 0. 6 s
T
SU, STO
St op Condit ion Set up Time 0. 6 sS
T
HD, DAT
Dat a in Hold Time 0 s
T
SU, DAT
Dat a in Set up Time 0. 1 s
T
LOW
SMBClk Low Time 1. 3 s
T
HI GH
SMBClk High Time 0. 6 s
I nt el

766
11. 4. 2. 3 Fl ash AC Speci f i cat i on
The 82599 is designed t o support a serial Flash. Applicable over recommended operat ing range from Ta
=
0
o
C t o + 70
o
C, VCC3P3 = 3.3V, Cload = 16 pF ( unless ot herwise not ed) . For Flash I / F t iming
specificat ions, see Table 11.18 and Figure 11. 5.
Fi gur e 11.4. SMBus I / F Ti mi ng Di agr am
Tabl e 11.18. Fl ash I / F Ti mi ng Par amet er s
Sy mbol Par amet er Mi n Ty p Max Uni t s Not e
t
SCK
FLSH_SCK Clock Frequency 0 12. 5 15 MHz [ 2]
t
RI
FLSH_SO Rise Time 2. 5 20 ns
t
FI
FLSH_SO Fall Time 2. 5 20 ns
t
WH
FLSH_SCK High Time 20 50 ns [ 1]
t
WL
FLSH_SCK Low Time 20 50 ns [ 1]
t
CS
FLSH_CE_N High Time 25 ns
t
CSS
FLSH_CE_N Set up Time 25 ns
t
CSH
FLSH_CE_N Hold Time 25 ns
t
SU
Dat a- in Set up Time 5 ns
t
H
Dat a- in Hold Time 5 ns
t
V
Out put Valid 20 ns
t
HO
Out put Hold Time 0 ns
t
DI S
Out put Disable Time 100 ns

767
11. 4. 2. 4 EEPROM AC Speci f i cat i on
The 82599 is designed t o support a st andard serial EEPROM. Applicable over recommended operat ing
range from Ta = - 0
o
C t o + 70
o
C, VCC3P3 = 3.3V, Cload = 16pF ( unless ot herwise not ed) . For EEPROM
I / F t iming specificat ionS, see Table 11. 19 and Figure 11.6.
t
EC
Erase Cycle Time per Sect or 1. 1 Seconds
t
BPC
Byt e Program Cycle Time 60 100 s
Not es:
1. 50% dut y cycle.
2. Clock is eit her 25 MHz or 26. 04 MHz divided by 2.
3. Table 11. 18 applies t o FLSH_SI , FLSH_SO, FLSH_SCK and FLSH_CE_N.
Fi gur e 11.5. Fl ash I / F Ti mi ng Di agr am
Tabl e 11.19. EEPROM I / F Ti mi ng Par amet er s
Sy mbol Par amet er Mi n Typ Max Uni t s Not e
t
SCK
EE_CK Clock Frequency 2 2. 1 MHz
t
RI
EE_DO Rise Time 2. 5 ns 2 s ns / s
t
FI
EE_DO Fall Time 2. 5 ns 2 s ns / s
t
WH
EE_CK High Time 200 250 ns
t
WL
EE_CK Low Time 200 250 ns
t
CS
EE_CS_N High Time 250 ns
t
CSS
EE_CS_N Set up Time 250 ns
t
CSH
EE_CS_N Hold Time 250 ns
t
SU
Dat a- in Set up Time 50 ns
t
H
Dat a- in Hold Time 50 ns
t
V
Out put Valid 0 200 ns
Tabl e 11.18. Fl ash I / F Ti mi ng Par amet er s
FLSH_CE_N
VIH
VIL
VIH
VIL

VIH
VIL
tcss
tWH tWL
tCSH
tCS
FLSH_SCK
VALID IN
tSU tH
FLSH_SI
VOH
VOL
HI-Z HI-Z
tHO tDIS
FLSH_SO
tv
I nt el

768
Not es:
1. Table 11. 19 applies t o EE_DI , EE_DO, EE_SK and EE_CS_N.
11. 4. 2. 5 NC- SI AC Speci f i cat i ons
The 82599 support s t he NC- SI st andard as defined in t he DMTF Net work Cont roller Sideband I nt erface
( NC_SI ) specificat ion. The NC- SI t iming specificat ions can be found in Table 11.20 and Figure 11. 7.
t
HO
Out put Hold Time 0 ns
t
DI S
Out put Disable Time 250 ns
t
WC
Writ e Cycle Time 10 ms
Fi gur e 11.6. EEPROM I / F Ti mi ng Di agr am
Tabl e 11.20. NC- SI I nt er f ace AC Speci f i cat i ons
Par amet er Sy mbol Condi t i ons Mi n. Ty p. Max . Uni t s Not es
REF_CLK Frequency 50 50+ 100 ppm MHz
REF_CLK Dut y Cycle 35 65 % 2
Clock- t o- Out
( 10pF< = cload< = 50 pF)
Tco 2. 5 12. 5 ns 1, 3
Skew Bet ween Clocks Tskew 1. 5 ns
TXD[ 1: 0] , TX_EN, RXD[ 1: 0] ,
CRS_DV, RX_ER Dat a Set up
t o REF_CLK Rising Edge
Tsu 3 ns 3
TXD[ 1: 0] , TX_EN, RXD[ 1: 0] ,
CRS_DV, RX_ER Dat a Hold
From REF_CLK Rising Edge
Thd 1 ns 3
Signal Rise/ Fall Time Tr/ Tf 1 6 ns 4
REF_CLK Rise/ Fall Time Tckr/ Tckf 0. 5 3. 5 ns
I nt erface Power- Up High
I mpedance I nt erval
Tpwrz 2 s
Tabl e 11.19. EEPROM I / F Ti mi ng Par amet er s
EE_CS_N
VIH
VIL
VIH
VIL

VIH
VIL
tcss
tWH tWL
tCSH
tCS
EE_CK
VALID IN
tSU tH
EE_DI
VOH
VOL
HI-Z HI-Z
tHO tDIS
EE_DO
tv

769
Power Up Transient I nt erval
( recommendat ion)
Tpwrt 100 ns
Power Up Transient Level
( recommendat ion)
Vpwrt - 200 200 mV
I nt erface Power- Up Out put
Enable I nt erval
Tpwre 10 ms
EXT_CLK St art up I nt erval Tclkst rt 100 ms
Not es:
1. This t iming relat es t o t he out put pins t iming while Tsu and Thd relat e t o t iming at t he input pins.
2. REF_CLK dut y cycle measurement s are made from Vckm t o Vckm. Clock skew Tskew is measured from Vckm t o Vckm of t wo
NC- SI devices and represent s maximum clock skew bet ween any t wo devices in t he syst em.
3. All t iming measurement s are made bet ween Vckm and Vm. All out put t iming paramet ers are measured wit h a capacit ive load
bet ween 10 pF and 50 pF.
4. Rise and fall t ime are measured bet ween point s t hat cross 10% and 90% of Vref ( see Table 11. 14) . The middle point s ( 50% of
Vref ) are marked as Vckm and Vm for clock and dat a, respect ively.
Fi gur e 11.7. NC- SI AC Ti mi ng Di agr am
Tabl e 11.20. NC- SI I nt er f ace AC Speci f i cat i ons ( Cont i nued)
Par amet er Sy mbol Condi t i ons Mi n. Ty p. Max . Uni t s Not es
Tsu
90%
10%
90%
10%
Vckm
Thd
SIGNALS
REF_CLK
gray = signals changing
GND
GND
Tco
Tck
Vm
I nt el

770
11. 4. 2. 6 JTAG AC Speci f i cat i on
The 82599 is designed t o support t he I EEE 1149.1 st andard. The following t iming specificat ions are
applicable over recommended operat ing range from Ta = 0
o
C t o + 70
o
C, VCC3P3 = 3. 3V, Cload =
16 pF ( unless ot herwise not ed) . For JTAG I / F t iming specificat ions, see Table 11.21 and Figure 11. 8.
Not es:
1. Table 11. 21 applies t o JTCK, JTMS, JTDI and JTDO.
2. Timing measured relat ive t o JTCK reference volt age of VCC3P3/ 2.
11. 4. 2. 7 MDI O AC Speci f i cat i on
The 82599 is designed t o support t he MDI O specificat ions defined in I EEE 802.3 clause 22. The
following t iming specificat ions are applicable over recommended operat ing range from Ta = 0
o
C t o + 70
o
C, VCC3P3 = 3. 3V, Cload = 16 pF ( unless ot herwise not ed) . For MDI O I / F t iming specificat ions, see
Table 11. 22, Figure 11.9 and Figure 11.10.
Tabl e 11.21. JTAG I / F Ti mi ng Par amet er s
t
JCLK
JTCK Clock Frequency 10 MHz
t
JH
JTMS and JTDI Hold Time 10 ns
t
JSU
JTMS and JTDI Set up Time 10 ns
t
JPR
JTDO Propagat ion Delay 15 ns
Fi gur e 11.8. JTAG AC Ti mi ng Di agr am
Tjsu
JTMS
JTDI
JTDO
Tjh
Tjclk
JTCK
Tjpr

771
Not es:
1. Table 11. 22 applies t o MDI O0, MDC0, MDI O1 and MDC1.
2. Timing measured relat ive t o MDC reference volt age of 2. 0V ( Vih) .
Tabl e 11.22. MDI O I / F Ti mi ng Par amet er s
t
MCLK
MDC Clock Frequency 2. 4 24 MHz
t
MH
MDI O Hold Time 10 ns
t
MSU
MDI O Set up Time 10 ns
t
MPR
MDI O Propagat ion Delay 10 30 ns
Fi gur e 11.9. MDI O I nput AC Ti mi ng Di agr am
Fi gur e 11.10.MDI O Out put AC Ti mi ng Di agr am
Tmsu Tmh
Tmclk
Tmpr
MDIO
Tmclk
MDC
I nt el

772
11. 4. 2. 8 Reset Si gnal s
For power- on indicat ion, t he 82599 can eit her use an int ernal power- on circuit , which monit ors t he 1.2V
power supply, or ext ernal reset using t he LAN_PWR_GOOD pin. The POR_BYPASS pin defines t he reset
source ( when high, t he device uses t he LAN_PWR_GOOD pad as power- on indicat ion) .
The t iming bet ween t he power- up sequence and t he different reset signals when using t he int ernal
power indicat ion is described in Sect ion 11. 3.1.1.
The BYPASS mode is described in Sect ion 11.4.2. 8. 1.
A schemat ic of t he power- on logic can be found in Figure 11.11:
11.4.2.8.1 Pow er - On Reset BYPASS
When assert ing t he POR_BYPASS pad, t he 82599 uses t he LAN_PWR_GOOD pin as power- on indicat ion.
Ot herwise, t he 82599 uses an int ernal power on det ect ion circuit in order t o generat e t he int ernal
power on reset signal.
Table 11. 23 list s t he t iming for t he ext ernal power- on signal.
LAN_PWR_GOOD and POR_BYPASS are 3.3V ( LVTTL) digit al I / Os. Their charact erist ics are described in
Sect ion 11.4. 1. 2.
Fi gur e 11. 11.Pow er - On Reset Logi c
Tabl e 11.23. Ex t er nal Reset Speci f i cat i on
Sy mbol Ti t l e Descr i pt i on Mi n Max Uni t s
Tlpgw LAN_PWR_GOOD Minimum Widt h Minimum widt h for LAN_PWR_GOOD. 10 n/ a s
Tlpg- per LAN_PWR_GOOD High Set up Relat ive t o PCI e power good. 100 n/ a ms
Tlpg LAN_PWR_GOOD High Hold
Hold t ime following power- up ( power
supplies in accept able operat ing
range) .
40 80 ms
Internal
POR
circuit
pad
pad
LAN_PWR_GOOD
POR_BYPASS
Device power-on
Power-On logic

773
11.4.3 PCI e I nt er f ace AC/ DC Speci f i cat i on
The 82599 PCI e int erface support s t he elect rical specificat ions defined in:
PCI Express* 2. 0 Card Elect romechanical Specificat ion.
PCI Express* 2. 0 Base Specificat ion, Chapt er 4.
Not e: Reference clock specificat ions are det ailed in bot h t he base and CEM specificat ion. Please
consult bot h specificat ions t o underst and t he full set of requirement s. Sect ions 4.3. 7 ( Base
specificat ion) and 2.1.3 ( CEM specificat ion) in part icular.
11.4.4 Net w or k ( MAUI ) I nt er f ace AC/ DC Speci f i cat i on
11. 4. 4. 1 KR I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 10GBASE- KR elect rical specificat ion defined in I EEE802. 3ap
clause 72.
11. 4. 4. 2 SFI + I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he SFI elect rical specificat ion defined in t he SFI + MSA ( SFF
Commit t ee SFF- 8431) .
11. 4. 4. 3 KX4 I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 10GBASE- KX4 elect rical specificat ion defined in I EEE802. 3ap
clause 71.
11. 4. 4. 4 BX4 I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 10GBASE- BX4 elect rical specificat ion defined in PI CMG 3. 1.
11. 4. 4. 5 CX4 I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 10GBASE- CX4 elect rical specificat ion defined in I EEE802.3ak
clause 54.
11. 4. 4. 6 XAUI I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 10G XAUI elect rical specificat ion defined in I EEE802.3ae clause
47.
11. 4. 4. 7 KX I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 1000BASE- KX elect rical specificat ion defined in I EEE802. 3ap
clause 70.
11. 4. 4. 8 BX I nt er f ace AC/ DC Speci f i cat i on
The 82599 MAUI int erface support s t he 1000BASE- BX elect rical specificat ion defined in PI CMG
3. 1
specificat ion.
I nt el

774
11.4. 5 Ser Des Cr y st al / Ref er ence Cl ock Speci f i cat i on
The 82599 SerDes clock can be supplied eit her by connect ing an ext ernal different ial oscillat or of 25
MHz or an ext ernal 25 MHz cryst al. SerDes clock frequency is set by t he OSC_FREQ_SE pin and cryst al
vs. oscillat or are select ed by t he OSC_SEL pin.
Figure 11.12 and Figure 11. 13 show connect ion opt ions t o t he REFCLKI N_p/ _n pins by using a cryst al
or by using an ext ernal oscillat or ( PECL or CML) . These schemes are not part of The 82599
specificat ions but rat her examples t hat meet t he required specificat ion.
11. 4. 5. 1 Ser Des Cr y st al Speci f i cat i on
Fi gur e 11.12.Cr yst al Connect i vi t y
Tabl e 11.24. Ser Des Cr yst al Speci f i cat i ons
Par amet er Name Sy mbol Recommended Val ue Condi t i ons
Frequency f
o
25. 000 [ MHz] @25 [ C]
Vibrat ion Mode Fundament al
Cut AT
Operat ing / Calibrat ion Mode Parallel
Frequency Tolerance @25 C Df/ f
o
@25 C 30 [ ppm] @25 [ C]
Temperat ure Tolerance Df/ f
o
30 [ ppm]
Operat ing Temperat ure T
opr
- 20 t o + 70 [ C]
Non Operat ing Temperat ure Range T
opr
- 40 t o + 90 [ C]
Equivalent Series Resist ance ( ESR) ESR 50 [ O] maximum @25 [ MHz]
Crystal
C1
C2
Cstray
(board & package traces)
LAN Controller
C load = + C stray
C1 x C2
C1 + C2
Lm Rs
Cm
Co
ESR = Rs x ( 1 + )
2
C o
C load
Equivalent Series Resistor
REFCLKIN_n REFCLKIN_p
25 MHz

775
11. 4. 5. 2 Ser Des Ref er ence Cl ock Speci f i cat i on
Load Capacit ance C
load
20 [ pF]
Shunt Capacit ance C
o
6 [ pF] maximum
Pullabilit y From Nominal Load
Capacit ance
Df/ C
load
15 [ ppm/ pF] maximum
Max Drive Level D
L
750 [ W]
I nsulat ion Resist ance I R 500 [ MW] minimum @ 100V DC
Aging Df/ f
o
5 [ ppm/ year]
Ext ernal Capacit ors C
1
, C
2
20 [ pF]
Board Resist ance R
s
0. 1 [ W]
Fi gur e 11.13.Ex ampl e Di agr am f or Ex t er nal PECL or CML Osci l l at or Connect i vi t y
Tabl e 11.25. I nput Ref er ence Cl ock El ect r i cal Char act er i st i cs
Sy m Par amet er Mi n Ty p Max Uni t Comment s
f Frequency 25 MHz
Af Frequency Variat ion - 100 + 100 ppm
DC Dut y Cycle 40 60 %
Tr Rise Time ( 20% - 80%) 300 1000 ps
Tf Fall Time ( 20% - 80%) 300 1000 ps
AMP
Different ial Peak- t o- Peak
Amplit ude
0. 6 1. 25 V
Tabl e 11.24. Ser Des Cr yst al Speci f i cat i ons
Par amet er Name Sy mbol Recommended Val ue Condi t i ons
100nF
100nF
26
26
147 147
LAN Controller
100nF
100nF
REFCLKIN_p
100
REFCLKIN_n
Q
QN
25MHz PECL
OSCILLATOR
100
Q
QN
25MHz CML
OSCILLATOR
100
REFCLKIN_p
100
REFCLKIN_n
LAN Controller
1.5pF
1.5pF
I nt el

776
Not e: I nt el recommends designing t o t he high- speed serial p- noise specificat ion allowing for
maximum flexibilit y wit h link configurat ion opt ions.
R
Different ial Terminat ion
Resist ance
100 O
C AC Coupling 100 nF
Cin I nput Capacit ance 1. 5 pF
DJ P2P
Det erminist ic Peak- t o- Peak
Jit t er
10 ps
p- noise
Phase Noise ( high- speed
serial - KR and SFI )
- 145 dBc/ Hz
See Figure 11. 15 for
phase noise graph
p- noise
Phase Noise ( non- high
speed serial)
- 136 dBc/ Hz
See Figure 11. 16 for
phase noise graph
Fi gur e 11.14.Ex t er nal Cl ock Ref er ence Ti mi ng
Tabl e 11.25. I nput Ref er ence Cl ock El ect r i cal Char act er i st i cs
Sy m Par amet er Mi n Typ Max Uni t Comment s
RCLKINTP-RCLKINTN
t
2
t
2
t
1
t
4
t
3
t
3
DC
1 / f
Tr Tf Delta f
RCLKINTP-RCLKINTN
t
2
t
2
t
1
t
4
t
3
t
3
DC
1 / f
Tr Tf Delta f

777
Fi gur e 11. 15.Max i mum Ex t er nal Osci l l at or Phase Noi se as a Funct i on of Fr equency ( Hi gh-
Speed Ser i al )
I nt el

778
Fi gur e 11.16.Ref cl k Phase Noi se as a Funct i on of Fr equency ( Non- Hi gh Speed Ser i al )
11.5 Pack age
11.5. 1 Mechani cal
The 82599 is assembled in a 25 x 25 FCGBA package wit h an 8- layer subst rat e.
11.5. 2 Ther mal
For t he 82599' s package t hermals please refer t o Sect ion 13.0.
11.5. 3 El ect r i cal
Package elect rical models are part of t he I BI S files.
Tabl e 11.26. Pack age Speci f i cat i ons
Body Si ze Bal l Count Bal l Pi t ch Bal l Mat r i x Subst r at e
25x25 mm
2
576 1 mm 24 X 24 Eight Layers

779
11.5.4 Mechani cal Pack age
11.6 Dev i ces Suppor t ed
11.6.1 Fl ash
The 82599 support s Flash devices wit h a SPI int erface. Sect ion 11.27 list s t he specific Flash t ypes
support ed,
Not es:
Fi gur e 11.17.Mechani cal Pack age
Tabl e 11.27. Suppor t ed Fl ash Dev i ces
Densi t y At mel PN STM PN
1 Mb AT25F1024N- 10SI - 2. 7 or AT25FS010 M25P10-AVMN6T
2 Mb AT25F2048N- 10SI - 2. 7 M25P20-AVMN6T
8 Mb M25P80-AVMN6T
16 Mb M25P16-AVMN6T
32 Mb M25P32-AVMN6T
I nt el

780
1. Since all SPI Flash memories have similar int erface charact erist ics, t here is no need t o t est t he int erface wit h all t he proposed
t ypes. I t s accept able t o t est t he largest Flash.
2. All support ed Flashes have an address size of 24 bit s.
11.6. 2 EEPROM
Sect ion 11.28 list s t he specific EEPROM devices support ed.
11. 6. 2. 1 Mi ni mum EEPROM Si zes
No manageabilit y - 16 KB ( 128 Kb)
No manageabilit y, SFI int erface - 16 KB ( 128 Kb)
SMBus/ NC- SI - 16 KB ( 128 Kb)
11. 6. 2. 2 Recommended EEPROM Si zes
No manageabilit y - 16 KB ( 128 Kb)
No manageabilit y, SFI int erface - 16 KB ( 128 Kb)
SMBus/ NC- SI - 32 KB ( 256 Kb)
Tabl e 11.28. Suppor t ed EEPROM Devi ces
Densi t y [ Kb] At mel PN STM PN Cat al yst PN
16 AT25160AN- 10SI - 2. 7 M95160WMN6T CAT25C16S-TE13
128 AT25128AN- 10SI - 2. 7 M95128WMN6T CAT25CS128-TE13
256 AT25256AN- 10SI - 2. 7 M95256WMN6T
Desi gn Consi der at i ons and Gui del i nes I nt el

781
12. 0 Desi gn Consi der at i ons and Gui del i nes
This sect ion provides recommendat ions for select ing component s, connect ing int erfaces, dealing wit h
special pins, and layout guidance.
Some unused int erfaces should be t erminat ed wit h pullup or pull- down resist ors. These are indicat ed
in Sect ion 2. 0 or reference schemat ics. There are reserved pins, ident ified as RSVD_3P3, RSVD_1P2
and RSVD_VSS. The 82599 might ent er special t est modes unless t hese st rapping resist ors are in
place.
Some unused int erfaces must be left open. Do not at t ach pullup or pull- down resist ors t o any balls
ident ified as No Connect or Reserved No Connect .
12.1 Connect i ng t he PCI e I nt er f ace
The 82599 connect s t o t he host syst em using a PCI e int erface. The int erface can be configured t o
operat e in several link modes. These are det ailed in Sect ion 3. 0. A link bet ween t he port s of t wo
devices is a collect ion of lanes. Each lane has t o be AC- coupled bet ween it s corresponding t ransmit t er
and receiver; wit h t he AC- coupling capacit or locat ed close t o t he t ransmit t er side ( wit hin 1 inch) . Each
end of t he link is t erminat ed on t he die int o nominal 100 O different ial DC impedance. Board
t erminat ion is not required.
Refer t o t he PCI Express* Base Specificat ion, Revision 2.0 and PCI Express* Card Elect romechanical
Specificat ion, Revision 2. 0.
12.1.1 Li nk Wi dt h Conf i gur at i on
The 82599 support s link widt hs of x8, x4, x2, or x1 as det ermined by t he PCI e init configurat ion. The
configurat ion is loaded using bit s 9: 4 in t he Max Link Widt h field of t he Link Capabilit ies regist er
( 0xAC) . The 82599 default is t he x8 link widt h.
During link configurat ion, t he plat form and t he 82599 negot iat e a common link widt h. I n order for t his
t o work, t he select ed maximum number of PCI e lanes must be connect ed t o t he host syst em.
12.1.2 Pol ar i t y I nver si on and Lane Rev er sal
To ease rout ing, designers have t he flexibilit y t o use t he lane reversal modes support ed by t he t he
82599. Polarit y inversion can also be used, since t he polarit y of each different ial pair is det ect ed during
t he link t raining sequence.
When lane reversal is used, some of t he downshift opt ions are not available. For a descript ion of
available combinat ions, see Sect ion 3. 0.
I nt el
82599 10 GbE Cont r ol l er Desi gn Consi der at i ons and Gui del i nes
782
12. 1. 3 PCI e Ref er ence Cl ock
For LOM designs, t he device requires a 100 MHz different ial reference clock, denot ed PE_CLK_p and
PE_CLK_n. This signal is t ypically generat ed on t he syst em board and rout ed t o t he PCI e port . For add-
in cards, t he clock is furnished at t he PCI e connect or.
The frequency t olerance for t he PCI e reference clock is + / - 300 ppm.
12. 1. 4 PCI e Anal og Bi as Resi st or
For proper biasing of t he PCI e analog int erface, a 24.9 O 0.5% resist or needs t o be connect ed from t he
PE_RBI AS t o t he VCC1P2 supply. The PE_RSENSE pin should be connect ed direct ly t o PE_RBI AS, as
close as possible t o t he 24.9 O resist or pad. To avoid noise coupled ont o t his reference signal, place t he
bias resist or close t o t he 82599 and keep t races as short as possible.
12.1. 5 Mi scel l aneous PCI e Si gnal s
The 82599 signals power management event s t o t he syst em by pulling low t he PE_WAKE# signal. This
signal operat es like t he PCI PME# signal. Not e t hat somewhere in t he syst em, t his signal has t o be
pulled high t o t he auxiliary 3. 3 V supply rail.
The PE_RST# signal, which serves as t he familiar reset funct ion for t he 82599, needs t o be connect ed
t o t he host syst ems corresponding signal.
12. 1. 6 PCI e Lay out Recommendat i ons
For informat ion regarding t he PCI e signal rout ing, refer t o t he I nt el
82599 10 GbE Cont roller

Checklist s for furt her layout guidance.
12.2 Connect i ng t he MAUI I nt er f aces
The 82599 has t wo high speed net work int erfaces t hat can be configured in different 1 Gb/ s and
10 Gb/ s modes ( CX4, KX, KX4, KR, XAUI , KR, and SFI + ) . Choose t he appropriat e configurat ion for your
syst em configurat ion.
12.2. 1 MAUI Channel s Lane Connect i ons
For BX, KX, KR, and SFI + connect ions, only t he first lane needs t o be connect ed ( TX0_L0_p, TX0_L0_n;
RX0_L0_p, RX0_L0_n) . For t he remainder of t he int erfaces, all four different ial pairs need t o be
connect ed for each direct ion.
These signals are 100 O t erminat ed different ial signals t hat are AC coupled near t he receiver. Place t he
AC coupling capacit ors less t han one inch away from t he receiver. For recommended capacit or values,
consult t he relevant I EEE 802.3 specificat ions and/ or t he relevant PI CMG specificat ions. Capacit or size
should be small t o reduce parasit ic induct ance. Use X5R or X7R, + 10% capacit ors in a 0402 or 0201
package size. For 10 Gb/ s KR, t he recommended package size for t he required AC coupling capacit ors is
t he 0201 package size.
Not e: SFI + board t races generally do not require AC coupling capacit ors because t hey are normally
int egrat ed int o t he SFP+ module.

783
12.2.2 MAUI Bi as Resi st or
For proper biasing of t he MAUI analog int erface, a 1 KO 0.5% resist or needs t o be connect ed bet ween
t he XA_RBI AS and XA_SENSE pins. To avoid noise coupled ont o t his reference signal, place t he bias
resist or close t o t he 82599 and keep t races as short as possible.
12.2.3 XAUI , KX/ KR, BX4, CX4, BX and SFI + Lay out Recommendat i ons
This sect ion provides recommendat ions for rout ing t he high- speed int erface. The int ent is t o rout e t his
int erface opt imally using FR4 t echnology. I nt el has t est ed and charact erized t hese recommendat ions.
12.2.4 Boar d St ack - Up Ex ampl e
Print ed Circuit Boards ( PCBs) for t hese designs t ypically have six, eight , or more layers. Alt hough, t he
t he 82599 does not dict at e st ackup, t he following examples are of t ypical st ackup opt ions.
Microst rip Example:
Layer 1 is a signal layer.
Layer 2 is a ground layer.
Layer 3 is used for power planes.
Layer 4 is a signal layer. Careful rout ing is necessary t o prevent crosst alk wit h layer 5.
Layer 5 is a signal layer. Careful rout ing is necessary t o prevent crosst alk wit h layer 4.
Layer 6 is used for power planes.
Layer 7 is a signal ground layer.
Not e: Layers 4 and 5 should be used most ly for low- speed signals because t hey are referenced t o
pot ent ially noisy power planes t hat might also be slot t ed.
St ripline Example:
Layer 2 is a ground layer.
Layer 4 is used for power planes
Layer 5 is used for power planes
Layer 7 is a signal ground layer.
Not e: To avoid t he effect of t he pot ent ially noisy power planes on t he high- speed signals, use offset
st ripline t opology. The dielect ric dist ance bet ween t he power plane and signal layer should be
t hree t imes t he dist ance bet ween ground and signal layer.
This board st ackup configurat ion can be adj ust ed t o conform t o your company' s design rules.
I nt el
784
12.2. 5 Tr ace Geomet r i es
Two t ypes of t races are included: Microst rip* or St ripline* t races. St ripline t ransmission line
environment s offer advant ages t hat improve performance. Microst rip t race geomet ries can be used
successfully, but it is our recommendat ion t hat st ripline geomet ries be followed.
Sect ion 12.1 list s t he height pair- t o- pair spacing differences t hat are recommended bet ween St ripline
and Microst rip geomet ries. Cont act your I nt el sales represent at ive for more det ails.
Tabl e 12- 1. Mi cr ost r i p Tr ace Di mensi ons f or SFI Usi ng Di f f er ent Di el ect r i c Mat er i al s
Tr ace
Type
Di el ect r i c
Mat er i al
Di el ect r i c
Const ant
( dk or Er )
2.5 GHz t o
5 GHz
Di ssi pat i on
Fact or ( df
or Loss
Tangent )
Di el ect r i c
Lay er
Thi ck ness ( or
Hei ght )
( mm)
Copper Tr ace
Thi ck ness
Af t er Pl at i ng
1

( mm)
1. Post - plat ing copper t hickness t olerance 0. 3 mils ( 0. 00762 mm) .
Max SFI Tx
Tr ace
Lengt h
( mm)
Max SFI Rx
Tr ace
Lengt h
( mm)
2
2. Short er SFI + t races are preferred; however, longer t races might be t olerable depending on t he dielect ric mat erial. Cont act your
I nt el sales represent at ive for det ailed informat ion about maximum SFI + t race lengt hs and about various suit able dielect ric
mat erials.
Mai n SFI
Rout i ng Tr ace
Wi dt h
( mm)
Mai n SFI
Rout i ng I n-
Pai r Tr ace
Separ at i on
( mm)
SFI Br eak out
Rout i ng Tr ace
Wi dt h
3
( mm)
3. For SFI t races t hat are 9 mils wide or less wit h 12 mils separat ion or less: Narrow breakout t race widt hs wit h smaller in- pair
t race separat ion dist ances are discouraged. Narrow SFI t races and/ or less in- pair separat ion should NOT be required when t he
main t race rout e is 9 mils wide or less. This is especially t rue for t he SFI Tx t race rout es.
SFI Br eak out
Rout i ng I n- Pai r
Tr ace Separ at i on
( mm)
3
Microst r ip
Nelco
N4000- 13
3. 7 0. 009
0. 1905
( 7. 5 mils)
0. 0508
( 2. 0 mils)
41. 148
( 1620 mils)
43. 434
( 1710 mils)
0. 3048
( 12 mils)
0. 4064
( 16 mils)
0. 1778
( 7 mils)
0. 1397
( 5. 5 mils)
Microst r ip
Nelco
N4000- 13
3. 7 0. 009
0. 1524
( 6. 0 mils)
0. 0508
( 2. 0 mils)
32. 385
( 1275 mils)
34. 036
( 1340 mils)
0. 2286
( 9. 0 mils)
0. 3048
( 12 mils)
0. 1880
2
( 7. 4 mils)
0. 1905
( 7. 5 mils)
Microst r ip
Panasonic
Megt ron6
3. 6 0. 003
0. 2032
( 8. 0 mils)
0. 0508
( 2. 0 mils)
41. 148
( 1620 mils)
43. 434
( 1710 mils)
0. 3302
( 13 mils)
0. 4064
( 16 mils)
0. 2083
( 8. 2 mils)
0. 1524
( 6 mils)
Microst r ip
Panasonic
Megt ron6
3. 4 0. 003
0. 1524
( 6. 0 mils)
0. 0508
( 2. 0 mils)
36. 739
( 1450 mils)
38. 780
( 1530 mils)
0. 2667
( 10. 5 mils)
0. 4572
( 18 mils)
0. 2032
( 8 mils)
0. 1905
( 7. 5 mils)
Microst r ip I sola FR408 3. 63 0. 013
0. 1534
( 6. 04 mils)
0. 0508
( 2. 0 mils)
24. 384
( 960 mils)
25. 654
( 1010 mils)
0. 2540
( 10 mils)
0. 4318
( 17 mils)
0. 1905
( 7. 5 mils)
0. 1854
( 7. 3 mils)
0. 1839
( 7. 24 mils)
0. 0508
( 2. 0 mils)
19. 05
( 750 mils)
20. 32
( 800 mils)
0. 2921
( 11. 5 mils)
0. 4064
( 16. 0 mils)
0. 1778
( 7 mils)
0. 1448
( 5. 7 mils)
0. 1636
( 6. 44 mils)
0. 0508
( 2. 0 mils)
17. 018
( 670 mils)
18. 034
( 710 mils)
0. 2540
( 10 mils)
0. 3683
( 14. 5 mils)
0. 1905
( 7. 5 mils)
0. 1803
( 7. 1 mils)
Microst r ip
FR4 2116,
2- ply
4. 2
4
0. 02
3
0. 2286
3
( 9. 0 mils)
0. 0508
( 2. 0 mils)
19. 558
( 770 mils)
20. 574
( 810 mils)
0. 3175
( 12. 5 mils)
0. 3759
( 14. 8 mils)
0. 1778
( 7. 0 mils)
0. 1422
( 5. 6 mils)
Microst r ip
FR4 2116,
2- ply
4. 2
3
0. 02
3
0. 2286
3
( 9. 0 mils)
0. 04572
( 1. 8 mils)
19. 30
( 760 mils)
20. 32
( 800 mils)
0. 3200
( 12. 6 mils)
0. 3683
( 14. 5 mils)
0. 1778
( 7. 0 mils)
0. 1372
( 5. 4 mils)
Microst r ip
FR4 2113,
2- ply
4. 0 0. 021
0. 2032
( 8. 0 mils)
0. 04826
( 1. 9 mils)
17. 02
( 670 mils)
18. 03
( 710 mils)
0. 292
( 11. 5 mils)
0. 356
( 14. 0 mils)
0. 1674
( 6. 6 mils)
0. 1371
( 5. 4 mils)
Microst r ip
FR4 2113,
2- ply
4. 05 0. 021
0. 2032
( 8. 0 mils)
0. 04572
( 1. 8 mils)
17. 53
( 690 mils)
18. 54
( 730 mils)
0. 305
( 12. 0 mils)
0. 419
( 16. 5 mils)
0. 1701
( 6. 7 mils)
0. 1397
( 5. 5 mils)

785
4. 2116 FR4 manufact ured by different vendors might have different dielect ric const ant s, dissipat ion fact ors, different dielect ric
t hicknesses ( height ) , or a combinat ion of t hese. Please check wit h your circuit board supplier t o obt ain t he correct propert ies
( at 5 GHz) for t he 2116 FR4 t hat you plan t o use. I f your 2116 FR4 has different elect rical propert ies or different nominal
t hickness, t he t race widt hs and t race separat ion might need t o be adj ust ed.
Fi gur e 12- 1. Di f f er ent i al Pai r Spaci ng
Stripline pair-to-pair
spacing should be > 6 x h
(dielectric height)
h dielectric
height
Microstrip pair-to-pair spacing should
be > 7 x h (dielectric height)
h dielectric
height
I nt el
786
12.2. 6 Ot her Hi gh- Speed Si gnal Rout i ng Pr act i ces
These layout and rout ing recommendat ions are applicable for t he MAUI int erfaces of t he t he 82599.
I n order t o keep impedance cont inuit y consist ent around signal via ant i- pad regions, I nt el recommends
adding t he ant i- pad diamet er requirement of 9t o 12 mils clearance t o vias t o ground and power. This
ensures t hat t he impedance variance is minimized. On plane layers, pairs of signal vias should share
t he same enlarged ellipt ical or oval ( merged) ant i- pads.
Enforce different ial symmet ry, even for grounds. Along wit h ensuring t hat t he MAUI int erface is rout ed
symmet rically in t erms of signal rout ing and balance, we also recommend t hat ground pat hs be rout ed
symmet rically. This helps reduce t he imbalance t hat can occur in t he different ret urn current pat hs.
I n cases where t here is a via and an AC coupling capacit or on t he same t race, t he signal t race bet ween
t he via and t he AC coupling capacit ors on t he MAUI int erface, t here is an int rinsic impedance mismat ch
because of t he required capacit ors. To minimize t he overall impact of having vias and AC coupling
capacit ors, we recommend t hat bot h via and capacit or layout pad be placed wit hin 100 mils of each
ot her.
Not e: For KR int erfaces, t his is not recommended unless simulat ions are performed and t he result s
confirm minimal impact t o impedance, insert ion loss, insert ion loss deviat ion, and crosst alk.
I t is best t o use a 0402 capacit or or smaller for t he AC coupling component s on t he MAUI int erface. The
pad geomet ries for a 0402 or smaller component s lend t hemselves t o maint aining a more consist ent
t ransmission line environment . For 10 Gb/ s KR, t he recommended package size for t he required AC
coupling capacit ors is t he 0201 package size. Not e t hat SFI + board t races normally do not require AC
coupling capacit ors. Cont act your I nt el sales represent at ive for more det ails.
Not e: To reduce shunt capacit ance from t he AC capacit ors solder- pads t o t he reference plane
beneat h t he solder- pads, we recommend t hat you void t he reference plane t hat is direct ly
under t he capacit or. The reference plane void should have t he same shape as t he capacit or
and it s solder pads. The size of t he reference plane void should be slight ly larger t han t he
size of t he capacit or and it ' s solder pad. I f you have access t o a 3- dimensional field solver, it
can and should be used t o det ermine t he opt imal size and shape for t he reference plane void
under each capacit or. To prevent noise problems, be careful not t o rout e any t races across t he
capacit or- shaped voids in t he reference plane.

787
Not e: The t op layout of Figure 12- 2 shows accept able guidelines. The bot t om layout of Figure 12- 2
shows t he preferred guidelines.
Use the smallest possible vias on board to optimize the impedance for the MAUI interface.
Fi gur e 12- 2. Ref er ence Pl ane Voi ds Under AC Caps and AC Caps Separ at ed t o Reduce St r ay
Capaci t ance Bet w een Caps
Differential traces are loosely
coupled, to prevent
impedance mismatches when
the differential traces separate
near the capacitors.
coupled, to prevent
impedance mismatches when
the differential traces separate
Below capacitors
in the areas
indicated it is
preferred to void
the plane
immediately under
component.
Capacitors should
be separated by >
30 mils
Differential traces are
loosely coupled, to
prevent impedance
mismatches when the
differential traces separate
coupled, to prevent impedance
mismatches when the
differential traces separate near
the capacitors.
Below capacitors in the
areas indicated it is
preferred to void the
plane immediately under
component.
Capacitors should
be separated by >
30 mils
I nt el
788
12. 2. 6. 1 Vi a Usage
Use vias t o opt imize signal int egrit y. Figure 12- 3 shows correct via usage. Figure 12- 4 shows t he t ype
of t opology t hat should be avoided.
Fi gur e 12- 3. Cor r ect Vi a Usage
Fi gur e 12- 4. I ncor r ect Vi a Usage

789
Any via st ubs on t he KR and/ or SFI + different ial signal t races must be less t han 35 mils in lengt h.
Keeping KR and SFI + signal via st ubs less t han or equal t o 20 mils is preferable.
Not e: Vias on SFI + t races are not recommended. SFI + Tx signals must not have any vias. Refer t o
t he SFI + layout sect ion for more informat ion.
Place ground vias adj acent t o signal vias used for t he MAUI int erface. Do NOT embed vias bet ween t he
high- speed signals, but place t hem adj acent t o t he signal vias ( see Figure 12- 5) . This helps t o creat e a
bet t er ground pat h for t he ret urn current of t he AC signals, which also helps address impedance
mismat ches and EMC performance.
We recommend t hat , in t he breakout region bet ween t he via and t he capacit or pad, you t arget a Z0 for
t he via t o capacit or t race equal t o 50 O. This minimizes impedance imbalance.
Fi gur e 12- 5. No Vi as Bet w een Hi gh- Speed Tr aces i n t he Same Di f f er ent i al Pai r
Incorrect usage of
via buried between
differential signals
I nt el
790
12. 2. 7 Ref er ence Pl anes
Do not cross plane split s wit h t he MAUI high- speed different ial signals. This causes impedance
mismat ches and negat ively affect s t he ret urn current pat hs for t he board design and layout . Refer t o
Figure 12- 6.
Traces should not cross power or ground plane split s if at all possible. Traces should st ay seven t imes
t he dielect ric height away from plane split s or voids. I f t races must cross split s, capacit ive coupling
should be added t o st it ch t he t wo planes t oget her in order t o provide a bet t er AC ret urn pat h for t he
high- speed signals. To be effect ive, t he capacit ors should be have low ESR and low equivalent series
induct ance.
Not e: Even wit h plane split st it ching capacit ors, crossing plane split s is ext remely high risk for
10 Gb/ s KR and 10 Gb/ s SFI + designs.
Fi gur e 12- 6. Do Not Cr oss Pl ane Spl i t s
Differential signals should
not cross splits in either
GND or PWR plane
reference.

791
Keep Rx and Tx separat e. This helps t o minimize crosst alk effect s since t he TX and RX signals are NOT
synchronous. This is t he more nat ural rout ing met hod and occurs wit hout much designer int erference.
We recommend t hat t he MAUI signals st ay at least seven t imes t he dielect ric height away from any
power or ground plane split ( see Figure 12- 7) . This improves impedance balance and ret urn current
pat hs.
I f a high- speed signal needs t o reference a power plane, t hen ensure t hat t he height of t he secondary
( power) reference plane is at least 3 x t he height of t he primary ( ground) reference plane.
12. 2. 8 Di el ect r i c Weav e Compensat i on
Because t he dielect ric weave can cause different propagat ion velocit y on each of t he t races wit hin one
different ial pair, I nt el recommends using one or more t race rout ing t echniques t hat can minimize signal
skewing caused by t he weave:
I nst ead of rout ing t races parallel t o eit her X or Y axis, t races should be rout ed at an angle t o t he
weave, and t he angle should be bet ween 11 and 45 degrees. Rout ing bot h t races wit hin each
different ial pair at an angle, wit h respect t o t he dielect ric weave, minimizes t he signal skew wit hin
each different ial pair.
Fi gur e 12- 7. Tr aces Shoul d St ay Seven Ti mes t he Di el ect r i c Hei ght Aw ay Fr om Pl ane Spl i t s
Or Voi ds
Differential signals should be > 7
x dielectric height away from
PWR and GND plane splits.
I nt el
792
The cent er- t o- cent er pit ch of t he t races wit hin t he diff pairs can be mat ched t o t he weave pit ch of
t he dielect ric mat erial. I f you plan t o uses a woven glass/ epoxy dielect ric mat erial, check wit h t he
mat erial supplier t o find out t he glass weave pit ch prior t o doing final different ial t race rout ing.
Traces can be rout ed t o include a series of 45 degree bends, wit h bends separat ed by several t ent hs
of an inch, t o shift t he t races in st eps by a few millimet ers each t ime. There should be an equal
number left t urns and right t urns along t he lengt h of t he t races. Trace segment s bet ween each pair
of bends should be different lengt hs ( if t hey are all t he same lengt h it could creat e an undesirable
resonance in t he line) .
I f different ial t races must be st raight and ort hogonal t o t he out line of t he circuit board for most of
t heir rout ed lengt hs, t hen rot at e CAD art work by 15, wit h respect t o t he weave of t he circuit
boards dielect ric weave.
12.2. 9 I mpedance Di scont i nui t i es
I mpedance discont inuit ies cause unwant ed signal reflect ions. Minimize vias ( signal t hrough holes) and
ot her t ransmission line irregularit ies. A t ot al of six t hrough holes ( a combinat ion of vias and connect or
t hrough holes) bet ween t he t wo chips connect ed by t he MAUI int erface is a reasonable maximum
budget for each different ial signal pat h. For example, if a backplane syst em has a t ot al of t hree boards
( blade server, mid- plane, and swit ch blade) in t he different ial signal pat h, t hen SFI + Tx must not have
any signal vias and SFI + Rx should not have more t han one signal via per SFI + signal t race. For t his
purpose, signal pin t hrough- holes for board connect ors are also count ed as signal vias. Signal via pads
on unconnect ed plane layers can be removed t o reduce capacit ance bet ween t he signal via and t he
surrounding met al plane. Alt ernat ively, t he ant i- pad diamet er can be increased t o provide 9t o 12 mils
clearance bet ween signal via ( pads) and power or gound.
12.2. 10 Reduci ng Ci r cui t I nduct ance
Traces should be rout ed over a cont inuous reference plane wit h no int errupt ions. I f t here are vacant
areas on a reference or power plane, t he signal conduct ors should not cross t he vacant area. Rout ing
over a void in t he reference plane causes impedance mismat ches and usually increases radiat ed noise
levels. Noisy logic grounds should NOT be locat ed near or under high- speed signals or near sensit ive
analog pin regions of t he LAN silicon. I f a noisy ground area must be near t hese sensit ive signals or I C
pins, ensure sufficient decoupling and bulk capacit ance in t hese areas. Noisy logic and swit ching power
supply grounds can somet imes affect sensit ive DC subsyst ems such as analog t o digit al conversion,
operat ional amplifiers, et c.
All ground vias should be connect ed t o every ground plane; and similarly, every power via should be
connect ed t o all equally pot ent ial power planes. This helps reduce circuit induct ance. Anot her
recommendat ion is t o physically locat e grounds t o minimize t he loop area bet ween a signal pat h and it s
ret urn pat h. Rise and fall t imes should be as slow as possible while st ill meet ing t he relevant elect rical
requirement s. Because signals wit h fast rise and fall t imes cont ain many high frequency harmonics,
which can radiat e significant ly. The most sensit ive signal ret urns closest t o t he chassis ground should
be connect ed t oget her. This result s in a smaller loop area and reduces t he likelihood of crosst alk. The
effect of different configurat ions on t he amount of crosst alk can be st udied using elect ronics modeling
and simulat ion soft ware.

793
12.2.11 Si gnal I sol at i on
To maint ain best signal int egrit y, keep digit al signals far away from t he analog t races. A good rule of
t humb is no digit al signal should be wit hin 7x t o 10x dielect ric height of t he different ial pairs. I f digit al
signals on ot her board layers cannot be separat ed by a ground plane, t hey should be rout ed at a right
angle ( 90 degrees) t o t he different ial signal t races. I f t here is anot her LAN cont roller on t he board, t ake
care t o keep t he different ial pairs from t hat circuit away. The same t hing applies t o swit ching regulat or
t races.
Rules t o follow for signal isolat ion:
Separat e and group signals by funct ion on separat e board layers if possible. Maint ain a separat ion
t hat is at least seven t imes t he t hinnest adj acent dielect ric height bet ween all different ial pairs
( Et hernet ) and ot her net s, but group associat ed different ial pairs t oget her. For example, Keep Tx
signals wit h Tx signals and keep Rx signals wit h Rx signals. Not e t hat if an Rx signal is rout ed
bet ween t wo Tx signals, t he higher levels of Tx crosst alk causes t he Rx signal- t o- noise rat io t o be
worse t han if t he Rx signal is rout ed bet ween t wo ot her Rx signals.)
Over t he lengt h of t he t race run, each different ial pair should be at least seven t imes t he t hinnest
adj acent dielect ric height away from any parallel signal t races.
Physically group t oget her all component s associat ed wit h one clock t race t o reduce t race lengt h and
radiat ion.
I solat e ot her I / O signals from high- speed signals t o minimize crosst alk because crosst alk can
increase radiat ed EMI and can increase suscept ibilit y t o EMI from ot her signals.
Avoid rout ing high- speed LAN t races near ot her high- frequency signals associat ed wit h a video
cont roller, cache cont roller, processor, or ot her similar devices.
12.2.12 Pow er and Gr ound Pl anes
Good grounding requires minimizing induct ance levels in t he int erconnect ions and keeping ground
ret urns short , signal loop areas small, and locat ing decoupling capacit ors at or near power input s t o
bypass t o t he signal ret urn. This will significant ly reduce EMI radiat ion.
These guidelines reduce circuit induct ance in bot h backplanes and mot herboards:
Rout e t races over a cont inuous plane wit h no int errupt ions. Do not rout e over a split power or
ground plane. I f t here are vacant areas on a ground or power plane, avoid rout ing signals over t he
vacant area. Rout ing signals over power or ground voids increases induct ance and increases
radiat ed EMI levels.
Use dist ance and/ or ext ra decoupling capacit ors t o separat e noisy digit al grounds from analog
grounds t o reduce coupling. Noisy digit al grounds may affect sensit ive DC subsyst ems.
All ground vias should be connect ed t o every ground plane; and every power via should be
connect ed t o all power planes at equal pot ent ial. This helps reduce circuit induct ance.
Physically locat e grounds bet ween a signal pat h and it s ret urn. This will minimize t he loop area.
Avoid fast rise/ fall t imes as much as possible. Signals wit h fast rise and fall t imes cont ain many
high frequency harmonics, which can radiat e EMI .
Do not rout e high- speed signals near swit ching regulat or circuit s.
There should not be any t est - point vias or t est - point pads on KR and SFI + t races.
I t s accept able t o put ground fill or t hieving on t he t race layers, but preferably not closer t han 50
mils t o t he different ial t races and t he connect or pins.
I nt el
794
I f different ial t races must be rout ed on anot her layer, t hen t he signal vias should carry t he signal t o
t he opposit e side of t he circuit board ( t o be near t he t op of t he circuit board) ; AND if t he high- speed
signals are being rout ed bet ween t wo connect ors on t he same board, t hen before t he signal t races
reach t he second connect or, t hey must ret urn t o t he original signal layer ( before reaching t he
connect or pin) . This st rat egy keeps via st ubs short wit hout requiring back drilling.
Each t ime different ial t races make a layer t ransit ion ( pass t hrough a pair of signal vias) , t here must
be at least one ground via locat ed near each signal via. Two ground vias near each signal via is
bet t er. See Figure 12- 8 and Figure 12- 9.
Fi gur e 12- 8. Good Gr ound Vi as f or Si gnal Ret ur n Pat hs One Ret ur n Pat h Vi a Per Si gnal Vi a
GND vias
are located
near each
signal via to
improve the
current
return path.

795
I f t he circuit board fabricat ion process permit s it , it is best t o remove signal via pads on unconnect ed
met al layers. See Figure 12- 10 and Figure 12- 11.
Fi gur e 12- 9. Bet t er Gr ound Vi as f or Si gnal Ret u r n Pat hs Tw o Ret ur n Pat h Vi as Per Si gnal
Vi a ( Less Ref l ect i on)
GND vias are
located near
each signal
via to improve
the current
return path
GND vias are
located near each
signal via to
improve the
current return
path.
I nt el
796
On met al layers where signal vias need t o have via pads, it is desirable t o reduce capacit ance bet ween
t he signal vias and ground plane layers. The ant i- pad diamet ers should be up t o 20 mils larger t han t he
via pad diamet ers. See Figure 12- 12. Clearance bet ween t he pad and t he surrounding met al should be
> = 10 mils.
Fi gur e 12- 10. Undesi r abl e: For Si gnal Vi as t o Have Pads on t he Unused Met al Layer s
Fi gur e 12- 11. Si gnal Vi a I mpr oved by Removi ng Unused Met al Layer Pads
These unused via pads degrade the signal
integrity of the signal path and should be
removed if possible.
The unused via pads have been
removed to improve signal quality.

797
Each t ime different ial signal vias pass t hrough a plane layer, wit hin each different ial pair, t he ant i- pads
should overlap. See Figure 12- 14 and Figure 12- 15.
Fi gur e 12- 12. I ncr ease Ant i - Pad Di amet er To Reduce Shunt Capaci t ance
Fi gur e 12- 13. Di f f er ent i al Si gnal Vi a Pads Shoul d Not Be Separ at ed By Met al
Via anti-pad
Via pad
Anti-pad diameter = Via
pad diameter + 20 mils
Via anti-pad
Via pad
Differential Via pads
should not be separated
by metal.
I nt el
798
12.2. 13 KR and SFI + Recommended Si mul at i ons
KR and SFI + signaling frequencies ext end above 5 GHz: relat ively short st ubs, small discont inuit ies,
and fairly small in- pair t race lengt h differences can cause an undesirable increase in bit errors. Before
ordering circuit boards, verify t hat :
Planned KR signal t race rout ing on t he circuit board complies wit h t he int erconnect charact erist ics
recommended in I EEE 802. 3ap sect ions 69.3 and 69.4.
Fi gur e 12- 14. Bet t er Di f f er ent i al Si gnal s Vi a Ant i - Pads
Fi gur e 12- 15. Best Di f f er ent i al Si gnal s Vi a Ant i - Pads
Via Anti-pad
Via pad
Better differential signal
anti-pad via usage.
Via Anti-pad
Via pad
Best differential signal
anti-pad via usage.

799
Planned SFI + signal t race rout ing on t he circuit board complies wit h t he guidance provided in t his
document and complies wit h t he int erconnect charact erist ics recommended in t he SFF- 8431
specificat ions. Cont act your I nt el sales represent at ive for more det ails.
For most KR board t races:
I f possible, export S- paramet ers for t he planned KR signal channels, and compare t hem t o t he
I EEE recommended elect rical charact erist ics. Opt imize t he KR signal pat h unt il it complies wit h
t he I EEE recommendat ions.
I EEE channel charact erist ics recommendat ions are for t he ent ire lengt h of t he board channels
from t he solder- pads for one KR I C device t o t he solder- pads for anot her KR device, at t he far-
end of t he ent ire KR channel pat h. This end- t o- end KR signal pat h t ypically includes t wo or
t hree circuit boards, connect ors, and AC coupling caps.
For unusual rout ing requirement s, which make it difficult t o meet t he I EEE channel
recommendat ions:
KR board t race channels, which have been opt imized by following t he layout guidelines
recommended wit hin t his document but which cannot be improved enough t o comply wit h I EEE
802.3ap recommended elect rical charact erist ics, might st ill work sat isfact orily wit h t he 82599
LAN silicon in KR mode ( see as follows) .
Wit h sufficient advance not ice, I nt el engineers can provide assist ance:
Trace rout ing should be opt imized prior t o t he next st eps request a layout review ( must be
willing t o provide board st ackup informat ion and t he KR t races CAD art work) .
Aft er KR t races have been opt imized, if t he I EEE recommended elect rical charact erist ics are st ill
not being met , t hen end- t o- end KR board channels S- paramet er models should be ext ract ed
( preferably in Touchst one* S4p format ) for addit ional invest igat ive simulat ions by I nt el signal
int egrit y engineers. Please request t he required S- paramet er frequency range, st ep size et c,
before ext ract ing Touchst one S- paramet er models.
KR values are at 2.5 and 5 GHz and pre/ post plat ing informat ion must also be provided.
12.2.14 Addi t i onal Di f f er ent i al Tr ace Lay out Gui del i nes f or SFI + Boar ds
As st at ed in t he SFF- 8431 specificat ions, SFI + different ial t races should have a nominal different ial
impedance t hat is 100 O wit h 10 O t olerance and wit h 7% different ial coupling ( nominal) .
Different ial coupling = [ ( 4 x Zcm) - Zdiff ] / [ ( 4 x Zcm) + Zdiff ] , where Zcm is t he common mode
impedance and Zdiff is t he different ial impedance. For example, when Zcm is 28. 76 O and Zdiff is
100 O, t he coupling is 7%.
Not e: Zdiff should be 100 O nominal wit h Zdiff t olerance wit hin + / - 10% AND when Zdiff nominal is
100 O, t hen Zcm nominal should be about 28. 76 O, maximum.
Signal vias should be avoided on SFI + t races. The SFI + t ransmit t races must not have any vias. I f
t here must be one or t wo signal vias on t he SFI + receive t races, t hen each via should be accompanied
by one or t wo ground ret urn vias, via st ubs should be < = 20 mils long, AND t he board' s SFI + channel
insert ion loss and ret urn loss should st ill conform t o t he SFF- 828431 Appendix A, SFI + channel
recommendat ions. To verify conformance, AC channel simulat ions should be performed.
Because t he SFP+ module connect or pads on t he end of t he SFI + t races are t ypically wider t han t he
SFI + t races, in order t o avoid excessive capacit ance, t he reference plane areas direct ly under each pair
of SFP+ module connect or pads must be voided. The voided areas under t he connect or pads should be
rect angular- like in shape, and should be a lit t le larger t han t he area occupied by each pair of SFP+
module connect or pads. Simulat ions should be performed, t o verify t hat 100 O different ial impedance
has been maint ained. The size and shape of t he reference plane voids should be adj ust ed t o maint ain
t he desired impedance ( see Figure 12- 7 for an example) .
I nt el
800
SFI + t race lengt hs and t race geomet ry: To meet t he st ringent t ransmit t er elect rical requirement s,
some t race geomet ry guidance is list ed in Figure 12- 16 and Figure 12- 17 show examples.Cont act your
I nt el sales represent at ive for more det ails.
Not e: Grey is t he ground plane.
Fi gur e 12- 16. Voi di ng t he Ref er ence Pl anes Under t he SFI + Connect or Pi n Sol der Pads
1
1
0

m
i
l
s
10mil
10mil
74 mils


801
Fi gur e 12- 17. SFI + Br eak out and Rout i ng Ex ampl e Fr om t he 82599 t o SFI + Connect or Pad
Not e: The SFI + t ransmit t races do not have any vias. Cont act your I nt el sales represent at ive for
more det ails.
12.3 Connect i ng t he Ser i al EEPROM
The 82599 uses a Serial Peripheral I nt erface ( SPI ) * EEPROM. Several words of t he EEPROM are
accessed aut omat ically by t he 82599 aft er reset t o provide pre- boot configurat ion dat a before it is
accessed by host soft ware. The remainder of t he EEPROM space is available t o soft ware for st oring t he
MAC address, serial numbers, and addit ional informat ion. For a complet e descript ion of t he cont ent
st ored in t he EEPROM see Sect ion 6. 0.
I nt el
802
12. 3. 1 Suppor t ed EEPROM Dev i ces
Table 12- 2 list s t he SPI EEPROMs t hat operat e sat isfact orily wit h t he t he 82599. SPI EEPROMs used
must be rat ed for a clock rat e of at least 2 MHz.
Tabl e 12- 2. Suppor t ed SPI EEPROM Devi ces
Use a 128 Kb EEPROM for all applicat ions unt il an appropriat e size for each applicat ion is det ermined.
Not e: Refer t o Sect ion 11. 6. 1 and Sect ion 11. 6. 2 for minimum and recommended EEPROM sizes.
For more informat ion on how t o properly at t ach t he EEPROM device t o t he t he 82599, follow t he
example provided in t he 82599 reference schemat ics. Cont act your I nt el sales represent at ive for
access.
12.4 Connect i ng t he Fl ash
The 82599 provides support for an SPI Flash device t hat is made accessible t o t he syst em t hrough t he
following:
Flash Base Address regist er ( PCI e Cont rol regist er at offset 0x14 or 0x18) .
An address range of t he I OADDR regist er, defined by t he I O Base Address regist er ( PCI e) Cont rol
regist er at offset 0x18 or 0x20) .
Expansion ROM Base Address regist er ( PCI e Cont rol regist er at offset 0x30) .
12.4. 1 Suppor t ed Fl ash Devi ces
The 82599 support s SPI Flash t ype. All support ed Flashes have address size of 24 bit s. Table 12- 4 list s
t he Flash t ypes support ed.
Tabl e 12- 3. Fl ash Ty pes Suppor t ed
Densi t y ( Kb) At mel * PN STM* PN Cat al y st * PN
16 AT25160AN- 1DSI - 2. 7 M9516DWMN6T CAT25C16S-TE13
128 AT25128AN- 1DSI - 2. 7 M951286DWMN6T CAT25C9128-TE13
256 AT25256AN- 1DSI - 2. 7 M95256DWMN6T
Densi t y At mel * PN STM* PN
512 Kb AT25F512N- 10SI - 2. 7 M25P05-AVMN6T
8 Mb M25P80-AVMN6T
16 Mb M25P16-AVMN6T
32 Mb M25P32-AVMN6T

803
For more informat ion on how t o properly at t ach t he Flash device t o t he 82599, follow t he example
provided in t he 82599 reference schemat ics. Cont act your I nt el sales represent at ive for access.
Not e: I f no Flash device is used, leave FLSH_CE_N, FLSH_SCK, FLSH_SI , FLSH_SO unconnect ed.
12. 5 SMBus and NC- SI
SMBus and NC- SI are int erfaces for pass- t hrough and configurat ion t raffic bet ween t he Management
Cont roller ( MC) and t he 82599.
Not e: I nt el recommends t hat t he SMBus be connect ed t o an MC for t he EEPROM recovery solut ion.
I f t he connect ion is t o a MC, it will be able t o send t he EEPROM release command.
The 82599 can be connect ed t o an ext ernal MC. I t operat es in one of t wo modes:
SMBus mode
NC- SI mode
The clock- out ( if enabled) is provided in all power st at es ( unless t he device is disabled) .
Fi gur e 12- 18. Ex t er nal MC Connect i ons w i t h NC- SI and SMBus
SMBus
Example connection of
SMBus signals
SMBCLK
SMBD
SMBALRT_N
NC-SI_RXD[1:0]
NC-SI_CRS_DV
NC-SI_TXD[1:0]
NC-SI_TX_EN
NC-SI_CLK_IN
NC-SI_CLK_OUT
NC-SI
Example connection of NC-SI
signals
OR
External MC
External MC
I nt el
804
12. 6 NC- SI
12.6.1 NC- SI Desi gn Requi r ement s
12.6. 1.1 Net w or k Cont r ol l er
The NC- SI I nt erface enables net work manageabilit y implement at ions required by informat ion
t echnology personnel for remot e cont rol and alert ing via t he LAN. Management packet s can be rout ed
t o or from a management processor.
12.6. 1.2 Ex t er nal Management Cont r ol l er ( MC)
An ext ernal MC is required t o meet t he requirement s called out in t he lat est NC- SI specificat ion as it
relat es t o t his int erface.
12.6. 1.3 Ref er ence Schemat i c
The following reference schemat ic ( provides connect ivit y requirement s for single and mulit - drop
applicat ions. This configurat ion only has a single connect ion t o t he MC. The net work device also
support s mult i- drop NC- SI configurat ion archit ect ure wit h soft ware arbit rat ion support from t he MC.
Refer t o t he NC- SI specificat ion for connect ivit y requirement s for mult i- drop applicat ions.
Fi gur e 12- 19. NC- SI Connect i on Schemat i c: Si ngl e- Dr op Conf i gur at i on
100
100
100

805
12.6.2 NC- SI Lay out Requi r ement s
12. 6. 2. 1 Boar d I mpedance
The NC- SI signaling int erface is a single ended signaling environment and as such I nt el recommends a
t arget board and t race impedance of 50 O plus 20% and minus 10%. This impedance ensures opt imal
signal int egrit y and qualit y.
Fi gur e 12- 20. NC- SI Connect i on Schemat i c: Mul t i - Dr op Conf i gur at i on
Device
NC-SI
Interface
Signals
NC-SI_CLK_IN
NC-SI_CRS_DV
NC-SI_RXD_0
NC-SI_RXD_1
NC-SI_TX_EN
NC-SI_TXD_0
NC-SI_TXD_1

MC
REF_CLK
CRS_DV
RXD_0
RXD_1
TX_EN
TXD_0
TXD_1
50 MHz Reference
Clock Buffer
50 MHz
33 33
22
22
10k 10k
3.3V
10k 10k
Device
NC-SI
Interface
Signals
NC-SI_CLK_IN
NC-SI_CRS_DV
NC-SI_RXD_0
NC-SI_RXD_1
NC-SI_TX_EN
NC-SI_TXD_0
NC-SI_TXD_1
33
100 100 100
I nt el
806
12.6. 2.2 Tr ace Lengt h Rest r i ct i ons
The recommended maximum t race lengt hs for each circuit board applicat ion is dependent on t he
number drops and t he t ot al capacit ive loading from all t he t race segment s on each NC- SI signal net .
The number vias must also be considered. Circuit board mat erial variat ions and t race et ch process
variat ions affect t he t race impedance and t race capacit ance. For each fixed design, highest t race
capacit ance occurs when t race impedance is lowest .For t he FR4 board st ackup provided in direct
connect applicat ions, t he maximum lengt h for a 50 O NC- SI t race would be approximat ely 9 inches on
a minus 10% board impedance skew. This ensures t hat signal int egrit y and qualit y are preserved and
enables t he design t o comply wit h NC- SI elect rical requirement s.
For special applicat ions which require longer NC- SI t races, t he t ot al funct ional NC- SI t race lengt h can
be ext ended wit h non- compliant rise t ime by:
providing good clock and signal alignment
t est ing wit h t he t arget receiver t o verify it meet s set up and hold requirement s.
For mult i- drop applicat ions, t he t ot al capacit ance and t he ext ra resist ive loading affect t he rise t ime. A
mult i- drop of t wo devices limit s t he t ot al lengt h t o 8 inches. A mult i- drop of four limit s t he t ot al lengt h
t o 6.5 inches. Capacit ive loading of ext ra vias have a nominal effect on t he t ot al load.
Fi gur e 12- 21. NC- SI Tr ace Lengt h Requi r ement f or Di r ect Connect
Device MC
8 inches
NCSI_TXD[1:0]
NCSI_RXD[1:0]
NCSI_TX_EN
NCSI_CRS_DV
NCSI_CLK_IN

807
Table 12- 4 list s how seven more vias increase t he rise t ime by 0.5 ns. Again, longer t race lengt hs can
be achieved.
Table 12- 5 list s t he example t race lengt hs for t he mult i- drop t opology of t wo and four represent ed in
t he figures t hat follow.
Tabl e 12- 4. St ack Up, Seven Vi as
I t em Val ue Uni t s
Trace widt h 4. 5 mils
Trace t hickness 1. 9 mils
Dielect ric t hickness 3. 0 mils
Dielect ric const ant 4. 1 - -
Loss Tangent 0. 024 - -
Nominal I mpedance 50 O
Trace Capacit ance 1. 39 pf/ inch
Tabl e 12- 5. Ex ampl e Tr ace Lengt hs f or Mul t i - Dr op Topol ogi es, 2 & 4
Mul t i - dr op l engt h
par amet er used i n
Fi gur e 12- 22 and
Fi gur e 12- 23
Segment l engt h ex ampl e f or mul t i dr op conf i gur at i ons
Tw o dr op conf i gur at i on Four dr op conf i gur at i on
Length
(Inches)
Trace capacitance (Pf) Length (Inches) Trace capacitance (Pf)
L1 2 2.8 1.5 8.8
L2 4 5.6 2 16.1
L3 2 2.8 1 8.1
Total 8 11.1 6.5 35.6
I nt el
808
Fi gur e 12- 22. Ex ampl e 2- Dr op Topol ogy
Device MC
L1
Device
NC-SI_TXD[1:0]
NC-SI_RXD[1:0]
NC-SI_TX_EN
NC-SI_CRS_DV
NC-SI_CLK_IN
L
2
L3

809
Fi gur e 12- 23. Ex ampl e 4- Dr op Topol ogy
Device MC
L1
NC-SI_TXD[1:0]
NC-SI_RXD[1:0]
NC-SI_TX_EN
NC-SI_CRS_DV
NC-SI_CLK_IN
L
2
Device
Device
Device
L3
I nt el
810

Ext ending NC- SI t o a maximum 11ns rise t ime increases t he maximum t race lengt h.
12.7 Reset s
Aft er power is applied, t he t he 82599 must be reset . There are t wo ways t o do t his:
1. Using t he int ernal power on reset circuit .
2. Using t he ext ernal LAN_PWR_GOOD signal.
By default , t he int ernal power on reset will reset t he 82599.
I f t he design relies on t he int ernal power on reset , t hen t he power supply sequencing t iming
requirement bet ween t he 3. 3V and 1. 2V power rails has t o be met . I f t his requirement is impossible t o
meet , t he alt ernat ive is t o bypass t he int ernal power on reset circuit by pulling POR_BYPASS high and
using an ext ernal power monit oring solut ion t o provide a LAN_PWR_GOOD signal.
For LAN_PWR_GOOD t iming requirement s, see Sect ion 4.0 and Sect ion 5.0.
Tabl e 12- 6. Compl i ant NC- SI Max i mum Lengt h on a 50 O - 10% Sk ew - boar d w i t h Ex ampl e
St ack - up
Topol ogy
Tot al max i mum compl i ant l i near
bus si ze ( i nches)
Number of v i as
Appr ox i mat e Net t r ace
capaci t ance mi nus l oad
capaci t ance ( pf )
4 mult i- drop 6. 0 1 8. 3
4 mult i- drop 5. 5 8 8. 3
2 mult i- drop 8. 0 1 11. 1
2 mult i- drop 7. 5 8 11. 1
Point t o point 9. 0 1 12. 5
Point t o point 8. 5 8 12. 5
Tabl e 12- 7. Funct i onal NC SI max i mum l engt h on a 50 O - 10% sk ew boar d w i t h Ex ampl e
St ack - up ( based on act ual l ab- measur ed sol ut i on)
Topol ogy
Tot al max i mum f unct i onal
l i near bus si ze ( i nches)
Number of vi as
Appr ox i mat e Net t r ace
capaci t ance mi nus l oad
capaci t ance ( pf )
4 mult i- drop 19 1 26. 4
4 mult i- drop 18 8 26. 4
2 mult i- drop 20 1 27. 8
2 mult i- drop 19 8 27. 8
Point t o point 22 1 30. 6
Point t o point 21 8 30. 6
Tabl e 12- 8. Reset Cont ex t f or POR_BYPASS and LAN_PWR_GOOD
POR_BYPASS Act i v e Reset Ci r cui t
I f = 0b I nt ernal POR
I f = 1b Ext ernal Reset

811
I t is import ant t o ensure t hat t he reset s for t he MC and t he 82599 are generat ed wit hin a specific t ime
int erval. The import ant requirement here is ensuring t hat t he NC- SI link is est ablished wit hin t wo
seconds of t he MC receiving t he power good signal from t he plat form. Bot h t he 82599 and t he ext ernal
MC need t o receive power good signals from t he plat form wit hin one second of each ot her.
This causes an int ernal power on reset wit hin t he 82599 and t hen init ializat ion as well as a t riggering
and init ializat ion sequence for t he MC. Once t hese power good signals are received by bot h t he 82599
and t he ext ernal MC, t he NC- SI int erface can be init ialized. The NC- SI specificat ion calls out a
requirement of link est ablishment wit hin t wo seconds. The MC should poll t his int erface and est ablish a
link for t wo seconds t o ensure specificat ion compliance.
12.8 Connect i ng t he MDI O I nt er f aces
The t he 82599 provides one MDI O int erface for each LAN port used as configurat ion int erface for an
ext ernal PHY at t ached t o t he 82599.
Connect t he MDI O and MDC signals t o t he corresponding pins on t he PHY chip. Make sure t o provide a
pullup resist or t o 3.3 V on t he MDI O signal.
12. 9 Connect i ng t he Sof t w ar e- Def i nabl e Pi ns ( SDPs)
The 82599 has eight SDPs per port t hat can be used for miscellaneous hardware or soft ware-
cont rollable purposes. These pins and t heir funct ion are bound t o a specific LAN device. The pins can
each be individually configured t o act as eit her input or out put pins via EEPROM. The init ial value in
case of an out put can also be configured in t he same way. However, t he silicon default for any of t hese
pins is t o be configured as out put s.
To avoid signal cont ent ion, all eight pins are set as input pins unt il aft er EEPROM configurat ion has been
loaded.
Choose t he right soft ware definable pins for your applicat ions keeping in mind t hat t wo of t he eight pins
( SDPx_6 and SDPx_7) are open drain. The rest are t ri- st at e buffers. Consider t hat four of t hese pins
( SDPx_0 SDPx_3) can be used as General Purpose I nt errupt ( GPI ) input s. To act as GPI pins, t he
desired pins must be configured as input s. A separat e GPI int errupt - det ect ion enable is t hen used t o
enable rising- edge det ect ion of t he input pin ( rising- edge det ect ion occurs by comparing values
sampled at 62.5 MHz, as opposed t o an edge- det ect ion circuit ) . When det ect ed, a corresponding GPI
int errupt is indicat ed in t he I nt errupt Cause regist er.
When connect ing t he SDPs t o different digit al signals, please keep in mind t hat t hese are 3.3 V signals
and use level shift ing if necessary.
The use, direct ion, and values of SDPs are cont rolled and accessed using fields in t he Ext ended SDP
Cont rol ( ESDP) and Ext ended OD SDP Cont rol ( EODSDP) regist ers.
LAN_PWR_GOOD
I f = 0b Held in reset .
I f = 1b I nit ialized, ready for normal operat ion.
Tabl e 12- 8. Reset Cont ex t f or POR_BYPASS and LAN_PWR_GOOD
I nt el
812
12.10 Connect i ng t he Li ght Emi t t i ng Di odes ( LEDs)
The 82599 provides four programmable high- current push- pull ( act ive high) out put s per port t o direct ly
drive LEDs for link act ivit y and speed indicat ion. Each LAN device provides an independent set of LED
out put s; t hese pins and t heir funct ion are bound t o a specific LAN device. Each of t he four LED out put s
can be individually configured t o select t he part icular event , st at e, or act ivit y, which is indicat ed on t hat
out put . I n addit ion, each LED can be individually configured for out put polarit y, as well as for blinking
versus non- blinking ( st eady- st at e) indicat ion.
The LED port s are fully programmable t hrough t he EEPROM int erface ( LEDCTL regist er) . I n addit ion,
t he hardware- default configurat ion for all LED out put s can be specified via an EEPROM field, t hus
support ing LED displays configurable t o a part icular OEM preference.
Provide separat e current limit ing resist ors for each LED connect ed.
Since t he LEDs are likely t o be placed close t o t he board edge and t o ext ernal int erconnect , t ake care t o
rout e t he LED t races away from pot ent ial sources of EMI noise. I n some cases, it might be desirable t o
at t ach filt er capacit ors.
12.11 Connect i ng Mi scel l aneous Si gnal s
12.11.1 LAN Di sabl e
The t he 82599 has t wo signals t hat can be used for disabling Et hernet funct ions from syst em BI OS.
LAN0_DI S_N and LAN1_DI S_N are t he separat ed port disable signals. Each signal can be driven from a
syst em out put port . Choose out put s from devices t hat ret ain t heir values during reset . For example,
some I CH GPI O out put s t ransit ion high during reset . I t is import ant not t o use t hese signals t o drive
LAN0_DI S_N or LAN1_DI S_N because t hese input s are lat ched upon t he rising edge of PE_RST_N or an
in- band reset end.
Each PHY can be disabled if it s LAN funct ion' s LAN disable input indicat es t hat t he relevant funct ion
should be disabled. Since t he PHY is shared bet ween t he LAN funct ion and manageabilit y, it might not
be desirable t o power down t he PHY in LAN disable. The PHY_in_LAN_Disable EEPROM bit det ermines
whet her t he PHY ( and MAC) are powered down when t he LAN disable pin is assert ed. Default is not t o
power down.
A LAN port might also be disabled t hrough EEPROM set t ings. I f t he LAN_DI S EEPROM bit is set , t he PHY
ent ers power down. Not e, however, t hat set t ing t he EEPROM LAN_PCI _DI S bit does not bring t he PHY
int o power down.

813
Tabl e 12- 9. PCI Funct i ons Mappi ng ( Legacy Mode)
Tabl e 12- 10. PCI Funct i ons Mappi ng ( Dummy Funct i on Mode)
When bot h LAN port s are disabled following a POR / LAN_PWR_Good/ PE_RST_N/ in- band reset , t he
LAN_DI S_N signals should be t ied st at ically t o low. At t his st at e t he 82599 is disabled, LAN port s are
powered down, all int ernal clocks are off and t he PCI e connect ion is powered down ( similar t o L2 st at e) .
12.11.2 BI OS Handl i ng of Devi ce Di sabl e
Assume t hat in t he following power up sequence t he LANx_DI S_N signals are driven high ( or is already
disabled) :
1. PCI e link is est ablished following t he PE_RST_N.
2. BI OS recognizes t hat t he 82599 should be disabled.
3. BI OS drives t he LANx_DI S_N signals t o t he low level.
4. BI OS issues PE_RST_N or an in- band PCI e reset .
5. As a result , t he 82599 samples t he LANx_DI S_N signals and ent ers t he desired device- disable
mode.
6. Re- enable could be done by driving high one of t he LANx_DI S_N signals and t hen issuing a
PE_RST_N t o rest art t he 82599.
12. 12 Osci l l at or Desi gn Consi der at i ons
This sect ion provides informat ion regarding oscillat ors for use wit h t he t he 82599.
All designs require an ext ernal clock. There are t wo opt ions for t his clock source: a 25 MHz different ial
clock or a 25 MHz cryst al. The t he 82599 uses t he clock source t o generat e clocks wit h frequency up t o
3. 125 GHz for t he high speed int erfaces.
PCI Funct i on #
LAN Funct i on
Sel ect
Funct i on 0 Funct i on 1
Bot h LAN funct ions are enabled
0 LAN 0 LAN 1
1 LAN 1 LAN 0
LAN 0 is disabled x LAN1 Disable
LAN 1 is disabled x LAN 0 Disable
Bot h LAN funct ions are disabled Bot h PCI funct ions are disabled. 82599 is in low power mode.
PCI Funct i on #
LAN Funct i on
Sel ect
Funct i on 0 Funct i on 1
Bot h LAN funct ions are enabled
0 LAN 0 LAN 1
1 LAN 1 LAN 0
LAN 0 is disabled
0 Dummy LAN1
1 LAN 1 Disable
LAN 1 is disabled
0 LAN 0 Disable
1 Dummy LAN 0
Bot h LAN funct ions are disabled Bot h PCI funct ions are disabled. 82599 is in low power mode.
I nt el
814
The chosen oscillat or or cryst al vendor should be consult ed early in t he design cycle. Oscillat or and
cryst al manufact urers familiar wit h net working equipment clock requirement s can provide assist ance in
select ing an opt imum, low- cost solut ion.
12.12.1 Osci l l at or Ty pes
12. 12. 1. 1 Fi x ed Cr y st al Osci l l at or
A packaged fixed cryst al oscillat or comprises an invert er, a quart z cryst al, and passive component s. The
device renders a consist ent square wave out put . Oscillat ors used wit h microprocessors are supplied in
many configurat ions and t olerances.
Cryst al oscillat ors can be used in special sit uat ions, such as shared clocking among devices. As clock
rout ing can be difficult t o accomplish, it is preferable t o provide a separat e cryst al for each device.
Recommended cryst als are:
12. 12. 1. 2 Pr ogr ammabl e Cr y st al Osci l l at or s
A programmable oscillat or can be configured t o operat e at many frequencies. The device cont ains a
cryst al frequency reference and a Phase Lock Loop ( PLL) clock generat or. The frequency mult ipliers and
divisors are cont rolled by programmable fuses.
PLLs are prone t o exhibit frequency j it t er. The t ransmit t ed signal can also have considerable j it t er even
wit h t he programmable oscillat or working wit hin it s specified frequency t olerance. PLLs must be
designed carefully t o lock ont o signals over a reasonable frequency range. I f t he t ransmit t ed signal has
high j it t er and t he receiver s PLL loses it s lock, t hen bit errors or link loss can occur.
PHY devices are deployed for many different communicat ion applicat ions. Some PHYs cont ain PLLs wit h
marginal lock range and cannot t olerat e t he j it t er inherent in dat a t ransmission clocked wit h a
programmable oscillat or. The American Nat ional St andards I nst it ut e ( ANSI ) X3. 263- 1995 st andard t est
met hod for t ransmit j it t er is not st ringent enough t o predict PLL- t o- PLL lock failures. Therefore, use of
programmable oscillat ors is generally not recommended.
12.12.2 Osci l l at or Sol ut i on
Choose a clock oscillat or wit h a PECL or CML out put . When connect ing t he out put of t he oscillat or t o an
t he 82599, use t he layout informat ion shown in Figure 11.13. Also, make sure t he oscillat or meet s t he
elect rical charact erist ics list ed in Table 11.24. Not e t hat t he EuroQuart z 3HPW5761-A- 25 25MHz PECL
Out put Cryst al- Cont rolled Oscillat or has been used successfully in 82599- based designs.
12.12.3 Osci l l at or Lay out Recommendat i ons
Oscillat ors should not be placed near I / O port s or board edges. Noise from t hese devices can be
coupled ont o t he I / O port s or out of t he syst em chassis. Oscillat ors should also be kept away from
net work int erface different ial pairs t o prevent int erference.
The reference clock should be rout ed different ially; use t he short est , most direct t races possible. Keep
pot ent ially noisy t races away from t he clock t race. I t is crit ical t o place t he t erminat ion resist ors and AC
coupling capacit ors as close t o t he t he 82599 as possible ( less t han 250 mils) .
Tabl e 12- 11. Par t Number s f or Recommended Cr y st al s
Ralt ron AS- 25. 000- 20- SMD-TR- NS7
TXC 9C25000551

815
12. 12. 4 Ref er ence Cl ock Measur ement Recommendat i ons
A low capacit ance, high impedance probe ( C < 1 pF, R > 500 K) should be used for t est ing. Probing
paramet ers can affect t he measurement of t he clock amplit ude and cause errors in t he adj ust ment . A
t est should be done aft er t he probe has been removed t o ensure circuit operat ion.
12.13 Pow er Suppl i es
The 82599 requires t wo power rails: 3. 3 V and 1. 2 V. A cent ral power supply can provide all t he
required volt age sources; or power can be derived from t he 3.3 V supply and regulat ed locally using an
ext ernal regulat or. I f t he LAN wake capabilit y is used, volt ages must remain present during syst em
power down. Local regulat ion of t he LAN volt ages from syst em 3.3 Vmain and 3.3 Vaux volt ages is
recommended.
Make sure t hat all t he ext ernal volt age regulat ors generat e t he proper volt age, meet t he out put current
requirement s ( wit h adequat e margin) , and provide t he proper power sequencing. See Sect ion 11.0.
12.13.1 Pow er Suppl y Sequenci ng
Due t o t he current demand, a Swit ching Volt age Regulat or ( SVR) is highly recommended for t he 1. 2 V
power rail. Regardless of t he t ype of regulat or used, all regulat ors need t o adhere t o t he sequencing
shown in Sect ion 11. 0 of t his document t o avoid lat ch- up and forward- biased int ernal diodes ( 1.2 V
must not exceed 3.3 V) .
The power supplies are all expect ed t o ramp during a short power- up int erval ( recommended int erval
20 ms or fast er) . Do not leave t he 82599 in a prolonged st at e where some, but not all, volt ages are
applied.
12. 13. 1. 1 Usi ng Regul at or s Wi t h Enabl e Pi ns
The use of regulat ors wit h enable pins is very helpful in cont rolling sequencing. Connect ing t he enable
of t he 1.2 V regulat or t o 3.3 V ensures t hat t he 1.2 V rail ramps aft er t he 3. 3V rail. This provides a
quick solut ion t o power sequencing. Make sure t o check design paramet ers for input s wit h t his
configurat ion. Alt ernat ively, power monit oring chips can be used t o provide t he proper sequencing by
keeping t he volt age regulat ors wit h lower out put in shut down unt il t he one immediat ely above doesnt
reach a cert ain out put volt age level.
12.13.2 Pow er Suppl y Fi l t er i ng
Provide several high- frequency bypass capacit ors for each power rail ( Table 12- 12) , select ing values in
t he range of 0. 001 F t o 0. 1 F. I f possible, orient t he capacit ors close t o t he 82599 and adj acent t o
power pads.
Traces bet ween decoupling and I / O filt er capacit ors should be as short and wide as pract ical. Long and
t hin t races are more induct ive and would reduce t he int ended effect of decoupling capacit ors. Also for
similar reasons, t races t o I / O signals and signal t erminat ions should be as short as possible. Vias t o t he
decoupling capacit ors should be sufficient ly large in diamet er t o decrease series induct ance.
Tabl e 12- 12. Mi ni mum Number of By pass Capaci t or s per Pow er Rai l
Pow er Rai l Tot al Bul k Capaci t ance 1. 0 F 0. 1 F 0. 001 F
3. 3 V 44 F 0 8 0
1. 2 V 132 F 6 36 12
I nt el
816
12.13.3 Suppor t f or Pow er Management and Wak e Up
A designer must connect t he MAI N_PWR_OK and t he AUX_PWR signals on t he board. These are digit al
input s t o t he t he 82599 and serve t he following purpose:
MAI N_PWR_OK signals t he t he 82599 cont roller t hat t he main power from t he syst em is up and st able.
For example, it could be pulled up t o t he 3.3V main rail or connect ed t o a power well signal available in
t he syst em.
When sampled high, AUX_PWR indicat es t hat auxiliary power is available t o t he 82599, and t herefore it
advert ises D3cold wake up support . The amount of power required for t he funct ion, which includes t he
ent ire net work int erface card, is advert ised in t he Power Management Dat a regist er, which is loaded
from t he EEPROM.
I f wakeup support is desired, AUX_PWR needs t o be pulled high and t he appropriat e wakeup LAN
address filt ers must also be set . The init ial power management set t ings are specified by EEPROM bit s.
When a wakeup event occurs, t he 82599 assert s t he PE_WAKEn signal t o wake t he syst em up.
PE_WAKEn remains assert ed unt il PME st at us is cleared in t he t he 82599 Power Management Cont rol/
St at us Regist er.
12.14 Connect i ng t he JTAG Por t
The t he 82599 cont ains a t est access port ( 3.3 V only) conforming t o t he I EEE 1149.1- 2001 Edit ion
( JTAG) specificat ion. To use t he t est access port , connect t hese balls t o pads accessible by your t est
equipment .
For proper operat ion, a pull- down resist or should be connect ed t o t he JTCK and JRST_N signals and
pullup resist ors t o t he JTDO, JTMS and JTDI signals.
A Boundary Scan Definit ion Language ( BSDL) file describing t he t he 82599 10 Gigabit Et hernet
Cont roller device is available for use in your t est environment .
Ther mal Desi gn Recommendat i ons I nt el

817
13. 0 Ther mal Desi gn Recommendat i ons
This sect ion provides a met hod for det ermining t he operat ing t emperat ure of t he 82599 in a specific
syst em based on case t emperat ure. Case t emperat ure is a funct ion of t he local ambient and int ernal
t emperat ures of t he component . This document specifies a maximum allowable Tcase for t he 82599.
13. 1 Ther mal Consi der at i ons
I n a syst em environment , t he t emperat ure of a component is a funct ion of bot h t he syst em and
component t hermal charact erist ics. Syst em- level t hermal const raint s consist of t he local ambient
t emperat ure at t he component , t he airflow over t he component and surrounding board, and t he
physical const raint s at , above, and surrounding t he component t hat may limit t he size of a t hermal
enhancement ( heat sink) .
The component ' s case/ die t emperat ure depends on:
Component power dissipat ion
Size
Packaging mat erials ( effect ive t hermal conduct ivit y)
Type of int erconnect ion t o t he subst rat e and mot herboard
Presence of a t hermal cooling solut ion
Power densit y of t he subst rat e, nearby component s, and mot herboard
These paramet ers are pushed by increased performance levels ( higher operat ing speeds, MHz) and
power densit y ( more t ransist ors) . As operat ing frequencies increase and packaging size decreases, t he
power densit y increases and t he t hermal cooling solut ion space and airflow become more const rained.
The result is an increased emphasis on syst em design t o ensure t hat t hermal design requirement s are
met for each component in t he syst em.
I nt el
82599 10 GbE Cont r ol l er Ther mal Desi gn Recommendat i ons

818
13.2 I mpor t ance of Ther mal Management
The t hermal management obj ect ive is t o ensure t hat all syst em component t emperat ures are
maint ained wit hin funct ional limit s. The funct ional t emperat ure limit is t he range in which t he elect rical
circuit s are expect ed t o meet specified performance. Operat ion out side t he funct ional limit can degrade
syst em performance, cause logic errors, or cause device and/ or syst em damage. Temperat ures
exceeding t he maximum operat ing limit s may result in irreversible changes in t he device operat ing
charact erist ics. Not e t hat sust ained operat ion at component maximum t emperat ure limit may affect
long- t erm device reliabilit y.
13.3 Pack agi ng Ter mi nol ogy
The following t erminology is used in t his chapt er:
FCBGA Flip Chip Ball Grid Array: A surface- mount package using a combinat ion of flip chip and BGA
st ruct ure whose PCB- int erconnect met hod consist s of solder ball array on t he int erconnect side of
t he package. The die is flipped and connect ed t o an organic build- up subst rat e wit h C4 bumps. An
int egrat ed heat spreader ( I HS) may be present for larger FCBGA packages for enhanced t hermal
performance ( but I HS is not present for t he 82599) .
Junct ion: Refers t o a P- N j unct ion on t he silicon. I n t his document , it is used as a t emperat ure
reference point ( for example, JA refers t o t he j unct ion t o ambient t hermal resist ance) .
Ambient : Refers t o local ambient t emperat ure of t he bulk air approaching t he component . I t can be
measured by placing a t hermocouple approximat ely 1 inch upst ream from t he component edge.
Lands: The pads on t he PCB t o which BGA balls are soldered.
PCB: Print ed circuit board.
Print ed Circuit Assembly ( PCA) : An assembled PCB.
Thermal Design Power ( TDP) : The est imat ed maximum possible/ expect ed power generat ed in a
component by a realist ic applicat ion. Use Maximum power requirement s list ed in Table 13- 2.
LFM: Linear feet per minut e ( airflow) .
JA ( Thet a JA) : Thermal resist ance j unct ion- t o- ambient , C/ W.
+JT ( Psi JT) : Junct ion- t o- t op ( of package) t hermal charact erizat ion paramet er, C/ W. +JT does not
represent t hermal resist ance, but inst ead is a charact erist ic paramet er t hat can be used t o convert
bet ween Tj and Tcase when knowing t he t ot al TDP. +JT is easy t o charact erize in simulat ions or
measurement s, and is equal t o Tj minus Tcase divided by t he t ot al TDP. This paramet er can vary by
environment condit ions like heat sink and airflow.
13.4 Ther mal Speci f i cat i ons
To ensure proper operat ion of t he 82599, t he t hermal solut ion must maint ain a case t emperat ure at or
below t he values specified in Table 13- 1. Syst em- level or component - level t hermal enhancement s are
required t o dissipat e t he generat ed heat t o ensure t he case t emperat ure never exceeds t he maximum
t emperat ures, list ed in Table 13- 2. Table 13- 1 list s t he t hermal performance paramet ers per JEDEC
JESD51- 2 st andard. I n Table 13- 1 t he uJA values should be used as reference only and can vary by
syst em environment . +JT values also can vary by syst em environment , and are given in Table 13- 1 as
t he maximum value for t he 82599 simulat ions.
Analysis indicat es t hat real applicat ions are unlikely t o cause t he 82599 t o be at Tcase- max for
sust ained periods of t ime. Given t hat Tcase should reasonably be expect ed t o be a dist ribut ion of
t emperat ures, sust ained operat ion at Tcase- max may affect long- t erm reliabilit y of t he 82599 and t he
syst em, and sust ained operat ion performance at Tcase- max should be evaluat ed during t he t hermal
design process and st eps t aken t o furt her reduce t he Tcase t emperat ure.

819
Good syst em airflow is crit ical t o dissipat e t he highest possible t hermal power. The size and number of
fans, vent s, and/ or duct s, and, t heir placement in relat ion t o component s and airflow channels wit hin
t he syst em det ermine airflow. Acoust ic noise const raint s may limit t he size and t ypes of fans, vent s and
duct s t hat can be used in a part icular design.
To develop a reliable, cost - effect ive t hermal solut ion, all of t he syst em variables must be considered.
Use syst em- level t hermal charact erist ics and simulat ions t o account for individual component t hermal
requirement s.
Thermal paramet ers defined above are based on simulat ed result s of packages assembled on st andard
mult i layer 2s2p 1.0- oz Cu layer boards in a nat ural convect ion environment . The maximum case
t emperat ure is based on t he maximum j unct ion t emperat ure and defined by t he relat ionship, maximum
Tcase = Tj max (
JT
x Power) where
JT
is t he j unct ion- t o- t op ( of package) t hermal charact erizat ion
paramet er. I f t he case t emperat ure exceeds t he specified Tcase max, t hermal enhancement s such as
heat sinks or forced air will be required.
JA
is t he t hermal resist ance j unct ion- t o- ambient of t he
package.
13.5 Case Temper at ur e
The 82599 is designed t o operat e properly as long as Tcase rat ing is not exceeded. This chapt er
discusses proper guidelines for measuring t he case t emperat ure.
Tabl e 13- 1. Pack age Ther mal Char act er i st i cs i n St andar d JEDEC Env i r onment
Pack age u
JA
( C/ W) +
JT
( C/ W)
25 mm FCBGA wit hout I HS
1
22. 6
4
0. 54
6
25 mm FCBGA wit hout I HS HS
( 7. 11mm height )
2
14. 5
5
0. 54
25 mm FCBGA wit hout I HS HS
( 11. 43mm height )
3
11. 3
5
0. 54
1. I nt egrat ed Heat Spreader ( t he 82599 is Bare die) .
2. Heat sink wit h low profile 7. 11 mm
3. Heat sink wit h high profile 11. 43 mm
4. I nt egrat ed Circuit Thermal Measurement Met hod- Elect rical Test Met hod EI A/ JESD51- 1, I nt egrat ed Circuit s Thermal Test
Met hod Environment al Condit ions Nat ural Convect ion ( St ill Air) , No Heat sink at t ached EI AJESD51- 2.
5. Nat ural Convect ion ( St ill Air) , Heat sink at t ached.
6. +
JT
is given as maximum value for a worst - case t he 82599 scenario, and might vary t o a lesser values in some
scenarios
Tabl e 13- 2. Absol ut e Ther mal Max i mum Rat i ng ( C)
Appl i cat i on TDP Pow er ( W)
1
Tcase Max - hs
2
( C)
I nt el
82599 10 GbE Cont roller 7. 1 @ 123 C Tj _max 119

1. Maximum power, also known as Thermal Design Power ( TDP) , is a syst em design t arget associat ed wit h t he maximum
component operat ing t emperat ure specificat ions. Maximum power values are det ermined based on t ypical DC elect rical
specificat ion and maximum ambient t emperat ure for a worst - case realist ic applicat ion running at maximum ut ilizat ion.
2. Tcase Max- hs is defined as t he maximum case t emperat ure at TDP condit ions. Tcase Max- hs is dict at ed by Tj _max equals t o
123
o
C.
I nt el

820
13.6 Ther mal At t r i but es
13.6. 1 Desi gni ng f or Ther mal Per f or mance
Sect ion 13.14 and Sect ion 13. 15 provide syst em design recommendat ions required t o opt imize product
line t hermal performance.
13.6. 2 Model Sy st em Def i ni t i on
A syst em wit h t he following at t ribut es was used t o generat e t hermal charact erist ics dat a:
Heat sink case described in Sect ion 13.9.
Six- layer, 4. 5 x 4 inch PCB.
Not e: All dat a is preliminary and is not validat ed against physical samples. Your syst em design may
be significant ly different . A larger board wit h more t han six copper layers may improve
t hermal performance.
13.6. 3 Pack age Ther mal Char act er i st i cs
See Table 13- 3 t o det ermine t he opt imum airflow and heat sink combinat ion for t he 82599. Figure 13- 1
shows t he required ambient t emperat ure versus airflow for a t ypical 82599 syst em.
Table 13- 3 shows Tcase as a funct ion of airflow and ambient t emperat ure at t he Thermal Design Power
( TDP) for a t ypical 82599 syst em. Your syst em design may vary from t he t ypical syst em board
environment used t o generat e t he values.

821
Not e: Thermal models are available upon request ( Flot herm* : 2- Resist or, Delphi, or Det ailed) .
Cont act your local I nt el sales represent at ive for product line t hermal models.
Fi gur e 13- 1. 82599 Max Al l ow abl e Ambi ent @ 8.82W ( JEDEC Car d)
I nt el

822
Tabl e 13- 3. 82599 Ex pect ed Tcase ( C) f or Tw o Heat Si nk s at 8.82 W ( JEDEC Car d)
Not e: The Orange blocked value( s) indicat e airflow/ ambient combinat ions t hat exceed t he allowable
case t emperat ure for t he 82599 at 8. 82 W.
13.7 Ther mal Enhancement s
One met hod frequent ly used t o improve t hermal performance is t o increase t he device surface area by
at t aching a met allic heat sink t o t he component t op. I ncreasing t he surface area of t he heat sink reduces
t he t hermal resist ance from t he heat sink t o t he air, increasing heat t ransfer.
13.8 Cl ear ances
A heat sink should have a pocket of air around it t hat is free of obst ruct ions. Though each design may
have unique mechanical rest rict ions, t he recommended clearances for a heat sink used wit h t he 82599
are shown in Figure 13- 2 assuming one of t he 40 x 40mm reference heat sinks is select ed. Ret ent ion
clip select ion is open, and example keep- out s and board t hrough holes are given in Figure 13- 2 and
Figure 13- 3 for a t orsion ret ent ion clip.

823
Fi gur e 13- 2. Heat si nk Keep- out Rest r i ct i ons
I nt el

824
13.9 Def aul t Enhanced Ther mal Sol ut i on
I f you have no cont rol over t he end- user s t hermal environment or you wish t o bypass t he t hermal
modeling and evaluat ion process, use t he Default Enhanced Thermal Solut ion ( see Figure 13- 4) .
I f, aft er implement ing t he recommended enhanced t hermal solut ion, t he case t emperat ure cont inues t o
exceed allowable values, t hen addit ional cooling is needed. This addit ional cooling may be achieved by
improving airflow t o t he component and/ or adding addit ional t hermal enhancement s.
13.10 Ex t r uded Heat si nk s
I f required, t he following ext ruded heat sinks are t he suggest ed for t he 82599 t hermal solut ions. Ot her
equivalent heat sinks and t heir sources are provided in Sect ion 13. 14.
Fi gur e 13- 3. Bot t om Si de Keep- out

825
13.11 At t achi ng t he Ex t r uded Heat si nk
The ext ruded heat sink may be at t ached using clips wit h a phase change t hermal int erface mat erial.
13.11.1 Cl i ps
A well- designed clip, in conj unct ion wit h a t hermal int erface mat erial ( t ape, grease, et c. ) oft en offers
t he best combinat ion of mechanical st abilit y and reworkabilit y. Use of a clip requires significant advance
planning as mount ing holes are required in t he PCB.
Low Profile 7. 11 mm Height Passive Heat Sink
High Profile 11. 43 mm Height Passive Heat Sink
Fi gur e 13- 4. Ex t r uded Heat si nk s
I nt el

826
Use non- plat ed mount ing wit h a grounded annular ring on t he solder side of t he board surrounding t he
hole. For a t ypical low- cost clip, set t he annular ring inner diamet er t o 150 mils and an out er diamet er
t o 300 mils. Define t he ring t o have at least eight ground connect ions. Set t he solder mask opening for
t hese holes wit h a radius of 300 mils.
13. 11. 2 Ther mal I nt er f ace ( PCM45 Ser i es)
The recommended t hermal int erface is PCM45 Series from Honeywell. The PCM45 Series t hermal
int erface pads are phase change mat erials formulat ed for use in high performance devices requiring
minimum t hermal resist ance for maximum heat sink performance and component reliabilit y. These
pads consist of an elect rically non- conduct ive, dry film t hat soft ens at device operat ing t emperat ures
result ing in greasy- like performance. However, I nt el has not fully validat ed t he PCM45 Series TI M.
Each PCA, syst em and heat sink combinat ion varies in at t ach st rengt h. Carefully evaluat e t he reliabilit y
of t ape at t aches prior t o high-volume use.
13.11.3 Av oi d Damagi ng Di e- Si de Capaci t or s w i t h Heat Si nk At t ached
Capacit ors on t he die side are not prot ect ed and can be damaged during heat sink at t achment . I f t he
heat sink is t ilt ed from t he die it is possible t hat t he heat sink will make cont act wit h t he capacit ors prior
t o making cont act wit h t he package subst rat e. Figure 13- 5 shows how t he capacit ors can be exposed t o
heat sink cont act by drawing a plane from t he die edge t o t he subst rat e edge. Figure 13- 6 shows an
example of t he damage caused by heat sink cont act . I t is recommended t hat heat sinks be at t ached
vert ically, wit h t he heat sink bot t om surface parallel t o t he die surface t o avoid cont act wit h t he
capacit ors.
Fi gur e 13- 5. Di e- Si de Capaci t or s Ex posed t o Heat Si nk Cont act

827
13.11.4 Max i mum St at i c Nor mal Load
t he 82599 package has a bare die t hat is capable of sust aining a maximum st at ic normal load of 15 lbf
( 66.7 N) . This load is a uniform compressive load in a direct ion perpendicular t o t he die t op surface.
This mechanical load limit must not be exceeded during heat sink inst allat ion, mechanical st ress t est ing,
st andard shipping condit ions, and/ or any ot her use condit ion. Not e t hat t he heat sink at t ach solut ion
must not include cont inuous st ress t o t he package, wit h t he except ion of a uniform load t o maint ain t he
heat sink- t o- package t hermal int erface. This load specificat ion is based on limit ed t est ing for design
charact erizat ion, and is for t he package only.
13. 12 Rel i abi l i t y
Each PCA, syst em and heat sink combinat ion varies in at t ach st rengt h and long- t erm adhesive
performance. Carefully evaluat e t he reliabilit y of t he complet ed assembly prior t o high-volume use.
Some reliabilit y recommendat ions are shown in Table 13- 4.
Fi gur e 13- 6. Ex ampl e f or Damage Caused by Heat Si nk Cont act
Tabl e 13- 4. Rel i abi l i t y Val i dat i on
Test
1

1. Performed t he above t est s on a sample size of at least 12 assemblies from 3 lot s of mat erial ( t ot al = 36 assemblies)
Requi r ement Pass/ Fai l Cr i t er i a
2

Mechanical Shock
50G t rapezoidal, board level
11 ms, 3 shocks/ axis
Visual and Elect rical Check
Random Vibrat ion
7. 3G, board level
45 minut es/ axis, 50 t o 2000 Hz
Visual and Elect rical Check
High-Temperat ure Life
85 C
2000 hours t ot al
Checkpoint s occur at 168, 500, 1000, and 2000 hours
Visual and Mechanical Check
Thermal Cycling
Per-Target Environment
( for example: - 40 C t o + 85 C)
500 Cycles
Humidit y
85% relat ive humidit y
85 C, 1000 hours
I nt el

828
13. 12. 1 Ther mal I nt er f ace Management f or Heat - Si nk Sol ut i ons
To opt imize t he 82599 heat sink design, it is import ant t o underst and t he int erface bet ween t he heat
spreader and t he heat sink base. Thermal conduct ivit y effect iveness depends on t he following:
Bond line t hickness
I nt erface mat erial area
I nt erface mat erial t hermal conduct ivit y
13. 12.1. 1 Bond Li ne Management
The gap bet ween t he heat spreader and t he heat sink base impact s heat - sink solut ion performance. The
larger t he gap bet ween t he t wo surfaces, t he great er t he t hermal resist ance. The t hickness of t he gap
is det ermined by t he flat ness of bot h t he heat sink base and t he heat spreader, plus t he t hickness of t he
t hermal int erface mat erial ( for example, PSA, t hermal grease, epoxy) used t o j oin t he t wo surfaces.
13. 12.1. 2 I nt er f ace Mat er i al Per f or mance
The following fact ors impact t he performance of t he int erface mat erial bet ween t he heat spreader and
t he heat sink base:
Thermal resist ance of t he mat erial
Wet t ing/ filling charact erist ics of t he mat erial
13. 12.1. 3 Ther mal Resi st ance of t he Mat er i al
Thermal resist ance describes t he abilit y of t he t hermal int erface mat erial t o t ransfer heat from one
surface t o anot her. The higher t he t hermal resist ance, t he less efficient t he heat t ransfer. The t hermal
resist ance of t he int erface mat erial has a significant impact on t he t hermal performance of t he overall
t hermal solut ion. The higher t he t hermal resist ance, t he larger t he t emperat ure drop required across
t he int erface.
13. 12. 1. 4 Wet t i ng/ Fi l l i ng Char act er i st i cs of t he Mat er i al
The wet t ing/ filling charact erist ic of t he t hermal int erface mat erial is it s abilit y t o fill t he gap bet ween t he
heat spreader t op surface and t he heat sink. Since air is an ext remely poor t hermal conduct or, t he more
complet ely t he int erface mat erial fills t he gaps, t he lower t he t emperat ure- drop across t he int erface,
increasing t he efficiency of t he t hermal solut ion.
13.13 Measur ement s f or Ther mal Speci f i cat i ons
Det ermining t he t hermal propert ies of t he syst em requires careful case t emperat ure measurement s.
Guidelines for measuring t he 82599 case t emperat ure are provided in Sect ion 13. 13. 1.
13.13.1 Case Temper at ur e Measur ement s
Maint ain t he 82599 Tcase at or below t he maximum case t emperat ures list ed in Table 13- 2 t o ensure
funct ionalit y and reliabilit y. Special care is required when measuring t he Tcase t emperat ure t o ensure
an accurat e t emperat ure measurement . Use t he following guidelines when making Tcase
measurement s:
Measure t he surface t emperat ure of t he case in t he geomet ric cent er of t he case t op.
2. Addit ional pass/ fail crit eria can be added at your discret ion.

829
Calibrat e t he t hermocouples used t o measure Tcase before making t emperat ure measurement s.
Use 36- gauge ( maximum) K- t ype t hermocouples.
Care must be t aken t o avoid int roducing errors int o t he measurement s when measuring a surface
t emperat ure t hat is a different t emperat ure from t he surrounding local ambient air. Measurement errors
may be due t o a poor t hermal cont act bet ween t he t hermocouple j unct ion and t he surface of t he
package, heat loss by radiat ion, convect ion, conduct ion t hrough t hermocouple leads, and/ or cont act
bet ween t he t hermocouple cement and t he heat - sink base ( if used) .
13.13.2 At t achi ng t he Ther mocoupl e ( No Heat si nk )
The following approach is recommended t o minimize measurement errors for at t aching t he
t hermocouple wit h no heat sink:
Use 36- gauge or smaller- diamet er K- t ype t hermocouples.
Ensure t hat t he t hermocouple has been properly calibrat ed.
At t ach t he t hermocouple bead or j unct ion t o t he t op surface of t he package ( case) in t he cent er of
t he heat spreader using high t hermal conduct ivit y cement s.
Not e: I t is crit ical t hat t he ent ire t hermocouple lead be but t ed t ight ly t o t he heat spreader.
At t ach t he t hermocouple at a 0 angle if t here is no int erference wit h t he t hermocouple at t ach locat ion
or leads ( see Figure 13- 7) . This is t he preferred met hod and is recommended for use wit h packages not
having a heat sink.
13.13.3 At t achi ng t he Ther mocoupl e ( Heat si nk )
The following approach is recommended t o minimize measurement errors for at t aching t he
t hermocouple wit h heat sink:
Use 36- gauge or smaller diamet er K- t ype t hermocouples.
Ensure t hat t he t hermocouple is properly calibrat ed.
At t ach t he t hermocouple bead or j unct ion t o t he cases t op surface in t he geomet ric cent er using a
high t hermal conduct ivit y cement .
Not e: I t is crit ical t hat t he ent ire t hermocouple lead be but t ed t ight ly against t he case.
At t ach t he t hermocouple at a 90 angle if t here is no int erference wit h t he t hermocouple at t ach
locat ion or leads ( Figure 13- 8) . This is t he preferred met hod and is recommended for use wit h
packages wit h heat sinks.
For t est ing purposes, a hole ( no larger t han 0.150 inches in diamet er) must be drilled vert ically
t hrough t he cent er of t he heat sink t o rout e t he t hermocouple wires out .
Fi gur e 13- 7. Techni que f or Measur i ng Tcase w i t h 0 Angl e At t achment , No Heat si nk s
I nt el

830
Ensure t here is no cont act bet ween t he t hermocouple cement and heat sink base. Any cont act
affect s t he t hermocouple reading.
13.14 Heat si nk and At t ach Suppl i er s
Fi gur e 13- 8. Techni que f or Measur i ng Tcase w i t h 90 Angl e At t achment
Tabl e 13- 5. Heat si nk and At t ach Suppl i er s
Par t Par t Number Suppl i er Cont act
Ext ruded Al Heat sink
+ Clip
+ PCM45 ( TI M)
Assembly
Generat ed specific t o
cust omer numbering
scheme
Cooler Mast er
Eugene Lai
Cooler Mast er USA, I NC. ( Fremont )
Office: 510- 770- 8566 # 222
yuchin_lai@coolermast er. com
PCM45 Series PCM45F Honeywell
Nort h America Technical Cont act : Paula Knoll
1349 Moffet t Park Dr.
Sunnyvale, CA 94089
Cell: 1- 858- 705- 1274 Business: 858- 279- 2956
paula. knoll@honeywell. com

831
13.15 PCB Gui del i nes
The following general PCB design guidelines are recommended t o maximize t hermal performance of
FCBGA packages:
When connect ing ground ( t hermal) vias t o t he ground planes, do not use t hermal- relief pat t erns.
Thermal- relief pat t erns are designed t o limit heat t ransfer bet ween vias and t he copper planes,
t hus const rict ing t he heat flow pat h from t he component t o t he ground planes in t he PCB.
As board t emperat ure also has an effect on t he t hermal performance of t he package, avoid placing
t he 82599 adj acent t o high- power dissipat ion devices.
I f airflow exist s, locat e t he component s in t he mainst ream of t he airflow pat h for maximum t hermal
performance. Avoid placing t he component s downst ream, behind larger devices or devices wit h
heat sinks t hat obst ruct t he air flow or supply excessively heat ed air.
Not e: The previous informat ion is provided as a general guideline t o help maximize t he t hermal
performance of t he component s.
I nt el

832
Di agnost i cs I nt el

833
14. 0 Di agnost i cs
14.1 Li nk Loopback Oper at i ons
Loopback operat ions are support ed by t he 82599 t o assist wit h syst em and device debug. Loopback
operat ion can be used t o t est t ransmit and receive aspect s of soft ware drivers, as well as t o verify
elect rical int egrit y of t he connect ions bet ween t he 82599 and t he syst em ( such as PCI e bus
connect ions, et c.) . Loopback operat ion is support ed as follows:
I nt ernal Loopback:
Tx- > Rx MAC Loopback This loopback is closed on t he int ernal XGMI I int erface of t he MAC core
( Does not apply t o PCS or analog cores) .
To configure t he 82599 for Tx- > Rx loopback operat ion:
1. Configure t he desire speed ( 10 GbE/ 1 GbE) .
2. I n AUTOC regist er ( see Sect ion 8.2. 3. 22. 22) set t he LMS field value t o t he desired speed ( 0x0
1 GbE, 0x1 10 GbE) and set t he FLU bit t o 1b in order t o force linkup. All ot her bit s are a don' t
care. I n t he HLREG0 regist er ( see Sect ion 8.2. 3. 22. 9) , set t he LPBK bit t o 1b.
Link indicat ion in regist er LI NKS ( see Sect ion 8. 2. 3. 22. 20) should be ignored:
LI NK configurat ion should be done as in regular funct ional mode ( see Sect ion 4. 6. 4) . All LI NK modes
can be configured, but aut o- negot iat ion should be disabled.
Rx- > Tx Loopback This loopback is closed in t he int ernal XGMI I int erface ( covers analog and t he
enabled PCS blocks) . Not e t hat 10b/ 8b encoding is done t hrough t his loopback, so I DLE pat t erns
might be different bet ween t he received and t ransmit t ed dat a.
To configure t he 82599 for Rx- > Tx loopback operat ion, bit 11 in regist er 0x042B8 should be set t o 1b.
For t he loopback t o be funct ional, a funct ional link ( wit h a link part ner) should be achieved ( sync and
alignment ) .
LI NK configurat ion should be done as in regular funct ional mode ( see Sect ion 4. 6. 3) , and all LI NK
modes can be configured.
Loopback limit at ions:
Short preamble wit h minimal I PG is not support ed wit h loopback operat ion.
Not e: Transmit t ed dat a might violat e t he minimum I PG specificat ion requirement s.For more det ails
on t he 82599 loopback modes, refer t o t he I nt el
Et hernet Cont rollers Loopback Modes

Guide.
I nt el
82599 10 GbE Cont r ol l er Di agnost i cs

834
Gl ossar y and Acr ony ms I nt el

835
15. 0 Gl ossar y and Acr ony ms
Ter m Def i ni t i on
1 KB A value of 1 KB equals 1024 byt es.
1s compliment
A syst em known as ones' complement can be used t o represent negat ive numbers in a binary syst em.
The ones' complement form of a negat ive binary number is t he bit wise NOT applied t o it .
2s compliment
A syst em of t wo' s- complement arit hmet ic represent s negat ive int egers by count ing backwards and
wrapping around. Any number whose left - most bit is 1 is considered negat ive.
1000BASE- BX
1000BASE- BX is t he PI CMG 3. 1 elect rical specificat ion for t ransmission of 1 Gb/ s Et hernet or 1 Gb/ s
fibre channel encoded dat a over t he backplane.
1000BASE-T
1000BASE-T is t he specificat ion for 1 Gb/ s Et hernet over cat egory 5e t wist ed pair cables as defined in
I EEE 802. 3 clause 40.
1000BASE- BX
1000BASE- BX is t he PI CMG 3. 1 elect rical specificat ion for t ransmission of 1 Gb/ s Et hernet or 1 Gb/ s
Fibre Channel encoded dat a over t he backplane.
1000BASE- CX
1000BASE- CX over specially shielded 150 O balanced copper j umper cable assemblies as specified in
I EEE 802. 3 Clause 39.
10GBASE- BX4
10GBASE- BX4 is t he PI CMG 3. 1 elect rical specificat ion for t ransmission of 10 Gb/ s Et hernet or 10 Gb/ s
Fibre Channel encoded dat a over t he backplane.
10GBASE- CX4
10GBASE- CX4 over shielded 100 O balanced copper j umper cable assemblies as specified in I EEE
802. 3 Clause 54.
AAD Addit ional Aut hent icat ion Dat a input , which is aut hent icat ed dat a t hat must be left un- encrypt ed.
ACBS Aut o Connect Bat t ery Saver
ACK Acknowledgement
ACPI Advanced Configurat ion and Power I nt erface ACPI reset is also known as D3hot - D0 t ransit ion.
ADC Analog t o Digit al Convert er
AEN Address Enable
AER Advanced Error Report ing
AFE Analog Front End
AH
I P Aut hent icat ion Header An I Psec header providing aut hent icat ion capabilit ies defined in RFC 2402
For an example of an AH packet diagram see below:
- Next Header: I dent ifies t he prot ocol of t he t ransferred dat a.
- Payload Lengt h: Size of AH packet .
- RESERVED: Reserved for fut ure use ( all zero unt il t hen) .
- Securit y Paramet ers I ndex ( SPI ) : I dent ifies t he securit y paramet ers, which, in combinat ion wit h t he
I P address, t hen ident ify t he Securit y Associat ion implement ed wit h t his packet .
- Sequence Number: Monot onically increasing number, used t o prevent replay at t acks.
Aut hent icat ion Dat a: Cont ains t he int egrit y check value ( I CV) necessary t o aut hent icat e t he packet ; it
may cont ain padding.
AI FS
Adapt ive I FS t hrot t les back- t o- back t ransmissions in t he t ransmit MAC and delays t heir t ransfer t o t he
CSMA/ CD t ransmit funct ion
AGC Aut omat ic Gain Cont rol
I nt el
82599 10 GbE Cont r ol l er Gl ossar y and Acr onyms

836
AMT Act ive Management Technology ( I nt el AMT)
AN Aut o negot iat ion
AN Associat ion Number
API C Advanced Programming I nt errupt Cont roller
APM Advanced Power Management
APT Advanced Pass Through mode
ARD Aut o- scan Read Dat a
ARI
Alt ernat ive Rout ing I D capabilit y st ruct ure This is a new capabilit y t hat allows an int erpret at ion of t he
Device and Funct ion fields as a single ident ificat ion of a funct ion wit hin t he bus.
ARI Alt ernat e Request er I D I nt erpret at ion
ARP Address Resolut ion Prot ocol
b/ w or BW Bandwidt h
backbone a bus shared by many client s for example a management backbone or a host backbone
BAR Base Address Regist er
BCN Backward Congest ion Not ificat ion.
BCNA BCN Address
BDF Bus/ Device/ Funct ion
BER Bit Error Rat e
BI OS Basic I nput / Out put Syst em.
BI ST Built - I n Self Test
BKM Best Known Met hod
BMC Best Mast er Clock
BMC Baseboard Management Cont roller
BME Bus Mast er Enable
BT Byt e Time.
BYTE alignment I mplies t hat t he physical addresses can be odd or even. Examples: 0FECBD9A1h, 02345ADC6h.
BWG Bandwidt h Group.
CA
secure Connect ivit y Associat ion ( CA) : A securit y relat ionship, est ablished and maint ained by key
agreement prot ocols, t hat comprises a fully connect ed subset of t he service access point s in st at ions
at t ached t o a single LAN t hat are t o be support ed by LinkSec.
CAM Cont ent Addressable Memory
CB Cir cuit Br eaker
CCS Current Cipher Suit e
Ciphert ext Encrypt ed dat a, whose lengt h is exact ly t hat of t he plaint ext .
CFI Canonical Form I ndicat or
CI M Common I nformat ion Model Specificat ion
CML Current Mode Logic
CM-Tag Congest ion Management t ag
concurrency
The concurrent ( simult aneous) execut ion of mult iple int eract ing comput at ional t asks. These t asks may
be implement ed as separat e programs, or as a set of processes or t hreads creat ed by a single
pr ogram.

837
corner case
is a problem or sit uat ion t hat occurs only out side of normal operat ing paramet ers specifically one
t hat manifest s it self when mult iple environment al variables or condit ions are simult aneously at
ext reme levels.
For example, a comput er server may be unreliable, but only wit h t he maximum complement of 64
processors, 512 GB of memory, and over 10, 000 signed- on users. From Wiki.
CPI D
Congest ion Point I dent ifier which should include t he congest ion point Et hernet MAC Address, as well
as a local ident ifier for t he local congest ion ent it y, usually a queue in t he swit ch.
CRC
Cyclic Redundancy Check
A cyclic redundancy check ( CRC) is a t ype of funct ion t hat t akes as input a dat a st ream of unlimit ed
lengt h and produces as out put a value of a cert ain fixed size. The t erm CRC is oft en used t o denot e
eit her t he funct ion or t he funct ion' s out put . A CRC can be used in t he same way as a checksum t o
det ect accident al alt erat ion of dat a during t ransmission or st orage. CRCs are popular because t hey are
simple t o implement in binary hardware, are easy t o analyze mat hemat ically, and are part icularly good
at det ect ing common errors caused by noise in t ransmission channels. From Wiki
CRS Carrier Sense I ndicat ion.
CSMA/ CD
802. 3 Carrier Sense Mult iple Access / Collision Domain Et hernet LCI - 2 I nt erface t o an ext ernal LAN
Connect ed Device t o provide wired LAN connect ivit y.
CSR Cont rol / St at us Regist er
CTS Cisco Trust ed Securit y
D0a
D0 Act ive
Act ive fully operat ional st at e. Once memory space is enabled all int ernal clocks are act ivat ed and t he
LAN Cont roller ent ers an act ive st at e.
D0u
D0
uninit ialized
The D0u st at e is a lowpower st at e used aft er PCI Reset ( SPXB Reset ) is deassert ed following power-
up ( cold or warm) , or on D3 exit .
D3Hot
I n D3 t he LAN Cont roller only responds t o PCI configurat ion accesses and does not generat e mast er
cycles.
D3Cold
Power Off if Vcc is removed from t he device and all of it s PCI funct ions t ransit ion immediat ely t o D3
cold. When power is rest ored a PCI Reset must be assert ed.
Dr I nt ernal Power management st at e when minimal funct ion is provided ( WoL, Manageabilit y)
DMoff
The DMoff st at e is a lowpower st at e following t he assert ion of PCI m reset or following programming of
t he DM st at e in t he PCI m configurat ion space t o 100b.
DA Dest inat ion Address
DAC Digit al t o Analog Convert er
DAC Dual Address Cycle messages
Dat a Frame FC Frames t hat carry read or writ e dat a.
DBU Dat a Buffer Unit
DCA Direct Cache Access
DCB Dat a Cent er Bridging.
DCX DCB Configurat ion Exchange prot ocol
DDP Direct Dat a placement
DFE Decision Feedback Equalizer
DFT Test abilit y.
DFX Design for *
DHCP
Dynamic Host Configurat ion Prot ocol ( prot ocol for aut omat ing t he configurat ion of comput ers t hat use
TCP/ I P)
DLLP Dat a Link Layer Packet / PCI e
DMA Direct Memory Addressing
I nt el

838
DMA engine dat a movement engine
DME different ial Manchest er encoding
DMTF NC- SI
Dist ribut ed Management Task Force
BMC- NI C int erconnect for management
DPC
Defer red Procedure Call
O/ S t ask for handling int errupt s.
DQ Descript or Queue.
DSP Digit al Signal Processor
DUT Device Under Test
DWORD ( Double-Word)
alignment
I mplies t hat t he physical addresses may only be aligned on 4- byt e boundaries; i. e., t he last nibble of
t he address may only end in 0, 4, 8, or Ch. For example, 0FECBD9A8h.
EAPOL Ext ensible Aut hent icat ion Prot ocol over LAN
EAS Ext ernal Archit ect ure Specificat ion.
ECC Error Correct ion Coding
ECRC End t o End CRC
EDB End Dat a Bit
ECC Error Correct ion Coding
EEPROM
Elect rically Erasable Programmable Memory. A non- volat ile memory locat ed on t he LAN cont roller t hat
is direct ly accessible from t he host .
EHS Ext ernal Heat Sink
EOP End- Of- Packet ; when set indicat es t he last descript or making up t he packet .
EP End point
ESN Ext ended Sequence Number
E- SOF FCoE St art of Frame
ESP
I P Encapsulat ing Securit y Payload An I Psec header providing encrypt ion and aut hent icat ion
capabilit ies defined in RFC 4303. The Encapsulat ing Securit y Payload ( ESP) ext ension header provides
origin aut hent icit y, int egrit y, and confident ialit y prot ect ion of a packet . ESP also support s encrypt ion-
only and aut hent icat ion- only configurat ions, but using encrypt ion wit hout aut hent icat ion is st rongly
discouraged. Unlike t he AH header, t he I P packet header is not account ed for. ESP operat es direct ly on
t op of I P, using I P prot ocol number 50. ESP fields:
- Securit y Paramet ers I ndex ( SPI ) : See AH
- Sequence Number: See AH
- Payload Dat a: See AH
- Padding: Used wit h some block ciphers t o pad t he dat a t o t he full lengt h of a block.
- Pad Lengt h: Size of padding in byt es.
- Next Header: I dent ifies t he prot ocol of t he t ransferred dat a.
- Aut hent icat ion Dat a: Cont ains t he dat a used t o aut hent icat e t he packet .
EUI I EEE defined 64- bit Ext ended Unique I dent ifier
Ext ension Header I Pv6 prot ocol.
Fail- over
failover is t he abilit y t o det ect t hat t he LAN connect ion on one port is lost , and enable t he ot her port
for t raffic.
FC Fiber Channel
FC Flow Cont rol.
FCoE Fiber Channel over Et hernet
FC Exchange
Complet e Fiber Channel Read or Fiber Channel Writ e flow. I t st art s wit h t he read or writ e request s by
t he init iat or ( t he host syst em) t ill t he complet ion indicat ion from t he t arget ( t he remot e disk) .
FCS Frame Check Sequence of Et hernet frames

839
FC Sequence
A Fiber Channel Exchange is composed of mult iple Fiber Channel sequences. Fiber Channel Sequence
can be a single or mult iple frames t hat are sent by t he init iat or or t he t arget . Each FC Sequence has a
unique Sequence I D.
FC Frame
Fiber Channel Frames are t he smallest unit s sent bet ween t he init iat or and t he t arget . The FC- FS- 2
spec define t he maximum frame size as 2112 byt es. Each Fiber Channel frame includes an FC header
and opt ional FC payload. I t can also may include Ext ended headers and FC opt ional headers. Ext ended
headers are not expect ed in FCoE net work and FC opt ional headers may not be used as well.
FCP_RSP Frame
Fiber Channel cont rol Frames t hat are sent from t he t arget t o t he init iat or which defines t he
complet ion of an FC read or writ e exchange.
FCS Frame Check Sequence of Et hernet frames
FEC Forward Error Correct ion
FEXT Far End Crosst alk
Firmware ( FW)
Embedded code on t he LAN cont roller t hat is responsible for t he implement at ion of t he NC- SI prot ocol
and pass t hrough funct ionalit y.
FLR
Funct ion level reset An OS in a VM must have complet e cont rol over a device, including it s
init ializat ion, wit hout int erfering wit h t he rest of t he funct ions.
FML Fast Management Link
Fragment Header An I Pv6 ext ension Header
Frame A unit composed of headers, dat a and foot ers t hat are sent or received by a device. Same as a Packet
FSM Finit e St at e Machine
FTS Fast Training Sequence
GbE Gigabit Et hernet ( I EEE 802. 3z- 1998)
GMRP GARP Mult icast Regist rat ion Prot ocol ( Cisco)
GPI O General Purpose I / O
GSP Group St rict Priorit y
HBA Host Bus Adapt ers
HDX Half duplex
Host I nt erface
RAM on t he LAN cont roller t hat is shared bet ween t he firmware and t he host . RAM is used t o pass
commands from t he host t o firmware and responses from t he firmware t o t he host .
HPC High Performance Comput ing.
HT core opt ion
Hyper Thread I nt el' s t rademark for implement at ion of t he simult aneous mult it hreading t echnology on
t he Pent ium 4 microarchit ect ure. I t is a more advanced form of Super- t hreading t hat debut ed on t he
I nt el Xeon processors and was lat er added t o Pent ium 4 processors. The t echnology improves
processor performance under cert ain workloads by providing useful work for execut ion unit s t hat
would ot herwise be idle, for example during a cache miss. A Pent ium 4 wit h Hyper-Threading enabled
is t reat ed by t he operat ing syst em as t wo processors inst ead of one. From Wiki
I 2C Two Serial Management I nt erfaces
I ANA I nt ernet Assigned Number Aut horit y
I CV
128- bit s I nt egrit y Check Value ( referred also as aut hent icat ion t ag) . used for LinkSec header and
signat ure
I DS int rusion det ect ion syst ems
I FCS I nsert Frame Check Sequence of Et hernet frames
I FS I nt er Frame Spacing
I KE I nt ernet Key Exchange
I OAT I / O Accelerat ion Technology
I OH I / O Hub
I nt el

840
I OV I nput Out put Virt ualizat ion
I OV mode operat ing t hrough an I OVM or I OVI
I OVI
I / O Virt ual I nt ermediary: A special virt ual machine t hat owns t he physical device and is responsible for
t he configurat ion of t he physical device.
Also Known As I OVM
I OVM
I / O Virt ual Machine: A special virt ual machine t hat owns t he physical device and is responsible for t he
configurat ion of t he physical device.
Also Known As I OVI
I P t unneling
I P t unneling is t he process of embedding one I P packet inside of anot her, for t he purpose of simulat ing
a physical connect ion bet ween t wo remot e net works across an int ermediat e net work.
I P t unnels are oft en used in conj unct ion wit h I PSec prot ocol t o creat e a VPN bet ween t wo or more
remot e net works across a " host ile" net work such as t he I nt ernet .
I PC I nt er Processor Communicat ion.
I P CPMP Carrier Performance Measurement Plan
I PG I nt er Packet Gap.
I P Sec
I P securit y) is a suit e of prot ocols for securing I nt ernet Prot ocol ( I P) communicat ions by
aut hent icat ing and/ or encrypt ing each I P packet in a dat a st ream. I Psec also includes prot ocols for
crypt ographic key est ablishment .
I Psec is implement ed by a set of crypt ographic prot ocols for ( 1) securing packet flows and ( 2) int ernet
key exchange. There are t wo families of key exchange prot ocols.
The I P securit y archit ect ure uses t he concept of a securit y associat ion as t he basis for building securit y
funct ions int o I P. A securit y associat ion is simply t he bundle of algorit hms and paramet ers ( such as
keys) t hat is being used t o encrypt a part icular flow. The act ual choice of algorit hm is left up t o t he
users. A securit y paramet er index ( SPI ) is provided along wit h t he dest inat ion address t o allow t he
securit y associat ion for a packet t o be looked up.
For mult icast , t herefore, a securit y associat ion is provided for t he group, and is duplicat ed across all
aut horized receivers of t he group. There may be more t han one securit y associat ion for a group, using
different SPI s, t hereby allowing mult iple levels and set s of securit y wit hin a group. I ndeed, each
sender can have mult iple securit y associat ions, allowing aut hent icat ion, since a receiver can only know
t hat someone knowing t he keys sent t he dat a. Not e t hat t he st andard doesn' t describe how t he
associat ion is chosen and duplicat ed across t he group; it is assumed t hat a responsible part y will make
t he choice. From Wiki
iSCSI
I nt er net SCSI ( iSCSI ) is a net work prot ocol st andard, officially rat ified on 2003- 02- 11 by t he I nt ernet
Engineering Task Force, t hat allows t he use of t he SCSI prot ocol over TCP/ I P net works. iSCSI is a
t ransport layer prot ocol in t he SCSI - 3 specificat ions framework. Ot her prot ocols in t he t ransport layer
include SCSI Parallel I nt erface ( SPI ) , Serial At t ached SCSI ( SAS) and Fibre Channel. From Wiki.
I SR I nt errupt Service Rout ine
I TR I nt errupt Throt t ling
I V I nt egrit y Value
I V I nit ializat ion Vect or
I V I nit ial Value
KaY
Key agreement ent it y ( KaY in 802. 1AE spec t erminology) i. e. cont rol and access t he off loading
engine ( SecY in 802. 1AE spec t erminology)
KVM Keyboard Video Mouse
LACP Link Aggregat ion Cont rol Prot ocol
LAN ( auxiliary Power- Up) The event of connect ing t he LAN cont roller t o a power source ( occurs even before syst em power- up) .
landing Zone
requirement s
General t arget s for t he product .
LCAPD LAN Cont roller Act ive Power Down
LF Local Fault

841
LinkSec ( or MACsec,
802. 1AE)
is a MAC level encrypt ion/ aut hent icat ion scheme defined in I EEE 802. 1AE t hat uses symmet ric
crypt ography. The 802. 1AE defines an AES- GCM 128 bit key as a mandat ory cipher suit e which can be
processed by t he LAN cont roller.
LLC header
802. 2 defines a special header t hat includes a SNAP ( subnet work access prot ocol) header. Some
prot ocols, part icularly t hose designed for t he OSI net working st ack, operat e direct ly on t op of 802. 2
LLC, which provides bot h dat agram and connect ion- orient ed net work services. This 802. 2 header is
current ly embedded in modern 802. 3 frames ( Et hernet I I frames, aka. DI X frames) .
The LLC header includes t wo addit ional eight - bit address fields, called service access point s or SAPs in
OSI t erminology; when bot h source and dest inat ion SAP are set t o t he value 0xAA, t he SNAP service is
request ed. The SNAP header allows Et herType values t o be used wit h all I EEE 802 prot ocols, as well as
support ing privat e prot ocol I D spaces. I n I EEE 802. 3x- 1997, t he I EEE Et hernet st andard was changed
t o explicit ly allow t he use of t he 16- bit field aft er t he Et hernet MAC Addresses t o be used as a lengt h
field or a t ype field. This definit ion is from Wiki
LLDP Link Layer Discovery Prot ocol
LLI NT Low Lat ency I nt errupt
Local Traffic I n a virt ual environment t raffic bet ween virt ual machines.
LOM LAN on Mot herboard.
LP Link Part ner
LSC Link St at us Change
LS Least significant / Lowest order ( for example: LS bit = Least significant bit )
LSO Large Send Offload, same as TSO
LSP Link St rict Priorit y
LTSSM Link Training and St at us St at e Machine Defined in t he PCI e specs.
MAC Media Access Cont rol.
MAUI Mult i Speed At t achment Unit I nt erface
MCH Memory Cont roller Hub
MDC Management Dat a Clock
MDI Management Dat a I nt erface
MDI C MDI Cont rol Regist er
MDI O Management Dat a I nput / Out put I nt erface over MDC/ MDI O lines.
MFVC Mult i- Funct ion Virt ual Channel Capabilit y st ruct ure
MI B Management I nt erface Bus
MI FS/ MI PG Minimum I nt er Frame Spacing/ Minimum I nt er Packet Gap.
MMD MDI O Managed Device
MMW Maximum Memory Window.
Mod / Modulo I n comput ing, t he modulo operat ion finds t he remainder of division of one number by anot her.
MPA Marker PDU Aligned Framing for TCP
MPDU MACSEC Prot ocol Dat a Unit including SecTag, User Dat a and I CV
MRQC Mult iple Receive Queues Command regist er
MS Most significant / Highest order ( for example: MS byt e = Most significant byt e)
MSFT RSS Microsoft RSS specificat ion
MSI Message Signaled I nt errupt
MSS Maximum Segment Size
MTA Mult icast Table Array
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MTU Maximum Transmission Unit
NACK Negat ive Acknowledgement
nat ive mode Used for GPI O pin t hat is set t o be cont rolled by t he int ernal logic rat her t han by soft ware.
NC- SI Net work Cont roller Sideband I nt erface
NEXT Near End Crosst alk
Next Generat ion VMDq
SW swit ch accelerat ion modecent ral management of t he net working resources by an I OVM or by t he
VMM.
Virt ual Machine Devices queue ( VMDq) is a mechanism t o share I / O resources among several
consumers. For example, in a virt ual syst em, mult iple OSs are loaded and each execut es as t hough
t he whole syst ems resources were at it s disposal. However, for t he limit ed number of I / O devices, t his
present s a problem because each OS may be in a separat e memory domain and all t he dat a movement
and device management has t o be done by a VMM ( Virt ual Machine Monit or) . VMM access adds
lat ency and delay t o I / O accesses and degrades I / O performance. VMDs ( Virt ual Machine Devices) are
designed t o reduce t he burden of VMM by making cert ain funct ions of an I / O device shared and t hus
can be accessed direct ly from each guest OS or Virt ual Machine ( VM) .
NI C Net work I nt erface Cont roller.
NFTS Number of Fast Training Signals
NFS Net work File Server
non- t eaming mode
I f t he LAN is in non- t eaming mode, t he SMBus is present ed as t wo SMBus devices on t he SMBus ( t wo
SMBus addresses) .
Nonce
96- bit s init ializat ion vect or used by t he AES- 128 engine, which is dist inct for each invocat ion of t he
encrypt ion operat ion for a fixed key. I t is formed by t he AES- 128 SALT field st ored for t hat I Psec flow
in t he Tx SA Table, appended wit h t he I nit ializat ion Vect or ( I V) field included in t he I Psec packet :
NOS Net work Operat ing Syst em
NPRD Non- Post ed Request Dat a
NRZ non- ret urn- t o- zero signaling
NTL No Touch Leakage
NTP Net work Time Prot ocol
OEM Original Equipment manufact urer
Core Net work I nt erface Regist ers
Packet
A unit composed of headers, dat a and foot ers t hat are sent or received by a device. Also known as a
frame.
PARAGRAPH alignment
I mplies t hat t he physical addresses may only be aligned on 16- byt e boundaries; i. e., t he last nibble
must be a 0. For example, 02345ADC0h.
Pass Filt ers Needs Definit ion Packet s t hat mat ch t his t ype of filt er cont inue on t o t heir dest inat ion?
PB Packet Buffer
PBA The nine- digit ( Print ed Board Assembly) number used for I nt el manufact ured adapt er cards.
PBA Pending Bit Array
PBA Print ed Board Assembly
PCS Physical Coding Sub layer.
PDU Prot ocol Dat a Unit s
PF Physical Funct ion ( in a virt ualizat ion cont ext ) .
PFC Priorit y Flow Cont rol
PHY Physical Layer Device.
Plaint ext Dat a t o be bot h aut hent icat ed and encrypt ed.

843
PMA Physical Medium At t achment
PMC Power Management Capabilit ies
PMD Physical Medium Dependent .
PME Power Management Event
PN
Packet Number ( PN) in a LinkSec cont ext : Monot onically increasing value used t o uniquely ident ify a
LinkSec frame in t he sequence.
Pool Virt ual port s
Power St at e D0a
Act ive fully operat ional st at e. Once memory space is enabled all int ernal clocks are act ivat ed and t he
LAN Cont roller ent ers an act ive st at e.
Power St at e D0u
The D0u st at e is a lowpower st at e used aft er SPXB Reset is deassert ed following power- up ( cold or
warm) , or on D3 exit .
Power St at e D3Hot A Power down st at e wit h t he PCI cont inuing t o receive a proper power supply.
Power St at e D3Cold A Power down st at e wit h t he PCI also in a power down st at e.
Power St at e Dr Device st at e when PCI e reset is assert ed.
Power St at e Sx Lan Connect ed Device: SMBus Act ive and PCI Powered down.
Power St at e DMoff
The DMoff st at e is a lowpower st at e following t he assert ion of PCI m reset or following programming of
t he DM st at e in t he PCI m configurat ion space t o 100b.
PPM Packet Processor Module
PRBS Pseudo- Random Binary Sequence
PT Pass Through
PTP Precision Time Prot ocol
QoS Qualit y of Service
QWORD ( Quad-Word)
alignment
I mplies t hat t he physical addresses may only be aligned on 8byt e boundaries; i. e., t he last nibble of
t he address may only end in 0, or 8. For example, 0FECBD9A8h.
Receive lat ency measured from packet recept ion from t he wire and unt il t he descript or is updat ed on PCI e.
RDMA Remot e Direct Memory Access
RDMAP Remot e Direct Memory Access Prot ocol
Relax ordering
When t he st rict order of packet s is not required, t he device can send packet s in an order t hat allows for
less power consumpt ion and great er CPU efficiency.
RI D Request er I D
RLT Rat e- limit ed flag bit
RMCP Remot e Management and Cont rol Prot ocol ( Dist ribut ed Management Task Force)
RMI I Reduced Media I ndependent I nt erface ( Reduced MI I )
RMI I NC- SI Reduced Media I ndependent I nt erface ( Reduced MI I ) .
RMON st at ist ics Remot e Net work Monit oring or Remot e Monit oring
RPC header Remot e Procedure Call
RS Rat e Scheduler
RSC
Receive Side Coalescing coalesces incoming TCP/ I P ( and pot ent ially UDP/ I P) packet s int o larger
receive segment s
RSS
Receive- Side Scaling is a mechanism t o dist ribut e received packet s int o several descript or queues.
Soft ware t hen assigns each queue t o a different processor, t herefore sharing t he load of packet
processing among several processors
RSTD Reset Sequence Done
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RSTI Reset Sequence in Process
RTT Round Trip Time
Rx, RX Receive
SA Securit y Associat ion
SA Source Address.
SA ( in a LinkSec cont ext )
Secure Associat ion ( SA) : A securit y relat ionship t hat provides securit y guarant ees for frames
t ransmit t ed from one member of a CA t o t he ot hers. Each SA is support ed by a single secret key, or a
single set of keys where t he crypt ographic operat ions used t o prot ect one frame require more t han one
key.
SAC Single Address Cycle ( SAC) messages
SAK Securit y Associat ions Key
salt
I n crypt ography, a salt consist s of random bit s used as one of t he input s t o a key derivat ion funct ion.
Somet imes t he init ializat ion vect or, a previously generat ed ( preferably random) value, is used as a
salt . The ot her input is usually a password or passphrase. The out put of t he key derivat ion funct ion is
oft en st ored as t he encrypt ed version of t he password. A salt value can also be used as a key for use in
a cipher or ot her crypt ographic algorit hm. A salt value is t ypically used in a hash funct ion. from Wiki
SAN St orage Area Net works
SAP Service Access Point an ident ifying label for net work endpoint s used in OSI net working.
SC Secure Channel Aut hent icat ion and key exchange
SC
Secure Channel ( SC) : A securit y relat ionship used t o provide securit y guarant ees for frames
t ransmit t ed from one member of a CA t o t he ot hers. An SC is support ed by a sequence of SAs t hus
allowing t he periodic use of fresh keys wit hout t erminat ing t he relat ionship.
SCI
Secure Channel I dent ifier A globally unique ident ifier for a secure channel, comprising a globally
unique Et hernet MAC Address and a Port I dent ifier, unique wit hin t he syst em allocat ed t hat address.
SCSI
Small Comput er Syst em I nt erface is a set of st andards for physically connect ing and t ransferring dat a
bet ween comput ers and peripheral devices. The SCSI st andards define commands, prot ocols, and
elect rical and opt ical int erfaces. SCSI is most commonly used for hard disks and t ape drives, but it can
connect a wide range of ot her devices, including scanners, and opt ical drives ( CD, DVD, et c. From
Wiki.
SCL signal SM Bus Clock
SCTP St ream Cont rol Transmission Prot ocol
SDA signal SM Bus Dat a
SDP Soft ware- Definable Pins
SecY 802. 1AE spec t erminology Securit y ent it y
Segment subsect ions of a packet
SerDes Serializer and De- Serializer Circuit .
SFD St art Frame Delimit er
SFI Serial Flash I nt erface
SI BI ST Serial I nt erface Built - in Self Test
SGMI I Serialized Gigabit Media I ndependent I nt erface.
SKU subset s of feat ures of a chip t hat can be disabled for market ing purposes.
SNMP St andard Net work Management Prot ocol
Smadar Regist ers XTAL and Bias Regist ers
SMB Semaphore Bit
SMBus
Syst em Management Bus. A bus t hat carries various manageabilit y component s, including t he LAN
cont roller, BI OS, sensors and remot e- cont rol devices.

845
SN Sequence Number cont ains a count er value t hat increases by one for each Et hernet frame sent .
SNAP Subnet work Access Prot ocol
SoL
Serial Over LAN
Serial Over LAN is a mechanism t hat enables t he input and out put of t he serial port of a managed
syst em t o be redirect ed via an I PMI ( I nt ernet Prot ocol Mult icast I nit iat ive) session over I P.
SPD Smart Power Down
SPI
The Securit y Paramet er I ndex is an ident ificat ion t ag added t o t he header while using I PSec for
t unneling t he I P t raffic. This t ag helps t he kernel discern bet ween t wo t raffic st reams where different
encrypt ion rules and algorit hms may be in use.
The SPI ( as per RFC 2401) is an essent ial part of an I PSec SA ( Securit y Associat ion) because it enables
t he receiving syst em t o select t he SA under which a received packet will be processed. An SPI has only
local significance, since is defined by t he creat or of t he SA; an SPI is generally viewed as an opaque bit
st ring. However, t he creat or of an SA may int erpret t he bit s in an SPI t o facilit at e local processing.
from Wikipedia
SPXB int erface PCI Express Backbone
Spoofing
I n comput er net working, t he t erm I P address spoofing is t he creat ion of I P packet s wit h a forged
( spoofed) source I P address wit h t he purpose t o conceal t he ident it y of t he sender or impersonat ing
anot her comput ing syst em. I P st ands for I nt ernet Prot ocol. from Wiki
SR- I OV PCI - SI G single- root I / O Virt ualizat ion init iat ive
SW Swit ch accelerat ion
mode
Cent ral management of t he net working resources by an I OVM or by t he VMM. Also known as VMDq2
mode.
SWI ZZLE
To convert ext ernal names, array indices, or references wit hin a dat a st ruct ure int o address point ers
when t he dat a st ruct ure is brought int o main memory from ext ernal st orage ( also called point er
swizzling) ;
Sx Lan Connect ed Device: SMBus Act ive and PCI Powered down.
SYN At t ack
A SYN at t ack is a form of denial- of- service at t ack in which an at t acker sends a succession of SYN
( synchronize) request s t o a t arget ' s syst em.
TC Traffic Class
TCI For 802. 1q, Tag Header field Tag Cont rol I nformat ion ( TCI ) ; 2 oct et s.
TCO Tot al Cost of Ownership ( Management )
TCP/ I P Transmission Cont rol Prot ocol/ I nt ernet Prot ocol
TDESC Transmit Descript or
TDP Tot al Device Power
TDR Time Domain Reflect omet ry
Teaming Mode
When t he LAN is in Teaming mode, t he 82599 is present ed over t he SMBus as one device and has one
SMBus address.
TFCS Transmit Flow Cont rol St at us
TLP Transact ion layer Packet s
ToS Type of Service
TPI D For 802. 1q, Tag Header field Tag Prot ocol I dent ifier; 2 oct et s.
TPPAC Transmit Packet Plane Arbit rat ion Cont rol
Transmit lat ency
measured from Tail updat e unt il t he packet is t ransmit t ed on t he wire. I t is assumed t hat a single
packet is submit t ed for t his t raffic class and it s lat ency is t hen measured in presence of t raffic
belonging t o ot her t raffic classes.
TS Time St amp
TSO
TCP or Transmit Segment at ion offload A mode in which a large TCP/ UDP I / O is handled t o t he device
and t he device segment s it t o L2 packet s according t o t he request ed MSS.
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846
TSS Transmit Side Scaling
Tx, TX Transmit
UBWG User Bandwidt h Group
ULP Upper Layer Prot ocol
UP User Priorit y
UR Error Report ing Unsupport ed Request Error
VF Virt ual Funct ion A part of a PF assigned t o a VI
VI
Virt ual I mage A virt ual machine t o which a part of t he I / O resources is assigned. Also known as a
VM.
VM Virt ual Machine
VMM Virt ual Machine Monit or
VPD Vit al Product Dat a ( PCI prot ocol) .
VT Virt ualizat ion
WB Writ e Back
WC Worst Case
WfM
Wired for Management
was a primarily hardware- based syst em allowing a newly built comput er wit hout any soft ware t o be
manipulat ed by a mast er comput er t hat could access t he hard disk of t he new PC t o past e t he inst all
program. I t could also be used t o updat e soft ware and monit or syst em st at us remot ely. I nt el
developed t he syst em in t he 1990s; it is now considered obsolet e.
WoL Wake- on- LAN Now called APM Wake up or Advanced power management Wake up.
WORD alignment
I mplies t hat physical addresses must be aligned on even boundaries; i. e., t he last nibble of t he address
may only end in 0, 2, 4, 6, 8, Ah, Ch, or Eh. For example, 0FECBD9A2h.
WRR Weight ed Round- Robin
WSP Weight ed St rict Priorit y
WWDM Wide Wave Division Mult iplexing
XAUI 10 Gigabit At t achment Unit I nt erface
XFP 10 Gigabit Small Form Fact or Pluggable modules
XGMI I 10 Gigabit Media I ndependent I nt erface
XGXS XGMI I Ext ender Sub layer
XMT Frame Out ( XFO) Most Recent Transmit Buffer Tail Regist er cont ent

847
15.1 Regi st er At t r i but es
At t r i but e Descr i pt i on
RO
Read Only: Writ es t o t his regist er set t ing do not affect t he regist er value. Reads ret urn eit her a
const ant or variable device st at e.
RW
Read Writ e: Writ es t o t his regist er set t ing alt er t he regist er value. Reads ret urn t he value of t he
regist er.
RW1C
Read Writ e Clear: Regist er t hat is set t o 1b by hardware, and cleared t o 0b by soft ware writ ing a 1b
t o t he regist er
RWS
Read Writ e Set : Regist er t hat is set t o1b by soft ware by writ ing a 1b t o t he regist er, and cleared t o
0b by hardware. Not at ion used in CSR sect ions
RWS
Read- writ e regist er: Regist er bit s are read- writ e and can be eit her set or reset by soft ware t o t he
desired st at e. Bit s are not cleared by reset and can only be reset wit h t he PWRGOOD signal.
Devices t hat consume AUX power are not allowed t o reset st icky bit s when AUX power consumpt ion
( eit her via AUX power or PME Enable) is enabled. Not at ion used in PCI Express* Programming
I nt erface chapt er.
WO Writ e Only: Writ es t o t his regist er alt ers t he regist er value. Reads always ret urn 0b.
RC
Read Clear. A regist er bit wit h t his at t ribut e is cleared aft er read. Writ es have no effect on t he bit
value.
RW/ RC Read/ Writ e and Read Clear.
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848

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82599 10 GbE Cont r ol l er Copy r i ght

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