IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO.

4, APRIL 2011

701

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor
Jaehyouk Choi, Stephen T. Kim, Woonyun Kim, Kwan-Woo Kim, Kyutae Lim, and Joy Laskar

AbstractA programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- m CMOS technology. Utilizing the proposed pulse generator, purely consisting of D ip ops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is 88.7 and 99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm . Index TermsClock generator, delay cell, delay locked loop (DLL), multiplication factor, programmable.

Fig. 1. Proposed DLL-based clock generator.

I. INTRODUCTION In recent years, there have been increasing demands on clock generators capable of providing multiple-frequency clock signals in a wide frequency band for microprocessors, clock and data recoveries and mobile communication systems. Delay locked loop (DLL)-based clock generators present strong advantages over conventional phase locked loop (PLL)-based approaches: better phase noise performance, robustness under PVT variation, simple, and compact loop lter design and fast settling times [1][4]. Recently, several DLL-based clock generators have been suggested in [4][9] that generate the multiplied output clock by combining sub-pulses from delayed edges of the voltage controlled delay line (VCDL). In prior architectures, two consecutive delayed edges were used to generate a sub-pulse. Thus, there exists an overhead on the number of unit delay cells because the number of required unit delay cells is 2n for achieving a frequency multiplication factor of n. Also, an additional pulse selection process is necessary to select the required sub-pulses from all of the generated ones to program a multiplication factor, which consumes unnecessary power. In this paper, a new simple clock generator consisting of a DLL, a pulse generator, and a pulse combiner is proposed. In the proposed architecture, each sub-pulse is generated from one corresponding unit delay cell. Therefore, a high multiplication factor and wide range of the output clock frequency can be obtained with a fewer number of delay cell stages. In addition, power dissipation is minimized because the pulse generator consists purely of D ip-ops (DFFs) and inverters operating only when triggered in their turn. Also, since only the required sub-pulses are generated from the pulse generator for a target output signal frequency, an additional pulse selection process has been eliminated. In the design of the VCDL, a saturated-type differential delay cell [10], [11] with a latch and transmission gates is adopted, which can
Manuscript received June 10, 2009; revised September 12, 2009. First published December 18, 2009; current version published March 23, 2011. The authors are with the Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: jchoi3@gatech.edu; stephen.kim@gatech.edu; wnkim@ece.gatech.edu; gth690p@mail.gatech.edu; ktlim@ece.gatech.edu; joy.laskar@ece.gatech. edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2009.2036433

easily provide a long time delay. Thus, the proposed clock generator can be locked to a low-frequency reference clock without sacricing physical area to integrate a large number of delay cells. Furthermore, owing to a saturated-type conguration adopting a latch, a sub-pulse has a fast and full switching transition edge, which is essential for enhancing phase noise performance [11]. Finally, a power/area-efcient start-controlled circuit for preventing harmonic locking, which is critical in wide range DLL-based architectures, is proposed. The proposed clock generator can take input reference frequencies from 30 to 90 MHz, and the multiplication factor can be any common divisors of the number of delay cell stages, 24. Thus, wide range clock signals from 120 MHz to 2.16 GHz can be obtained from the proposed clock generator. II. OVERALL ARCHITECTURE Fig. 1 shows the overall block diagram of the proposed DLL-based clock generator consisting of a DLL, a pulse generator and a pulse combiner.WhentheDLL, implementedwith aphasedetector, achargepump, a loop lter, and a VCDL, locks to the reference clock, the VCDL generates 24 uniformly-spaced differential phase-shifted signals. The pulse generator detects the rising edge of the selected phase-shifted signals among 24 streams according to the programmed 2-bit signals and creates a short pulse from each selected signal. Then, the pulse combiner collects these short pulses and provides a multiplied clock. A. Proposed Pulse Generator Fig. 2 details the operation of the proposed pulse generator and the pulse combiner, specically, when M equals 12. When the phase shifted signal from the VCDL, 8k , enters to the corresponding k th DFF, Qk goes high if the value in the D node, Sk , is set to 1. In the meanwhile, Qbk goes low and resets Qk by triggering the RSTb node. Since this reset process takes two-inverter delay time, a short pulse of duration, 1 , is generated at Qk . Finally, the subsequent pulse combiner collects these pulses. In order to create only the required pulses, each Sk is set to either 0 or 1 according to the programmed 2-bit signals, C0 and C1 . Thus, one of four multiplication factors4, 8, 12, and 24can be selected. In the proposed pulse generator, since each DFF generates one pulse from the corresponding delay cell, a high multiplication factor of up to 24 has been obtained with the same number of delay cells in VCDL. Also, power consumption is reduced because the DFFs and inverters are operating only when clocks are triggering them. Furthermore, since unnecessary pulses for the specic output clock are not generated, a separate phase selection process is not required.

1063-8210/$26.00 2009 IEEE

702

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011

Fig. 2. Detail operation of the proposed pulse generator and combiner when equals 12.

Fig. 3. Delay cells adopted in the VCDL: (a) proposed delay cell (b) conventional Maneatis load delay cell [15].

The proposed clock generator targets mobile communication systems using only rising edges. However, some digital applications using both of rising and falling edges require 50% duty cycle. In the proposed delay cell, the differential signals, 8k and 8k b, are inherently generated from the differential-type architecture. Since another clock from 8k bs is supposed to have phase difference of  regarding the counterpart from 8k s, 50% duty cycle can be obtained by use of both clocks without sacricing the maximum output frequency. B. Proposed Delay Cell in the VCDL In order to be utilized in a DLL, the delay from the VCDL should be long enough to lock to the input reference clock. Generally, a long delay can be generated in two ways. First, utilizing a large number of delay cells with a relatively short unit delay can be considered. In this case, increase in area and power consumption is inevitable. Conversely, if a small number of delay cells are used, each unit-delay cell should generate a considerably long delay. This prevents a signal from having a fast-switching transition edge; the slow-switching edges are more prone to degrade phase noise performance [11]. The phase noise performance of the unit delay cell is the important factor determining that of the overall DLL-based clock generator [13]. This can be explained from the relation between the timing error variance of the unit delay cell, E (1d2 ), and that of the overall VCDL, E (1t2 VCDL ) as follows [13]:
E
2 1tVCDL = E (1d2 )
1

Fig. 4. Time transient simulation on generating 920 ps time-delay of the proposed delay cell and the conventional delay cell with a Maneatis load.

2N
I

(1)

where N , ICP , Kd , and CL denote the number of unit delay cell in the VCDL, the charge pump current, the gain of the delay cell, and the capacitance of the loop lter capacitor, respectively. Since the timing error variance can be directly translated to a jitter or a phase noise performance, (1) shows that a good phase noise performance of the delay cell is indispensable for achieving a good phase noise performance of the VCDL or the clock generator. Therefore, to create a long unit-delay with a fast-switching edge avoiding phase noise degradation, the architectural idea was adopted from the ring-type oscillator of [14]. Fig. 3(a) shows the proposed delay cell based on a pseudo-differential saturated-type conguration. In conventional delay cells, creating a long unit-delay inevitably results in slow signal transition, irrespective of a delay-making mechanism. However, in the proposed delay cell, the signal regains fast-switching edges by the cross-coupled pMOS latch. When the signal is injected, the latch

operates in the direction of opposing the signal transition in the pMOSs. However, after a while, the function of the latch changes into a positive feedback and accelerates the signal transition. Fig. 4 shows the signal transition characteristics of the proposed delay cell. When a 920 ps-delay is generated, the proposed delay cell makes a much steeper transition compared to the conventional Maneatis delay cell in Fig. 3(b). Also, due to the saturated-type conguration eliminating the tail transistor, the proposed delay cell allows for rail-to-rail output swing. Qualitatively, the more time transistors are turned-on, the more thermal noise current is generated from those devices. The fast-switching transition and the rail-to-rail swing imply shorter duration for transistors being turned-on, which intrinsically improves phase noise performance [10][12]. In addition, the elimination of the tail transistor reduces 1/f noise which is mainly contributed by bias devices, [16], [17]. This also can be explained by the phase noise analysis of ring oscillators [10]
L

(1!)= 512F27kT VR 3 
1 1 1

VDD

where F , SRmax , 1! , !o , kT , VDD and R are the excess noise factor, the maximum output slew rate, the angular frequency offset from the center frequency, the center frequency, the thermal energy, the power supply voltage and the equivalent output resistance of a delay cell, respectively. In (2), the increase of the maximum slew rate of the signal

PP

!o 2 ; VP P !

=2 SRmax !
o

(2)

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011

703

Fig. 5. Delay time from the proposed unit delay cell according to the swept control voltage V and the bias voltage V .

and Vpp due to the fast rail-to-rail signal transition of the proposed delay cell reduces phase noise. Therefore, (2) conrms that the adoption of a latch improves the phase noise performance of the delay cell even when utilized with a long delay-making mechanism. By utilizing a transmission gate as a long delay-making method, the proposed delay cell can create a wide-range variable delay. Fig. 5 shows the simulation result on a delay from one unit delay cell when sweeping the control voltage, Vcn . Since the delay changes in a linear fashion over a wide range, the proposed delay cell can be usefully adopted to a DLL for locking any widely varying input reference frequency by just changing the preselection voltage of Vbp [18]. C. Start-Controlled Circuit for Anti-Harmonic Locking Generally, DLL-based architectures covering a wide range are vulnerable to harmonic locking. In previous research, several novel techniques have been reported. First, a single replica delay cell can be utilized to limit the range of the VCDL [19], [20]. Second, a harmonic locking detector block to monitor the harmonic lock can be adopted [9]. Third, a PFD combined with a startup controlled circuit can solve the problem [21][23]. In this work, a power/area-efcient architecture based on the third concept is proposed as Fig. 6(a). Fig. 6(b) details the timing diagram explaining the sequential operation. In the beginning, the start signal is set to zero, and the capacitor in the loop lter is charged through the PMOS on the top of the capacitor instead of the disabled charge pump. Also, the start signal disables the inverter transferring the reference clock fclk to the PFD. Thus, the signal into the port C of the PFD fc is stuck to zero and the PFD detects only the signal into the V node, fv , which makes UP and DN maintain their status as low and high, respectively. After a while, Vcn goes near VDD, and the delay from the VCDL is forced to set to the minimum. When the signal start goes high, the capacitor charging is controlled by the charge pump, and the signal of fclk is transferred to the PFD, simultaneously. By the rst rising edge of fc , DN is reset to low, and the DLL starts the lock-acquisition process without concerns on the harmonic locking problem. The proposed start-controlled circuit is simple and power-efcient by requiring only three inverters and two inverter switches, additionally. Also, since this circuit is insensitive to the change timing of the start signal as long as the capacitor is precharged enough, it can successfully tackle the harmonic locking problem when adopted to DLL applications with a wide operating range. III. MEASUREMENT RESULTS The proposed programmable DLL-based clock generator has been fabricated in a 0.18-m CMOS technology. For the input reference frequency of 30 to 90 MHz, SMU 200A has been used. Fig. 7 shows the

Fig. 6. Anti-harmonic start-controlled circuit: (a) schematic and (b) timing diagram of the operation.

Fig. 7. Measured SSB phase noise when a 50 MHz input reference clock is multiplied by 24, generating a 1.2 GHz output clock.

single-side band (SSB) phase noise of the output signal with a 1.2 GHz operating frequency when an input reference frequency of 50 MHz is multiplied 24 times. The phase noise performance is 088.7 and 099.8 dBc/Hz at 10 kHz and 100 kHz offset frequencies, respectively, which can be translated into a 1.7 ps RMS jitter. Fig. 8 shows the waveforms of the multiplied output clocks for multiplication factors of 8 and 24 when a 90 MHz input reference clock was injected. For time transient measurement, the output frequency was divided using the divide-by-10 frequency divider, as shown in Fig. 1. Thus, the frequencies of 720 MHz and 2.16 GHz were measured as 72 and 216 MHz, respectively. Uneven duty-cycle of the waveforms was due to frequency dividing operation of the divide-by-10 divider, and the limited output buffer bandwidth resulted in degradation on slew rate of waveforms. The proposed clock generator can provide multiplied clock signals from the input clock with a reference frequency as low as 30 MHz. Fig. 9 shows that a 30 MHz input reference clock is multiplied four times at the output. Thus, from Fig. 8 and Fig. 9, the proposed clock generator can provide the output clock frequency from 120 MHz to 2.16 GHz. The power consumption of the proposed clock generator was 16.2 mW from a 1.8 V power supply for a 2.16 GHz output clock. Only 9 mW was consumed in the pulse generator, the pulse combiner and the VDCL combined. Fig. 10 shows the micrograph of the prototype chip. The active chip area takes only 0.051 mm2 despite its capability to

704

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011

TABLE II PERFORMANCE COMPARISON WITH PRIOR WORKS

Fig. 8. Measured waveforms of the output clock when 90 MHz of the input and divided by 10: (a) ; (b) reference frequency is multiplied by .

M = 24

M=8

Converted from phase noise Peak-to-peak Jitter: 19 ps @1 GHz

Fig. 9. Measured waveforms of the output clock with the minimum operating frequency, 120 MHz, when a 30 MHz input reference frequency is multiplied by 4 and divided by 10.

while consuming only 16.2 mW when generating a 2.16 GHz output clock. Also, since the proposed saturated-type unit delay cell is capable of providing a long time delay without sacricing phase noise performance and chip area occupancy, the DLL can lock up an input reference frequency as low as 30 MHz. The phase noise performance is 088.7 and 099.8 dBc/Hz at 10 and 100 kHz offsets from the operating frequency of 1.2 GHz, respectively, which is equivalent to a 1.7 ps RMS jitter. Also, the proposed power/area-efcient startup controlled circuit successfully tackled the harmonic locking problem. The active chip area is only 0.051 mm2 . The output clock frequency ranges from 120 MHz to 2.16 GHz.

Fig. 10. Micrograph of the proposed programmable DLL-based clock generator. TABLE I PERFORMANCE SUMMARY OF THE PROPOSED CLOCK GENERATOR

generate the required long delay for a 30 MHz input clock. Finally, the performance of the proposed clock generator is summarized in Table I. Table II summarizes the performance comparison of the proposed design with prior works. IV. CONCLUSION In this paper, a programmable DLL-based clock generator has been presented. Based on the proposed pulse generating scheme, the proposed clock generator provides a high multiplication factor of up to 24

REFERENCES [1] G. Chien and P. R. Gray, A 900-MHz local oscillator using a DLL based frequency multiplier technique for PCS applications, IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 19961999, Dec. 2000. [2] D. J. Foley and M. P. Flynn, CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 417423, Mar. 2001. [3] R. Farjad-Rad, W. Dally, Ng. Hiok-Tiaq, R. Senthinathan, M. Lee, R. Rathi, and J. Poulton, A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips, IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 18041812, Dec. 2002. [4] C. Kim, I. C. Hwang, and S. M. Kang, A low-power small-area 7.28 ps jitter 1 GHz DLL-based clock generator, IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 14141420, Nov. 2002. [5] C.-C. Chung and C.-Y. Lee, A new DLL-based approach for all-digital multiphase clock generation, IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 469475, Mar. 2004. [6] J.-H. Kim, Y. Kwak, M. Kim, S. Kim, and C. Kim, A 120-MHz 1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling, IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 20772082, Sep. 2006. [7] C.-H. Lin and C.-T. Chiu, A 2.24 GHz wide range low jitter DLL based frequency multiplier using pMOS active load for communication applications, in Proc. IEEE Int. Symp. Circuits Syst., 2007, pp. 38883891. [8] C.-C. Wang, Y.-L. Tseng, H.-C. She, and R. Hu, A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 12, pp. 13771381, Dec. 2004. [9] J. Koo, S. Ok, and C. Kim, A low-power programmable DLL-based clock generator with wide-range antiharmonic lock, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 2125, Jan. 2009. [10] C. H. Park and B. Kim, A low-noise 900 MHz VCO in 0.6 m CMOS, IEEE J. Solid-State Circuits, vol. 34, pp. 586591, May 1999. [11] L. Dai and R. Harjani, Design of low-phase-noise CMOS ring oscillators, IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 49, no. 5, pp. 328338, May 2002.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011

705

[12] I. C. Hwang, C. Kim, and S. Kang, A CMOS self-regulating VCO with low supply sensitivity, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 4248, Jan. 2004. [13] Van de Beek, E. Klumperink, C. Vaucher, and B. Nauta, Low-jitter clock multiplication: A comparison between PLLs and DLLs, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 49, no. 8, pp. 555566, Aug. 2002. [14] J. Choi, K. Lim, and J. Laskar, A ring VCO with wide and linear tuning characteristics for a cognitive radio system, in RFIC Symp. Dig. Papers, Jun. 2008, pp. 395398. [15] J. G. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 17231732, Nov. 1996. [16] B. Razavi, A study of phase noise in CMOS oscillators, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331343, Mar. 1996. [17] A. Abidi and S. Samadian, Phase noise in inverter-based and differential CMOS ring oscillators, in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2005, pp. 1821. [18] G. Konstanznig, A. Springer, and R. Weigel, A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12 m standard CMOS, in Proc. IEEE Int. Symp. Circuits Syst., May 2003, pp. 288291. [19] Y. Moon, J. Choi, K. Lee, D. Jeong, and M. Kim, An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 377384, Mar. 2000. [20] E. Song, S. Lee, J. Lee, J. Park, and S. Chae, A reset-free anti-harmonic delay-locked loop using a cycle period detector, IEEE J. SolidState Circuits, vol. 39, no. 11, pp. 20552061, Nov. 2004. [21] C. H. Kim, J. Lee, B. Kim, C. Park, S. Lee, J. Roh, H. Nam, D. Kim, D. Lee, T. Jung, H. Yoon, and S. Cho, A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system, IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 17031710, Nov. 1998. [22] H.-H. Chang, J.-W. Lin, C.-Y. Yang, and S.-I. Liu, A wide-range delay-locked loop with a xed latency of one clock cycle, IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 10211027, Aug. 2002. [23] R. C.-H. Chang, H.-M. Chen, and P.-J. Huang, A multiphase-output delay-locked loop with a novel start-controlled phase/frequency detector, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 9, pp. 24832490, Oct. 2008.

Fig. 1. Proposed architecture for the receiver frontend.

I. INTRODUCTION With the emerging applications in the wireless sensor networks and the wireless personal area networks, the development of low-power RF systems for short-range communications has attracted great attention in recent years. As for the choices of the fabrication technologies, the CMOS process provided by the commercial foundries has always been the most desirable platform to realize such systems due to its unparalleled advantages in the implementation cost and the capability for high-level system integration. However, the inherently low transconductance of the MOSFETs, especially at reduced bias current, imposes fundamental limitations on the RF performance of the integrated circuits operating at multi-gigahertz frequencies. In order to achieve the required circuit performance while maintaining low power consumption, various design strategies and circuit techniques have been proposed in the past decade. Among the proposed approaches, operating the RF circuits at a reduced supply voltage [1][4] is one of the most promising solutions. Considering the gate oxide reliability for the deep-submicrometer CMOS technologies, low-voltage circuit operation is an inevitable trend along the path of device scaling. Furthermore, the potential usage of the green energy such as integrated solar cells also motivates the development of low-voltage RF techniques. In this paper, CMOS RF frontends suitable for ultra-low-power and ultra-low-voltage operations are presented. To explore the high-frequency capability of the proposed RF circuits, experimental receiver and transmitter frontends are designed and fabricated at the 5-GHz frequency band using a standard 0.18-m CMOS process. This paper is organized as follows. Section II introduces the proposed circuit techniques for the receiver frontend while the details of the transmitter frontend design are shown in Section III. The experimental results of the fabricated circuits are presented in Section IV. Finally, concluding remarks are provided in Section V. II. PROPOSED RECEIVER FRONTEND Fig. 1 shows the block diagram of the proposed receiver frontend including a low-noise amplier (LNA) and a down-conversion mixer. In order to achieve high gain with reduced supply voltage and minimum power consumption, a current-reused technique is adopted for the complementary cascaded LNA design [5]. As for the down-conversion mixer, a folded cascode topology is employed to minimize the required voltage headroom while the multiple-gated transistors [6] are incorporated to improve the circuit linearity under such extreme bias conditions. A. Low-Noise Amplier The circuit schematic of the LNA is shown in Fig. 2, where the common-source MOSFETs M1 ; M2 , and M3 represent the rst, second, and third gain stages, respectively. By connecting the drain inductors of the individual transistors together with an ac ground provided by the bypass capacitor CP , the complementary current-reused topology is established. As for the dc bias, the gate of M1 is connected

Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations

Hsieh-Hung Hsieh, Huan-Sheng Chen, Ping-Hsi Hung, and Liang-Hung Lu
AbstractThis paper presents experimental CMOS RF frontends suitable for ultra-low-power and ultra-low-voltage operations. In order to achieve the desirable gain and linearity of the receiver chain at a reduced supply voltage, the current-reused bias technique and the multiple-gated transistors are employed. As for the transmitter frontend, a low-voltage double-balanced mixer is utilized to maximize the conversion gain. In addition, a differential-to-single-ended circuit is also included to increase the saturated output power. Using a standard 0.18- m CMOS process, the proposed circuits are realized for 5-GHz RF applications with a supply voltage of 0.6 V. The fabricated receiver frontend demonstrates a conversion gain of 14.5 dB and an IIP of 16 dBm with a power consumption of 2.1 mW, while the conversion gain and the output 1-dB compression of the transmitter frontend are 12.9 dB and 4.1 dBm, respectively, provided a dc power of 6 mW. Index TermsCMOS RFIC, current-reused bias technique, low-power, low-voltage, moderate inversion, multiple-gated transistors, receiver frontend, transmitter frontend. Manuscript received May 13, 2009; revised August 31, 2009. First published December 31, 2009; current version published March 23, 2011. The authors are with the Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan (e-mail: lhlu@cc.ee.ntu.edu.tw). Digital Object Identier 10.1109/TVLSI.2009.2037885

1063-8210/$26.00 2009 IEEE