A Direct Sequence - Spread Spectrum Modulator/Demodulator Design 1

Mohammad Sharawi
Electronics Engineering Princess Sumaya University College for Technology ( Royal Scientic Society) AmmanJordan June 2000

c 2000 by Mohammad Sharawi All rights Reserved. No part of this report is to be copied, reproduced, or distributed in anyway, without written consent of the Author.

To Mom, and Dad.

Abstract
his report demonstrates the design of a simplied Direct SequenceSpread Spectrum system. Due to the rapid movement towards the Multiple Access Mobile world, i found it interesting to clarify the design process of these complicated widely used systems. The aim of this report is to give the reader a rough idea of such systems, and how to start implementing similar designs. This report is intended for educational purposes, the design is based on simplied models, that do not exactly represent real life applications, which incorporate much complex issues. I hope that my design might be of some help to those who are seeking knowledge in such eld.

Contents
1 Direct Sequence-Spread Spectrum 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pseudo Noise (PN) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Direct Sequence Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 The 2.1 2.2 2.3 Design of the DS-SS Modulator The PN Generator Design . . . . . . . . . . . . . . . . . . . . . The Input Word Generator Design . . . . . . . . . . . . . . . . . The BPSK Modulator Design . . . . . . . . . . . . . . . . . . . 4 4 4 5 8 8 10 11

14 3 The Design of the DS-SS Demodulator 3.1 The Low Pass Filter Design . . . . . . . . . . . . . . . . . . . . . 14 3.2 The BPSK Demodulator Design . . . . . . . . . . . . . . . . . . 15 4 Conclusion and Further Enhancements 21

List of Figures
1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 3.2 3.3 3.4 3.5 PN Generator Block Diagram . . . . DS-SS Transmitter Block Diagram . m(t) and p(t) for a Maximum Length DS-SS receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PN generator, with m=3. . . . . . . . . . . . . . . . . 5 6 6 7 9 9 10 11 12 13 13 15 16 17 18

The PN Generator Circuit Diagram. . . . . . . . . . . . . . . . The PN Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . The 8-bit Word Generator Circuit diagram, with a data rate (period of one bit) of 6.666 KHz. . . . . . . . . . . . . . . . . . . . The 8-bit Word Signal. . . . . . . . . . . . . . . . . . . . . . . . The Spread Signal W ord P N (Word XNOR PN). The word signal at bottom, the Spread signal at top. . . . . . . . . . . . . The BPSK Modulator Circuit. . . . . . . . . . . . . . . . . . . . Sss (t). The DS-SS signal coming out of the Modulator. . . . . . Sallen-Key Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . The Filtered output and the output of the Demodulators Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ltered output and the output of the Comparator. . . . . . A delay of 1bit is observed, between the transmitted and received signals (before being despread). . . . . . . . . . . . . . . The inputs to the XNOR gate, after a delay of 1bit was added to the PN signal.(down is the PN signal) (up is the incoming signal from DFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The original word signal (up), and the received one (down) . . . DS-SS receiver circuit diagram. . . . . . . . . . . . . . . . . . .

3.6 3.7

18 19 20

Chapter 1

Direct Sequence-Spread Spectrum

1.1 Introduction

Spread Spectrum techniques were and are still used in military applications,
because of their high security, and their less susceptibility to interference from other parties. In this technique, the same bandwidth is shared by multiple users, without signicantly interfering with each other. The spreading waveform is controlled by a Pseudo-Noise (PN) sequence, which is a binary random sequence. This PN is then multiplied with the original baseband signal, which has a lower frequency, which yields a spread waveform that has a noise like properties. In the receiver, the opposite happens, when the passband signal is rst demodulated, and then despread using the same PN waveform. An important factor here is the synchronization between the two generated sequences. In this report, I will try to illustrate the design process of such a system, and then come up with a full circuit design.

1.2

Pseudo Noise (PN)

s we mentioned earlier, PN is the key factor in DS-SS systems. A Pseudo Noise or Pseudorandom sequence is a binary sequence with an autocorrelation that resembles, over a period, the autocorrelation of a random binary sequence [Rap96]. It is generated using a Shift Register, and a Combinational Logic circuit as its feedback. The Logic Circuit determines the PN words. In this design i used the so called MaximumLength PN sequence. It is a sequence of period 2m 1 generated by a linear feedback shift register, which has a feedback logic of only modulo2 adders (XOR Gates). Some properties of the MaximumLength sequences are: In each period of a maximumlength sequence, the number of 1s is always one more than the number of 0s. This is called the Balance property. Among the runs of 1s and 0s in each period of such sequence, onehalf the runs of each kind are of length one, onefourth are of length two, oneeighth are of length three, and so on. This is called the Run property.

CHAPTER 1. DIRECT SEQUENCE-SPREAD SPECTRUM  modulo2  adder  6 - 2 6

CLK

1 6

3 6

4 6

PN signal -

Figure 1.1: PN Generator Block Diagram the Autocorrelation function of such sequence is periodic and binary valued. This is called the Correlation property1 . A block diagram of a MaximumLength PN generator is shown in g.1.1 with a 4bit register and one modulo2 adder. This has a period of 24 1 = 15, and it was the conguration used in this design as we will show later.

1.3

Direct Sequence Spread Spectrum

n Direct Sequence-Spread Spectrum the baseband waveform is multiplied by the PN sequence. The PN is produced using a PN generator. Frequency of the PN is higher than the Data signal. This generator consists of a shift register, and a logic circuit that determines the PN signal. After spreading, the signal is modulated and transmitted. The most widely modulation scheme is BPSK (Binary Phase Shift Keying). The equation that represents this DS-SS signal is shown in eq.(1.1), and the block diagram is shown in g.(1.2). Sss = 2Es m(t)p(t) cos (2fc t + ) Ts (1.1)

where m(t) is the data sequence, p(t) is the PN spreading sequence, fc is the carrier frequency, and is the carrier phase angle at t=0. Each symbol in m(t) represents a data symbol and has a duration of Ts . Each pulse in p(t) represents a chip, and has a duration of Tc . The transitions of the data symbols and chips coincide such that the ratio Ts to Tc is an integer [Rap96]. The waveforms m(t) and p(t) are shown in g.(1.3). Here we notice the higher frequency of the spreading signal p(t). The resulting spread signal is then modulated using the BPSK scheme. The carrier frequency fc should have a frequency at least 5 times the chip frequency p(t). In the demodulator section, we simply reverse the process. We Demodulate the BPSK signal rst, Low Pass Filter the signal, and then Despread the ltered signal, to obtain the original message. The process is described by the following equations: m(t) = Sss (t) cos (2fc t + ) (1.2)
1 For

a full derivation of the Correlation property, please refer to [Hay94]

CHAPTER 1. DIRECT SEQUENCE-SPREAD SPECTRUM

Binary Sequence

mk

NON-Return - to Zero Encoder

m(t) -

 m(t)p(t) BPSK Modulator  6 6 p(t) fc

Sss (t)-

PN

Oscillator

Figure 1.2: DS-SS Transmitter Block Diagram 6 1 m(t) -1 16 p(t) -1 -

Figure 1.3: m(t) and p(t) for a Maximum Length PN generator, with m=3. and we know that , cos cos = this yields, 1 2Es m(t)p(t) [1 + cos(4fc t + )] (1.3) Ts 2 As shown in eq.(1.2)and eq.(1.3) when we multiply two cosine signals together, we will obtain two expressions, one of which has twice the frequency of the original message. And this part can be removed by a LPF. The output is mss (t) as shown in g.(1.4). My design is based on Coherent Detection BPSK, so we dont have to worry about carrier synchronization issues. As for the PN sequence in the receiver, i mentioned earlier that it should be an exact replica of the one used in the transmitter, with no delays, cause this might cause severe errors in the incoming message. Again, my design is based on the idea that PN sequences are matched, and actually i am going to use the same generator for both to ease the design. There are various techniques that deals with PN delay problems and mismatches, but i am not going to encounter any in this design. m(t) = 1 [1 + cos (2 )] 2

CHAPTER 1. DIRECT SEQUENCE-SPREAD SPECTRUM

Sss (t) BPSK Demodulator 6 fc Oscillator

m(t)

LPF

mss (t) -

  6 p(t)

Tb 0

- Decision Device

mk

Original Input Data

PN

Figure 1.4: DS-SS receiver. After the signal gets multiplied with the PN sequence, the signal despreads, and we obtain the original bit signal m(t), that was transmitted. The block diagram of the receiver is shown in g.(1.4). This simple straight forward description of DS-SS systems, will allow us to design the Modulator/Demodulator circuits with some ease. We are going to take advantage of the block diagrams for each one of them.

Chapter 2

The Design of the DS-SS Modulator

n this chapter, I am going to illustrate the circuit design and simulation of the DS-SS Modulator(Transmitter). Simulations were conducted using the EWB 5.0 software. Ideal components were used for the ease of the design, and to try to avoid other factors, that might directly aect the performance of the system. And since i am going to design a simple circuit for educational purposes, i decided to use the ideal components oered inside the software. Though, one can substitute for any other nonideal component and test the results, which i consider a great practice for someone who wants to know more about the system.

2.1

The PN Generator Design

The design of the PN generator is based on the block diagram shown in g.(1.1). Here we are going to need 4 DFlipFlops (FFs), a XNOR gate, and a Clock source. Since we are using 4 FFs, m=4 and the PN signal will repeat it self every 15 clock cycles. I have chosen the CLK frequency, fCLK =100KHz. The period 1 of the PN chip is TP N chip = 100K = 105 seconds. The total period of the PN sequence TP N = 15TP N = 15105 seconds. The period of the Binary Input signal (per bit) is going to be Tb = TP N =15104 seconds, that is a frequency fb = 6.6667KHz. The Clock signal was taken from an external source (a Function Generator). We can design a clock using an oscillator and a shaper. But we are not going to go into that. The Circuit that resembles this PN is now easily understood. It is shown in g.(2.1). The only trick in the design is the clock assignment, and its aect on the incoming Binary Sequence coming from the Word Generator, which is discussed next. As you notice from this design, the output level from the PN is not 1,-1 as was indicated in the signal diagram of p(t). Here the output is either a 5V, or 0V (Logic Levels). Dont get confused, i will explain why i used these levels later on. The output PN sequence is shown in g.(2.2).

CHAPTER 2. THE DESIGN OF THE DS-SS MODULATOR

Figure 2.1: The PN Generator Circuit Diagram.

Figure 2.2: The PN Signal.

CHAPTER 2. THE DESIGN OF THE DS-SS MODULATOR

10

Figure 2.3: The 8-bit Word Generator Circuit diagram, with a data rate (period of one bit) of 6.666 KHz.

2.2

The Input Word Generator Design

The Word Generator Circuit design is based on the one designed and illustrated in [SA99]. I am not going to discuss it in detail, but for further information regarding its design, please refer to the indicated reference. The Word Generator consists of two ICs, an Inverter, a Clock signal with frequency of 6.666KHz, and a DC supply. The 74163 IC is a TTL 4-bit binary counter, and the 74166 is a TTL 8-bit Parallel-In/Serial-Out Shift Register. The Clock signal feeds both ICs as shown in g.(2.3). The shift register loads the levels on its inputs when the Parallel Load signal is activated. Then it starts to shift the data, and sends them serially. The Parallel Load signal is taken from a 4-bit binary counter, so that after the counter nishes its count cycle, it will issue the RCO1 signal, which is used to trigger the shift counter to activate the Parallel Load function. By this we will obtain a controllable 8-bit periodic Word Generator signal. The Signal obtained is shown is g.(2.4). The 8-bit Word is then multiplied by the PN signal. This is shown in the block diagram in g.(1.2). In the block diagram we used a NRZE2 to adjust the Word level voltages. Now, assuming that we are using the NRZE, the out put of the multiplier given the Word signal shown in g.(2.4) and the PN signal shown in
Carry Out. A carry bit that is generated at the end of each cycle. to Zero Encoder, leveling circuit, that allows you to change the 5-0 Volts level to a 5-5 level.
2 Non-Return 1 Repeated

CHAPTER 2. THE DESIGN OF THE DS-SS MODULATOR

11

Figure 2.4: The 8-bit Word Signal. g.(2.2), will be: 1111+11+111+1+11+1+1+1 +1+1+1+1+1+1+1+1+1+1+1+1+1+1+1 1111+11+111+1+11+1+1+1 1111+11+111+1+11+1+1+1 111111111111111 +1+1+1+11+11+1+111+1111

We can see how does the PN signal aects the Incoming word signal that is 1 15 of its frequency. When a 5 is multiplied with a +5 the result is 25. And when a 5 is multiplied by a 5 the result is a +25. I mentioned in the previous section that the output of the PN is a 05 volts, not a 55 level. Also, the Word levels are 05 not 55. This means that i cant use the multiplication procedure here, cause a 00 = 1 . To come over this problem, and to eliminate the use of a NRZE for the word signal, i substituted the Multiplier with a XNOR gate. The function of the Gate on the previous signal (PN, and Word) will be as follows: 000010100110111 111111111111111 000010100110111 000010100110111 000000000000000 111101011001000

These two ZeroOne signals are the exact replica of the above 55 levels. But here i tried to perform a Digital Multiplication process that exactly resembles the analog one, and it did give the same results. The obtained signal is shown in g.(2.5). Dont bother from the very small glitches that occur when the word signal changes its state from 10 or 01. These glitches occur due to some very small timing mismatch, but have no signicant eect in this design. This concludes the design of the 8bit Word Generator, and the Multiplier that Spreads the incoming Digital Data coming from the Word Generator using the PN signal.

2.3

The BPSK Modulator Design

The design is directly based on the block diagram shown in g.(1.2). A more detailed analysis of this design is shown in [SA99]. The design and simulations are based on the use of ideal components. The BPSK Modulator is based on the idea of changing the phase of the carrier signal whenever the incoming Bit changes its state. For example, if the
3 Binary

This section illustrates the design of the BPSK3 modulator.

Phase shift Keying.

CHAPTER 2. THE DESIGN OF THE DS-SS MODULATOR

12

Figure 2.5: The Spread Signal W ord at bottom, the Spread signal at top.

P N (Word XNOR PN). The word signal

incoming message changes its state from 01, the carrier changes its phase by +180 , and if it changes its state from 10 the carrier changes its phase by 180 . To accomplish this task, we can now add the NRZ Encoder circuit, to map the 05 Volts to 55 Volts level. This is done easily by a leveling circuit that consists of two resistors of equal value, a noninverting amplier with a gain of 2, and a negative supply of 5 Volts. This is shown in g.(2.6). You can easily notice that i used an amplier before and another one after the leveling circuit. The rst one will change the signal levels from 05 to 010 Volts. After leaving the leveling circuit, the level of the signal is 2.52.5 Volts ( i will leave it to the reader to gure out how did i obtained such levels), which is then applied to another amplier with a gain of 2, to yield an output of 55 Volts, that will enter the Multiplier circuit. The signal then enters the Multiplier circuit. Here an ideal Multiplier with a gain of 1 is used4 . The carrier frequency used in this design is 5 times fP N chip , which is 500KHz. Though one can rise the frequency of the signal in Wireless applications to end up with a shorter antenna for the device. Anyway, this isnt our concern in this report. After the Multiplication process, we nally get the Sss (t) which is the signal obtained from the output of the Modulator circuit. The output of the DS-SS Modulator is shown in g.(2.7). Here, a couple of bits from Sss (t) are shown, just to illustrate the frequency changes of the output signal.

4 In [SA99], one can nd a detailed description of the design of a Balanced Modulator using the MC1496 IC. This is very important to those who are willing to implement such design

CHAPTER 2. THE DESIGN OF THE DS-SS MODULATOR

13

Figure 2.6: The BPSK Modulator Circuit.

Figure 2.7: Sss (t). The DS-SS signal coming out of the Modulator.

Chapter 3

The Design of the DS-SS Demodulator

e have nished the modulator part of our Direct Sequence-Spread Spectrum system. And we now come to the demodulator part that has the block diagram shown in g.(1.4). As the gure illustrates, the incoming DS-SS signal is multiplied by the carrier in the BPSK demodulator. This gives us the spread signal that was initially transmitted, which is now called m(t). This signal has a higher frequency component that results from the multiplication process as was indicated in eq.(1.3). This is removed using a LPF1 . After the signal is ltered out, it is multiplied by the PN signal to despread it, and obtain the original transmitted data. In this chapter we will illustrate the design of the LPF, and the BPFK demodulator.

3.1

The Low Pass Filter Design

Our LPF is based on the SallenKey active lter design method. We will design
a second order Butterworth LPF with a cuto frequency of fcutof f = 105KHz, which is very close to the frequency of the PN signal to be detected after the removal of the carrier. The LPF is going to look like the one shown in g.(3.1). Our duty is to nd the appropriate values for the components shown. As I mentioned earlier, we need to have fcutof f = 105KHz. The procedure to design such values is indicated in [EM88]. First, we have to nd the constant K, which can be found by: K= 104 fcutof f C1

If we choose C1 = 109 F , then K = 0.953. Now with the aid of table(3.1), and choosing the gain of our lter to be 2, we obtain the following values: R1 = K 1.126K = 1.07K R2 = K 2.25K = 2.15K R3 = K 6.752K = 6.43K R4 = K 6.752K = 6.43K
1 Low

Pass Filter

14

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR

15

Figure 3.1: Sallen-Key Filter. C1 = C1 = 109 F arads By this we come to the end of the SallenKey Second Order Active lter design. The output from the lter is shown in g.(3.2). In the gure, we can see the output of the lter having very long rise and fall times. This causes delay in the incoming signal, also the periods arent precise. We can overcome this obstacle by adding a Comparator right after the lter to do the shaping on the ltered signal. The output of the Comparator is shown in g.(3.3). The ltration process aects the period of the incoming bits. To overcome such a problem, we add a D-FF with a clock of 200KHz. This will give us bits with periods of 100KHz, as the ones that were transmitted by the modulator (after being spread). This will add additional delay to the incoming signal, we will get over this delay in the coming section.

3.2

The BPSK Demodulator Design

In this section we will demonstrate the over all design of the BPSK Demodulator
circuit. It is based on the Block diagram of the DS-SS receiver shown in g.(1.4). The signal entering the receiver is rst multiplied by the carrier frequency, to demodulate the spread signal. After the multiplication process we will obtain m(t). This signal contains higher frequency components that are ltered out

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR

16

Gain R1 R2 R3 R4 C1

1 1.422 5.399 Open 0 0.33C

2 1.126 2.250 6.752 6.752 C

4 0.824 1.537 3.148 9.444 2C

6 0.617 2.051 3.203 16.012 2C

8 0.521 2.429 3.372 23.602 2C

10 0.462 2.742 3.560 32.038 2C

Table 3.1: Second order Low Pass Batterworth Filter design values (All resistor values are in K ).

Figure 3.2: The Filtered output and the output of the Demodulators Multiplier.

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR

17

Figure 3.3: The ltered output and the output of the Comparator. by our SallenKey LPF, which will give us an unshaped analog signal, as the one shown in g.(3.3). This is shaped by using a simple Comparator circuit, to obtain a shaped signal like the one shown in g.(3.3). Another issue rises at this moment, which is the period of each bit. We have to have a matched period like the original signal sent to be able to reconstruct it again, cause any kind of mismatch in the bit period will result in an error in the detected signal, after being despread. So to ensure that we have proper bit periods, i inserted a D-FF with a clock frequency of 200KHz, to reconstruct the proper periods of the detected bits. It was inserted after the Comparator. Comparing the sent and detected spread signals, we will notice that there is a delay of 1bit between the two, as shown in g.(3.4). This 1bit delay has a 1 timing delay of Tdelay = 100KHz = 0.01mS. Which means that we have to have the same amount of delay in the receivers PN signal, in order to have an exact timing (synchronization) edges when being multiplied with the received signal. I added a 1bit delay to the PN signal, before it entered the Digital Multiplier, i.e. the XNOR gate. The inputs of the XNOR gate after adding the delay are shown in g.(3.5). The delay of 1bit of the PN signal was achieved using two DFFs, that has inverted Clocks with each other, each of 200KHz. The signal is then applied to one of the XNORs gate inputs, the other has the delayed PN sequence. The output of the XNOR gate is the despread received signal, which is an exact replica of the original transmitted one, the word signal. The two signals are shown in g.(3.6). The delay of 0.01mS is not that obvious, because the signal period is (period of 1bit word) 0.15mS, which is 15 times the delay. The full circuit diagram of the receiver is shown in g.(3.7).

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR

18

Figure 3.4: A delay of 1bit is observed, between the transmitted and received signals (before being despread).

Figure 3.5: The inputs to the XNOR gate, after a delay of 1bit was added to the PN signal.(down is the PN signal) (up is the incoming signal from DFF).

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR

19

Figure 3.6: The original word signal (up), and the received one (down) . Again, all designs and simulations were conducted using the EWB2 5.0 software, which gave me the expected results from such a system, and was more than enough to fulll the tasks of this report.

2 c EWB: Electronics Work Bench 5.0, an electronics simulation tool from Interactive Image Technologies 1996.

CHAPTER 3. THE DESIGN OF THE DS-SS DEMODULATOR

20

Figure 3.7: DS-SS receiver circuit diagram.

Chapter 4

Conclusion and Further Enhancements

his report described the design of a Direct Sequence-Spread Spectrum system, that included the design of the Modulator and Demodulator circuits. The design and simulations were intended to give anyone who is in the Communications eld a very rough insight about such systems, which are starting to invade the Telecommunication market. Or to be more precise, they are already in it for years. But we started to see their wide spread recently. So, this report describes how to design simple systems based on the idea of DS-SS technique. The design was a total success. All the circuits functioned properly, and can be implemented easily to demonstrate the exact behavior of DS-SS systems. As i mentioned before, this design can be implemented physically, using available components like the familiar 74XX logic family, and a couple of analog devices like resistors, and capacitors. We veried in this design that DS-SS can be of commercial use, and in fact it is used in our daily used Cell Phones. They are using CDMA1 technique, which is based on DS-SS. The dierence between our design and the commercial one is that many dierent factors are taken into account in the ones used, while our design is just a simplied version that is based on the implementation and design of the original basic DS-SS block diagram, for educational purposes. Finally, i hope that this report has supplied you with some new information, techniques, and ideas, and i wish that you havent found any diculties reading it2 . Again, it is intended to be as an educational supplement for any advanced communications course, were the student wants to see a practical application on what he is studying.

Division Multiple Access comments of any kind are highly appreciable and welcomed. Please do not hesitate to send me your comment what so ever. As i said, this is a report for educational purposes, so if you have any question, or comment, please send me an e-mail, and ill do my best to answer you. My e-mail is : msharawi@go.com.jo
2 Any

1 Code

21

Bibliography
[EM88] E. I. El-Masri. Analog Filter Design. Technical University of Nova Scotia, 1988.

A [GRM99] Michel Gossens, Sebastian Rahtz, and Frank Mittelbach. The L TEX Graphics Companion. AddisonWesley, fourth edition, 1999.

[Hay88] [Hay94] [KD99]

Simon Hayken. Digital Communications. John Wiley and Sons, second edition, 1988. Simon Hayken. Communication Systems. John Wiley and Sons, third edition, 1994.
A Helmut Kopka and Patric Daly. A Guide To L TEX: Dcument Preparation for Bigenners and Advanced Users. AddisonWesley, third edition, 1999.

[Rap96] [Raz98] [SA99]

Theodore Rapparport. Wireless Communications. PrenticeHall Inc., third edition, 1996. Behzad Razavi. RF Microelectronics. PrenticeHall Inc., second edition, 1998. Mohammad Sharawi and Husam Abu Ajwah. Digital communication training kit. Technical report, Princess Sumaya University College for Technology, 1999. Bernard Sklar. Digital Communications. PrenticeHall Inc., third edition, 1988. A. Sedra and K. Smith. Microelectronic Circuits. John Wiley and Sons, third edition, 1994.

[Skl88] [SS94]

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BIBLIOGRAPHY

23

Mohammad Sharawi Electronics Engineer Obtained his B.Sc in Electronics Engineering with Honors from Princess Sumaya University College for Technology in AmmanJordan in Feb 2000. His interests are in RF circuit Design, Digital Communications, Wireless Systems, and VLSI.