II.

Combinational Logic Network (CLN)

2.1 Definition and Classification Definition : CLN is that network in which the outputs at moment t depend only on inputs at moment t.

In general a CLN has n inputs and k outputs:

Fig. 2.1 - A CLN - general case The operation of a CLN is described by an input/output relation of the type y = f ( x ) where x and y are vectors. Obviously a CLN belongs to a memory less automaton. If the input vector x is known, then the output vector is immediately determined. The operation of the CLN is given by truth table of the type: x1, , xn 00 ... 0 00 ... 1 . . 11 ... 1 y1, , yk y10, , yk0 y11, , yk1
. .

Y12 n 1 , , Yk 2 n 1

The first subscript refers to the number of the output and the second subscript specifies the decimal index of the input vector. An important class of functional blocks of the DC is represented by CLNs: multiplexors, decoders, priority encoders, comparators, shifters, adders, substractors, a.s.o. Depending upon the nature of the switching logic elements (circuits) the CLNs are classified as follows: 1. Branch type networks 2. Gate type networks

The branch type are constructed from branch type elements, called also contact elements. Such as relays, cryotrons and others. All these devices have a common attribute, namely all devices switch a path, that is at a given moment there exists a close path between certain terminals or there doesnt exist such a path. We shall not focus on this type of networks. Definition : A gate type network represents any finite organisation of logic gates as they were defined at digital integrated circuits discipline.

The rule of constructing a gate CLN is: output of any logic circuit may not be connected to the input of another logic circuit to form a closed loop (no feedback). The second rule to be observed is: two outputs are never connected to the same input. Definition : The transmission function of a gate type CLN is a switching function which is true (1) only when the output terminal is active.

If in general the CLN is designed by N then the transmission function is designed by FN. This transmission function can be determined by an experiment applied on the CLN. The input terminals are known and on these terminals we apply successively all 2 n input vectors. For each input vector the output node (terminal) is measured. The corresponding input - output table is filled in. This table defines a switching function which is named the transmission function. Definition: Given a gate type CLN, N, it is called its structural expression or structural form (formula), the Boolean expression associated to a given network respecting rigorously its structure; it will be used the notation with parenthesis. This Boolean form is denoted AN. A Boolean function associated to the structural formula of a gate type CLN is the switching function corresponding to AN, designed fAN.

Definition:

Proposition: The transmission function and the function associated to the structural formula must be equal: fN=fAN.

In general, for a logic gate to be useful it must satisfy several requirements: 1. The input voltage levels and the output levels should be the same. 2. It must be possible to cascade several stages (several gates) without degrading performance. 3. Each gate must be capable of driving several other gates. 4. The circuit should require small amounts of power. 5. The logic levels should be separated by a wide enough difference so that the determination of a given logic level VH or VL is easy and, in addition, the noise will have a minimal effect.

2.2 Logic Assignment. Positive and Negative Logic It is very important to distinguish between the logic design and the circuit design. The former is concerned only with the logical aspect of the design problem, where the latter concerns the electronic circuit realisation of the logic design. The tie between the logic design and the circuit design is assigned by a mapping from logic levels designated 0 and 1 to two circuit voltage levels of a logic gate circuit. Nowadays, the usual gate elements are integrated circuits which may be SSI, LSI. There are many different types of voltage sensitive gating circuits - resistor, transistor logic (RTL), diode transistor logic (DTL), transistor transistor logic (TTL), emitter - coupled logic (ECL), metal - oxide semiconductor logic (MOS), complementary metal oxide semiconductor logic (CMOS), integrated injection logic (IIL or I2L), a.s.o. Let us consider a simple switching device with 2 inputs and one output, which is described by a functional table.

Fig. 2.2

This table contains the voltage levels measured on input and output terminals. Such a table corresponds to the electronic operation of the device. The table is filled in with effective values measured with a voltmeter: X1 0.2 V 0.2 V 3.6 V 4.25 V X2 0.25 V 4.1 V 0.1 V 4.1 V Y 3.5 V 0.25 V 0.35 V 0.1 V

But in logic design we are not concerned with the effective values of signals. We are interested with a qualitative analysis. This truth table is transformed in a symbolic truth table using symbols H and L. If a voltage is greater than 1.6 V then we insert the letter H. If a voltage is smaller than 1.6 V, we insert the letter L and so we obtain the symbolic truth table, which is familiar for the logic designer. X1 L L H H X2 L H L H Y H L L L

But in the synthesis procedure, the designer uses 1 and 0, and not H and L. Therefore, we have to move from this symbolic truth table to the logic truth table. This is accomplished if the logic assignment function is used. Definition : Definition : A logic assignment function is that mapping realising a correspondence between symbols L and H and the logic values 0 and 1. Any logic assignment function where the symbol H is associated to 1 and the symbol L is associated to 0 is called a positive logic assignment.

If, for all variables, in our example we use the positive logic, we get: X1 0 0 X2 0 1 Y 1 0

1 0 1 1 corresponding to the symbol NOR gate: Definition :

0 0
y = x1 x 2

If for all variables the symbol H is associated to 0 and the symbol L to 1 then we obtain the negative logic assignment.

In our example, for a negative logic assignment we have the following truth table, corresponding to the NAND logic function: y = x1 x 2 X1 0 0 1 1 Definition: X2 0 1 0 1 Y 0 1 1 1

If a logic assignment of a part of digital circuit is positive and that of the other part is negative, then the logic assignment of the entire circuit is called mixed logic assignment.

Reconsidering the same symbolic truth table, but using positive logic for input variables and negative logic for the output variables we obtain the following logic truth table, corresponding to the OR function. X1 0 0 1 1 X2 0 1 0 1 Y 0 1 1 1

We can continue our analysis for the other 5 combinations and we shall remark that every time, a new function is determined. Conclusion Although the physical device is the same, according to the logic assignment function we define different logic input - output relations. Observations

A convenient way to indicate the mapping of the voltage levels (H or L) to the logic levels (1 or 0) to an input - output variable of a gate is to use a voltage specification by placing a + or a - at each input or output terminals.

Fig. 2.3 - A way of indicating mapping of the voltage levels to an variable Sometimes, the negative logic is marked with 0.

Example:

Fig. 2.4 - A way of indicating the negative logic

It is worth while noting that each basic gate, each electronic circuit can perform several different logic operations upon the logic assignment being used. Definition : Two electronic digital circuits are said to be electrically equivalent if they have the same voltage truth table. This equivalence relation is denoted by .

2.3 Logic Networks and Graphs As it is known from mathematics, a graph can be represented by 2 sets: V and E, where V is the set of vertices or nodes and E is the set of edges. The elements of E are pairs of vertices (i,j) where i , j V . If the elements are ordered pairs, then the graph is directed; otherwise it is undirected. There exist a strong connection between logic networks and the graph theory. The analysis and synthesis procedures of the logic networks may be transferred to the graph theory concepts. Let A=(1,2,, n) a set of n elements. Let B={(i,j)} be ordered pairs of elements from A, where i , j A, i j . Let F=(F1F2Fr) - a set of r switching functions. We define a correspondence between sets A and F such that for each element from A, a function Fi is associated. Definition : The union of the sets A, B and F and the correspondence between the sets A and F is called a logic network.

Observation: 1. This definition is completely different of previously introduced notions. 2. Such a definition corresponds to the concept of a directed graph, where the nodes of the graph are the elements of A, the directed edges are the pairs of the set B; each node of the directed graph is assigned a function F from the set F. Example:

There are given the sets A, B and F and a mapping from A to F. The initial directed graph is: A={1,2,3,45,6} B={(1,2),(3,4),(4,5),(2,5),(3,5)} F={f1, f2, f3}
f 1 1,4,5,6 f2 2 f3 3

Fig. 2.5 - The initial graph Let us now consider another set X=(x1,,x5) named the set of input terminals (points). The following correspondence is defined on this set: C: X A . This correspondence attach to each element from X an element I from the set A. Similarly, let us consider Y=(y1y2yk) representing the output terminals (points) and the correspondence Y of the set Y onto the set A, L: Y A , so that to each element of Y an element I from A is attached. Hence the previous directed graph will be expanded to include the input and output: X={x1x2x3x4x5} C={[(x1x2x3),1], [x1,2], [x3,3], [x5,4], [(x1x4x5),6]} Y={y1y2} L={[y1,1], [y2,5]}

Fig. 2.6 - The initial graph expanded A node without any leaving edge is eliminated together with all edges terminating in that node. For instance node 6 is such a node. It hasnt any leaving edge. It have to be removed from the graph in association with all edges terminating in it. Definition : The graph obtained after this brushing up is called logic multipole. Any logic multipole is characterised by an input output relation which can be derived from this directed graph.

Fig. 2.7 - The final graph The operation of such a logic multipole is described by a set of k switching functions, named also the set of proper functions. Any logic multipole is specified by the number of inputs and by the number of outputs.LM(s,k) Definition : If the set B contains only pairs satisfying the condition i<j then the logic network is called without feedback.

Observation: Logic networks without feedback correspond to CLNs. Definition : Definition : A logic network is called regular only if the number of edges terminating in a vertex I called in degree is less or equal to the number of arguments for the function fi attached to that node. A logic network which is regular and without feedback is called correct logic network.

Observation: We are studying further correct logic networks. 2.4 Analysis of CLNs

As it was defined in the first part of the course, the main goal of the analysis procedure is to determine the input - output relation of the given CLN. It is assumed that the CLN is known as structure and input - output terminals. The analysis begins with removals of all auxiliary elements of the network, like filters, amplifiers, attenuators, a.s.o., retaining only the logic gates and their interconnections. After that the structure formed is derived from which the transmission function is obtained. Sometimes it is possible to construct from the beginning the truth table due to the CLN. After identifying all n inputs we apply successively all 2n input vectors and compute from level to level the logic values from the input output paths, until the output terminal is reached. This kind of analysis may be done experimentally too, as it was mentioned for the transmission function. In case of MSI implementations, such an analysis must be done carefully, only after an attentive inspection of the input - output relations of each integrated circuits module, which are extracted from the components catalog. Rule: If a CLN is consistently defined, then the solution of any analysis problem has a unique form. We strongly recommend to take advantage of the newly created simulation tools available on the market. The global analysis problem is divided into 2 domains: 1. Logic analysis or the ideal analysis. 2. Timing analysis or the real operation analysis - when time responses are taken into consideration. The analysis of CLNs so far has concentrated on static behaviour of the combinational networks. The analysis adequately describes a circuit in steady - state, but its not enough to tell us about the circuits dynamic behaviour. Its well known that the propagation of signals through the network is not instantaneous. This characteristic may be sometimes useful, for example when constructing circuits that output pulse signals. But, in general, it causes big problems if the momentary changes of signals at the outputs lead to logical errors. Such transient output changes are called GLITCHES. A logic circuit is said to have a hazard if it has the potential for this glitches. As logic designers, it is extremely important to be able to visualise the behaviour of circuit as a function of time, that is, to be able to look at the

circuit and see how signals move through it, recognising asymmetric delays along paths that can lead to transitory behaviour of the outputs. This is not a easy skill to acquire even after extensive design experience. Fortunately, simulation tools may offer great support in visualising the time based behaviour of the circuits. We know that outputs in combinational logic are functions of the inputs and some delay. Gate delay is the amount of time it takes for a change at a gate input to cause a change at its output. Most circuit families define delays in terms of minimum (best case), typical (average) and maximum (worst case) times. A corollary to Murphys law which is well known to experienced digital designers, is that: If a circuit can run at its worst case delay, it will, so that never assume that your design will be able to run with minimal delays. From catalogues we see the delays for all families of logic gates. Two conclusions are evident from this catalog data: 1. Propagation delays often depend on whether the output is going from low to high (tPLH) or from high to low (tPHL). 2. The faster a component is, the more power it consumes. The timing analysis is accomplished with timing wave forms. Such a timing wave form corresponds to the real operation of CLNs. The main goal of such analysis is to detect any potential hazards and to eliminate it.