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Application Report SLAA448B – August 2010 – Revised November 2011 MSP430F5xx and MSP430F6xx Core Libraries

Application Report

SLAA448B August 2010 Revised November 2011

MSP430F5xx and MSP430F6xx Core Libraries

Stefan Schauer, Miguel Morales, Priya Thanigai

MSP430

ABSTRACT

The Power Management Module (PMM), Unified Clock System (UCS), Port Map (PMAP), and Flash modules are very flexible peripherals that require initialization within many applications. The MSP430F5xx and MSP430F6xx Core Library provide functions that implement the most common operations using the PMM, UCS, PMAP and Flash modules, such as changing the core voltage to operate at higher frequencies, crystal/clock initialization, mapping port I/O, and write/erase flash operations. This application note documents the definition and proper use of the available library calls.

Project collateral and source code discussed in this application report can be downloaded from

Contents

1 PMM Library Files

2

2 UCS Library Files

7

3 Port Map Library Files

16

4 Flash Library Files

17

5 Tag Length Value (TLV) Libraries

19

6 Associated Software

22

7 References

23

List of Figures

1 System Frequency vs Supply Voltage

2

2 Changing V CORE and SVM L / SVS L Levels

3

3 Latched OFIFG Architecture

8

List of Tables

1 Recommended SVSH Settings

4

2 HAL_PMM Symbol Definitions

5

3 HAL_PMM Macro Definitions

5

4 Clock Sources on the MSP430

7

5 System Clocks and Functionality on the MSP430

7

6 HAL_UCS.h Macros

9

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PMM Library Files

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System Frequency - MHz

1 PMM Library Files

1.1 Importance of the Power Management Module (PMM)

The PMM manages the following internal circuitry:

An integrated low-dropout voltage regulator (LDO) that produces a secondary core voltage (V CORE ) from the primary voltage that is applied to the device (DV CC )

Supply voltage supervisors (SVS) and supply voltage monitors (SVM) for the primary voltage (DV CC ) and the secondary voltage (V CORE ). The SVS and SVM include programmable threshold levels and power-fail indicators.

Therefore, the PMM plays a crucial role in defining the maximum performance, valid voltage conditions, and current consumption for an application running on an MSP430x5xx or MSP430x6xx device.

The secondary voltage that is generated by the integrated LDO, V CORE , is programmable to one of four core voltage levels, shown as 0, 1, 2, and 3 in Figure 1. Each increase in V CORE allows the CPU to operate at a higher maximum frequency, f MAX , shown as f 0 , f 1 ,f 2 , or f 3 in Figure 1. The values of these frequencies are specified in the device-specific data sheet. This feature allows the user the flexibility to trade power consumption in active and low-power modes for different degrees of maximum performance and minimum supply voltage.

f 3

f 2

f 1

f 0

0

and minimum supply voltage. f 3 f 2 f 1 f 0 0 0 0, 1
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1

0 0, 1

2

1 1, 2

0, 1, 2

0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2
0 0, 1 2 1 1, 2 0, 1, 2

3

2, 3

1, 2, 3

0, 1, 2, 3

3 2, 3 1, 2, 3 0, 1, 2, 3

1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

Figure 1. System Frequency vs Supply Voltage

Both the primary and secondary voltages, DV CC and V CORE , are protected by built-in SVM and SVS circuitry. Each SVM and SVS circuit is programmable to four voltage levels that map to the V CORE and minimum DV CC levels that are required for robust run-time behavior. The intended interaction between monitor and supervisor is as follows: the monitor has a threshold voltage slightly higher than the supervisor and triggers an interrupt in a decreasing voltage condition, so that the application can store any critical run-time parameters. If the voltage continues to fall and reaches the supervisor threshold, the PMM resets the device. For a detailed description of the SVS and SVM behavior and the status and error flags that are referenced in this application report, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208). [1]

NOTE:

To align with the nomenclature in the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208) [1], the primary voltage domain (DV CC ) is referred to as the high-side voltage (SVS H /SVM H ) and the secondary voltage domain (V CORE ) is referred to as the low-side voltage (SVS L /SVM L ).

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Moving between the different V CORE voltages requires a specific sequence of events and can be done only one level at a time; for example, to change from level 0 to level 3, the application code must step through level 1 and level 2. Figure 2 shows the sequence of events required to modify V CORE .

Voltage

V CORE SVM L 6 1 3 4 5 2 SVS L Time Figure 2.
V
CORE
SVM L
6
1
3
4
5
2
SVS L
Time
Figure 2. Changing V CORE and SVM L / SVS L Levels

V CORE increase:

1. SVM L monitor level is incremented.

2. V CORE level is incremented.

3. The SVM L Level Reached Interrupt Flag (SVSMLVLRIFG) in the PMMIFG register is polled. When asserted, SVSMLVLRIFG indicates that the V CORE voltage has reached its next level.

4. SVS L is increased. SVS L is changed last, because if SVS L were incremented prior to V CORE , it would potentially cause a reset.

V CORE decrease:

5. Decrement SVM L and SVS L levels.

6. Decrement V CORE .

The SetVCore() function appropriately handles an increase or decrease of the core voltage.

NOTE:

The procedure recommended above provides a workaround for the erratum FLASH37. See the device-specific erratasheet to determine if a device is affected by FLASH37. The workaround is also highlighted in the source code for the PMM library (HAL_PMM.c).

1.2 Recommended SVS and SVM Settings

The SVS and SVM on both the high side and the low side are enabled in normal performance mode following a brown-out reset condition. The device is held in reset until the SVS and SVM verify that the external and core voltages meet the minimum requirements of the default core voltage, which is level zero. The SVS and SVM remain enabled unless disabled by the firmware.

The low-side SVS and SVM are useful for verifying the startup conditions and for verifying any modification to the core voltage. However, in their default mode, they prevent the CPU from executing code on wake-up from low-power modes 2, 3, and 4 for a full 150 µs, not 5 µs. This is because, in their default states, the SVS L and SVM L are powered down in the low-power mode of the PMM and need time for their comparators to wake and stabilize before they can verify the voltage condition and release the CPU for execution. Note that the high-side SVS and SVM do not influence the wake time from low-power modes.

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If the wake-up from low-power modes needs to be shortened to 5 µs, the SVS L and SVM L should be

disabled after the initialization of the core voltage at the beginning of the application. Disabling SVS L and SVM L prevents them from gating the CPU on wake-up from LPM2, LPM3, and LPM4. The application is still protected on the high side with SVS H and SVM H . The SetVCore() function automatically enables and disables the SVS and SVM as necessary if a non-zero core voltage level is required. If the application does not require a change in the core voltage (that is, when the target MCLK is less than 8 MHz), the DISABLE_SVSL_SVML() and ENABLE_SVSH_RESET() macros can be used to disable the low-side SVS and SVM circuitry and enable only the high-side SVS POR reset, respectively.

1.3 Setting SVS/SVM Threshold Levels

The voltage thresholds for the SVS and SVM modules are programmable. On the high side, there are two bit fields that control these threshold levels the SVSHRVL and SVSMHRRL. The SVSHRVL field defines the voltage threshold at which the SVS H triggers a reset (also known as the SVS H ON voltage level). The SVSMHRRL field defines the voltage threshold at which the SVS H releases the device from a reset (also known as SVS H OFF voltage level). The MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208) [1] recommends the settings shown in Table 1 when setting these bits. The SetVCore() function defined in the file HAL_PMM.c follows these recommendations and ensures that the SVS levels match the core voltage levels that are used.

Table 1. Recommended SVSH Settings

Maximum f sys (MHz)

DV

CC

     

(V)

SVSHRVL[1:0]

SVSMHRRL[2:0]

PMMCOREV[1:0]

8

>1.8

00

000

00

12

>2.0

01

001

01

20

>2.2

10

101

10

25

>2.4

11

011

11

It is possible to set SVSMHRRL = 4, 5, 6, and 7 when the device is operating with SVSHRVL = 3 and PMMVCOREV = 3.

1.4 Advanced SVS Controls and Trade-Offs

In addition to the default SVS settings that are provided with the SetVCore() function, the SVS/SVM

modules can be optimized for wake-up speed, response time (propagation delay), and current consumption, as needed. The controls for this are provided in the macro definitions in Table 2.

The following controls can be optimized for the SVS/SVM modules:

Protection in low power modes - LPM2, LPM3, and LPM4

Wake-up time from LPM2, LPM3, and LPM4

Response time to react to an SVS event

Selecting the LPM option, wake-up time, and response time that is best suited for the application is left to the user.

A few typical examples illustrate the trade-offs:

Case A: The most robust protection that stays on in LPMs and has the fastest response and wake-up time consumes the most power.

Case B: With SVS high side active only in AM, no protection in LPMs, slow wake-up, and slow response time has SVS protection with the least current consumption.

Case C: An optimized case may be the one described in Section 1.2: turn off the low-side monitor and supervisor, thereby saving power while keeping response time fast on the high side to help with timing critical applications.

The user can call the SetVCore() function, which configures SVS/SVM high side and low side with the recommended or default configurations, or can call the macros provided to control the parameters as the application demands.

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Any writes to the SVSMLCTL and SVSMHCTL registers require a delay time for these registers to settle before the new settings take effect. This delay time is dependent on whether the SVS and SVM modules are configured for normal or full performance. See device-specific data sheet for exact delay times.

1.5 Using HAL_PMM.h and HAL_PMM.c

Table 2 shows the symbol definitions used in HAL_PMM.

Table 2. HAL_PMM Symbol Definitions

Symbol Definitions

Description

_HAL_PMM_DISABLE_SVML_

Disables the low-side SVM when SetVCore is called

_HAL_PMM_DISABLE_SVSL_

Disables the low-side SVS when SetVCore is called

_HAL_PMM_DISABLE_FULL_PERFORMANCE_

Disables the low-side full-performance mode when SetVCore is called

Table 3. HAL_PMM Macro Definitions

Macro Name

Description (1)

ENABLE_SVSL() / DISABLE_SVSL()

Enables or disables the low-side SVS circuitry

ENABLE_SVML() / DISABLE_SVML()

Enables or disables the low-side SVM circuitry

ENABLE_SVSH() / DISABLE_SVSH()

Enables or disables the high-side SVS circuitry

ENABLE_SVMH() / DISABLE_SVMH()

Enables or disables the high-side SVM circuitry

ENABLE_SVSL_SVML() / DISABLE_SVSL_SVML()

Enables or disables the low-side SVS and SVM circuitry

ENABLE_SVSH_SVMH() / DISABLE_SVSH_SVMH()

Enables or disables the high-side SVS and SVM circuitry

ENABLE_SVSL_RESET() / DISABLE_SVSL_RESET()

Enables or disables the POR signal generation when a low-voltage event is registered by the low-side SVS

ENABLE_SVML_INTERRUPT() / DISABLE_SVML_INTERRUPT()

Enables or disables the interrupt generation when a low-voltage event is registered by the low-side SVM

ENABLE_SVSH_RESET() / DISABLE_SVSH_RESET()

Enables or disables the POR signal generation when a low-voltage event is registered by the high-side SVS

ENABLE_SVMH_INTERRUPT() / DISABLE_SVMH_INTERRUPT()

Enables or disables the interrupt generation when a low-voltage event is registered by the high-side SVM

CLEAR_PMM_IFGS()

Clear all interrupt flags for the PMM

SVSL_ENABLED_IN_LPM_FAST_WAKE()

Enables supervisor low side in LPM with t wake-up-fast (1) from LPM2, LPM3, and

LPM4

SVSL_ENABLED_IN_LPM_SLOW_WAKE()

Enables supervisor low side in LPM with t wake-up-slow (1) from LPM2, LPM3, and LPM4

SVSL_DISABLED_IN_LPM_FAST_WAKE()

Disables supervisor low side in LPM with t wake-up-fast (1) from LPM2, LPM3, and LPM4

SVSL_DISABLED_IN_LPM_SLOW_WAKE()

Disables supervisor low side in LPM with t wake-up-slow (1) from LPM2, LPM3, and LPM4

SVSH_ENABLED_IN_LPM_NORM_PERF()

Enables supervisor high side in LPM with t pd = 20 µs (1)

SVSH_ENABLED_IN_LPM_FULL_PERF()

Enables supervisor high side in LPM with t pd = 2.5 µs (1)

SVSH_DISABLED_IN_LPM_NORM_PERF()

Disables supervisor high side in LPM with t pd = 20 µs (1)

SVSH_DISABLED_IN_LPM_FULL_PERF()

Disables supervisor high side in LPM with t pd = 2.5 µs (1)

SVSL_OPTIMIZED_IN_LPM_FAST_WAKE()

Optimized to provide t wake-up-fast (1) from LPM2, LPM3, and LPM4 with least power

SVSH_OPTIMIZED_IN_LPM_FULL_PERF()

Optimized to provide t pd = 2.5 µs (1) in LPM with least power

(1)

See device-specific data sheet for accurate values of t pd and t wake-up .

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1.5.1 uint16_t SetVCore(uint8_t level)

Description Sets the appropriate V CORE level. Calls the static SetVCoreUp() or SetVCoreDown() function the required number of times depending on the current V CORE level, because the levels must be stepped through individually.

Parameters level The target V CORE level

Returns A status indicator equal to zero (PMM_STATUS_OK) or one (PMM_STATUS_ERROR) that indicates a valid or invalid V CORE transition, respectively. An invalid V CORE transition exists if DV CC is less than the minimum required voltage for the target V CORE voltage.

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UCS Library Files

2.1

Importance of the UCS

The Unified Clock System (UCS) of the MSP430x5xx and MSP430x6xx devices is a natural evolution of the ultra-low power clock system from previous device families. The UCS is based on five available clock sources (VLO, REFO, XT1, XT2, and DCO) providing signals to three system clocks (MCLK, SMCLK, ACLK). Different low power modes are achieved by turning off the MCLK, SMCLK, ACLK, and integrated LDO. A short description of the clock sources and the systems clock are shown in Table 4 and Table 5. For a more detailed description, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208).

Table 4. Clock Sources on the MSP430

System Clock

 

Description

VLO

Internal very-low-power low-frequency oscillator; 10 kHz (±0.5%/°C, ±4%/V)

 

REFO

Reference oscillator. 32 kHz (±1%, ±3% over full temp range)

 

XT1 (LFXT1, HFXT1)

Ultralow-power oscillator, compatible with low-frequency 32768-Hz watch crystals and with standard crystals, resonators, or external clock sources in the 4-MHz to 32-MHz range, including digital inputs. Most commonly used as 32-kHz watch crystal oscillator.

XT2

Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clock sources in the 4-MHz to 32-MHz range, including digital inputs.

DCO

Internal digitally controlled oscillator (DCO) that can be stabilized by a frequency lock loop (FLL) that sets the DCO to a specified multiple of a reference frequency.

 

Table 5. System Clocks and Functionality on the MSP430

 

System Clock

Description

Low-Power Modes

MCLK

   

Master Clock

Services the CPU. Commonly sourced by DCO.

Active mode only

SMCLK Subsystem Master Clock

Services 'fast' system peripherals. Commonly sourced by DCO.

Active mode, LPM0 and LPM1

ACLK

 

Active mode, LPM0 to LPM3

Auxiliary Clock

Services 'slow' system peripherals. Commonly used for 32-kHz signal.

System clocks of the MSP430x5xx generation are automatically enabled, regardless of the LPM mode of operation, if they are required for the proper operation of the peripheral module that they source. This additional flexibility of the UCS, along with improved fail-safe logic, provides a robust clocking scheme for all applications.

2.1.1 Fail-Safe Logic

The UCS fail-safe logic plays an important part in providing a robust clocking scheme for MSP430x5xx and MSP430x6xx applications. This feature hinges on the ability to detect an oscillator fault for the XT1 in both low-frequency and high-frequency modes (XT1LFOFFG and XT1HFOFFG respectively), the high-frequency XT2 (XT2OFFG), and the DCO (DCOFFG). These flags are set and latched when the respective oscillator is enabled but not operating properly; therefore, they must be explicitly cleared in software. First call all clock initialization, then call Clear_All_Osc_Flags(), and finally enable interrupts. Figure 3 shows the oscillator fault logic.

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DCO _Fault DCO _OF S S Q Q DCOFFG R R R POR XT 1_LF_OscFault
DCO _Fault
DCO _OF
S
S
Q
Q
DCOFFG
R
R
R
POR
XT 1_LF_OscFault
S
S
XT 1_LFOF
Q
Q
XT 1LFOFFG
R
R
R
XT 1_HF _OscFault
S
S
XT 1_HFOF
Q
Q
XT 1HFOFFG
R
R
R
XT 2_OscFault
S
S
XT 2_OF
Q
Q
XT 2OFFG
OscFault_Set
OFIFG
R
R
R
S
Q
NMIRS
Q
OscFault_Clr
OFIE
S
Q
R
R
PUC
NMI _IRQA

Figure 3. Latched OFIFG Architecture

The oscillator fault flags on previous MSP430 generations are not latched and are asserted only as long as the failing condition exists. Therefore, an important difference between the families is that the fail-safe behavior in a 5xx-based MSP430 remains active until both the OFIFG and the respective fault flag are cleared in software.

This fail-safe behavior is implemented at the oscillator level, at the system clock level and, consequently, at the module level. Some notable highlights of this behavior are described below. For the full description of fail-safe behavior and conditions, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208).

Low-frequency crystal oscillator 1 (LFXT1) The low-frequency (32768 Hz) crystal oscillator is the default reference clock to the FLL. An asserted XT1LFOFFG switches the FLL reference from the failing LFXT1 to the internal 32-kHz REFO. This can influence the DCO accuracy, because the FLL crystal ppm specification is typically tighter than the REFO accuracy over temperature and voltage of ±3%.

System Clocks (ACLK, SMCLK, MCLK)

A fault on the oscillator that is sourcing a system clock switches the source from the failing oscillator to

the DCO oscillator (DCOCLKDIV). This is true for all clock sources except the LFXT1. As previously described, a fault on the LFXT1 switches the source to the REFO. Because ACLK is the active clock in LPM3, there is a notable difference in the LPM3 current consumption when the REFO is the clock source (~3 µA active) versus the LFXT1 (~300 nA active).

Modules (WDT_A)

In watchdog mode, when SMCLK or ACLK fails, the clock source defaults to the VLOCLK.

The HAL_UCS.h and HAL_UCS.c library functions show how to properly initialize the XT1 in low-frequency and high-frequency modes, the XT2, and the FLL.

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2.2 Using HAL_UCS.h and HAL_UCS.c

Table 6 describes the macros in HAL_UCS.h.

Table 6. HAL_UCS.h Macros

Macro Name

 

Macro Description (1)

 

SELECT_FLLREF(source)

Selects the source for the reference into the FLL

 

Example: SELECT_FLLREF(SELREF

XT1CLK)

SELECT_ACLK(source)

Selects the source for ACLK Example: SELECT_ACLK(SELA

XT1CLK)

SELECT_MCLK(source)

Selects the source for MCLK Example: SELECT_MCLK(SELM

XT2CLK)

SELECT_SMCLK(source)

Selects the source for SMCLK Example: SELECT_SMCLK(SELS

XT2CLK)

SELECT_MCLK_SMCLK(source)

Selects the source for MCLK and SMCLK Example: SELECT_MCLK_SMCLK(SELM

DCOCLK

| SELS

DCOCLK)

ACLK_DIV(x)

Sets ACLK frequency = ACLK/x; x = {1, 2, 4, 8, 12, 16}

 

MCLK_DIV(x)

Sets MCLK frequency = MCLK/x; x = {1, 2, 4, 8, 12, 16}

 

SMCLK_DIV(x)

Sets SMCLK frequency = SMCLK/x; x = {1, 2, 4, 8, 12, 16}

 

SELECT_FLLREFDIV(source)

Sets the FLL reference frequency = FLLREF/x; x = {1, 2, 4, 8, 12, 16}

(1)

All macros mask the required bit changes in the UCS registers so that other clock settings are not affected.

2.2.1 void LFXT_Start(uint16_t xtdrive)

Description

Initializes the XT1 crystal oscillator to operate in low-frequency mode. This mode supports 32768-Hz crystals. Loops until all oscillator fault flags are cleared, with no timeout, and sets the drive strength to a user-defined level. The maximum drive strength is used to initiate the crystal startup, but then the user level is programmed to the UCS registers.

Parameters

xtdrive

The target drive strength after the oscillator has been successfully initialized. The lowest drive strength is the recommended setting to provide low-power operation and reliable crystal operation. The highest drive strength is recommended when the application environment causes a high degree of risk to the crystal oscillation.

Returns

None

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2.2.2 uint16_t LFXT_Start_Timeout(uint16_t xtdrive, uint16_t timeout)

Description

Initializes the XT1 crystal oscillator to operate in low-frequency mode. This mode supports 32768-Hz crystals. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented and equals to zero. Sets the drive strength to a user-defined level. The maximum drive strength is used to initiate the crystal startup, and then the user level is programmed to the UCS registers.

Parameters

xtdrive

The target drive strength after the oscillator has been successfully initialized. The lowest

timeout

drive strength is the recommended setting to provide low-power operation and reliable crystal operation. The highest drive strength is recommended when the application environment causes a high degree of risk to the crystal oscillation. A count variable that is decremented every time the loop that clears the oscillator fault

Returns

flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.

A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). A UCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.

2.2.3 void XT1_Start(uint16_t xtdrive)

Description

Initializes the XT1 crystal oscillator to operate in high-frequency mode. This mode supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet for appropriate drive settings.

Parameters

xtdrive

The target drive strength for the XT1 crystal oscillator.

Returns

None

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2.2.4 uint16_t XT1_Start_Timeout(uint16_t xtdrive, uint16_t timeout)

Description

Initializes the XT1 crystal oscillator to operate in high-frequency mode. This mode supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented and equals zero. See the device-specific data sheet for appropriate drive settings.

Parameters

xtdrive

The target drive strength for the XT1 crystal oscillator.

timeout

A count variable that is decremented every time the loop that clears the oscillator fault

Returns

flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.

A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). A UCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.

2.2.5 void XT1_Bypass(void)

Description

Initializes the XT1 oscillator to accept an external logic-level input square wave between 4 MHz and 32 MHz in frequency. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet (general purpose I/O) for appropriate logic levels.

Parameters

None

Returns

None

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2.2.6 void XT2_Start(uint16_t int xtdrive)

Description

Initializes the XT2 crystal oscillator, which supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet for appropriate drive settings.

Parameters

xtdrive

The target drive strength for the XT1 crystal oscillator.

Returns

None

NOTE:

When calling XT2_Start() or XT2_Start_Timeout() on a device that does not define XT2DRIVE_x bits, pass zero as the xtdrive parameter.

2.2.7 uint16_t XT2_Start_Timeout(uint16_t xtdrive, uint16_t timeout)

Description

Initializes the XT2 crystal oscillator, which supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented and equals zero. See the device-specific data sheet for appropriate drive settings.

Parameters

xtdrive

The target drive strength for the XT2 crystal oscillator.

timeout

A count variable that is decremented every time the loop that clears the oscillator fault

Returns

flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.

A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). A UCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.

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2.2.8 void XT2_Bypass(void)

Description

Initializes the XT2 oscillator to accept an external logic-level input square wave between 4 MHz and 32 MHz in frequency. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet (general purpose I/O) for appropriate logic levels.

Parameters

None

Returns

None

2.2.9 void Init_FLL_Settle(uint16_t int fsystem, uint16_t ratio)

Description

Initializes the DCO to operate a frequency that is a multiple of the reference frequency into the FLL. Loops until all oscillator fault flags are cleared, with no timeout. If the frequency is greater than 16 MHz, the function sets the MCLK and SMCLK source to the undivided DCO frequency. Otherwise, the function sets the MCLK and SMCLK source to the DCOCLKDIV frequency. Note that the default FLL reference frequency is LFXT1. Therefore, call the LFXT_Start or LFXT_Start_Timeout function before calling Init_FLL to properly initialize and clear the oscillator fault flags of LFXT1. Otherwise, the fail-safe behavior of LFXT1 switches the FLL reference to the internal REFO, which operates at slightly higher current and is slightly less accurate than an external 32-kHz crystal. The FLL reference divider is assumed to be one. For dividers greater than one, the ratio parameter must account for the divider in the factor y (FLL reference frequency). This function executes a software delay that is proportional in length to the ratio of the target FLL frequency and the FLL reference. This allows the FLL an appropriate settling time before any other code is executed.

Parameters

f system

ratio

Returns

None

The target frequency for MCLK in kHz The ratio x/y, where x = f system and y = FLL reference frequency.

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UCS Library Files

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2.2.10 void XT2_Stop(void) Description

Stops the XT2 oscillator using the XT2OFF bit.

Parameters

None

Returns

None

2.2.11 void XT1_Stop(void) Description

Stops the XT1 oscillator using the XT1OFF bit.

Parameters

None

Returns

None

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2.2.12 uint16_t Clear_All_Osc_Flags(uint16_t timeout)

Description

Clears and checks all oscillator fault flags. It uses a timeout feature and returns the appropriate oscillator fault flag errors. This function should be called after initializing all system clocks. For example:

// Startup LFXT1 32 kHz crystal do{ status = LFXT_Start_Timeout(XT1DRIVE_0, 50000); }while(status == UCS_STATUS_ERROR);

// Startup HF XT2 crystal do{ status = XT2_Start_Timeout(XT2DRIVE_3, 50000); }while(status == UCS_STATUS_ERROR);

SELECT_ACLK(SELA

SELECT_SMCLK(SELS

XT1CLK);

XT2CLK);

// Select XT1 as ACLK source // Select XT2 as SMCLK source

// Clear all and global oscillator fault flags

Clear_All_Osc_Flags(1000);

See the example API function call in MSP430xxxx_UCS_07.c.

Parameters

timeout

A count variable that is decremented every time the loop that clears the oscillator fault flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.

Returns

Fault

Oscillator fault flags. Software must parse the return value to determine the specific fault flag.

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Port Map Library Files

Port Map Library Files www.ti.com
Port Map Library Files www.ti.com

3

Port Map Library Files

3.1

Importance of the Port Map Module

The Port Map feature of the MSP430x5xx and MSP430x6xx devices brings simplicity back to digital hardware design. Port mapping allows the user to define the port pin on which certain peripheral signals are available, as specified in the device data sheet. The relationship between the available port map signals to the port pins can be one-to-one, one-to-many, or even many-to-one, because the port mapping is reconfigurable in application. When the port pin is configured to peripheral mode, it reflects the peripheral signal that is programmed into its respective PxMAPy register. For a full description of the Port Mapping module, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208).

3.2

Using HAL_PMAP.h and HAL_PMAP.c

3.2.1 void configure_ports(const uint8_t *port_mapping, uint8_t *PxMAPy, uint8_t num_of_ports, uint8_t port_map_reconfig)

Description

The following code snippet shows proper use of the configure_ports function. This is also shown in the code example that comes with this application report.

/* port_mapping array - shows proper usage of the PM_ symbols to define P1-P3 */ const unsigned char port_mapping[] =

{

// Port P1:

PM_TA0CCR0A, PM_TA0CCR1A, PM_TA0CCR2A, PM_TA0CCR3A, PM_TA0CCR4A, PM_TA1CCR0A, PM_TA1CCR1A, PM_TA1CCR2A, // Port P2:

PM_UCA0RXD, PM_UCA0TXD, PM_NONE, PM_NONE, PM_UCB0SOMI, PM_UCA0SIMO, PM_UCB0CLK, PM_UCB0STE, // Port P3:

PM_NONE, PM_NONE, PM_NONE, PM_NONE, PM_NONE, PM_NONE, PM_NONE, PM_NONE,

};

void main(void)

{

// pass port_mapping array, start mapping at P1.0, map three ports, lock configuration configure_ports((const unsigned char *) port_mapping, (unsigned char *) &P1MAP0, 3, 0);

}

Parameters

port_mapping

Pointer to initialization array

PxMAPy

Pointer to the first PortMap register to initialize

num_of_ports

Number of ports to be initialized

port_map_reconfig

Flag to enable/disable reconfiguration

Returns

None

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Flash Library Files

4

Flash Library Files

For the full description of the Flash programming module, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208).

4.1

Using HAL_FLASH.h and HAL_FLASH.c

4.1.1 void Flash_SegmentErase(uint16_t *Flash_ptr)

Description

Erase a single segment of the flash memory.

Parameter

Flash_ptr

Pointer into the flash segment to be erased

Returns

None

4.1.2 uint8_t Flash_EraseCheck(uint16_t *Flash_ptr, uint16_t len)

Description

Erase check of the flash memory.

Parameters

Flash_ptr

Pointer to the starting location of the erase check

len

Number of bytes to be checked

Returns

A status indicator equal to 1 (FLASH_ERROR) or 0 (FLASH_OK). A FLASH_ERROR indicates a block of length len starting at address Flash_ptr.

4.1.3 void FlashWrite_8(uint8_t *Data_ptr, uint8_t *Flash_ptr, uint16_t count)

Description

Write data into the flash memory in byte format.

Parameters

Data_ptr

Pointer to the data to be written

Flash_ptr

Pointer into which to write the data

count

Number of bytes to be written

Returns

None

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Flash Library Files

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4.1.4 void FlashWrite_16(uint16_t *Data_ptr, uint16_t *Flash_ptr, uint16_t count)

Description

Write data into the flash memory in word format.

Parameters

Data_ptr

Pointer to the data to be written

Flash_ptr

Pointer into which to write the data

count

Number of bytes to be written

Returns

None

4.1.5 void FlashWrite_32(uint32_t *Data_ptr, uint32_t *Flash_ptr, uint16_t count)

Description

Write data into the flash memory in long format, pass by reference

Parameters

Data_ptr

Pointer to the data to be written

Flash_ptr

Pointer into which to write the data

count

Number of bytes to be written

Returns

None

4.1.6 void FlashMemoryFill_32(uint32_t value, uint32_t *Flash_ptr, uint16_t count)

Description

Write data into the flash memory in long format, pass by value

Parameters

Data_ptr

Pointer to the data to be written

Flash_ptr

Pointer into which to write the data

count

Number of bytes to be written

Returns

None

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Tag Length Value (TLV) Libraries

5

Tag Length Value (TLV) Libraries

The TLV structure is a table stored in flash memory that contains device-specific information. This table is read-only and is write-protected. It contains important information for using and calibrating the device. A list of the contents of the TLV is available in the device-specific data sheet (in the Device Descriptors section), and an explanation on its functionality is available in the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208).

5.1

Using HAL_TLV.h and HAL_TLV.c

5.1.1 void Get_TLV_Info(uint8_t tag, uint8_t instance, uint8_t *length, uint16_t **data_address)

Description

The TLV structure uses a tag or base address to identify segments of the table where information is stored. Some examples of TLV tags are Peripheral Descriptor, Interrupts, Info Block and Die Record. This function retrieves the value of a tag and the length of the tag.

Parameters

tag

This value represents the tag for which the information needs to be retrieved. Various

instance

tags such as ADC (TLV_ADCCAL), Peripheral Descriptor (TLV_PDTAG) are defined in the header file HAL_TLV.h. In some cases a specific tag may have more than one instance. For example there

*length

may be multiple instances of timer calibration data present under a single Timer Cal tag. This variable specifies the instance for which information is to be retrieved (0, 1, etc.). When only one instance exists; 0 is passed. This variable acts as a return through indirect reference. The function retrieves the

**data_address

value of the TLV tag length. This value is pointed to by *length and can be used by the application level once the function is called. If the specified tag is not found then the pointer is null 0. This variable acts as a return through indirect reference. Once the function is called

Returns

data_address points to the pointer that holds the values retrieved from the specified TLV tag. If the specified tag is not found then the pointer is null 0.

See description of parameters.

5.1.2 uint16_t Get_Device_Type(void)

Description

Retrieves the unique device ID from the TLV structure.

Parameters

None

Returns

The device ID is returned as type unsigned int.

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Tag Length Value (TLV) Libraries

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5.1.3 uint16_t Get_TLV_Memory(uint8_t instance)

Description

The Peripheral Descriptor tag is split into two portions a list of the available flash memory blocks followed by a list of available peripherals. This function is used to parse through the first portion and calculate the total flash memory available in a device. The typical usage is to call the Get_TLV_Memory which returns a non-zero value until the entire memory list has been parsed. When a zero is returned, it indicates that all the memory blocks have been counted and the next address holds the beginning of the device peripheral list.

Parameters

instance

In some cases a specific tag may have more than one instance. This variable specifies the instance for which information is to be retrieved (0, 1 etc). When only one instance exists; 0 is passed.

Returns

The returned value is zero if the end of the memory list is reached.

5.1.4 uint16_t Get_TLV_Peripheral(uint8_t tag, uint8_t instance)

Description

The Peripheral Descriptor tag is split into two portions a list of the available flash memory blocks followed by a list of available peripherals. This function is used to parse through the second portion and can be used to check if a specific peripheral is present in a device. The function calls Get_TLV_Memory() recursively until the end of the memory list and consequently the beginning of the peripheral list is reached.

Parameters

tag

This value represents the tag for a specific peripheral for which the information needs to

instance

be retrieved. In the header file HAL_TLV.h specific peripheral tags are pre-defined, for example USCIA_B and TA0 are defined as TLV_PID_USCI_AB and TLV_PID_TA2 respectively In some cases a specific tag may have more than one instance. For example a device

Returns

may have more than a single USCI module, each of which is defined by an instance number 0, 1, 2, etc. When only one instance exists; 0 is passed.

The returned value is zero if the specified tag value (peripheral) is not available in the device.

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Tag Length Value (TLV) Libraries

5.1.5 uint8_t Get_TLV_Interrupt(uint8_t tag)

Description

This function is used to retrieve information on available interrupt vectors. It allows the user to check if a specific interrupt vector is defined in a given device.

Parameters

tag

This value represents the tag for the interrupt vector. Interrupt vector tags number from 0 to N depending on the number of available interrupts. Refer to the device datasheet for a list of available interrupts.

Returns

The returned value is zero is the specified interrupt vector is not defined.

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Associated Software

Associated Software www.ti.com
Associated Software www.ti.com

6

Associated Software

See the accompanying zip file for the software that is associated with this library. The zip file can be downloaded from http://www.ti.com/lit/zip/slaa448. The file structure and a brief description of the included files are provided in the Readme.txt file present in the zip folder, and they are also described here.

The associated software is divided into two sections:

(A) F5xx_F6xx_Core_Lib: This folder contains all of the librarys source code files. These include the HAL_xxx.c and HAL_xxx.h files for each peripheral PMM, UCS, PMAP, and flash. (B) Application Examples: The application examples call functions from the Core library and show their use based on functionality. The examples are divided based on the device. See the file Index.txt for a list of code examples for each device.

6.1

Creating Projects and Workspaces

This section provides information on how to get the code examples working out-of-the-box. The instructions apply to Code Composer Studio V4.0 or later and IAR Embedded Workbench V5.10 or later.

6.1.1 Using the Library in IAR

1. Create a project in IAR and select the required device specialization under Project Options.

2. The project is created in the same directory level as the folders F5xx_F6xx_Core_Lib and Fxxxx Application Examples.

3. Right click on Project name Add Group and create a group F5xx_F6xx_Core_Lib.

4. Right click on CoreLib and add all files in folder F5xx_6xx_Core_Lib to the group.

5. Add the required example file from the folder Fxxxx Application Examples.

6. Add the include directory path so the Project can find the location of the header file. This is done by Project Options C/C++ Compiler Preprocessor Tab. Insert the line: $PROJ_DIR$\F5xx_F6xx_Core_Lib\ in the blank space provided.

Now the project is ready to compile.

6.1.2 Using the Library in CCS

1. Open CCS and select a Workspace or create a new Workspace.

2. Create a new CCS Project (click File New CCS Project). Name the project, choose the appropriate Project Type (MSP430), and choose the device variant that corresponds to the device in use.

3. Right click on Project Name New Folder. Select the Project Name as the parent folder and name the new folder CoreLib.

4. Add all the files in the folder F5xx_6xx_Core_Lib to the Project:

Right click on Project Name Add Files (select files). Move the files to the CoreLib folder: Select files and right click Move select 'CoreLib' folder.

5. Add required example file from the folder MSP430xxxx Application Examples:

Right click on Project Name Add Files.

6. Double check that the predefined symbol under Project Properties C/C++ Build Predefined "

Symbols corresponds to the device in use such as "

MSP430F5438A.

MSP430F5438A

in case of an

7. Change the Include directory path so the Project can find the location of the F5xx_F6xx_Core_Lib folder.

Click Project Properties C/C++ Build Include Options. Select the icon with the green plus sign and specify the path to the CoreLib folder.

Now the project is ready to compile.

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www.ti.com References
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References

7

References

1. MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208), Power Management Module and Supply Voltage Supervisor chapter

2. MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208), Unified Clock System (UCS) chapter

3. MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208), Port Mapping Controller chapter

4. MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208), Flash Memory Controller chapter

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