DATASHEET

CADENCE BASELINE FOUNDRY PROCESS DESIGN KITS (PDK)

You have access to the foundry technology and design tools to begin your design, but you still need help developing your design kitwhat do you do? Cadence Baseline Foundry Process Design Kits (PDKs) jumpstart your design through access to Cadence custom IC design tools and popular foundry technologies. Furthermore, Cadence PDKs are maintained for process technology revisions as well as Cadence tool revisions.

KEY BENEFITS
Support of front-to-back custom IC design flow Accelerated time-to Tape-out Volume Technology Process Design tools
Process Design Kit (PDK) Schematic driven Libraries, cells, and views Device parameters and connectivity

Reduced overhead on design kit development and support Top quality design kits Optimized for Cadence design solutions Support of correct-by-construction design flow Easy technology migration Maintained for both process revisions and tool revisions

FEATURES
Supports the following areas of the front-to-back custom IC design flow (see Figure 1): Schematic entry Circuit simulation Device generation Connectivity driven layout Device/cell placement Interconnect routing Correct-by-construction Schematic symbols

Virtuoso Schematic Composer

Compatible with foundry Spectre models Drives parameterized cells for automated device generation in Virtuoso-XL Layout Editor (see Figure 2) Call-backs for error checking and technology limits

Cell physical design Tech files, Pcells, and symbol connectivity Advanced layout editor Advanced custom router

Device/cell placement and route Virtuoso-XL Layout Editor

Cell physical verification Interactive DRC/LVS Verification rules: DRC, LVS, and LPE

Cell interactive physical verification Diva

Figure 1: Schematic-driven layout

 Support Round-the-clock support through Cadence SourceLink online customer support Process technology revisions Cadence tool technology revisions Can be used with the following Cadence products: Virtuoso Schematic Composer Spectre and SpectreRF Cadence Analog Design Environment Virtuoso Layout Editor Virtuoso XL Layout Editor
Figure 2: Virtuoso-XL Layout Editor design environment

Virtuoso Custom Placer Virtuoso Custom Router

Parameterized cells Automatic device generation Design Rule Check (DRC) correct Relative object design (ROD) based for more complex device structures Programmed in SKILL Multifingered devices DRC and LVS correct auto-abutment (see Figures 3 & 4) Supports folding and chaining Stretch handles Schematic-driven Analog or digital designs

Device list NMOS transistors PMOS transistors N+ diffused resistors P+ diffused resistors N-well resistor Low value P+ poly resistor High value P+ poly resistor MOS capacitor Metal capacitor Technology File Virtuoso-XL Layout Editor Virtuoso Custom Placer Virtuoso Custom Router Customizable display file Physical Verification Downloadable Diva DRC deck and Assura DRC/LVS decks from foundry website Diva LVS deck provided in Cadence Baseline Foundry PDK

Diva Verification Assura Physical Verification

FOR MORE INFORMATION

Email icinfo@cadence.com or log on to www.cadence.com

Figure 3: Before abutment

Figure 4: After abutment

2002 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Diva, Spectre, Virtuoso, and SourceLink, are registered trademarks, and how big can you dream? and Assura are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. Stock #3251B 02/02