Abstract A number of research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based

architectures. This whitepaper summarizes the limitations of traditional bus-based approaches, intro duces the advantages of the generic concept of NoC, and provides specific data a bout Arteris NoC, the first commercial implementation of such architectures. Using a generic design example we provide detailed comparisons of scalability, perform ance and area of traditional busses or crossbars vs. Arteris NoC. 1. Trends Busses have successfully been implemented in virtually all complex System on Chi p (SoC) Silicon designs. Busses have typically been handcrafted around either a specific set of features relevant to a narrow target market, or support for a specific processor. Several trends have forced evolutions of systems architectures, in turn driving evolutions of required busses. These trends are:

Application convergence: The mixing of various traffic types in the same SoC desig n (Video, Communication, Computing and etc.). These traffic types, although very different in nature, for example from the Quality of Service point of view, must now share resources that were assumed to be private and h ndcrafted to the particular traffic in previous designs.

Moore s law is driving the integration of many IP Blocks in a single chip. This is an enabler to application convergence, but also allows entirely new approaches (parallel processing on a c hip using many small processors) or simply allows SoCs to process more data streams (such as communic ation channels) Consequences of silicon process evolutions between generations: Gates cost relativ ely less than wires, both from an area and performance perspective, than a few years ago. Time-To-Market pressures are driving most designs to make heavy use of synthesizab le RTL rather than manual layout, in turn restricting the choice of available implementation soluti ons to fit a bus architecture into a design flow. These trends have driven of the evolution of many new bus architectures. These i nclude the introduction of split and retry techniques, removal of tri-state buffers and multi-phase-clocks, intro duction of pipelining, and various attempts to define standard communication sockets. However, history has shown that there are conflicting tradeoffs between compatib ility requirements, driven by IP blocks reuse strategies, and the introduction of the necessary bus evoluti ons driven by technology changes : In many cases, introducing new features has required many changes in t he bus implementation, but more importantly in the bus interfaces (for example, the evolution from AMBA ASB to AHB2.0, then AMBA

AHB-Lite, then AMBA AXI), with major impacts on IP reusability and new IP design . Busses do not decouple the activities generally classified as transaction, trans port and physical layer behaviors. This is the key reason they cannot adapt to changes in the system arc hitecture or take advantage of the rapid advances in silicon process technology. Consequently, changes to bus physical implementation can have serious ripple eff ects upon the implementations of higher-level bus behaviors. Replacing tri-state techniques with multiplexers has had little effect upon the transaction levels. Conversely, the introduction of flexible pipelining to ease timing closure has massive effec ts on all bus architectures up through the transaction level. Similarly, system architecture changes may require new transaction types or tran saction characteristics. Recently, such new transaction types as exclusive accesses have been introduced near simultaneously within OCP2.0 and AMBA AXI socket standards. Out-of-order response capability is another example. Unfortunately, such evolutions typically impact the intended bus architectures d own to the physical layer, if only by addition of new wires or op-codes. Thus, the bus implementation must be redesigned. As a consequence, bus architectures can not closely follow process evolution, no r system architecture evolution. The bus architects must always make compromises between the various d riving forces, and resist change as much as possible. In the data communications space, LANs & WANs have successfully dealt with simil ar problems by employing a layered architecture. By relying on the OSI model, upper and lower l ayer protocols have independently evolved in response to advancing transmission technology and trans action level services. The decoupling of communication layers using the OSI model has successfully driv en commercial network architectures, and enabled networks to follow very closely both physical layer e volutions (from the Ethernet multi-master coaxial cable to twisted pairs, ADSL, fiber optics, wirele ss..) and transaction level evolutions (TCP, UDP, streaming voice/video data). This has produced incredible flexibility at the application level (web browsing, peer-to-peer, secure web commerce, instant messaging, etc.), while maintaining upward compatibility ( old-style 10Mb/s or even 1Mb/s Ethernet devices are still commonly connected to LANs).