PDC Chapter 5 Problems

Pulse and Digital Circuits Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Chapter-5
Non-linear Waveshaping: Clamping Circuits

1. Design a diode clamper shown in Fig. 5p.1 to restore the positive peaks of the
input signal to a voltage level to 5 V. Assume the diode cut-in voltage is 0.5 V, f
= 1 kHz, R
f
= 1 k, R
r
= 200 k and RC = 20 T.

Fig. 5p.1 The given clamping circuit with reference voltage V
R

Solution:
We know,
r f
R R R = =
3 3
1 10 200 10 14.14 k =
We have, RC = 20 T
20 T
C
R
= =
3
3
20 1 10
1.414 F
14.14 10

As the positive peak is required to be clamped to + 5 V, the reference voltage source is
chosen as
v
o
= V
R
+ V
D

5= V
R
+ 0.5
V
R
= 4.5 V

2. For the excitation as in Fig.5p.2 and the clamping circuit [Fig. 2.1], calculate and plot
to scale the steady-state output. R
f
= R
s
=100O, R= 100 K, C = 0.1 F

T
1
= 100 s T
2
=
1000 s.

(a) (b)
Fig.5p.2 (a)The given input and the clamping circuit
Solution:
When the unsymmetrical square wave shown in Fig. 5p.2(b) is transmitted through the
clamping circuit, the output voltage takes the form shown in Fig. 2.1 in the steady-state.
Dorling Kindersley India Pvt. Ltd 2010

1

Fig.2.1 Steady-state output
This waveform can be plotted by evaluating V
1
,
'
, V
1
V
2
and
'
2
. V
We have from Eq. (5.6)
(i) V =
f
s f
R
R R +
V
1

R
R R
s
+

'

2
V
100 =
1
)
100
100 100
( V
+
' )
100000
100 100000
(
2
V
+

100 = 2V
1
1.001
'
2
V (1)
From Eq. (5.9),
V =
f
s f
R
R R +
'
1
V
R
R R
s
+
V
2

100 = 2 1.001V
'
1
V
2

(2)
From Eq. (5.10)
'
1
V = V
1

C R R
T
s f
e
) (
1
+

= V
1
6
6
10 1 . 0 ) 100 100 (
) 10 100 (
+

e
'
1
V = V
1
e
-5
= (6.738 10
-3
)V
1
(3)
From Eq. (5.11)
'
= V
2
V
2

C R R
T
s
e
) (
2
+
= V
2

6
6
10 1 . 0 ) 100 100000 (
) 10 1000 (
+

e
= V
2
e
0.0999
'
2
V = 0.905V
2
(4)
From Eqs. (1)(4), we get V
1
, , V
'
1
V
2
and
'
2
as: V
'
1
V = (6.738 10
-3
)V
1
(5)
'
= 0.905V
2
V
2
(6)
100 = 2V
1
1.001
'
2
(7) V
100 = 2 1.001V
'
1
V
2
(8)
Solving Eqs. (5)(8), we get:
V
1
= 4.83 V, = 0.03258 V
'
1
V

2

V
2
= 99.823 V,
'
= 90.894 V
2
V
Note: (V
1

'
2
) and (
'
V V
1
V
2
) should, in fact, be V which is 100 V here. But due to
approximation in calculations, V is not exactly 100 V.

3. Sketch the steady-state output voltage for the clamper circuit shown in Fig. 5p.3
and locate the output dc level and the zero level. The diode used has R
f
= 100 O,
R
r
= 500 k , . C is arbitrarily large and R = 20 k O 0 =
V O. The input is a +20 V

square wave with 50 per cent duty cycle.

Fig. 5p.3 The given clamping circuit for Problem 3
Solution:
Duty cycle = 0.5 =
2 1
1
T T
T
+

T
1
= T
2

We know clamping theorem,
R
R
T V
T V
f
=
2 2
1 1
,
where V
2
= V V
1

R
R
T V V
T V
f
=
2 1
1 1
) (

3
1
1
10 20
100
) 40 (
=
V
V

V
1
= 0.199V
As per given data, C is large, hence there is no tilt in forward and reverse directions.


3

4. For the circuit shown in Fig. 5p.4(a), R
s
= R
f
= 50O, R=10 kO, R
r
= , C=2.0 F
,
the
input varies as shown in Fig.5p.4(b). Plot the output waveform.
(a) (b)

Fig. 5p.4 (a) The given input, (b) and the clamping circuit

Solution:
D conducts from t = 0.1 ms to 0.2 ms as in Fig.4.1.
(i) At t = 0.1 ms
v
o
=
100
50 5
= 2.5 V
During the period 0.1 to 0.2 ms, D is ON and as the input is constant the output decays
and at t = 0.2 ms
v
o
= 2.5e
) 10 2 )( 50 50 (
10 1 . 0
6
3
+

=2.5e
0.5
=1.516 V

Fig. 4.1 Equivalent circuit when D is ON
The voltage across the capacitor = 5 2
A
v 1.516 = 1.968 V.

(ii) At t = 0.2 ms, D is OFF as in Fig. 4.2.


4

Fig. 4.2 Equivalent circuit when D is OFF

v
o
= 10 1.968 = 11.968 V.
During 0.2 to 0.3 ms, output decays and at t = 0.3 ms
v
o
= 11.968e
) 10 2 )( 10000 50 (
10 1 . 0
6
3
+

= 11.90 V
A
v = 10 + 11.90 = 1.90 V
A
v = 1.90 V
(v) v
o
at t = 0.3 ms, D is ON. The equivalent to be considered is in Fig. 4.3.

Fig. 4.3 Circuit to calculate the output

v
o
=
2
90 . 1 10
= 4.05 V
During 0.30.4 ms, the output decays and at t = 0.4 ms:
v
o
= 4.05e
0.5
= 2.45 V.
The output voltage now varies as in Fig. 4.4.

Fig. 4.4 Steady-state output waveform

5. The input as shown in Fig. 5p.5(a) is applied to the clamping circuit shown in Fig.
5p.5(b) with R
s
= R
f
= 100 , R = 10 k O O , R
r
=, C = 1.0F;
= 0. Draw the output

waveform and label all the voltages.
V

5

(a) (b)

Fig. 5p.5 (a) The given input; and (b) the given clamping circuit

Solution:

(i) At t = 0 ms, the input is 10 V, the diode conducts as shown in Fig. 5.1.
v
o
= v
s
s f
f
R R
R
+
= 10
200
100
= 5 V

Fig. 5.1 Equivalent circuit when D is ON
(ii) During the period from 0 to 0.1 ms, as the input remains constant, the output decays
exponentially with the time constant.
f
t = (R
s
+ R
f
)C = (100+100)1 = 200
6
10
s = 0.2 ms
v
o
(t = 0.1 ms) = 5
2 . 0
1 . 0
e = 3.032 V.
The voltage across the capacitor = = 10 + 2
A
v 3.032 = 3.936 V.
At t = 0.1 ms, input rises to 10 V and the diode is OFF. The equivalent circuit is as shown
in Fig. 5.2.

6

Fig. 5.2 Equivalent circuit when D is OFF

v
o
= (10 + 3.936)
1 . 0 10
10
+
= 13.798 V
As the input remains constant from 0.1 to 0.3 ms, the output decays as:
v
o
(t = 0.3 ms) = 13.798
3
3
10 1 . 10
10 2 . 0

e = 13.52 V
The voltage across the capacitor = = 10 13.52 = 3.52 V
A
v
At t = 0.3 ms, v
s
abruptly falls to 5 V
v
o
(t = 0.3 ms) = (5 + 3.52)
100 100
100
+
= 1.48
2
1
= 0.74 V
As the input remains constant from 0.3 to 0.4 ms, the output decays:
v
o
(t = 0.4 ms) = 0.74
2 . 0
1 . 0
e = 0.448 V.

The output waveform is shown in Fig. 5.3 .

Fig. 5.3 Steady-state output waveform

6. A clamping circuit and input applied to it are shown in Fig. 5p.6. Assume that C is
quite large. Find at which voltage level the positive peak is clamped in the output if

7

T
1
= 1 ms, T
2
= 1 s, R
f
= 100O and R = 100 kO.

Fig. 5p.6 The given input and clamping circuit for Problem 6

(Hint: Use clamping theorem)

Solution:
We know clamping theorem,
R
R
T V
T V
f
=
2 2
1 1

R
R
T V V
T V
f
=
2 1
1 1
) (

3 6
1
3
1
10 100
100
10 1 ) 10 (
10 1
V
V

6
1 1
10 ) 10 (

= V V
V 10
10 ) 10 1 (
5
1
5 6
1

~
= +
V
V

10 10 10
5
1 2
= = =

V V V V

7. Calculate and draw the steady-state output waveform of the circuit in Fig. 5p.7.
Assume R
f
= 50 , R O
r
= 500 k and T O
1
= T
2
= 1 ms.

Fig. 5p.7 The given clamping circuit with large V
YY

8

Solution:

At t = 0+, D ON and v
o
= 0 V.
Then capacitor charges during ON period is V
A
= v
s
v
o
= 40 0 = 40 V
At t = T
1
+, D OFF and v
o
= v
s
V
A
= 0 40 = 40 V.
At t = T
2
,
3
1
3 6
1 10 ( )
500 10 0.1 10
o
40 40 40 0.98 39.2
T T
v e e
t

= = = = V
V
A
= v
s
v
o
= 0 +39.2 = 39.2 V
At t = T
2
+, v
o
= v
s
V
A
= 40 39.2 = 0.8 V
At t = T
3
,
3
6
1 10
50 0.1 10
o
0.8 0.8 0 0 v e

= = = V
V
A
= v
s
v
o
= 40 0 = 40 V

Fig. 7.1 The output waveform

8. Design a biased clamping circuit to derive the output voltage as shown in Fig. 5p.8(b),
given the input as shown in Fig.5p.8(a): f = 1000 Hz, R
f
= 100 O , R
r
= 1 M and O
10 =
T
RC
. D is ideal.

(a) (b)
Fig.5p.8 (a) The given input to the clamping circuit; and (b) the required output

Solution:

We know
r f
R R R = =
3
100 1 10 10 k =
We have, RC = 10T

9


10
R
T
C
10
= =
3
3
10 1 10
1 F
10 10

As the negative peak is required to be clamped to 5 V, the reference voltage source is
chosen as
v
o
= V
R
+ V
D

5= V
R
+ 0
V
R
= 5V

Fig. 8.1The biased clamping circuit

PDC Chapter 5 Problems

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PDC Chapter 5 Problems

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Pulse and Digital Circuits Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

V O. The input is a +20 V

= 0. Draw the output

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