MOS integrated circuits

The other major class of integrated circuits is called MOS because its principal device is a metal oxide semiconductor field-effect transistor (MOSFET). It is more suitable for very large-scale integration (VLSI) than bipolar circuits because MOS transistors are self-isolating and can have an average size of less than 107 in.2 (105 mm2). This has made it practical to use millions of transistors per circuit. Because of this high-density capability, MOS transistors are used for highdensity random-access memories (RAMs), read-only memories (ROMs), and microprocessors. See also Computer storage technology; Microprocessor; Semiconductor memories. Several major types of MOS device fabrication technologies have been developed since the mid1960s. They are (1) metal-gate p-channel MOS (PMOS), which uses aluminum for electrodes and interconnections; (2) silicon-gate p-channel MOS, employing polycrystalline silicon for gate electrodes and the first interconnection layer; (3) n-channel MOS (NMOS), which is usually silicon gate; and (4) complementary MOS (CMOS), which employs both p-channel and n-channel devices. Both conceptually and structurally the MOS transistor is a much simpler device than the bipolar transistor. In fact, its principle of operation has been known since the late 1930s, and the research effort that led to the discovery of the bipolar transistor was originally aimed at developing the MOS transistor. What kept this simple device from commercial utilization until 1964 is the fact that it depends on the properties of the semiconductor surface for its operation, while the bipolar transistor depends principally on the bulk properties of the semiconductor crystal. Hence MOS transistors became practical only when understanding and control of the properties of the oxidized silicon surface had been perfected to a very great degree. A simple CMOS inverter circuit is shown in Fig. 2. The gates of the n-channel and p-channel transistors are connected together as are the drains. The common gate connection is the input node while the common drain connection is the output node. A capacitor is added to the output node to model the loading expected from the subsequent stages on typical circuits.

Simple CMOS inverter circuit. (a) Schematic cross section. (b) Current flow when input is low at 0 V. (c) Current flow when input is high at 5 V. When the input node is in the low state, at 0 V, the n-channel gate to source voltage is 0 V while the p-channel gate to source voltage is 5 V. The n-channel transistor requires a positive gate-tosource voltage, which is greater than the transistor threshold voltage (typically 0.51 V), before it will start conducting current between the drain and source. Thus, with a 0-V gate-to-source voltage it will be off and no current will flow through the drain and source regions. The p-channel transistor, however, requires a negative voltage between the gate and source which is less than its threshold voltage (typically 0.5 to 1.5 V). The 5-V gate-to-source potential is clearly less than the threshold voltage, and the p-channel will be turned on, conducting current from the source to the drain, and thereby charging up the loading capacitor. Once the capacitor is charged to the high state at 5 V, the transistor will no longer conduct because there will no longer be a potential difference between the source and drain regions. When the input is now put to the high state at 5 V, just the opposite occurs. The n-channel transistor will be turned on while the p-channel will be off. This will allow the load capacitor to discharge through the n-channel transistor resulting in the output voltage dropping from a high

state at 5 V to a low state at 0 V. Again, once there is no potential difference between the drain and source (capacitor discharged to 0 V), the current flow will stop, and the circuit will be stable. This simple circuit illustrates a very important feature of CMOS circuits. Once the loading capacitor has been either charged to 5 V or discharged back to 0 V, there is no current flow, and the standby power is very low. This is the reason for the high popularity of CMOS for batterybased systems. None of the other MOS technologies offers this feature without complex circuit techniques, and even then will typically not match the low standby power of CMOS. The bipolar circuits discussed above require even more power than these other MOS technologies. The price for CMOS's lower power are the additional fabrication steps required (1020% more) when compared to NMOS. Read more: http://www.answers.com/topic/integrated-circuit#ixzz1flp8KFF8

MOSFET's Explained: The metal-oxide-FET or MOSFET was developed as an improvement on the JFET, and it has become the most important form of FET. Figure 7-a illustrates an N-channel depletion-mode MOSFET with a negative gate bias. The gate of this MOSFET is fully insulated from the adjacent channel. This is the most important distinction between an N-type depletion-mode MOSFET and an N-type JFET, which is manufactured with a doped gate region directly under and in contact with the gate. The surface of the silicon P-type wafer is first coated with a layer of silicon dioxide (SiO2), and the source and drain windows are masked and etched to expose the P-type substrate. N-dopants are

heavily diffused or implanted into those regions. Another window is masked and etched over the channel, and it is given a lighter concentration of N dopant. In subsequent steps, the channel is recoated with an insulating oxide, and the metal source, drain, and gate terminals are deposited. When the drain is positive with respect to the source, a drain current will flow, even with zero gate voltage. However, if the gate is made negative with respect to the substrate, positive charge carriers (holes) induced in the N-channel will combine with the electrons and cause channel resistance to increase. With increasing negative bias, the pinchoff voltage will be reached, and drain current will cease. However, if the gate is made positive with respect to the substrate, additional electrons are induced, and the channel current then increases. The schematic symbol for the N-type depletion-mode MOSFET is shown in Figure 7-b. The path or channel between the source and drain is shown as a solid bar. THe symbol for the P-channel depletion-mode MOSFET is identical to the N-type, except that the arrow points outwards. Figure 8 is a drain-to-source characteristic curve for an N-channel depletion-mode MOSFET. It can be seen that the current drain, ID, is inversely proportional to the magnitude of the negative gate voltages, VGS. Compare Fig. 8 with Fig. 3 for the N-channel JFET to see their similarities. Planar enhancement-mode MOSFET's are made by the same methods as planar depletion-mode MOSFET's. However, the Nchannel enhancement-mode MOSFET shown in Fig. 9 does not have the N-doped drain-to-source channel through the P-type substrate of the N-channel depletion-mode MOSFET. Therefore, there is no conduction between drain and source at zero gate bias. To turn an enhancement-mode MOSFET on, positive gate bias is needed. As the gate voltage is increased, more electrons are induced into the channel. They cannot flow across the oxide layer of the gate, so they accumulate at the substrate surface below the gate oxide. When a sufficient number of electrons has accumulated, the P-type substrate material is converted into an N-channel, and drain-to-source conduction occurs. The magnitude of the drain current depends on the channel resistance, but it is controlled by the gate voltage. The schematic symbol for an N-type enhancement-mode MOSFET is shown in Fig. 9-b. In this symbol, the gate does not make direct contact with the channel. The arrowhead points from the Ptype substrate toward the (induced) N-type channel, shown as a line broken into three sections to indicate an intermittent current channel. Current flow in the channels of both kinds of enhancement-mode MOSFET's is proportional to the voltage on their gates, VGS. this can be seen for an N-type enhancement-mode MOSFET by examining the family of gate voltage VGS curves in Fig. 10. Current drain, ID, is directly

proportional to the positive value of gate voltage. A P-channel enhancement-mode MOSFET is made the same way as the N-channel device except that P-channel drain and source regions are diffused into an N-type substrate. The symbol for a Ptype enhancement-mode MOSFET is the same as the one shown in Fig. 9-b except that the direction of the arrow is reversed. In the case of a P-type enhancement-mode MOSFET, the drain current is directly proportional to the negative values of its grid voltage. The high gate impedance of all MOSFET's, makes them susceptible to damage from even lowenergy electrostatic discharge (ESD). For this reason many discrete MOSFET's and IC's based on MOSFET's are protected with on-chip Zener diode circuits. CMOS Logic Devices: An enhancement-mode MOSFET can act as a switch when it is turned on or off by a voltage applied to the gate electrode: N-channel MOSFET's are switched with positive gate voltage, and Pchannel MOSFET's are switched with negative voltage. These are known as complementary responses, and they form the basis for complementary MOS or CMOS digital logic families. Figure 11-a is a section view of a complementary pair of MOSFET's on a common substrate, the basic topography for all CMOS gates. The common substrate that is used for this pair is an N-doped silicon wafer. To make an N-channel MOSFET on an N-doped substrate, it is necessary to diffuse or implant a P-doped well in the substrate. The smaller N-type wells can then be formed in this P-doped region. Because the substrate is N-doped, fewer steps are required to form the P-channel FET. The P- and Ndoped guard bands isolate and insulate the individual transistors in this integrated circuit to prevent mutual interference. Although not illustrated here, these guard bands are actually N- or P-doped rings formed around the complete FET below the oxide layer in this CMOS technology. The two transistors in the section view, Fig. 11-a, can be connected to form a CMOS logic inverter, the simplest of digital logic circuits. This is accomplished by connecting the gates together to form an input (VIN) terminal, and taking the output (VOUT) from the common drain. The source on the left side of the diagram, VSS, is grounded, while the source on the right side is connected to the positive supply, VDD. Those connections are schematically shown in Figure 11-b. How does the inverter work? Consider the P-channel device to be the driver and the N-channel device to be the load. Recall that an Nchannel enhancement MOSFET conducts with a negative gate voltage. When the voltage input to the inverter is low (logic 0), the gate voltage of the P-channel device is negative, equal to the supply voltage VDD. As a result, the P-channel MOSFET is switched on, and

there is a low impedance path from the output to VDD. Because the N-channel is off (gate voltage is zero), there is a very high impedance path from the output to ground. Therefore, the output voltage rises to VDD. When the input voltage is high (logic 1), the situation is reversed. The P-channel FET is cut off, and the N-channel FET is on, so the output voltage falls to zero. Therefore, the circuit is a logic inverter: a low input results in a high output, and vice versa. In either logic state one FET is ON while the other is OFF. Because one FET is always turned OFF, the quiescent current of the the CMOS unit is extremely low. These properties of N- and Ptype enhancement-mode FET's combined to form CMOS gates provide many advantages:

Extremely low power consumption. Wide power supply voltage range. High DC noise margin. High input impedance. Wide operating temperature range.

The diagram in Fig. 11-a illustrates standard CMOS metal-gate technology (74C/4000), but there are many other CMOS technologies including the high-speed silicon-gate HC, HCT, and FACT families. Another digital logic technology called BiCMOS takes advantage of the lower power consumption and higher integration density of CMOS, and the higher speed adn superior drive capability of bipolar transistors. Power MOSFET's: Power MOSFET's exhibit the properties of small-signal MOSFET's such as high-input impedance and voltage control, and they have drains, sources and gater, but they are designed to handle higher currents. As majority-carrier devices that store no charges, they can switch faster than bipolar power transistors. Figure 12 is a section view of an NChannel, enhancement-mode power MOSFET. Unlike its small-signal counterpart, the latest power MOSFET's are fabricated with vertical rather than planar structures. They are made with the double diffused (DMOS) process, and they have conductive silicon (polysilicon) gates. The gate of this device is isolated from the source by a layer of insulating silicon oxide. When a voltage is applied between the gate and source terminals, an electric field is set up within the MOSFET. This field alters the resistance between the drain and source terminals, and it permits conventional current to flow in the drain in response to the applied drain circuit voltage. There are also Pchannel, enhancement-mode power MOSFET's in which conventional current flows in the opposite direction of the N-channel device. Fig. 13 is the schematic symbol for a DMOS enhancement-mode, N-channel power MOSFET. Figure 14 is an cutaway view of a typical DMOS power MOSFET. It is made up of many cells or transistor element connected in parallel. Each source cell consists of a closed rectangular or hexagonal channel which separates a source region from the substrate drain body. The cells are formed in an integrated circuit process, and there might be more than a half million cells per square inch of substrate. All of the source cells are connected in paralleled by a continuous deposition of aluminum metallization, which forms the grid-like common source terminal. The DMOS power MOSFET contains an inherent PN junction diode, and its equivalent circuit can be considered as a

diode in parallel with the source-to-drain channel, as shown in the schematic symbol of Fig. 13. International Rectifier (IR) makes DMOS power MOSFET's that have hexagonally shaped cells, so it calls its products HEXFET's. Motorola Semiconductor also offers DMOS products MOSFET's, but its devices have rectangular rather than hexagonal cells. Motorola named its power MOSFET's TMOS to call attention to the T-shaped current flow that occurs in the cells between the common drain and the channels to the multiple sources. Power MOSFET's are widely specified for high-frequency switching power supplies (generally those that switch at frequencies above 100kHz), AC and DC motor speed controls, high-frequency generators for induction heating, ultrasonic generators, audio amplifiers, and amplitude modulation transmitters. The advantages to using power MOSFET's over power bipolar transistors include:

Faster switching speeds and lower switching losses. Absence of the bipolar's second breakdown. Wider safe operating area. Higher input impedance. High, if not higher, gain. Faster rise and fall times. Simple drive circuitry.

The principal disadvantages of power MOSFET's are their higher cost and a higher static drain-tosource on-state resistance, which can cause unacceptable power losses in certain switching applications.. However, the manufacturers have made progress in reducing those resistance values. DMOS geometry had largely replaced the V-groove or VMOS process that was widely used to fabricate power MOSFET's back in the 1970's. Radio-Frequency power MOSFET's are now available that will operate over the 2 to 200 MHz frequency range. The high power and high gain of these devices makes them suitable as power amplifiers in solid-state transmitters for FM and TV br5oadcasting.

http://tams-www.informatik.uni-hamburg.de/applets/cmos/

Informatics / TAMS / Applets / CMOS Java CMOS This page demonstrates how CMOS transistors and basic gates work. It is intended Gate for our computer science undergraduate students. The applets were written as a test Demonstration and working demonstration for Java/Hotjava. All comments, hints and bug reports are welcome: Please contact Norman Hendrich. Further Java demonstrations on our server (ever wanted to learn ballroom dancing on the Net?) can be found here. Java 1.0 version. The applets use different colors to indicate voltage levels: They will only display correctly on a color display. You need a Java 1.0 (or higher)

compatible browser like Netscape, MSIE, or Suns appletviewer to run the applets. Basic CMOS In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type Technology and P-type transistors are used to realize logic functions. Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). The main advantage of CMOS over NMOS and bipolar technology is the much smaller power dissipation. Unlike NMOS or bipolar circuits, a CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows to integrate many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance. The following applets demonstrate the N-type and P-type transistors used in CMOS technology, the basic CMOS inverter, NAND and NOR gates, and an AOI32 complex gate. Finally, it demonstrates the CMOS transmission-gate and a transmisson-gate D-latch. The first applet illustrates the function of both N-type and P-type MOS transistors. Click on the source and gate contacts of the transistors to toggle the corresponding voltage levels and watch the resulting output value on the drain contacts. The applet uses colors to display the different voltages.

A logical '1' corresponding to electrical level VCC (typical values for current technolgies are +5V or +3.3V) is shown in red, a logical '0' (corresponding to 0V or GND) in blue. A floating wire (not connected to either VCC or GND) is shown in orange.

Note that the N-type transistor is conducting when its input is '1', while the P-type transistor is conducting when its input is '0'. The applet displays the channel of a conducting transistor as a rectangle filled with the color of its source voltage. The channel of a nonconducting transistor is shown as rectangle outline in black. The CMOS The most important CMOS gate is the CMOS inverter. It consists of only two Inverter transistors, a pair of one N-type and one P-type transistor. The applet demonstrates how the inverter works. Voltage levels are shown in colors as above: a logical '1' corresponding to electrical level VCC is shown in red, a logical '0' (corresponding to 0V or GND) in blue. Again, a floating wire (not connected to either VCC or GND) is shown in orange. Because of parasitic effects, the voltage level on such wire may reach some undefined voltage between VCC and GND after some time. A floating wire will cause problems, when its voltage is around VCC/2, because a gate voltage around VCC/2 on either N-type and P-type transistors implies that the transistor is conducting. The applet illustrates why this is a serious problem: When both transistors are conducting, there is a direct path from VCC to GND, and this implies a short-circuit condition (shown in light green), which dissipates much energy and may destroy the device. Click anywhere in the applet to toggle the input voltage for the inverter from GND to

VCC to Z (unknown) to GND. If the input voltage is '1' (VCC) the P-type transistor on top is nonconducting, but the N-type transistor is conducting and provides a path from GND to the output Y. The output level therefore is '0'. On the other hand, if the input level is '0', the P-type transistor is conducting and provides a path from VCC to the output Y, so that the output level is '1', while the N-type transistor is blocked. If the input is floating, both transistors may be conducting and a short-circuit condition is possible: Power The previous discussion of the CMOS inverter shows why CMOS logic has (almost) Consumption of no static power dissipation: If the gate voltage is either '1' or '0' there is no conducting the CMOS path from VCC to GND, and there is no static current through the inverter. In normal Inverter operation, the short-circuit condition shown in the applet above arises only during the very short interval, when the gate voltage is switched. Typical switching times for the gate are around 1 ns, and the static current dissipation occurs only during a fraction of this time (while the input voltage is near VCC/2). All other basic CMOS gates have almost no static power dissipation as well. But there is a dynamic current dissipation in CMOS gates. The applet below illustrates this effect for the CMOS inverter. The gate of a MOS transistor forms a small capacitor. Typical values for the gate capacity are of order Cg = 10 fF. If the input of the inverter is connected to VCC at time t1, this capacitor is charged (Charge Q = Cg * VCC). If the input is connected to GND at time t2 it is discharged. The net effect of this is a very small current of I = dQ/dt = (Cg * VCC)/(t2-t1). However, due to several reasons the total current drawn by a big CMOS chip, for example a microprocessor, can be quite large:

A modern microprocessor may contain about five million transistors, that is, about one million gates. Typically, about one percent of all gates switch during one cycle. Operating frequencies are up to 200 MHz (cycle time 5 ns) at an operating voltage of VCC = 3.3V. On VLSI chips, the wires connecting the gates have a capacity Cw that is much bigger than the transistor gate capacities Cg. When switching an input, not only the transistor gate capacities but also the whole wire needs to be charged or discharged: Ctotal=Cg+Cw. Typical wire loads are about 1 pF

The total current resulting from the short-circuit currents during switching is difficult to estimate. But the current resulting from switching the input capacitance alone is quite large in the example: I ~ #gates * (Ctotal*VCC) / dt = (1% * 1.000.000) * (1pF * 3.3V) / 5ns = 6.6 A On the other hand, the quiescent current in typical static CMOS ICs is very small. For example, an 2K*8 bit CMOS SRAM dissipates only 1 uA when idle.

The next applet illustrates the current dissipation in the CMOS inverter. If the input voltage stays at '1' or '0', either the N-type or the P-type transistor in nonconducting, and there is no current through the inverter.

If the input is switched, the gates of the transistors are charged/discharged. The applet draws a moving electron to illustrate this. If the input is switched, the input voltage passes the region near VCC/2, where both transistors are conducting. That is, during a very short time after each switching, there is a direct (short-circuit) current through the inverter. This current again is shown by a moving electron.

The power consumption of static CMOS logic is therefore directly proportional to switching frequency. The following plot shows simulated voltages and currents for a typical inverter. From top to bottom: input voltage, inverter output voltage, inverter short circuit current, inverter input current.

Basic NAND The following three applets demonstrate the basic 2-input NAND and NOR gates, and NOR Gates and a 3-input NAND gate. As in all static CMOS gates, each input is connected to the gates of a pair of N-type and P-type transistor. Usage of the applets: The applets are similar to the Inverter applet. Wires with logical '1' (VCC) are again shown in red, wires with logical '0' (GND) in blue. Unknown floating values are shown in orange color, a short-circuit is shown in green.

Click the mouse near the inputs to toggle the input voltages and watch the resulting output voltage. The corresponding combination of input and output values is hightlighted in the function-table on the right. Click on a function-table entry to select the corresponding input voltages.

Clicking on the top line of the function-table will step through the functiontable.

To simplify the applet, only '1' and '0' levels are allowed as input values. Obviously, a short-circuit may occur in these gates as well, if the input voltages are floating near VCC/2 (because both N-type and P-type will be conducting, thereby providing direct paths from VCC to GND). The NOR2 Gate The 2-input NOR gate is the simplest CMOS gate to illustrate the name complementary MOS: The P-type transistors are connected in series between VCC and the output Y, while the N-type transistors are connected in parallel between GND and the output Y. That is, the N-type and the P-type parts of the CMOS gate are complementary (in respect to topology, and therefore function). Only if both inputs A and B are '0' (corresponding to GND), there is a conducting path from VCC to the output (output level '1'). A input combination with A or B '1' blocks the path from VCC to the output, but opens a path from GND to the output (so that the output level is '0'). Watch the voltage level between the two P-type transistors. If both are nonconducting, the voltage level is unknown (floating). However, as that wire is not connected to any MOS-transistor gate, there is no problem: The NAND2 In the two-input NAND gate the P-type transistors are connected in parallel between Gate VCC and the output Y, while the N-type transistors are connected in series from GND to the output Y. The NAND3 The generalization of the 2-input NOR and NAND gates is obvious. As an example, Gate the next applet shows a NAND gate with 3-inputs. As for the 2-input NAND, all (three) P-type transistors are connected in parallel between VCC and the output Y, while all N-type transistors are connected in series. Again, the wires connecting the N-type transistors may have floating voltage levels when the transistors are nonconducting. That is no problem, because these wires are not connected to any transistor gate.

NOR gates with three and more inputs are constructed correspondingly - all P-type transistors are connected in series and the N-type transistors are connected in parallel between GND and the output Y. However, the series connection of transistors implies longer propagation delay (especially for P-type transistors) and a voltage drop across the transistors. Therefore, NAND gates for actual CMOS cell libraries are usually limited to 4-inputs (4 N-type transistors in series) and NOR gates to 3-inputs (3 P-type transistors in series). NAND and NOR gates with more inputs are realized as a combination of simpler gates with up to 3 (4) inputs. Complex Gates As in NMOS technology, there are certain logic functions that can be realized very

efficiently by CMOS gates. These gates are called complex gates because they realize a complex logic function - although the gates themselves are rather simple. Typical example for complex gates found in almost all cell libraries are combinations of AND-OR-INVERT and OR-AND-INVERT gates. For example, the gate for the logic function Y = !((A ^ B) | (C ^ D ^ E)) - that is, the NOT of the OR of two ANDs - is typically called an AOI32 gate. This gate is shown in the next applet. It needs 10 transistors only (5 pairs of N-type and P-type transistors, one pair for each input). To simplify the circuit schematic, the input wires are not drawn completely. Rather, all input wires are broken into two pieces, connected to the corresponding N-type and P-type transistors. For example, to toggle the input voltage for input A, you can click both near the N-type or the P-type transistor gate connected to input A. Note that again the N-type and P-type paths in this gate are complementary. P-type transistors connected in series correspond to N-type transistors connected in parallel, and vice versa.

The generalization to other complex gates should be obvious. Again, gates with more than three transistors connected in series are not used. Most cell libraries contain gates from AOI21 and OAI21 up to aOI33 and OAI33. Try to construct one of these on paper and understand how it works! The CMOS As in NMOS technology, there are certain logic functions that can be realized very Transmission efficiently by CMOS gates. The first applet on this page demonstrated the switching Gate behaviour of N-type and P-type transistors. However, while both N-type and P-type transistors indeed have a very large resistance between source and drain when switched off, a detailed analysis reveals that the resistance between source and drain depends on the source and drain voltages when switched on. Especially, there is a voltage drop across a conducting N-type transistor when the source voltage is near VCC, and a voltage drop across a conducting P-type transistor when its source voltage is near GND. (Note that thhis poses no problem in the static CMOS gates, where all source contacts of N-type transistors are connected to GND and all source contactes of P-type transistors are connected to VCC.) Therefore, the use of single N-type or P-type transistors as switches is limited to circuits where the voltage drop across the conducting transistors is not critical. A series connection of transistors used as switches is usually not possible in digital circuits. But a combination of N-type and P-type transistors allows to realize efficient switches in CMOS technology. The circuit consists of one N-type and one P-type transistor connected in parallel and controlled by inverted gate voltages. This circuit, called a transmission gate (T-gate) is demonstrated in the following applet:

Click on the gate of either the N-type or the P-type transistor to invert (both) gate voltages. A T-gate requires that the N-type and P-type transistors have inverted gate voltages. Click on the 'L' (source) or 'R' (drain) contacts to toggle the corresponding

voltage from GND to VCC to Z. To better demonstrate the switching behaviour of the T-gate, the new voltage just selected by clicking 'wins' over the previous value.

If the gate voltage of the N-type transistor is 'GND', the P-type transistors has a gate voltage of 'VCC' and both transistors are nonconducting. On the other hand, if the gate voltage of the N-type transistor is 'VCC' and the gate voltage of the P-type transistor is 'GND', both transistors are conducting. If the source voltage is near VCC, there is a voltage drop across the N-type transistor but (almost) no voltage drop across the P-type transistor. If the source voltage is near GND, the N-type transistor has (almost) no voltage drop. Because of the symmetry of standard MOS transistors, there is no reason to differantiate between source and drain in a T-gate. The contacts are therefore usually called 'L' (left) and 'R' (right). The CMOS D- In CMOS technology, T-gates allow efficient realizations of several important logical Latch functions. Perhaps the most important use is demonstrated in the next applet. A standard D-latch (level controlled flipflop) can be build from four 2-input NAND gates. Therefore, 16 transistors are needed for one D-latch. (Try to construct this circuit on paper - the simple D-latch circuit is one of our pet examination problems!) The applets shows how a D-latch can be realized using only 8 transistors (2 inverters and 2 T-gates), if both the clock and the inverted clock signal are available - a savings of 50% of transistors and therefore chip-area. If the inverted clock is not available, an additional inverter is needed to provide the control signal for the two T-gates, still with a savings of 10 transistors versus 16.

Click near the D input to select the data input value for the D-latch. Click near the C (clock) or NC (inverted clock) input to toggle the current clock input value. To simplify the circuit schematic, the C and NC wires are not drawn completely. Rather, the corresponding T-gate gate inputs are labeled with C or NC. Note that the input T-gate (on the left) is controlled by C, while the feedback T-gate (on top) is controlled by NC.

The current values for data input D, clock input C, and data output Q are plotted as waveforms on the bottom of the applet. This allows to demonstrate the data storage in the latch when the C input is '0'. If you click anywhere else, the input voltages are not changed. However, simulation time is increased, and the waveforms are updated.

The function of the T-gate D-latch is very easy to understand. If the C input is '1', the input T-gate is conducting, and the data input value is connected to the first inverter input, which generates !D. The second inverter generates !!D = D, that is, the output Q equals D (the latch is transparent). If the C input is switched to '0', the first T-gate is blocked while the feedback T-gate

(whose R contact is connected to Q, which still equals D) is opened. Therefore, the circuit feeds its Q signal back to the first inverter (!Q) and to the second inverter !! Q=Q. That is, the value of Q is stored until the C input becomes '1' again. SRAM cell Please click here for a demonstration of the six-transistor cell used for static CMOS memories, e.g. processor cache memories. Related topics on our server

The Hamburg VHDL archive (VHDL tools and models) Chip-gallery (documentation about ICs we designed)

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