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ICS9LPRS511 Advance Information

Low Power Programmable Timing Control Hub for P4 processor

Recommended Application: Low Power CK505 Programmable clock Output Features: 2 - 0.8V differential push-pull CPU pairs 1 - 25 MHz 5 - PCI (33MHz) 1 - USB, 48MHz 1 - 24/48MHz 1 - REF, 14.318MHz 8 - PCIEX 0.8V differential push-pull pairs 1 - PCIEX/DOT96MHz selectable pairs 1 - SATACLK differential pair 1 - 24.576MHz output Key Specifications: CPU outputs cycle-cycle jitter < 85ps PCIEX outputs cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on CPU & PCIEX clocks Functionality Table
Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FSLC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FSLB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FSLA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 134.66 202.00 168.33 274.66 137.33 206.00 N/A 279.99 140.00 210.00 N/A 285.33 142.66 214.00 N/A PCIEX MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 103.00 103.00 103.00 N/A 105.00 105.00 105.00 N/A 107.00 107.00 107.00 N/A PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.66 33.66 33.66 33.66 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 35.66 35.66 35.66 35.66 SATA MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00

Features/Benefits: Programmable output frequencies Programmable output skew. Programmable spread percentage for EMI control. Programmable watch dog safe frequency. Supports tight ppm accuracy clocks for Serial-ATA Supports spread spectrum modulation, 0.25% center spread. Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Low Power differential outputs (50ohm resistor to GND not needed) Integrated 33 series resistor on all differential outputs

Pin Configuration
**RLATCH GND VDD **GSEL/24.576Mhz VDDPCI GND **DOC_1 PCICLK0 PCICLK1_3x FSLB/PCICLK2_2x SELRSET/RESET#/PCICLK3 PCICLK4 **DOC_0 VDD48 FSLA/USB_48MHz *SEL24_48#/24_48Mhz GND Vtt_PwrGd/WOL_STOP# DOT96T_LR/PCIeT_LR0 DOT96C_LR/PCIeC_LR0 GND PCIeT_LR1 PCIeC_LR1 PCIeT_LR2 PCIeC_LR2 GND PCIeT_LR3 PCIeC_LR3 PCIeT_LR4 PCIeC_LR4 GND VDDPCIEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25Mhz_0F_2x/Freerun* GND VDD25Mhz VDDSATA SATACLKT_LR SATACLKC_LR GND REF0_2x/FSLC GND X1 X2 VDDREF SDATA SCLK GND CPUT_LR0 CPUC_LR0 VDDCPU CPUT_LR1 CPUC_LR1 VDDI/O GNDA VDDA PCIeT_LR8 PCIeC_LR8 PCIeT_LR7 PCIeC_LR7 GND PCIeT_LR6 PCIeC_LR6 PCIeT_LR5 PCIeC_LR5

64-Pin TSSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor RESET pin is 3.3V tolerant

113709/05/08 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

ICS9LPRS511

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Pin Description
Pin# Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 **RLATCH GND VDD **GSEL/24.576Mhz VDDPCI GND **DOC_1 PCICLK0 PCICLK1_3x FSLB/PCICLK2_2x SELRSET/RESET#/PCICLK3 PCICLK4 **DOC_0 VDD48 FSLA/USB_48MHz *SEL24_48#/24_48Mhz GND Vtt_PwrGd/WOL_STOP# Type Pin Description Asynchronous input pin used in combination with VTTPWRGD signal to determine IN whether to reset I2c. PWR Ground pin. PWR Power supply, nominal 3.3V Latch input to select PCIEX0 and DOT96 output. GSEL = 1, selects DOT 96Mhz ; I/O GSEL = 0, selects PCIEX0. / 24.576Mhz clock output PWR Power supply for PCI clocks, nominal 3.3V PWR Ground pin. Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will IN transition to a preprogrammed value in the I2c. OUT PCI clock output. OUT Programmable 3x strength PCICLK, default 2x I/O I/O 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.

Latch select input pin. SELRSET = 0, selects PCICLK, SELRSET = 1 selects RESET# OUT PCI clock output. Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will IN transition to a preprogrammed value in the I2c. PWR Power pin for the 48MHz output.3.3V I/O I/O PWR IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. Ground pin. This active high 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled / Asynchronous active low input pin that stops all outputs except free running 25Mhz True clock of differential pair for 96.00MHz non-spreading DOT clock/ True clock of PCIEX0 Clock pair - selectable by GSEL; both 0.75V differential pairs are 0.75V pushpull outputs with integrated 33ohm series resistor. Complementary clock of differential pair for 96.00MHz non-spreading DOT clock/ Complementary clock of PCIEX0 Clock pair - selectable by GSEL; both 0.75V differential pairs are 0.75V push-pull outputs with integrated 33ohm series resistor. Ground pin. True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor Ground pin. True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm series resistor Ground pin. Power supply for PCI Express clocks, nominal 3.3V

19

DOT96T_LR/PCIeT_LR0

OUT

20 21 22 23 24 25 26 27 28 29 30 31 32

DOT96C_LR/PCIeC_LR0 GND PCIeT_LR1 PCIeC_LR1 PCIeT_LR2 PCIeC_LR2 GND PCIeT_LR3 PCIeC_LR3 PCIeT_LR4 PCIeC_LR4 GND VDDPCIEX

OUT PWR OUT OUT OUT OUT PWR OUT OUT OUT OUT PWR PWR

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Pin Description (Continued)

Pin# Pin Name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 25Mhz_0F_2x/Freerun* PCIeC_LR5 PCIeT_LR5 PCIeC_LR6 PCIeT_LR6 GND PCIeC_LR7 PCIeT_LR7 PCIeC_LR8 PCIeT_LR8 VDDA GNDA VDDI/O CPUC_LR1 CPUT_LR1 VDDCPU CPUC_LR0 CPUT_LR0 GND SCLK SDATA VDDREF X2 X1 GND REF0_2x/FSLC GND SATACLKC_LR SATACLKT_LR VDDSATA VDD25Mhz GND Type Pin Description Complement clock of 0.75V differential push-pull PCI_Express pair with integrated OUT 33ohm series resistor True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm OUT series resistor Complement clock of 0.75V differential push-pull PCI_Express pair with integrated OUT 33ohm series resistor True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm OUT series resistor PWR Ground pin. Complement clock of 0.75V differential push-pull PCI_Express pair with integrated OUT 33ohm series resistor True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm OUT series resistor Complement clock of 0.75V differential push-pull PCI_Express pair with integrated OUT 33ohm series resistor True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm OUT series resistor PWR 3.3V power for the PLL core. PWR Ground pin for the PLL core. PWR Power supply for differential outputs Complementary clock of differential pair 0.75V push-pull CPU outputs with integrated OUT 33ohm series resistor. True clock of differential pair 0.75V push-pull CPU outputs with integrated 33ohm OUT series resistor. PWR Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair 0.75V push-pull CPU outputs with integrated OUT 33ohm series resistor. True clock of differential pair 0.75V push-pull CPU outputs with integrated 33ohm OUT series resistor. PWR Ground pin. IN Clock pin of SMBus circuitry, 5V tolerant. I/O Data pin for SMBus circuitry, 5V tolerant. PWR Ref, XTAL power supply, nominal 3.3V OUT Crystal output, Nominally 14.318MHz IN Crystal input, Nominally 14.318MHz. PWR Ground pin. 2x strength 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency I/O selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. PWR Ground pin. Complement clock of 0.75V push-pull differential SATA pair with integrated 33ohm OUT series resistor. True clock of 0.75V push-pull differential SATA pair with integrated 33ohm series OUT resistor. PWR Supply for SATA clocks, 3.3V nominal PWR Power supply for 25MHz clocks, 3.3V nominal. PWR Ground pin. 2x strength 25MHz clock output, 3.3V (free running by default) / Latch input to select if I/O 25Mhz_0 is freerunning or stoppable on power up default. Freerun = 1, 25Mhz_0 is free running, Freerun = 0, 25Mhz_0 is stoppable.

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General Description
ICS9LPRS511 follows the Intel CK505-compliant clock specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPRS511 is driven with a 14.318MHz crystal.

Block Diagram

24.576MHz 25MHz 48MHz, USB 24_48MHz Fixed PLL X1 X2 Frequency Dividers DOTCLKT96/PCIEXT0 DOTCLKC96/PCIEXC0 XTAL REF0

PCICLK (4:0) Programmable Frequency Divider Array CPUCLKT (1:0) STOP Logic CPUCLKC (1:0) SATACLKT SATACLKC PCIEXT(8:1) PCIEXC(8:1)

SCLK SDATA FSLA FSLB FSLC VttPwrgd/WOL_STOP# DOC (1:0) SEL24_48# SELRSET RLATCH GSEL

PLL Array Control Logic

Reset#

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Table1: CPU PLL Frequency Selection Table

B0b4 B0b3 B0b2 FSLC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B0b1 B0b0 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 134.66 202.00 168.33 274.66 137.33 206.00 N/A 279.99 140.00 210.00 N/A 285.33 142.66 214.00 N/A PCIEX (B21b7 = 1) MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 103.00 103.00 103.00 N/A 105.00 105.00 105.00 N/A 107.00 107.00 107.00 N/A % Spread

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

FSLB FSLA 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center

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Table2: PCIEX PLL Frequency Selection Table

B19b4 B19b3 B19b2 B19b1 B19b0 FSLC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSLB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSLA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PCIEX (B21b7 = 0) MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 103.00 103.00 103.00 103.00 105.00 105.00 105.00 105.00 107.00 107.00 107.00 107.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.66 33.66 33.66 33.66 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 35.66 35.66 35.66 35.66 SATA (B21b6 = 0) MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 103.00 103.00 103.00 103.00 105.00 105.00 105.00 105.00 107.00 107.00 107.00 107.00 Spread %

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down 0-0.5% Down +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center +/- 0.3% Center

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General I2C serial interface information for the ICS9LPRS511 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit

How to Read:
Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)

Index Block Read Operation

Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)

ACK

ACK

Byte N + X - 1 ACK P stoP bit

ACK

Byte N + X - 1 N P Not acknowledge stoP bit

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I2C Table: Frequency Select Register Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ROD PCIEX_SS CPU_SS FS4 FS3 FSLC FSLB FSLA Control Function Reset on Demand PCIEX PLL Spread Enable CPU PLL Spread Enable Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type RW RW RW RW RW RW RW RW 0 Disable OFF OFF 1 Enable ON ON PWD A/B 0 1 1 0 0 Latch Latch Latch PWD C/D/E/H/J 0 0 1 0 0 Latch Latch Latch

See Table 1: Frequency Selection Table

I2C Table: Frequency Select Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SEL24_48 I2c RB SELRSET PCIEX PLL MNEN CPU PLL MNEN 25Mhz_0F Reserved GSEL Control Function Select 24_48Mhz Select I2c readback from Select RESET PCIEX PLL M/N Enable CPU PLL M/N Enable Free-running control during WOL_STOP Reserved GSEL selection Type RW RW RW RW RW RW RW RW 0 48 Shadow RAM PCICLK4 Disable Disable Stoppable PCIEX0 1 24 Active RAM Reset# Enable Enable Free-running DOT96Mhz PWD A/B/C/D/E/H/J latch 1 latch 0 0 latch 0 latch

I2C Table: Output Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name USB_48Mhz PCIEXT/C8 SATACLK PCICLK5 PCICLK4 PCICLK3 PCICLK2 Reserved Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Reserved Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable PWD A/B/C/D/E/H/J 1 1 1 1 1 1 1 1

I2C Table: Output Control Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCICLK1 PCICLK0 PCIEXT/C7 PCIEXT/C6 PCIEXT/C5 PCIEXT/C4 PCIEXT/C3 PCIEXT/C2 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD A/B/C/D/E/H/J 1 1 1 1 1 1 1 1

I2C Table: Output Control Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCIEXT/C1 REF0 CPUCLK1 CPUCLK0 24.576Mhz Dot96Mhz/PCIEXT/C0 25Mhz_0F Reserved Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Reserved RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable PWD A/B/C/D/E/H/J 1 1 1 1 1 1 1 1

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I2C Table: Output Control Register Byte 5 Bit Bit Bit Bit 7 6 5 4 Name 24_48Mhz Diff AMP Diff AMP Reserved iAMT EN (only applicable to revisions H and J, otherwise this is a reserved bit) Reserved Reserved Load Control Control Function Output Control Differential output Amplitude Control Reserved iAMT Enable Control Reserved Reserved IIC Load control RW RW RW RW RW RW RW RW 0 Disable 00 = 600mV 10 = 800mV Stoppable Load 1 Enable 01 = 900mV 11 = 700mV Free-running Do not Load PWD A/B/C/D/E/H/J 1 1 0 0 0 0 0 0

Bit 3 Bit 2 Bit 1 Bit 0

I2C Table: Reserved Register Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD A/B/C/D/E/H/J 0 0 0 0 0 0 0 0

I2C Table: Revision and Vendor ID Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function Type R R R R R R R R 0 001 = ICS 1 PWD A/B 0 0 0 0 0 0 0 1 PWD C/D 0 0 1 0 0 0 0 1 PWD PWD PWD E H J 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1

Revision ID

VENDOR ID

I2C Table: Byte Count Register Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type R R R RW RW RW RW RW PWD A/B/C/D/E/H/J 0 0 0 Writing to this register will configure how many bytes will be 0 read back, default is 0F = 15 bytes. 1 1 1 1 0 1

Byte Count Programming b(7:0)

I2C Table: Watch Dog Timer Control Register Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name HWD_EN SWD_EN WD Hard Status WD Soft Status WDTCtrl HWD2 HWD1 HWD0

Control Function Watchdog Hard Alarm Enable Watchdog Soft Alarm Enable WD Hard Alarm Status WD Soft Alarm Status Watch Dog Alarm Time base Control WD Hard Alarm Timer Bit 2 WD Hard Alarm Timer Bit 1 WD Hard Alarm Timer Bit 0

Type RW RW R R RW RW RW RW

0 Disable Disable Normal Normal 290ms Base

1 Enable Enable Alarm Alarm 1160ms Base

PWD A/B/C/D/E/H/J 0 0 X X 0 1

These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s.

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I2C Table: WD Safe Frequency Control Register Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SWD2 SWD1 SWD0 WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 Control Function WD Soft Alarm Timer Bit 2 WD Soft Alarm Timer Bit 1 WD Soft Alarm Timer Bit 0 Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J 1 These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 1 2s. 1 0 0 Writing to these bit will configure the safe frequency as 0 Byte10 bit (4:0). 0 0 0 1

Watch Dog Safe Freq Programming bits

I2C Table: CPU PLL Frequency Control Register Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name N Div2 N Div1 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Prog bit 2 N Divider Prog bit 1 Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J X X X The decimal representation of M and N Divider in Byte 11 X and 12 will configure the CPU PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency X = 14.318 x Ndiv(10:0)/Mdiv(5:0) X X X 0 1

M Divider Programming bit (5:0)

I2C Table: CPU PLL Frequency Control Register (DOC0 = 0) Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name N Div10 N Div9 N Div8 N Div7 N Div6 N Div5 N Div4 N Div3 Control Function Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J X X X The decimal representation of M and N Divider in Byte 11 X and 12 will configure the CPU PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency X = 14.318 x Ndiv(10:0)/Mdiv(5:0) X X X 0 1

N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6)

I2C Table: CPU PLL Spread Spectrum Control Register Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J X X X X These Spread Spectrum bits in Byte 13 and 14 will program the spread percentage of CPU PLL X X X X 0 1

Spread Spectrum Programming bit(7:0)

I2C Table: CPU PLL Spread Spectrum Control Register Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J 0 X X These Spread Spectrum bits in Byte 13 and 14 will program X the spread percentage of CPU PLL X X X X 0 1

Spread Spectrum Programming bit(14:8)

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I2C Table: PCIEX PLL Frequency Control Register Byte 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name N Div2 N Div1 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Prog bit 2 N Divider Prog bit 1 Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J X X X The decimal representation of M and N Divider in Byte 15 and 16 will configure the PCIEX PLL VCO frequency. Default X at power up = latch-in or Byte 0 Rom table. VCO Frequency X = 14.318 x Ndiv(10:0)/Mdiv(5:0) X X X 0 1

M Divider Programming bit (5:0)

I2C Table: PCIEX PLL Frequency Control Register (DOC0 = 0) Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name N Div10 N Div9 N Div8 N Div7 N Div6 N Div5 N Div4 N Div3 Control Function Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J X X X The decimal representation of M and N Divider in Byte 15 and 16 will configure the PCIEX PLL VCO frequency. Default X at power up = latch-in or Byte 0 Rom table. VCO Frequency X = 14.318 x Ndiv(10:0)/Mdiv(5:0) X X X 0 1

N Divider Programming Byte16 bit(7:0) and Byte15 bit(7:6)

I2C Table: PCIEX PLL Spread Spectrum Control Register Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J X X X These Spread Spectrum bits in Byte 17 and 18 will program X the spread percentage of PCIEX PLL X X X X 0 1

Spread Spectrum Programming bit(7:0)

I2C Table: PCIEX PLL Spread Spectrum Control Register Byte 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Type RW RW RW RW RW RW RW RW PWD A/B/C/D/E/H/J 0 X X X These Spread Spectrum bits in Byte 17 and 18 will program the spread percentage of PCIEX PLL X X X X 0 1

Spread Spectrum Programming bit(14:8)

I2C Table: PCIEX PLL Frequency Select Register Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved FS4 FS3 FSLC FSLB FSLA Control Function Reserved Reserved Reserved Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type RW RW RW RW RW RW RW RW 0 1 PWD A/B/C/D/E/H/J 1 0 0 0 0 Latch Latch Latch

See Table 2: PCIEX PLL Frequency Selection Table

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I2C Table: Output Control Register Byte 20 Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 Name Reserved Reserved Reserved Reserved PCIEX PLL TBEN CPU PLL TBEN Reserved RESET Sync Control Function Reserved Reserved Reserved Reserved PCIEX PLL Turbo Enable CPU PLL Turbo Enable Reserved Reset Synchronization upon Reset (Byte 21) Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable 1 Enable Enable Enable PWD A/B/C/D/E/H/J 0 0 0 0 0 0 0 0

Bit 0

I2C Table: Synchronization Control Register Byte 21 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCIEX Source SATA Source Reserved Reserved Reserved Reserved Reserved Reserved Control Function PCIEX Source SATA Source Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 PCIEX PLL PCIEX PLL 1 CPU PLL Fixed PLL PWD A/B 0 1 1 1 1 1 1 1 PWD C/D/E/H 1 1 1 1 1 1 1 1 PWD J 0 1 1 1 1 1 1 1

I2C Table: DOC pin control register Byte 22 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCIEX CPU Reserved Reserved Reserved Reserved Reserved Reserved Control Function PCIEX PLL DOC0 pin control CPU PLL DOC0 pin control Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Enabled Enabled 1 Disabled Disabled PWD A/B/C/D/E/H/J 1 0 0 0 0 0 1 1

I2C Table: CPU PLL DOC 1 N programming Register (DOC0 = 1) Byte 23 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name N Div10 N Div9 N Div8 N Div7 N Div6 N Div5 N Div4 N Div3 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD A/B/C/D/E/H/J X X X X X X X X

N Divider Programming Byte23 bit(7:0) and Byte11 bit(7:6)

The decimal representation of M and N Divider in Byte 11 and 23 will configure the CPU PLL VCO frequency. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0)

Bytes 24 and 25 are reserved

I2C Table: PCIEX PLL DOC 1 N programming Register (DOC0 = 1) Byte 26 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name N Div10 N Div9 N Div8 N Div7 N Div6 N Div5 N Div4 N Div3

Control Function

Type RW RW RW RW RW RW RW RW

N Divider Programming Byte26 bit(7:0) and Byte15 bit(7:6)

The decimal representation of M and N Divider in Byte 15 and 26 will configure the PCIEX PLL VCO frequency. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0)

PWD A/B/C/D/E/H/J X X X X X X X X

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Bytes 27 and 28 are reserved

I2C Table: Programmable output divider Register Byte 29 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name CPUDiv3 CPUDiv2 CPUDiv1 CPUDiv0 PCIEXDiv3 PCIEXDiv2 PCIEXDiv1 PCIEXDiv0 Control Function CPU Divider Ratio Programming Bits Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/7 0000:/2 0001:/3 0010:/5 0011:/7 0 0100:/4 0101:/6 0110:/10 0111:/14 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1000:/8 1001:/12 1010:/20 1011:/28 1 1100:/16 1101:/24 1110:/20 1111:/56 1100:/10 1101:/24 1110:/20 1111:/56 PWD A/B/C/D/E/H/J X X X X X X X X

PCIEX Divider Ratio Programming Bits for CPU PLL

I2C Table: Programmable output divider Register Byte 30 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name PCIEXDiv3 PCIEXDiv2 PCIEXDiv1 PCIEXDiv0 PCIDiv3 PCIDiv2 PCIDiv1 PCIDiv0 Control Function PCIEX Divider Ratio Programming Bits for PCIEX PLL Type RW RW RW RW RW RW RW RW 0000:/5 0001:/3 0010:/N/A 0011:/N/A 0000:/N/A 0001:/3 0010:/9 0011:/N/A 0 0100:/10 0101:/6 0110:/N/A 0111:/N/A 0100:/N/A 0101:/6 0110:/18 0111:/N/A 1000:/20 1001:/12 1010:/N/A 1011:/N/A 1000:/N/A 1001:/12 1010:/36 1011:/N/A 1 1100:/40 1101:/24 1110:/N/A 1111:/N/A 1100:/N/A 1101:/24 1110:/72 1111:/N/A PWD A/B/C/D/E/H/J X X X X X X X X

PCI Divider Ratio Programming Bits

I2C Table: Strength Control Register Byte 31 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name 25Str_1 25Str_0 REFStr_1 REFStr_0 PCIStr_1 PCIStr_0 PCIStr_1 PCIStr_0 Control Function 25Mhz_0 Strength Control REFCLK0 Strength Control PCICLK1 Strength Control PCICLK2 Strength Control Type RW RW RW RW RW RW RW RW 0 00 = tristated 01 = 0.1x 00 = tristated 01 = 0.1x 00 = tristated 01 = 2.00x 00 = tristated 01 = 0.1x 1 10 = 1.00x 11 = 2.00x 10 = 1.00x 11 = 2.00x 10 = 1.00x 11 = 3.00x 10 = 1.00x 11 = 2.00x PWD A/B/C/D/E/H/J 1 1 1 1 0 1 1 1

I2C Table: Skew programming Register Byte 32 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name CPUSkw3 CPUSkw2 CPUSkw1 CPUSkw0 CPUSkw3 CPUSkw2 CPUSkw1 CPUSkw0 Control Function CPUCLK0 Skew Control (ps) Type RW RW RW RW RW RW RW RW 0000:0 0001:100 0010:200 0011:300 0000:0 0001:100 0010:200 0011:300 0 0100:400 0101:500 0110:600 0111:700 0100:400 0101:500 0110:600 0111:700 1000:800 1001:900 1010:1000 1011:1100 1000:800 1001:900 1010:1000 1011:1100 1 1100:1200 1101:1300 1110:1400 1111:1500 1100:1200 1101:1300 1110:1400 1111:1500 PWD A/B/C/D/E/H/J 0 0 0 0 0 0 0 0

CPUCLK1 Skew Control (ps)

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Absolute Maximum Ratings

PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Case Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts Tcase ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Human Body Model 2000 GND - 0.5 -65 150 115 MIN MAX 4.6 3.8 4.6 UNITS Notes V V V V

1,7 1,7 1,7,8 1,7 1,7 1 1,7

C V

Electrical Characteristics - Input/Supply/Common Output Parameters

PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage (Test Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE IIN IINRES VOHSE VOLSE VOHDIF VOLDIF VIH_FS_TEST VIH_FS VIL_FS IDD_DEFAULT IDD_PLL3DIF Operating Supply Current IDD_PLL3SE IDD_IO IDD_PD3.3 Power Down Current IDD_PDIO IDD_iAMT3.3 IDD_iAMT0.8 Fi Lpin CIN Input Capacitance Spread Spectrum Modulation Frequency
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CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Differential Outputs, IOH = TBD mA Differential Outputs, IOL = TBD mA 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3V supply, PLL3 off 3.3V supply, PLL3 Differential Out 3.3V supply, PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 0.8V IO supply, Power Down Mode 3.3V supply, iAMT Mode 0.8V IO supply, iAMTMode VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation

MIN 0 3.135 1.05 2 VSS - 0.3 -5 -200 2.4

MAX 70 3.465 3.465 VDD + 0.3 0.8 5 200

UNITS Notes C V V V V uA uA V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1

0.4 0.7 0.9 0.4 2 0.7 VSS - 0.3 VDD + 0.3 1.5 0.35 TBD TBD TBD TBD TBD TBD TBD TBD TBD 7 1.5 5 6 TBD 30 33

V V V V V V mA mA mA mA mA mA mA mA MHz nH pF pF pF kHz

iAMT Mode Current Input Frequency Pin Inductance

COUT CINX fSSMOD

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AC Electrical Characteristics - Input/Common Parameters

PARAMETER Clk Stabilization Tdrive_SRC Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL TSTAB T DRSRC TDRPD T DRSRC T FALL T RISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MIN MAX 1.8 15 300 10 5 5 UNITS Notes ms ns us ns ns ns 1 1 1 1 1 1

AC Electrical Characteristics - (CPU, PCIEX, SATACLK, DOT96Mhz) Low Power Differential Outputs
PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 100 150 TBD MIN 2.5 2.5 MAX 8 8 20 1150 UNITS NOTES V/ns V/ns % mV mV mV mV mV % ps ps ps ps ps ps 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1

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Electrical Characteristics - PCICLK/PCICLK_F

PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Skew Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tskew tjcyc-cyc CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 33.33MHz output nominal/spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 1 1 45 30 38 4 4 55 250 500 -33 -33 MIN -300 29.99100 29.49100 2.4 0.4 MAX 300 30.00900 30.15980 30.65980 UNITS NOTES 1,6 ppm ns ns ns V V mA mA mA mA V/ns V/ns % ps ps 6 6 6 1 1 1 1 1 1 1 1 1 1 1

Electrical Characteristics - USB48MHz, 24_48Mhz

PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V 1 1 45 29 27 2 2 55 350 -29 -23 MIN -100 20.83125 20.48130 2.4 0.4 MAX 100 20.83542 21.18540 UNITS NOTES ppm 1,2 ns ns V V mA mA mA mA V/ns V/ns % ps 2 2 1 1 1 1 1 1 1 1 1 1

Electrical Characteristics - SMBus Interface

PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency
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SYMBOL VDD VOLSMB IPULLUP T RI2C T FI2C F SMBUS

CONDITIONS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode

MIN 2.7

MAX 5.5 0.4

UNITS Notes V V mA 1 1 1 1 1 1

4 1000 300 100

ns ns kHz

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Electrical Characteristics - REF-14.318MHz

PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS Notes ppm ns ns V V mA mA V/ns V/ns % ps 1,2 2 2 1 1 1 1 1 1 1 1

Notes on Electrical Characteristics:

1 2 3 4 5

Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK#

Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
7 8

Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD

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SYMBOL A A1 A2 b c D E E1 e L N aaa VARIATIONS

E1 INDEX AREA

1 2

D

A2 A1

6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004

-Ce
b SEATING PLANE

N 64

D mm. MIN 16.90 MAX 17.10 MIN .665

D (inch) MAX .673

aaa C

Reference Doc.: JEDEC Publication 95, MO-153

10-0039

Ordering Information
ICS9LPRS511yGLF-T
Example:

ICS XXXX y G LF- T

Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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Revision History
Rev. 0.1 0.2 0.3 0.4 Issue Date 8/3/2005 8/17/2005 8/25/2005 8/31/2005 Description Page # Initial Release Updated pinout and invert VTTPWRGD/WOL_STOP polarity 1-4 Added I2c Tables 8-21 Updated pinout (DOC1 removed, PCICLK1 added) 1-3, 19-21 1) Updated pinout, pin description (move freerun latch from PCICLK to 25Mhz_0) 1-3, 8-18 2) Updated I2c Bytes 1, 5, 22, 31 1) Changed pin 42, 53, 61 and 62 from Standby (Non Collapsible) Power to Standard Power. 1,3, 2) Removed Power Groups Table. 4 Updated I2C. 8-18 1. Updated Pinout. 2. Updated Pin Description. 1,2 1. Updated I2C. 8-13 1. Updated Output Features to represent low power. 2. Updated I2C. Various Updated Functionality and CPU frequency table 1, 5 Added Case Temperature @ 115C to Max Rating Table. 14

0.5

9/19/2005

0.6 0.7 0.5 0.6 0.7 0.8 0.9

10/6/2005 4/7/2006 7/31/2006 9/26/2006 11/2/2006 10/4/2007 9/5/2008

Silicon Revision History

Rev. 0.1 B0b6 = 1 in revisions [A:B] B0b6 = 0 in revisions [C:J] B7 = 01h in revisions [A:B] B7 = 21h in revisions [C:D] B7 = 41h in revision E B7 = 51h in revision H B7 = 61h in revision J B21b7 = 0 in revisions [A:B] B21b7 = 1 in revisions [C:H] B21b7 = 0 in revision J Description

0.2

0.3

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This product is protected by United States Patent NO. 7,342,420 and other patents.

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