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I. INTRODUCTION The human central and/or peripheral nervous system has been a subject of study and fascination of the neuroscience and biomedical engineering communities for many decades. The neural signal recording has been an important research issue and is widely considered as key topics for better understanding, controlling and eventually restoring neurological functions using implantable microsystems. These ones require a long term simultaneous recording of neural activity from many neurons simultaneously. The ideal system for long term recording would be a fully implantable device which is capable of amplifying the neural signals and transmitting them to the outside world [1], [2], [3]. Extracellular neural action potentials are one of the most challenging ones to record. They contain frequency components from 0.1 ~ 10 kHz and amplitudes in 50 ~ 500 V range [4]. These signals usually carry DC baselines up to 500 mV due to electrode electrolyte interactions. The low-level signal amplitude, wide frequency range, and large DC baseline are the major challenges one would face when designing neural recording amplifiers. In addition, robustness of the amplifier in order to guarantee its proper operation in spite of the process and ambient variations is a major
requirement. Further, it would be useful to have a robust amplifier with tunable bandwidth as well as variable gain that could be used for different types of biopotential signals or different components in one type of signal [4]. The most critical block in neural recording system is low-power low-noise neural amplifier which is the first stage in the neural recording system. There have been considerable research efforts in the design of low-power low-noise neural amplifiers in recent years. Harrison et al. described a low-noise low-power single-ended operational transconductance amplifier (OTA) with capacitive feedback for neural recording applications [5]. Although bioamplifiers that retrieve weak bioelectrical signals have been developed extensively [5]-[11], very few reported designs meet the noise, power, and size requirements for massive integration in implantable multichannel recording devices. Furthermore, the integrated designs that have been proposed give a high CMRR and a low power dissipation for safe permanent usage with an acceptable input referred noise. The architecture of the neural recording system is discussed in Section II followed by the theoretical study of the neural amplifier in Section III. Section IV provides simulation results and Section V is the conclusion. II. NEURAL RECORDING SYSTEM ARCHITECTURE The block diagram of the neural recording signal is shown in fig. 1. It consists of two units: an implantable transmitter and an external receiver unit. The implantable transmitter acquires neural signals from microelectrode array, amplifies, processes and transmits them to external unit wirelessly through a miniature antenna. The receiver picks up the neural signal, digitizes it, and transfers it to the PC for further signal processing, recording and visualization. The implantable part is supplied by power and data via inductive link, not included in fig.1 [12].
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Va Vb =
Computer Interface
Receiver
Amplifiers
With
gmI = gm1 = gm2 gmII = gm4 = gm5 gmIII = gm6 = gm7
Skin
Microelectrodes
And
k= gmIII gm6 gm7 = = gmII gm4 gm5
III. THEORETICAL STUDY A. Small signal analysis In the small signal analysis, we focus only on the input differential stage. Fig.2 (a) and fig.2 (b) show respectively the transistor differential stage and the simplified equivalent diagram of the differential stage.
Vdd
M9 MP
C. Neural amplifier circuit analysis Fig.2 shows the schematic of the neural recording amplifier which composed of a differential stage and an output gain stage.
Vdd M4 MP M6 MP M7 MP M5 MP M15 MP M8 MP M16 MP
M4 MP
M6 MP
M7 MP
M5 MP
M17 MP M1 MN INM2 MN IN+ MN M14 M18 MN Out
CL
Va Vb
Vbias
MN M13
0
M3 MN
IN-
V1
M1 MN
M2 MN
V2
M11 MN
M12 MN
IN+
Vdd Ibias M10 MN Vss Vdd Vdd 1Vdc Vss Vss 1Vdc
Ibias
Vss
(a)
Va Vb gm7.Vb gm6.Va
Vss
1/gm4 gm1.V1
(b) Fig.2. (a) Circuit differential input stage (b) Small-signal equivalent circuit
We note that gmi is the tranconductance of the transistor Mi, with i={1, 27}. B. Setting of equation From the small-signal fig.2.(b)), we calculate;
Va = gm1 .V1 .
If k > 1; the structure given by fig.3 works as a hysteresis comparator. If k < 1; therefore, it works as a differential amplifier, and for maximum voltage gain, k must tend to 1, and gmI must be very large compared to gmII. By operating the transistors M1 and M2 in weak inversion, we can simplify the equation (3) to :
1+ k (V2 V1 ) (8) 1 k Referring to fig.3, we can express the output voltage Vout in terms of the differential amplifier input; Va Vb Vout = Va gm9 Rout Vb gm8 Rout
equivalent
circuit
(see
(1)
(9)
and
1 1 Vb = gm2 .V2 . gm6 .Va . (2) gm5 gm5 We obtain a relation between the differential output voltage ( Va Vb ) and the differential input voltage
With Rout is the amplifier output resistance, and gm8, gm9 are the respective transconductance of transistors M8 and M9. Following a small-signal study of the output stage, we calculate the output resistance as follows:
( V2 V1 ) given by:
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(10) We consider the case where gm8 = gm9, and from equations (8) and (9), we obtain an output voltage as:
12
(rds
gm18 rds18 )
We apply an AC source in the input of amplifier given in fig.3. The schema in fig.4 is use to draw Bode diagram and to extract its dynamic characteristics.
Vdd
(11)
10mVac 0Vdc V1
D. Technological specification In order to realize a low power and low noise amplifier, to amplify neurological signals which have low amplitude (from 50 to 500V). We must respond to technological specifications and requirements listed in Table I.
TABLE I SPECIFICATIONS AND REQUIREMENTS Specifications and requirements Technology AMS 0.35m Supply voltage 1V Gain at least 40 dB Gain bandwidth at least 1 MHz Phase margin at least 60 Power consumption less than 20A Common Mode Ratio Rejection at least 80 dB CMRR Power Supply Rejection Ratio PSRR at least 60 dB Load capacitance upper to 7pF 0 0 0
Fig.4: AC simulation
Fig.5 shows the Bode diagram that gives a gain=43.95 dB (equivalent to 157.57). The phase margin is equal to 64.6 , hence the stability of the system. The gainbandwidth is GBW = 1.1294MHz.
1 -0d 2 G a i n ( d B ) 0 50 P h a s e -100d D e g r e -200d e
-50
-300d
-100
-400d
10KHz
100KHz Frequency
1.0MHz
10MHz
100MHz
1.0GHz
IV. SIMULATION RESULTS Referring to fig.3 and respecting the specifications and the requirements shown in table 1, we calculate the size of different devices. Table.2 presents the parameters values of the neural recording amplifier.
TABLE II NEURAL AMPLIFIER PARAMETER VALUES Devices M1-M2 M3, M10, M11, M12, M13, M18, M14 M4, M5, M8, M9, M15, M16, M17 M6-M7 Supply voltage Load capacitance Bias current Value W=100m W=1.5m W=6m W=5m Vdd=1V CL=7pF Ibias =1A L=1m L=1m L=1m L=1m Vss=-1V
Fig.5 Simulated transfer function of amplifier Magnitude (dB) and phase (degree)
Noise analysis The input-referred noise voltage of CMOS amplifier is dominated by flicker (1/f) noise at low frequencies and thermal/shot noise at higher frequencies. The frequency at which the noise tail intersects the noise floor is called the flicker-noise corner frequency. By representing the noise sources of each transistor by a voltage source at its input, the total input-referred noise contribution can be calculated by considering the voltage gains from the device to the amplifier output. In order to examine the noise performance of neural amplifier was simulated using the Pspice. Fig.6 shows the input-referred noise voltage versus frequency.
1.5uV
1.0uV
By using Pspice, we process to simulate the circuit given by fig.3. We determine various characteristics such as gain, phase margin, power, noise, CMRR, PSRR, and offset. Frequency analysis
0.5uV
0V 10Hz V(INOISE)
100Hz
1.0KHz
10KHz Frequency
100KHz
1.0MHz
10MHz
The Root Mean Square (RMS) of the input-referred noise voltage: Vni,rms = 14.8 Vrms calculated for a
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frequency range 100Hz ~ 10 KHz. This value is competitive compared to other developed recording amplifiers reported in the literature [10], [13]. Noise Efficiency Factor We are interested in minimizing noise within a strict power budget; we must consider the tradeoff between power and noise. To compare the powernoise tradeoff among amplifiers, we adopt the noise efficiency factor (NEF) which is widely used to compare neural amplifier designs. The noise efficiency factor is expressed as:
NEF = Vni, rms
about 9.22 W and an input referred noise about 14.8Vrms were achieved. Future work will focus on the study of closed-loop amplifier with adjustable gain and low cut off frequency. REFERENCES
[1] P. Mohseni, K. Najafi, S. J. Eliades, and X. Wang, Wireless multichannel biopotential recording using an integrated FM telemetry circuit, IEEE Trans. Neural. Syst. Rehab. Eng., vol. 13, no. 3, pp. 263-271, September 2005. Nathan M. Neihart, and Reid R. Harrison, Micropower Circuits for Bidirectional Wireless Telemetry in Neural Recording Applications IEEE Trans. Biomed. Eng., vol. 52, no. 11, pp. 1950-1959, Nov 2005. Ming Yin; Ghovanloo, M., A Clockless Ultra Low-Noise Low-Power Wireless Implantable Neural Recording System, Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on. Volume , Issue , 18-21. pp.1756 1759, May 2008. Ming Yin; Ghovanloo, M., A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording Applications Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on. Volume, Issue, 27-30 May 2007 Page(s):321 324. Digital Object Identifier 10.1109/ISCAS.2007.378400 R. R. Harrison and C. Charles, A low-power low-noise CMOS amplifier for neural recording applications, IEEE J. Solid-State Circuits, vol. 38, pp. 958 965, June 2003. J. Parthasarathy et al., An Integrated CMOS Bio-potential Amplifier with a Feed-Forward DC Cancellation Topology, Froc. 28rd Annu. IEEE E? vIBS Conf, pp. 2974 2977, 2006. P.Mosheni and K.Najafi, A fully integrated neural recording amplifier with DC input stabilization, IEEE Trans. Bionied. Eng., vol. 51, pp. 832 837, May 2004. G. E. Perlin, and K. D. Wise, Neural recording front-end designs for fully implantable neuroscience applications and neural prosthetic Microsystems. Proceedings of the 28th IEEE, EMBS Annual International Conference, New York City, USA, Aug 30-Sept 3, 2006. Roy H. Olsson III, and Kensall D. Wise, A ThreeDimensional Neural Recording Microsystem With Implantable Data Compression Circuitry IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2796-2804, December 2005. T. Horiuchi, T. Swindell, D. Sander, and P. Abshire, A lowpower CMOS neural amplifier with amplitude measurements for spike sorting. Froc. IEEE Int. Symp. Circ. Sys., vol. 4, pp.29-32, May 2004. Reid R. Harrison, Paul T. Watkins, Ryan J. Kier, Robert O. Lovejoy, Daniel J. Black, Bradley Greger, and Florian Solzbacher, A Low-Power Integrated Circuit for a Wireless 100 Electrode Neural Recording System, IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 123-133, January 2007. Ghazi BEN HMIDA, Hamadi GHARIANI and Mounir SAMET : Design of Wireless Power and Data Transmission Circuits for Implantable Biomicrosystem. Biotechnology 6(2): 153-164, 2007. ISSN 1682-296X 2007 Asian Network for Scientific Information. Roy H. Olsson. III, Derek L. Buhl, Anton M. Sirota, Gyorgy Buzsaki, and Kensall D. Wise, Band-Tunable and Multiplexed Integrated Circuits for Simultaneous Recording and Stimulation with Microelectrode Arrays, IEEE Transactions on Biomedical Engineering, vol. 52, no. 7, pp. 1303-1311, July 2005.
[2]
(12)
[3]
Where Vni,rms is the total input-referred noise, Itot is the total supply current, and BW is the -3 dB bandwidth of the amplifier. UT is the thermal voltage, KB is the Boltzmann constant and T is the temperature. For UT=25mV, T=27C=300K, KB=1.3806.10-23 [J/K], Itot=4.617A, Vni,rms = 1,4888E-05 Vrms and BW= [100Hz, 10KHz]. We obtain NEF=13,22 which is competitive compared to [7]. Summary table Table III summarizes the simulation results of the neural recording amplifier.
TABLE III SIMULATED PERFORMANCE CHARACTERISTICS OF NEURAL AMPLIFIER Parameters Gain Phase margin Gain-BandWidth Power Consumption Total Current absorbed Common Mode Rejection Ratio Power Supply Rejection Ratio Output-voltage swing DC Offset Input Referred Noise Noise Efficiency Factor Value GdB = 43.95 dB M = 64.6 GBW = 1.1294 MHz Ptot= 9.22 W Itot=4.617 A CMRR=113.27dB CMRR > 92dB @ f < 10KHz PSRRVss=73.11dB PSRRVdd=75.29dB CMR+=806mV CMR-=992mV 196V Vni,rms = 14.8 Vrms NEF=13,22
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
IV. CONCLUSION This paper presents the design of an integrated micropower amplifier for neural recording signal. The architecture of the neural recording system was discussed and followed by the theoretical study of the neural amplifier. Furthermore, PSpice simulation which using a real transistor model was presented. In particular, the transfer function of amplifier and the noise analysis were presented. A power dissipation of
[12]
[13]
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